cs5535.c 6.3 KB

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  1. /*
  2. * linux/drivers/ide/pci/cs5535.c
  3. *
  4. * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
  5. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  6. *
  7. * History:
  8. * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
  9. * - Reworked tuneproc, set_drive, misc mods to prep for mainline
  10. * - Work was sponsored by CIS (M) Sdn Bhd.
  11. * Ported to Kernel 2.6.11 on June 26, 2005 by
  12. * Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
  13. * Alexander Kiausch <alex.kiausch@t-online.de>
  14. * Originally developed by AMD for 2.4/2.6
  15. *
  16. * Development of this chipset driver was funded
  17. * by the nice folks at National Semiconductor/AMD.
  18. *
  19. * This program is free software; you can redistribute it and/or modify it
  20. * under the terms of the GNU General Public License version 2 as published by
  21. * the Free Software Foundation.
  22. *
  23. * Documentation:
  24. * CS5535 documentation available from AMD
  25. */
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/ide.h>
  29. #include "ide-timing.h"
  30. #define MSR_ATAC_BASE 0x51300000
  31. #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
  32. #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
  33. #define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
  34. #define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
  35. #define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
  36. #define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
  37. #define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
  38. #define ATAC_RESET (MSR_ATAC_BASE+0x10)
  39. #define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
  40. #define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
  41. #define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
  42. #define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
  43. #define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
  44. #define ATAC_BM0_CMD_PRIM 0x00
  45. #define ATAC_BM0_STS_PRIM 0x02
  46. #define ATAC_BM0_PRD 0x04
  47. #define CS5535_CABLE_DETECT 0x48
  48. /* Format I PIO settings. We separate out cmd and data for safer timings */
  49. static unsigned int cs5535_pio_cmd_timings[5] =
  50. { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
  51. static unsigned int cs5535_pio_dta_timings[5] =
  52. { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
  53. static unsigned int cs5535_mwdma_timings[3] =
  54. { 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
  55. static unsigned int cs5535_udma_timings[5] =
  56. { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
  57. /* Macros to check if the register is the reset value - reset value is an
  58. invalid timing and indicates the register has not been set previously */
  59. #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
  60. #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
  61. /****
  62. * cs5535_set_speed - Configure the chipset to the new speed
  63. * @drive: Drive to set up
  64. * @speed: desired speed
  65. *
  66. * cs5535_set_speed() configures the chipset to a new speed.
  67. */
  68. static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
  69. {
  70. u32 reg = 0, dummy;
  71. int unit = drive->select.b.unit;
  72. /* Set the PIO timings */
  73. if ((speed & XFER_MODE) == XFER_PIO) {
  74. ide_drive_t *pair = ide_get_paired_drive(drive);
  75. u8 cmd, pioa;
  76. cmd = pioa = speed - XFER_PIO_0;
  77. if (pair->present) {
  78. u8 piob = ide_get_best_pio_mode(pair, 255, 4);
  79. if (piob < cmd)
  80. cmd = piob;
  81. }
  82. /* Write the speed of the current drive */
  83. reg = (cs5535_pio_cmd_timings[cmd] << 16) |
  84. cs5535_pio_dta_timings[pioa];
  85. wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
  86. /* And if nessesary - change the speed of the other drive */
  87. rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
  88. if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
  89. cs5535_pio_cmd_timings[cmd]) {
  90. reg &= 0x0000FFFF;
  91. reg |= cs5535_pio_cmd_timings[cmd] << 16;
  92. wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
  93. }
  94. /* Set bit 31 of the DMA register for PIO format 1 timings */
  95. rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
  96. wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
  97. reg | 0x80000000UL, 0);
  98. } else {
  99. rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
  100. reg &= 0x80000000UL; /* Preserve the PIO format bit */
  101. if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
  102. reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
  103. else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
  104. reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
  105. else
  106. return;
  107. wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
  108. }
  109. }
  110. /**
  111. * cs5535_set_dma_mode - set host controller for DMA mode
  112. * @drive: drive
  113. * @speed: DMA mode
  114. *
  115. * Programs the chipset for DMA mode.
  116. */
  117. static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
  118. {
  119. cs5535_set_speed(drive, speed);
  120. }
  121. /**
  122. * cs5535_set_pio_mode - set host controller for PIO mode
  123. * @drive: drive
  124. * @pio: PIO mode number
  125. *
  126. * A callback from the upper layers for PIO-only tuning.
  127. */
  128. static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
  129. {
  130. cs5535_set_speed(drive, XFER_PIO_0 + pio);
  131. }
  132. static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
  133. {
  134. u8 bit;
  135. /* if a 80 wire cable was detected */
  136. pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
  137. return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  138. }
  139. /****
  140. * init_hwif_cs5535 - Initialize one ide cannel
  141. * @hwif: Channel descriptor
  142. *
  143. * This gets invoked by the IDE driver once for each channel. It
  144. * performs channel-specific pre-initialization before drive probing.
  145. *
  146. */
  147. static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
  148. {
  149. hwif->set_pio_mode = &cs5535_set_pio_mode;
  150. hwif->set_dma_mode = &cs5535_set_dma_mode;
  151. if (hwif->dma_base == 0)
  152. return;
  153. hwif->cbl = cs5535_cable_detect(hwif->pci_dev);
  154. }
  155. static const struct ide_port_info cs5535_chipset __devinitdata = {
  156. .name = "CS5535",
  157. .init_hwif = init_hwif_cs5535,
  158. .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
  159. IDE_HFLAG_BOOTABLE,
  160. .pio_mask = ATA_PIO4,
  161. .mwdma_mask = ATA_MWDMA2,
  162. .udma_mask = ATA_UDMA4,
  163. };
  164. static int __devinit cs5535_init_one(struct pci_dev *dev,
  165. const struct pci_device_id *id)
  166. {
  167. return ide_setup_pci_device(dev, &cs5535_chipset);
  168. }
  169. static const struct pci_device_id cs5535_pci_tbl[] = {
  170. { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
  171. { 0, },
  172. };
  173. MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
  174. static struct pci_driver driver = {
  175. .name = "CS5535_IDE",
  176. .id_table = cs5535_pci_tbl,
  177. .probe = cs5535_init_one,
  178. };
  179. static int __init cs5535_ide_init(void)
  180. {
  181. return ide_pci_register_driver(&driver);
  182. }
  183. module_init(cs5535_ide_init);
  184. MODULE_AUTHOR("AMD");
  185. MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
  186. MODULE_LICENSE("GPL");