pasemi_mac.c 30 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include "pasemi_mac.h"
  35. /* TODO list
  36. *
  37. * - Get rid of pci_{read,write}_config(), map registers with ioremap
  38. * for performance
  39. * - PHY support
  40. * - Multicast support
  41. * - Large MTU support
  42. * - Other performance improvements
  43. */
  44. /* Must be a power of two */
  45. #define RX_RING_SIZE 512
  46. #define TX_RING_SIZE 512
  47. #define DEFAULT_MSG_ENABLE \
  48. (NETIF_MSG_DRV | \
  49. NETIF_MSG_PROBE | \
  50. NETIF_MSG_LINK | \
  51. NETIF_MSG_TIMER | \
  52. NETIF_MSG_IFDOWN | \
  53. NETIF_MSG_IFUP | \
  54. NETIF_MSG_RX_ERR | \
  55. NETIF_MSG_TX_ERR)
  56. #define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)])
  57. #define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)])
  58. #define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)])
  59. #define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)])
  60. #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
  61. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  62. MODULE_LICENSE("GPL");
  63. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  64. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  65. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  66. module_param(debug, int, 0);
  67. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  68. static struct pasdma_status *dma_status;
  69. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  70. {
  71. struct pci_dev *pdev = mac->pdev;
  72. struct device_node *dn = pci_device_to_OF_node(pdev);
  73. const u8 *maddr;
  74. u8 addr[6];
  75. if (!dn) {
  76. dev_dbg(&pdev->dev,
  77. "No device node for mac, not configuring\n");
  78. return -ENOENT;
  79. }
  80. maddr = of_get_property(dn, "local-mac-address", NULL);
  81. /* Fall back to mac-address for older firmware */
  82. if (maddr == NULL)
  83. maddr = of_get_property(dn, "mac-address", NULL);
  84. if (maddr == NULL) {
  85. dev_warn(&pdev->dev,
  86. "no mac address in device tree, not configuring\n");
  87. return -ENOENT;
  88. }
  89. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  90. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  91. dev_warn(&pdev->dev,
  92. "can't parse mac address, not configuring\n");
  93. return -EINVAL;
  94. }
  95. memcpy(mac->mac_addr, addr, sizeof(addr));
  96. return 0;
  97. }
  98. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  99. {
  100. struct pasemi_mac_rxring *ring;
  101. struct pasemi_mac *mac = netdev_priv(dev);
  102. int chan_id = mac->dma_rxch;
  103. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  104. if (!ring)
  105. goto out_ring;
  106. spin_lock_init(&ring->lock);
  107. ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  108. RX_RING_SIZE, GFP_KERNEL);
  109. if (!ring->desc_info)
  110. goto out_desc_info;
  111. /* Allocate descriptors */
  112. ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
  113. RX_RING_SIZE *
  114. sizeof(struct pas_dma_xct_descr),
  115. &ring->dma, GFP_KERNEL);
  116. if (!ring->desc)
  117. goto out_desc;
  118. memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
  119. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  120. RX_RING_SIZE * sizeof(u64),
  121. &ring->buf_dma, GFP_KERNEL);
  122. if (!ring->buffers)
  123. goto out_buffers;
  124. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  125. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id),
  126. PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
  127. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id),
  128. PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
  129. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
  130. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id),
  131. PAS_DMA_RXCHAN_CFG_HBU(1));
  132. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if),
  133. PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
  134. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if),
  135. PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
  136. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  137. ring->next_to_fill = 0;
  138. ring->next_to_clean = 0;
  139. snprintf(ring->irq_name, sizeof(ring->irq_name),
  140. "%s rx", dev->name);
  141. mac->rx = ring;
  142. return 0;
  143. out_buffers:
  144. dma_free_coherent(&mac->dma_pdev->dev,
  145. RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  146. mac->rx->desc, mac->rx->dma);
  147. out_desc:
  148. kfree(ring->desc_info);
  149. out_desc_info:
  150. kfree(ring);
  151. out_ring:
  152. return -ENOMEM;
  153. }
  154. static int pasemi_mac_setup_tx_resources(struct net_device *dev)
  155. {
  156. struct pasemi_mac *mac = netdev_priv(dev);
  157. u32 val;
  158. int chan_id = mac->dma_txch;
  159. struct pasemi_mac_txring *ring;
  160. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  161. if (!ring)
  162. goto out_ring;
  163. spin_lock_init(&ring->lock);
  164. ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  165. TX_RING_SIZE, GFP_KERNEL);
  166. if (!ring->desc_info)
  167. goto out_desc_info;
  168. /* Allocate descriptors */
  169. ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
  170. TX_RING_SIZE *
  171. sizeof(struct pas_dma_xct_descr),
  172. &ring->dma, GFP_KERNEL);
  173. if (!ring->desc)
  174. goto out_desc;
  175. memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
  176. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id),
  177. PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
  178. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
  179. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2);
  180. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val);
  181. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id),
  182. PAS_DMA_TXCHAN_CFG_TY_IFACE |
  183. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  184. PAS_DMA_TXCHAN_CFG_UP |
  185. PAS_DMA_TXCHAN_CFG_WT(2));
  186. ring->next_to_use = 0;
  187. ring->next_to_clean = 0;
  188. snprintf(ring->irq_name, sizeof(ring->irq_name),
  189. "%s tx", dev->name);
  190. mac->tx = ring;
  191. return 0;
  192. out_desc:
  193. kfree(ring->desc_info);
  194. out_desc_info:
  195. kfree(ring);
  196. out_ring:
  197. return -ENOMEM;
  198. }
  199. static void pasemi_mac_free_tx_resources(struct net_device *dev)
  200. {
  201. struct pasemi_mac *mac = netdev_priv(dev);
  202. unsigned int i;
  203. struct pasemi_mac_buffer *info;
  204. struct pas_dma_xct_descr *dp;
  205. for (i = 0; i < TX_RING_SIZE; i++) {
  206. info = &TX_DESC_INFO(mac, i);
  207. dp = &TX_DESC(mac, i);
  208. if (info->dma) {
  209. if (info->skb) {
  210. pci_unmap_single(mac->dma_pdev,
  211. info->dma,
  212. info->skb->len,
  213. PCI_DMA_TODEVICE);
  214. dev_kfree_skb_any(info->skb);
  215. }
  216. info->dma = 0;
  217. info->skb = NULL;
  218. dp->mactx = 0;
  219. dp->ptr = 0;
  220. }
  221. }
  222. dma_free_coherent(&mac->dma_pdev->dev,
  223. TX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  224. mac->tx->desc, mac->tx->dma);
  225. kfree(mac->tx->desc_info);
  226. kfree(mac->tx);
  227. mac->tx = NULL;
  228. }
  229. static void pasemi_mac_free_rx_resources(struct net_device *dev)
  230. {
  231. struct pasemi_mac *mac = netdev_priv(dev);
  232. unsigned int i;
  233. struct pasemi_mac_buffer *info;
  234. struct pas_dma_xct_descr *dp;
  235. for (i = 0; i < RX_RING_SIZE; i++) {
  236. info = &RX_DESC_INFO(mac, i);
  237. dp = &RX_DESC(mac, i);
  238. if (info->skb) {
  239. if (info->dma) {
  240. pci_unmap_single(mac->dma_pdev,
  241. info->dma,
  242. info->skb->len,
  243. PCI_DMA_FROMDEVICE);
  244. dev_kfree_skb_any(info->skb);
  245. }
  246. info->dma = 0;
  247. info->skb = NULL;
  248. dp->macrx = 0;
  249. dp->ptr = 0;
  250. }
  251. }
  252. dma_free_coherent(&mac->dma_pdev->dev,
  253. RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  254. mac->rx->desc, mac->rx->dma);
  255. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  256. mac->rx->buffers, mac->rx->buf_dma);
  257. kfree(mac->rx->desc_info);
  258. kfree(mac->rx);
  259. mac->rx = NULL;
  260. }
  261. static void pasemi_mac_replenish_rx_ring(struct net_device *dev)
  262. {
  263. struct pasemi_mac *mac = netdev_priv(dev);
  264. unsigned int i;
  265. int start = mac->rx->next_to_fill;
  266. unsigned int limit, count;
  267. limit = (mac->rx->next_to_clean + RX_RING_SIZE -
  268. mac->rx->next_to_fill) & (RX_RING_SIZE - 1);
  269. /* Check to see if we're doing first-time setup */
  270. if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0))
  271. limit = RX_RING_SIZE;
  272. if (limit <= 0)
  273. return;
  274. i = start;
  275. for (count = limit; count; count--) {
  276. struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i);
  277. u64 *buff = &RX_BUFF(mac, i);
  278. struct sk_buff *skb;
  279. dma_addr_t dma;
  280. /* skb might still be in there for recycle on short receives */
  281. if (info->skb)
  282. skb = info->skb;
  283. else
  284. skb = dev_alloc_skb(BUF_SIZE);
  285. if (unlikely(!skb))
  286. break;
  287. dma = pci_map_single(mac->dma_pdev, skb->data, skb->len,
  288. PCI_DMA_FROMDEVICE);
  289. if (unlikely(dma_mapping_error(dma))) {
  290. dev_kfree_skb_irq(info->skb);
  291. break;
  292. }
  293. info->skb = skb;
  294. info->dma = dma;
  295. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  296. i++;
  297. }
  298. wmb();
  299. pci_write_config_dword(mac->dma_pdev,
  300. PAS_DMA_RXCHAN_INCR(mac->dma_rxch),
  301. limit - count);
  302. pci_write_config_dword(mac->dma_pdev,
  303. PAS_DMA_RXINT_INCR(mac->dma_if),
  304. limit - count);
  305. mac->rx->next_to_fill += limit - count;
  306. }
  307. static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
  308. {
  309. unsigned int reg, stat;
  310. /* Re-enable packet count interrupts: finally
  311. * ack the packet count interrupt we got in rx_intr.
  312. */
  313. pci_read_config_dword(mac->iob_pdev,
  314. PAS_IOB_DMA_RXCH_STAT(mac->dma_rxch),
  315. &stat);
  316. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(stat & PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
  317. | PAS_IOB_DMA_RXCH_RESET_PINTC;
  318. pci_write_config_dword(mac->iob_pdev,
  319. PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch),
  320. reg);
  321. }
  322. static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
  323. {
  324. unsigned int reg, stat;
  325. /* Re-enable packet count interrupts */
  326. pci_read_config_dword(mac->iob_pdev,
  327. PAS_IOB_DMA_TXCH_STAT(mac->dma_txch), &stat);
  328. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(stat & PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
  329. | PAS_IOB_DMA_TXCH_RESET_PINTC;
  330. pci_write_config_dword(mac->iob_pdev,
  331. PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  332. }
  333. static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
  334. {
  335. unsigned int n;
  336. int count;
  337. struct pas_dma_xct_descr *dp;
  338. struct pasemi_mac_buffer *info;
  339. struct sk_buff *skb;
  340. unsigned int i, len;
  341. u64 macrx;
  342. dma_addr_t dma;
  343. spin_lock(&mac->rx->lock);
  344. n = mac->rx->next_to_clean;
  345. for (count = limit; count; count--) {
  346. rmb();
  347. dp = &RX_DESC(mac, n);
  348. macrx = dp->macrx;
  349. if (!(macrx & XCT_MACRX_O))
  350. break;
  351. info = NULL;
  352. /* We have to scan for our skb since there's no way
  353. * to back-map them from the descriptor, and if we
  354. * have several receive channels then they might not
  355. * show up in the same order as they were put on the
  356. * interface ring.
  357. */
  358. dma = (dp->ptr & XCT_PTR_ADDR_M);
  359. for (i = n; i < (n + RX_RING_SIZE); i++) {
  360. info = &RX_DESC_INFO(mac, i);
  361. if (info->dma == dma)
  362. break;
  363. }
  364. skb = info->skb;
  365. info->dma = 0;
  366. pci_unmap_single(mac->dma_pdev, dma, skb->len,
  367. PCI_DMA_FROMDEVICE);
  368. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  369. if (len < 256) {
  370. struct sk_buff *new_skb =
  371. netdev_alloc_skb(mac->netdev, len + NET_IP_ALIGN);
  372. if (new_skb) {
  373. skb_reserve(new_skb, NET_IP_ALIGN);
  374. memcpy(new_skb->data - NET_IP_ALIGN,
  375. skb->data - NET_IP_ALIGN,
  376. len + NET_IP_ALIGN);
  377. /* save the skb in buffer_info as good */
  378. skb = new_skb;
  379. }
  380. /* else just continue with the old one */
  381. } else
  382. info->skb = NULL;
  383. skb_put(skb, len);
  384. skb->protocol = eth_type_trans(skb, mac->netdev);
  385. if ((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) {
  386. skb->ip_summed = CHECKSUM_COMPLETE;
  387. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  388. XCT_MACRX_CSUM_S;
  389. } else
  390. skb->ip_summed = CHECKSUM_NONE;
  391. mac->stats.rx_bytes += len;
  392. mac->stats.rx_packets++;
  393. netif_receive_skb(skb);
  394. dp->ptr = 0;
  395. dp->macrx = 0;
  396. n++;
  397. }
  398. mac->rx->next_to_clean += limit - count;
  399. pasemi_mac_replenish_rx_ring(mac->netdev);
  400. spin_unlock(&mac->rx->lock);
  401. return count;
  402. }
  403. static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
  404. {
  405. int i;
  406. struct pasemi_mac_buffer *info;
  407. struct pas_dma_xct_descr *dp;
  408. int start, count;
  409. int flags;
  410. spin_lock_irqsave(&mac->tx->lock, flags);
  411. start = mac->tx->next_to_clean;
  412. count = 0;
  413. for (i = start; i < mac->tx->next_to_use; i++) {
  414. dp = &TX_DESC(mac, i);
  415. if (!dp || (dp->mactx & XCT_MACTX_O))
  416. break;
  417. count++;
  418. info = &TX_DESC_INFO(mac, i);
  419. pci_unmap_single(mac->dma_pdev, info->dma,
  420. info->skb->len, PCI_DMA_TODEVICE);
  421. dev_kfree_skb_irq(info->skb);
  422. info->skb = NULL;
  423. info->dma = 0;
  424. dp->mactx = 0;
  425. dp->ptr = 0;
  426. }
  427. mac->tx->next_to_clean += count;
  428. spin_unlock_irqrestore(&mac->tx->lock, flags);
  429. netif_wake_queue(mac->netdev);
  430. return count;
  431. }
  432. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  433. {
  434. struct net_device *dev = data;
  435. struct pasemi_mac *mac = netdev_priv(dev);
  436. unsigned int reg;
  437. if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
  438. return IRQ_NONE;
  439. if (*mac->rx_status & PAS_STATUS_ERROR)
  440. printk("rx_status reported error\n");
  441. /* Don't reset packet count so it won't fire again but clear
  442. * all others.
  443. */
  444. pci_read_config_dword(mac->dma_pdev, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), &reg);
  445. reg = 0;
  446. if (*mac->rx_status & PAS_STATUS_SOFT)
  447. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  448. if (*mac->rx_status & PAS_STATUS_ERROR)
  449. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  450. if (*mac->rx_status & PAS_STATUS_TIMER)
  451. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  452. netif_rx_schedule(dev);
  453. pci_write_config_dword(mac->iob_pdev,
  454. PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  455. return IRQ_HANDLED;
  456. }
  457. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  458. {
  459. struct net_device *dev = data;
  460. struct pasemi_mac *mac = netdev_priv(dev);
  461. unsigned int reg;
  462. if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
  463. return IRQ_NONE;
  464. pasemi_mac_clean_tx(mac);
  465. reg = PAS_IOB_DMA_TXCH_RESET_PINTC;
  466. if (*mac->tx_status & PAS_STATUS_SOFT)
  467. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  468. if (*mac->tx_status & PAS_STATUS_ERROR)
  469. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  470. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch),
  471. reg);
  472. return IRQ_HANDLED;
  473. }
  474. static void pasemi_adjust_link(struct net_device *dev)
  475. {
  476. struct pasemi_mac *mac = netdev_priv(dev);
  477. int msg;
  478. unsigned int flags;
  479. unsigned int new_flags;
  480. if (!mac->phydev->link) {
  481. /* If no link, MAC speed settings don't matter. Just report
  482. * link down and return.
  483. */
  484. if (mac->link && netif_msg_link(mac))
  485. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  486. netif_carrier_off(dev);
  487. mac->link = 0;
  488. return;
  489. } else
  490. netif_carrier_on(dev);
  491. pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
  492. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  493. PAS_MAC_CFG_PCFG_TSR_M);
  494. if (!mac->phydev->duplex)
  495. new_flags |= PAS_MAC_CFG_PCFG_HD;
  496. switch (mac->phydev->speed) {
  497. case 1000:
  498. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  499. PAS_MAC_CFG_PCFG_TSR_1G;
  500. break;
  501. case 100:
  502. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  503. PAS_MAC_CFG_PCFG_TSR_100M;
  504. break;
  505. case 10:
  506. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  507. PAS_MAC_CFG_PCFG_TSR_10M;
  508. break;
  509. default:
  510. printk("Unsupported speed %d\n", mac->phydev->speed);
  511. }
  512. /* Print on link or speed/duplex change */
  513. msg = mac->link != mac->phydev->link || flags != new_flags;
  514. mac->duplex = mac->phydev->duplex;
  515. mac->speed = mac->phydev->speed;
  516. mac->link = mac->phydev->link;
  517. if (new_flags != flags)
  518. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, new_flags);
  519. if (msg && netif_msg_link(mac))
  520. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  521. dev->name, mac->speed, mac->duplex ? "full" : "half");
  522. }
  523. static int pasemi_mac_phy_init(struct net_device *dev)
  524. {
  525. struct pasemi_mac *mac = netdev_priv(dev);
  526. struct device_node *dn, *phy_dn;
  527. struct phy_device *phydev;
  528. unsigned int phy_id;
  529. const phandle *ph;
  530. const unsigned int *prop;
  531. struct resource r;
  532. int ret;
  533. dn = pci_device_to_OF_node(mac->pdev);
  534. ph = of_get_property(dn, "phy-handle", NULL);
  535. if (!ph)
  536. return -ENODEV;
  537. phy_dn = of_find_node_by_phandle(*ph);
  538. prop = of_get_property(phy_dn, "reg", NULL);
  539. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  540. if (ret)
  541. goto err;
  542. phy_id = *prop;
  543. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  544. of_node_put(phy_dn);
  545. mac->link = 0;
  546. mac->speed = 0;
  547. mac->duplex = -1;
  548. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  549. if (IS_ERR(phydev)) {
  550. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  551. return PTR_ERR(phydev);
  552. }
  553. mac->phydev = phydev;
  554. return 0;
  555. err:
  556. of_node_put(phy_dn);
  557. return -ENODEV;
  558. }
  559. static int pasemi_mac_open(struct net_device *dev)
  560. {
  561. struct pasemi_mac *mac = netdev_priv(dev);
  562. int base_irq;
  563. unsigned int flags;
  564. int ret;
  565. /* enable rx section */
  566. pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD,
  567. PAS_DMA_COM_RXCMD_EN);
  568. /* enable tx section */
  569. pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD,
  570. PAS_DMA_COM_TXCMD_EN);
  571. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  572. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  573. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  574. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags);
  575. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  576. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  577. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  578. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
  579. PAS_IOB_DMA_RXCH_CFG_CNTTH(1));
  580. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
  581. PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
  582. /* Clear out any residual packet count state from firmware */
  583. pasemi_mac_restart_rx_intr(mac);
  584. pasemi_mac_restart_tx_intr(mac);
  585. /* 0xffffff is max value, about 16ms */
  586. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
  587. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  588. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
  589. ret = pasemi_mac_setup_rx_resources(dev);
  590. if (ret)
  591. goto out_rx_resources;
  592. ret = pasemi_mac_setup_tx_resources(dev);
  593. if (ret)
  594. goto out_tx_resources;
  595. pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL,
  596. PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
  597. PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
  598. /* enable rx if */
  599. pci_write_config_dword(mac->dma_pdev,
  600. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  601. PAS_DMA_RXINT_RCMDSTA_EN);
  602. /* enable rx channel */
  603. pci_write_config_dword(mac->dma_pdev,
  604. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  605. PAS_DMA_RXCHAN_CCMDSTA_EN |
  606. PAS_DMA_RXCHAN_CCMDSTA_DU);
  607. /* enable tx channel */
  608. pci_write_config_dword(mac->dma_pdev,
  609. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  610. PAS_DMA_TXCHAN_TCMDSTA_EN);
  611. pasemi_mac_replenish_rx_ring(dev);
  612. ret = pasemi_mac_phy_init(dev);
  613. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  614. * failed init due to -ENODEV.
  615. */
  616. if (ret && ret != -ENODEV)
  617. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  618. netif_start_queue(dev);
  619. netif_poll_enable(dev);
  620. /* Interrupts are a bit different for our DMA controller: While
  621. * it's got one a regular PCI device header, the interrupt there
  622. * is really the base of the range it's using. Each tx and rx
  623. * channel has it's own interrupt source.
  624. */
  625. base_irq = virq_to_hw(mac->dma_pdev->irq);
  626. mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
  627. mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
  628. ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  629. mac->tx->irq_name, dev);
  630. if (ret) {
  631. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  632. base_irq + mac->dma_txch, ret);
  633. goto out_tx_int;
  634. }
  635. ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  636. mac->rx->irq_name, dev);
  637. if (ret) {
  638. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  639. base_irq + 20 + mac->dma_rxch, ret);
  640. goto out_rx_int;
  641. }
  642. if (mac->phydev)
  643. phy_start(mac->phydev);
  644. return 0;
  645. out_rx_int:
  646. free_irq(mac->tx_irq, dev);
  647. out_tx_int:
  648. netif_poll_disable(dev);
  649. netif_stop_queue(dev);
  650. pasemi_mac_free_tx_resources(dev);
  651. out_tx_resources:
  652. pasemi_mac_free_rx_resources(dev);
  653. out_rx_resources:
  654. return ret;
  655. }
  656. #define MAX_RETRIES 5000
  657. static int pasemi_mac_close(struct net_device *dev)
  658. {
  659. struct pasemi_mac *mac = netdev_priv(dev);
  660. unsigned int stat;
  661. int retries;
  662. if (mac->phydev) {
  663. phy_stop(mac->phydev);
  664. phy_disconnect(mac->phydev);
  665. }
  666. netif_stop_queue(dev);
  667. /* Clean out any pending buffers */
  668. pasemi_mac_clean_tx(mac);
  669. pasemi_mac_clean_rx(mac, RX_RING_SIZE);
  670. /* Disable interface */
  671. pci_write_config_dword(mac->dma_pdev,
  672. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  673. PAS_DMA_TXCHAN_TCMDSTA_ST);
  674. pci_write_config_dword(mac->dma_pdev,
  675. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  676. PAS_DMA_RXINT_RCMDSTA_ST);
  677. pci_write_config_dword(mac->dma_pdev,
  678. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  679. PAS_DMA_RXCHAN_CCMDSTA_ST);
  680. for (retries = 0; retries < MAX_RETRIES; retries++) {
  681. pci_read_config_dword(mac->dma_pdev,
  682. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  683. &stat);
  684. if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  685. break;
  686. cond_resched();
  687. }
  688. if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  689. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  690. for (retries = 0; retries < MAX_RETRIES; retries++) {
  691. pci_read_config_dword(mac->dma_pdev,
  692. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  693. &stat);
  694. if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  695. break;
  696. cond_resched();
  697. }
  698. if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  699. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  700. for (retries = 0; retries < MAX_RETRIES; retries++) {
  701. pci_read_config_dword(mac->dma_pdev,
  702. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  703. &stat);
  704. if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
  705. break;
  706. cond_resched();
  707. }
  708. if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
  709. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  710. /* Then, disable the channel. This must be done separately from
  711. * stopping, since you can't disable when active.
  712. */
  713. pci_write_config_dword(mac->dma_pdev,
  714. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
  715. pci_write_config_dword(mac->dma_pdev,
  716. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
  717. pci_write_config_dword(mac->dma_pdev,
  718. PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  719. free_irq(mac->tx_irq, dev);
  720. free_irq(mac->rx_irq, dev);
  721. /* Free resources */
  722. pasemi_mac_free_rx_resources(dev);
  723. pasemi_mac_free_tx_resources(dev);
  724. return 0;
  725. }
  726. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  727. {
  728. struct pasemi_mac *mac = netdev_priv(dev);
  729. struct pasemi_mac_txring *txring;
  730. struct pasemi_mac_buffer *info;
  731. struct pas_dma_xct_descr *dp;
  732. u64 dflags;
  733. dma_addr_t map;
  734. int flags;
  735. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
  736. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  737. const unsigned char *nh = skb_network_header(skb);
  738. switch (ip_hdr(skb)->protocol) {
  739. case IPPROTO_TCP:
  740. dflags |= XCT_MACTX_CSUM_TCP;
  741. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  742. dflags |= XCT_MACTX_IPO(nh - skb->data);
  743. break;
  744. case IPPROTO_UDP:
  745. dflags |= XCT_MACTX_CSUM_UDP;
  746. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  747. dflags |= XCT_MACTX_IPO(nh - skb->data);
  748. break;
  749. }
  750. }
  751. map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
  752. if (dma_mapping_error(map))
  753. return NETDEV_TX_BUSY;
  754. txring = mac->tx;
  755. spin_lock_irqsave(&txring->lock, flags);
  756. if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) {
  757. spin_unlock_irqrestore(&txring->lock, flags);
  758. pasemi_mac_clean_tx(mac);
  759. spin_lock_irqsave(&txring->lock, flags);
  760. if (txring->next_to_clean - txring->next_to_use ==
  761. TX_RING_SIZE) {
  762. /* Still no room -- stop the queue and wait for tx
  763. * intr when there's room.
  764. */
  765. netif_stop_queue(dev);
  766. goto out_err;
  767. }
  768. }
  769. dp = &TX_DESC(mac, txring->next_to_use);
  770. info = &TX_DESC_INFO(mac, txring->next_to_use);
  771. dp->mactx = dflags | XCT_MACTX_LLEN(skb->len);
  772. dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map);
  773. info->dma = map;
  774. info->skb = skb;
  775. txring->next_to_use++;
  776. mac->stats.tx_packets++;
  777. mac->stats.tx_bytes += skb->len;
  778. spin_unlock_irqrestore(&txring->lock, flags);
  779. pci_write_config_dword(mac->dma_pdev,
  780. PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1);
  781. return NETDEV_TX_OK;
  782. out_err:
  783. spin_unlock_irqrestore(&txring->lock, flags);
  784. pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE);
  785. return NETDEV_TX_BUSY;
  786. }
  787. static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev)
  788. {
  789. struct pasemi_mac *mac = netdev_priv(dev);
  790. return &mac->stats;
  791. }
  792. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  793. {
  794. struct pasemi_mac *mac = netdev_priv(dev);
  795. unsigned int flags;
  796. pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
  797. /* Set promiscuous */
  798. if (dev->flags & IFF_PROMISC)
  799. flags |= PAS_MAC_CFG_PCFG_PR;
  800. else
  801. flags &= ~PAS_MAC_CFG_PCFG_PR;
  802. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
  803. }
  804. static int pasemi_mac_poll(struct net_device *dev, int *budget)
  805. {
  806. int pkts, limit = min(*budget, dev->quota);
  807. struct pasemi_mac *mac = netdev_priv(dev);
  808. pkts = pasemi_mac_clean_rx(mac, limit);
  809. dev->quota -= pkts;
  810. *budget -= pkts;
  811. if (pkts < limit) {
  812. /* all done, no more packets present */
  813. netif_rx_complete(dev);
  814. pasemi_mac_restart_rx_intr(mac);
  815. return 0;
  816. } else {
  817. /* used up our quantum, so reschedule */
  818. return 1;
  819. }
  820. }
  821. static int __devinit
  822. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  823. {
  824. static int index = 0;
  825. struct net_device *dev;
  826. struct pasemi_mac *mac;
  827. int err;
  828. err = pci_enable_device(pdev);
  829. if (err)
  830. return err;
  831. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  832. if (dev == NULL) {
  833. dev_err(&pdev->dev,
  834. "pasemi_mac: Could not allocate ethernet device.\n");
  835. err = -ENOMEM;
  836. goto out_disable_device;
  837. }
  838. SET_MODULE_OWNER(dev);
  839. pci_set_drvdata(pdev, dev);
  840. SET_NETDEV_DEV(dev, &pdev->dev);
  841. mac = netdev_priv(dev);
  842. mac->pdev = pdev;
  843. mac->netdev = dev;
  844. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  845. if (!mac->dma_pdev) {
  846. dev_err(&pdev->dev, "Can't find DMA Controller\n");
  847. err = -ENODEV;
  848. goto out_free_netdev;
  849. }
  850. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  851. if (!mac->iob_pdev) {
  852. dev_err(&pdev->dev, "Can't find I/O Bridge\n");
  853. err = -ENODEV;
  854. goto out_put_dma_pdev;
  855. }
  856. /* These should come out of the device tree eventually */
  857. mac->dma_txch = index;
  858. mac->dma_rxch = index;
  859. /* We probe GMAC before XAUI, but the DMA interfaces are
  860. * in XAUI, GMAC order.
  861. */
  862. if (index < 4)
  863. mac->dma_if = index + 2;
  864. else
  865. mac->dma_if = index - 4;
  866. index++;
  867. switch (pdev->device) {
  868. case 0xa005:
  869. mac->type = MAC_TYPE_GMAC;
  870. break;
  871. case 0xa006:
  872. mac->type = MAC_TYPE_XAUI;
  873. break;
  874. default:
  875. err = -ENODEV;
  876. goto out;
  877. }
  878. /* get mac addr from device tree */
  879. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  880. err = -ENODEV;
  881. goto out;
  882. }
  883. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  884. dev->open = pasemi_mac_open;
  885. dev->stop = pasemi_mac_close;
  886. dev->hard_start_xmit = pasemi_mac_start_tx;
  887. dev->get_stats = pasemi_mac_get_stats;
  888. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  889. dev->weight = 64;
  890. dev->poll = pasemi_mac_poll;
  891. dev->features = NETIF_F_HW_CSUM;
  892. /* The dma status structure is located in the I/O bridge, and
  893. * is cache coherent.
  894. */
  895. if (!dma_status)
  896. /* XXXOJN This should come from the device tree */
  897. dma_status = __ioremap(0xfd800000, 0x1000, 0);
  898. mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
  899. mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
  900. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  901. /* Enable most messages by default */
  902. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  903. err = register_netdev(dev);
  904. if (err) {
  905. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  906. err);
  907. goto out;
  908. } else
  909. printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
  910. "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  911. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  912. mac->dma_if, mac->dma_txch, mac->dma_rxch,
  913. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  914. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  915. return err;
  916. out:
  917. pci_dev_put(mac->iob_pdev);
  918. out_put_dma_pdev:
  919. pci_dev_put(mac->dma_pdev);
  920. out_free_netdev:
  921. free_netdev(dev);
  922. out_disable_device:
  923. pci_disable_device(pdev);
  924. return err;
  925. }
  926. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  927. {
  928. struct net_device *netdev = pci_get_drvdata(pdev);
  929. struct pasemi_mac *mac;
  930. if (!netdev)
  931. return;
  932. mac = netdev_priv(netdev);
  933. unregister_netdev(netdev);
  934. pci_disable_device(pdev);
  935. pci_dev_put(mac->dma_pdev);
  936. pci_dev_put(mac->iob_pdev);
  937. pci_set_drvdata(pdev, NULL);
  938. free_netdev(netdev);
  939. }
  940. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  941. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  942. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  943. };
  944. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  945. static struct pci_driver pasemi_mac_driver = {
  946. .name = "pasemi_mac",
  947. .id_table = pasemi_mac_pci_tbl,
  948. .probe = pasemi_mac_probe,
  949. .remove = __devexit_p(pasemi_mac_remove),
  950. };
  951. static void __exit pasemi_mac_cleanup_module(void)
  952. {
  953. pci_unregister_driver(&pasemi_mac_driver);
  954. __iounmap(dma_status);
  955. dma_status = NULL;
  956. }
  957. int pasemi_mac_init_module(void)
  958. {
  959. return pci_register_driver(&pasemi_mac_driver);
  960. }
  961. module_init(pasemi_mac_init_module);
  962. module_exit(pasemi_mac_cleanup_module);