ioapic.c 12 KB

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  1. /*
  2. * Copyright (C) 2001 MandrakeSoft S.A.
  3. * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  4. *
  5. * MandrakeSoft S.A.
  6. * 43, rue d'Aboukir
  7. * 75002 Paris - France
  8. * http://www.linux-mandrake.com/
  9. * http://www.mandrakesoft.com/
  10. *
  11. * This library is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU Lesser General Public
  13. * License as published by the Free Software Foundation; either
  14. * version 2 of the License, or (at your option) any later version.
  15. *
  16. * This library is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * Lesser General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU Lesser General Public
  22. * License along with this library; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. * Yunhong Jiang <yunhong.jiang@intel.com>
  26. * Yaozu (Eddie) Dong <eddie.dong@intel.com>
  27. * Based on Xen 3.1 code.
  28. */
  29. #include <linux/kvm_host.h>
  30. #include <linux/kvm.h>
  31. #include <linux/mm.h>
  32. #include <linux/highmem.h>
  33. #include <linux/smp.h>
  34. #include <linux/hrtimer.h>
  35. #include <linux/io.h>
  36. #include <linux/slab.h>
  37. #include <linux/export.h>
  38. #include <asm/processor.h>
  39. #include <asm/page.h>
  40. #include <asm/current.h>
  41. #include <trace/events/kvm.h>
  42. #include "ioapic.h"
  43. #include "lapic.h"
  44. #include "irq.h"
  45. #if 0
  46. #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  47. #else
  48. #define ioapic_debug(fmt, arg...)
  49. #endif
  50. static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  51. static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  52. unsigned long addr,
  53. unsigned long length)
  54. {
  55. unsigned long result = 0;
  56. switch (ioapic->ioregsel) {
  57. case IOAPIC_REG_VERSION:
  58. result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  59. | (IOAPIC_VERSION_ID & 0xff));
  60. break;
  61. case IOAPIC_REG_APIC_ID:
  62. case IOAPIC_REG_ARB_ID:
  63. result = ((ioapic->id & 0xf) << 24);
  64. break;
  65. default:
  66. {
  67. u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  68. u64 redir_content;
  69. if (redir_index < IOAPIC_NUM_PINS)
  70. redir_content =
  71. ioapic->redirtbl[redir_index].bits;
  72. else
  73. redir_content = ~0ULL;
  74. result = (ioapic->ioregsel & 0x1) ?
  75. (redir_content >> 32) & 0xffffffff :
  76. redir_content & 0xffffffff;
  77. break;
  78. }
  79. }
  80. return result;
  81. }
  82. static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  83. {
  84. union kvm_ioapic_redirect_entry *pent;
  85. int injected = -1;
  86. pent = &ioapic->redirtbl[idx];
  87. if (!pent->fields.mask) {
  88. injected = ioapic_deliver(ioapic, idx);
  89. if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  90. pent->fields.remote_irr = 1;
  91. }
  92. return injected;
  93. }
  94. static void update_handled_vectors(struct kvm_ioapic *ioapic)
  95. {
  96. DECLARE_BITMAP(handled_vectors, 256);
  97. int i;
  98. memset(handled_vectors, 0, sizeof(handled_vectors));
  99. for (i = 0; i < IOAPIC_NUM_PINS; ++i)
  100. __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
  101. memcpy(ioapic->handled_vectors, handled_vectors,
  102. sizeof(handled_vectors));
  103. smp_wmb();
  104. }
  105. void kvm_ioapic_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
  106. u64 *eoi_exit_bitmap)
  107. {
  108. struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
  109. union kvm_ioapic_redirect_entry *e;
  110. struct kvm_lapic_irq irqe;
  111. int index;
  112. spin_lock(&ioapic->lock);
  113. /* traverse ioapic entry to set eoi exit bitmap*/
  114. for (index = 0; index < IOAPIC_NUM_PINS; index++) {
  115. e = &ioapic->redirtbl[index];
  116. if (!e->fields.mask &&
  117. (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
  118. kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC,
  119. index))) {
  120. irqe.dest_id = e->fields.dest_id;
  121. irqe.vector = e->fields.vector;
  122. irqe.dest_mode = e->fields.dest_mode;
  123. irqe.delivery_mode = e->fields.delivery_mode << 8;
  124. kvm_calculate_eoi_exitmap(vcpu, &irqe, eoi_exit_bitmap);
  125. }
  126. }
  127. spin_unlock(&ioapic->lock);
  128. }
  129. EXPORT_SYMBOL_GPL(kvm_ioapic_calculate_eoi_exitmap);
  130. void kvm_ioapic_make_eoibitmap_request(struct kvm *kvm)
  131. {
  132. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  133. if (!kvm_apic_vid_enabled(kvm) || !ioapic)
  134. return;
  135. kvm_make_update_eoibitmap_request(kvm);
  136. }
  137. static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
  138. {
  139. unsigned index;
  140. bool mask_before, mask_after;
  141. union kvm_ioapic_redirect_entry *e;
  142. switch (ioapic->ioregsel) {
  143. case IOAPIC_REG_VERSION:
  144. /* Writes are ignored. */
  145. break;
  146. case IOAPIC_REG_APIC_ID:
  147. ioapic->id = (val >> 24) & 0xf;
  148. break;
  149. case IOAPIC_REG_ARB_ID:
  150. break;
  151. default:
  152. index = (ioapic->ioregsel - 0x10) >> 1;
  153. ioapic_debug("change redir index %x val %x\n", index, val);
  154. if (index >= IOAPIC_NUM_PINS)
  155. return;
  156. e = &ioapic->redirtbl[index];
  157. mask_before = e->fields.mask;
  158. if (ioapic->ioregsel & 1) {
  159. e->bits &= 0xffffffff;
  160. e->bits |= (u64) val << 32;
  161. } else {
  162. e->bits &= ~0xffffffffULL;
  163. e->bits |= (u32) val;
  164. e->fields.remote_irr = 0;
  165. }
  166. update_handled_vectors(ioapic);
  167. mask_after = e->fields.mask;
  168. if (mask_before != mask_after)
  169. kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
  170. if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
  171. && ioapic->irr & (1 << index))
  172. ioapic_service(ioapic, index);
  173. kvm_ioapic_make_eoibitmap_request(ioapic->kvm);
  174. break;
  175. }
  176. }
  177. static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
  178. {
  179. union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
  180. struct kvm_lapic_irq irqe;
  181. ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
  182. "vector=%x trig_mode=%x\n",
  183. entry->fields.dest_id, entry->fields.dest_mode,
  184. entry->fields.delivery_mode, entry->fields.vector,
  185. entry->fields.trig_mode);
  186. irqe.dest_id = entry->fields.dest_id;
  187. irqe.vector = entry->fields.vector;
  188. irqe.dest_mode = entry->fields.dest_mode;
  189. irqe.trig_mode = entry->fields.trig_mode;
  190. irqe.delivery_mode = entry->fields.delivery_mode << 8;
  191. irqe.level = 1;
  192. irqe.shorthand = 0;
  193. return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
  194. }
  195. int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
  196. int level)
  197. {
  198. u32 old_irr;
  199. u32 mask = 1 << irq;
  200. union kvm_ioapic_redirect_entry entry;
  201. int ret, irq_level;
  202. BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
  203. spin_lock(&ioapic->lock);
  204. old_irr = ioapic->irr;
  205. irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
  206. irq_source_id, level);
  207. entry = ioapic->redirtbl[irq];
  208. irq_level ^= entry.fields.polarity;
  209. if (!irq_level) {
  210. ioapic->irr &= ~mask;
  211. ret = 1;
  212. } else {
  213. int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
  214. ioapic->irr |= mask;
  215. if ((edge && old_irr != ioapic->irr) ||
  216. (!edge && !entry.fields.remote_irr))
  217. ret = ioapic_service(ioapic, irq);
  218. else
  219. ret = 0; /* report coalesced interrupt */
  220. }
  221. trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
  222. spin_unlock(&ioapic->lock);
  223. return ret;
  224. }
  225. void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
  226. {
  227. int i;
  228. spin_lock(&ioapic->lock);
  229. for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
  230. __clear_bit(irq_source_id, &ioapic->irq_states[i]);
  231. spin_unlock(&ioapic->lock);
  232. }
  233. static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
  234. int trigger_mode)
  235. {
  236. int i;
  237. for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  238. union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
  239. if (ent->fields.vector != vector)
  240. continue;
  241. /*
  242. * We are dropping lock while calling ack notifiers because ack
  243. * notifier callbacks for assigned devices call into IOAPIC
  244. * recursively. Since remote_irr is cleared only after call
  245. * to notifiers if the same vector will be delivered while lock
  246. * is dropped it will be put into irr and will be delivered
  247. * after ack notifier returns.
  248. */
  249. spin_unlock(&ioapic->lock);
  250. kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
  251. spin_lock(&ioapic->lock);
  252. if (trigger_mode != IOAPIC_LEVEL_TRIG)
  253. continue;
  254. ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
  255. ent->fields.remote_irr = 0;
  256. if (!ent->fields.mask && (ioapic->irr & (1 << i)))
  257. ioapic_service(ioapic, i);
  258. }
  259. }
  260. bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
  261. {
  262. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  263. smp_rmb();
  264. return test_bit(vector, ioapic->handled_vectors);
  265. }
  266. void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
  267. {
  268. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  269. spin_lock(&ioapic->lock);
  270. __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
  271. spin_unlock(&ioapic->lock);
  272. }
  273. static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
  274. {
  275. return container_of(dev, struct kvm_ioapic, dev);
  276. }
  277. static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
  278. {
  279. return ((addr >= ioapic->base_address &&
  280. (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
  281. }
  282. static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
  283. void *val)
  284. {
  285. struct kvm_ioapic *ioapic = to_ioapic(this);
  286. u32 result;
  287. if (!ioapic_in_range(ioapic, addr))
  288. return -EOPNOTSUPP;
  289. ioapic_debug("addr %lx\n", (unsigned long)addr);
  290. ASSERT(!(addr & 0xf)); /* check alignment */
  291. addr &= 0xff;
  292. spin_lock(&ioapic->lock);
  293. switch (addr) {
  294. case IOAPIC_REG_SELECT:
  295. result = ioapic->ioregsel;
  296. break;
  297. case IOAPIC_REG_WINDOW:
  298. result = ioapic_read_indirect(ioapic, addr, len);
  299. break;
  300. default:
  301. result = 0;
  302. break;
  303. }
  304. spin_unlock(&ioapic->lock);
  305. switch (len) {
  306. case 8:
  307. *(u64 *) val = result;
  308. break;
  309. case 1:
  310. case 2:
  311. case 4:
  312. memcpy(val, (char *)&result, len);
  313. break;
  314. default:
  315. printk(KERN_WARNING "ioapic: wrong length %d\n", len);
  316. }
  317. return 0;
  318. }
  319. static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
  320. const void *val)
  321. {
  322. struct kvm_ioapic *ioapic = to_ioapic(this);
  323. u32 data;
  324. if (!ioapic_in_range(ioapic, addr))
  325. return -EOPNOTSUPP;
  326. ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
  327. (void*)addr, len, val);
  328. ASSERT(!(addr & 0xf)); /* check alignment */
  329. switch (len) {
  330. case 8:
  331. case 4:
  332. data = *(u32 *) val;
  333. break;
  334. case 2:
  335. data = *(u16 *) val;
  336. break;
  337. case 1:
  338. data = *(u8 *) val;
  339. break;
  340. default:
  341. printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
  342. return 0;
  343. }
  344. addr &= 0xff;
  345. spin_lock(&ioapic->lock);
  346. switch (addr) {
  347. case IOAPIC_REG_SELECT:
  348. ioapic->ioregsel = data & 0xFF; /* 8-bit register */
  349. break;
  350. case IOAPIC_REG_WINDOW:
  351. ioapic_write_indirect(ioapic, data);
  352. break;
  353. #ifdef CONFIG_IA64
  354. case IOAPIC_REG_EOI:
  355. __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
  356. break;
  357. #endif
  358. default:
  359. break;
  360. }
  361. spin_unlock(&ioapic->lock);
  362. return 0;
  363. }
  364. void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
  365. {
  366. int i;
  367. for (i = 0; i < IOAPIC_NUM_PINS; i++)
  368. ioapic->redirtbl[i].fields.mask = 1;
  369. ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
  370. ioapic->ioregsel = 0;
  371. ioapic->irr = 0;
  372. ioapic->id = 0;
  373. update_handled_vectors(ioapic);
  374. }
  375. static const struct kvm_io_device_ops ioapic_mmio_ops = {
  376. .read = ioapic_mmio_read,
  377. .write = ioapic_mmio_write,
  378. };
  379. int kvm_ioapic_init(struct kvm *kvm)
  380. {
  381. struct kvm_ioapic *ioapic;
  382. int ret;
  383. ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
  384. if (!ioapic)
  385. return -ENOMEM;
  386. spin_lock_init(&ioapic->lock);
  387. kvm->arch.vioapic = ioapic;
  388. kvm_ioapic_reset(ioapic);
  389. kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
  390. ioapic->kvm = kvm;
  391. mutex_lock(&kvm->slots_lock);
  392. ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
  393. IOAPIC_MEM_LENGTH, &ioapic->dev);
  394. mutex_unlock(&kvm->slots_lock);
  395. if (ret < 0) {
  396. kvm->arch.vioapic = NULL;
  397. kfree(ioapic);
  398. }
  399. return ret;
  400. }
  401. void kvm_ioapic_destroy(struct kvm *kvm)
  402. {
  403. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  404. if (ioapic) {
  405. kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
  406. kvm->arch.vioapic = NULL;
  407. kfree(ioapic);
  408. }
  409. }
  410. int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
  411. {
  412. struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
  413. if (!ioapic)
  414. return -EINVAL;
  415. spin_lock(&ioapic->lock);
  416. memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
  417. spin_unlock(&ioapic->lock);
  418. return 0;
  419. }
  420. int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
  421. {
  422. struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
  423. if (!ioapic)
  424. return -EINVAL;
  425. spin_lock(&ioapic->lock);
  426. memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
  427. update_handled_vectors(ioapic);
  428. kvm_ioapic_make_eoibitmap_request(kvm);
  429. spin_unlock(&ioapic->lock);
  430. return 0;
  431. }