tegra30_i2s.c 14 KB

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  1. /*
  2. * tegra30_i2s.c - Tegra30 I2S driver
  3. *
  4. * Author: Stephen Warren <swarren@nvidia.com>
  5. * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Based on code copyright/by:
  8. *
  9. * Copyright (c) 2009-2010, NVIDIA Corporation.
  10. * Scott Peterson <speterson@nvidia.com>
  11. *
  12. * Copyright (C) 2010 Google, Inc.
  13. * Iliyan Malchev <malchev@google.com>
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms and conditions of the GNU General Public License,
  17. * version 2, as published by the Free Software Foundation.
  18. *
  19. * This program is distributed in the hope it will be useful, but WITHOUT
  20. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  22. * more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  26. */
  27. #include <linux/clk.h>
  28. #include <linux/device.h>
  29. #include <linux/io.h>
  30. #include <linux/module.h>
  31. #include <linux/of.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/regmap.h>
  35. #include <linux/slab.h>
  36. #include <sound/core.h>
  37. #include <sound/pcm.h>
  38. #include <sound/pcm_params.h>
  39. #include <sound/soc.h>
  40. #include "tegra30_ahub.h"
  41. #include "tegra30_i2s.h"
  42. #define DRV_NAME "tegra30-i2s"
  43. static int tegra30_i2s_runtime_suspend(struct device *dev)
  44. {
  45. struct tegra30_i2s *i2s = dev_get_drvdata(dev);
  46. regcache_cache_only(i2s->regmap, true);
  47. clk_disable_unprepare(i2s->clk_i2s);
  48. return 0;
  49. }
  50. static int tegra30_i2s_runtime_resume(struct device *dev)
  51. {
  52. struct tegra30_i2s *i2s = dev_get_drvdata(dev);
  53. int ret;
  54. ret = clk_prepare_enable(i2s->clk_i2s);
  55. if (ret) {
  56. dev_err(dev, "clk_enable failed: %d\n", ret);
  57. return ret;
  58. }
  59. regcache_cache_only(i2s->regmap, false);
  60. return 0;
  61. }
  62. static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
  63. struct snd_soc_dai *dai)
  64. {
  65. struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  66. int ret;
  67. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  68. ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
  69. &i2s->playback_dma_data.addr,
  70. &i2s->playback_dma_data.req_sel);
  71. i2s->playback_dma_data.wrap = 4;
  72. i2s->playback_dma_data.width = 32;
  73. tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
  74. i2s->playback_fifo_cif);
  75. } else {
  76. ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
  77. &i2s->capture_dma_data.addr,
  78. &i2s->capture_dma_data.req_sel);
  79. i2s->capture_dma_data.wrap = 4;
  80. i2s->capture_dma_data.width = 32;
  81. tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
  82. i2s->capture_i2s_cif);
  83. }
  84. return ret;
  85. }
  86. static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
  87. struct snd_soc_dai *dai)
  88. {
  89. struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  90. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  91. tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
  92. tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
  93. } else {
  94. tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
  95. tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
  96. }
  97. }
  98. static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
  99. unsigned int fmt)
  100. {
  101. struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  102. unsigned int mask, val;
  103. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  104. case SND_SOC_DAIFMT_NB_NF:
  105. break;
  106. default:
  107. return -EINVAL;
  108. }
  109. mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
  110. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  111. case SND_SOC_DAIFMT_CBS_CFS:
  112. val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
  113. break;
  114. case SND_SOC_DAIFMT_CBM_CFM:
  115. break;
  116. default:
  117. return -EINVAL;
  118. }
  119. mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
  120. TEGRA30_I2S_CTRL_LRCK_MASK;
  121. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  122. case SND_SOC_DAIFMT_DSP_A:
  123. val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
  124. val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
  125. break;
  126. case SND_SOC_DAIFMT_DSP_B:
  127. val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
  128. val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
  129. break;
  130. case SND_SOC_DAIFMT_I2S:
  131. val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
  132. val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
  133. break;
  134. case SND_SOC_DAIFMT_RIGHT_J:
  135. val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
  136. val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
  137. break;
  138. case SND_SOC_DAIFMT_LEFT_J:
  139. val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
  140. val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
  141. break;
  142. default:
  143. return -EINVAL;
  144. }
  145. pm_runtime_get_sync(dai->dev);
  146. regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
  147. pm_runtime_put(dai->dev);
  148. return 0;
  149. }
  150. static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
  151. struct snd_pcm_hw_params *params,
  152. struct snd_soc_dai *dai)
  153. {
  154. struct device *dev = dai->dev;
  155. struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  156. unsigned int mask, val, reg;
  157. int ret, sample_size, srate, i2sclock, bitcnt;
  158. if (params_channels(params) != 2)
  159. return -EINVAL;
  160. mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
  161. switch (params_format(params)) {
  162. case SNDRV_PCM_FORMAT_S16_LE:
  163. val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
  164. sample_size = 16;
  165. break;
  166. default:
  167. return -EINVAL;
  168. }
  169. regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
  170. srate = params_rate(params);
  171. /* Final "* 2" required by Tegra hardware */
  172. i2sclock = srate * params_channels(params) * sample_size * 2;
  173. bitcnt = (i2sclock / (2 * srate)) - 1;
  174. if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
  175. return -EINVAL;
  176. ret = clk_set_rate(i2s->clk_i2s, i2sclock);
  177. if (ret) {
  178. dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
  179. return ret;
  180. }
  181. val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
  182. if (i2sclock % (2 * srate))
  183. val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
  184. regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
  185. val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
  186. (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
  187. (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
  188. TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
  189. TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
  190. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  191. val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
  192. reg = TEGRA30_I2S_CIF_RX_CTRL;
  193. } else {
  194. val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
  195. reg = TEGRA30_I2S_CIF_RX_CTRL;
  196. }
  197. regmap_write(i2s->regmap, reg, val);
  198. val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
  199. (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
  200. regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
  201. return 0;
  202. }
  203. static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
  204. {
  205. tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
  206. regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
  207. TEGRA30_I2S_CTRL_XFER_EN_TX,
  208. TEGRA30_I2S_CTRL_XFER_EN_TX);
  209. }
  210. static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
  211. {
  212. tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
  213. regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
  214. TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
  215. }
  216. static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
  217. {
  218. tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
  219. regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
  220. TEGRA30_I2S_CTRL_XFER_EN_RX,
  221. TEGRA30_I2S_CTRL_XFER_EN_RX);
  222. }
  223. static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
  224. {
  225. tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
  226. regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
  227. TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
  228. }
  229. static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  230. struct snd_soc_dai *dai)
  231. {
  232. struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  233. switch (cmd) {
  234. case SNDRV_PCM_TRIGGER_START:
  235. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  236. case SNDRV_PCM_TRIGGER_RESUME:
  237. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  238. tegra30_i2s_start_playback(i2s);
  239. else
  240. tegra30_i2s_start_capture(i2s);
  241. break;
  242. case SNDRV_PCM_TRIGGER_STOP:
  243. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  244. case SNDRV_PCM_TRIGGER_SUSPEND:
  245. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  246. tegra30_i2s_stop_playback(i2s);
  247. else
  248. tegra30_i2s_stop_capture(i2s);
  249. break;
  250. default:
  251. return -EINVAL;
  252. }
  253. return 0;
  254. }
  255. static int tegra30_i2s_probe(struct snd_soc_dai *dai)
  256. {
  257. struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  258. dai->capture_dma_data = &i2s->capture_dma_data;
  259. dai->playback_dma_data = &i2s->playback_dma_data;
  260. return 0;
  261. }
  262. static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
  263. .startup = tegra30_i2s_startup,
  264. .shutdown = tegra30_i2s_shutdown,
  265. .set_fmt = tegra30_i2s_set_fmt,
  266. .hw_params = tegra30_i2s_hw_params,
  267. .trigger = tegra30_i2s_trigger,
  268. };
  269. static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
  270. .probe = tegra30_i2s_probe,
  271. .playback = {
  272. .stream_name = "Playback",
  273. .channels_min = 2,
  274. .channels_max = 2,
  275. .rates = SNDRV_PCM_RATE_8000_96000,
  276. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  277. },
  278. .capture = {
  279. .stream_name = "Capture",
  280. .channels_min = 2,
  281. .channels_max = 2,
  282. .rates = SNDRV_PCM_RATE_8000_96000,
  283. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  284. },
  285. .ops = &tegra30_i2s_dai_ops,
  286. .symmetric_rates = 1,
  287. };
  288. static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
  289. {
  290. switch (reg) {
  291. case TEGRA30_I2S_CTRL:
  292. case TEGRA30_I2S_TIMING:
  293. case TEGRA30_I2S_OFFSET:
  294. case TEGRA30_I2S_CH_CTRL:
  295. case TEGRA30_I2S_SLOT_CTRL:
  296. case TEGRA30_I2S_CIF_RX_CTRL:
  297. case TEGRA30_I2S_CIF_TX_CTRL:
  298. case TEGRA30_I2S_FLOWCTL:
  299. case TEGRA30_I2S_TX_STEP:
  300. case TEGRA30_I2S_FLOW_STATUS:
  301. case TEGRA30_I2S_FLOW_TOTAL:
  302. case TEGRA30_I2S_FLOW_OVER:
  303. case TEGRA30_I2S_FLOW_UNDER:
  304. case TEGRA30_I2S_LCOEF_1_4_0:
  305. case TEGRA30_I2S_LCOEF_1_4_1:
  306. case TEGRA30_I2S_LCOEF_1_4_2:
  307. case TEGRA30_I2S_LCOEF_1_4_3:
  308. case TEGRA30_I2S_LCOEF_1_4_4:
  309. case TEGRA30_I2S_LCOEF_1_4_5:
  310. case TEGRA30_I2S_LCOEF_2_4_0:
  311. case TEGRA30_I2S_LCOEF_2_4_1:
  312. case TEGRA30_I2S_LCOEF_2_4_2:
  313. return true;
  314. default:
  315. return false;
  316. };
  317. }
  318. static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
  319. {
  320. switch (reg) {
  321. case TEGRA30_I2S_FLOW_STATUS:
  322. case TEGRA30_I2S_FLOW_TOTAL:
  323. case TEGRA30_I2S_FLOW_OVER:
  324. case TEGRA30_I2S_FLOW_UNDER:
  325. return true;
  326. default:
  327. return false;
  328. };
  329. }
  330. static const struct regmap_config tegra30_i2s_regmap_config = {
  331. .reg_bits = 32,
  332. .reg_stride = 4,
  333. .val_bits = 32,
  334. .max_register = TEGRA30_I2S_LCOEF_2_4_2,
  335. .writeable_reg = tegra30_i2s_wr_rd_reg,
  336. .readable_reg = tegra30_i2s_wr_rd_reg,
  337. .volatile_reg = tegra30_i2s_volatile_reg,
  338. .cache_type = REGCACHE_RBTREE,
  339. };
  340. static int tegra30_i2s_platform_probe(struct platform_device *pdev)
  341. {
  342. struct tegra30_i2s *i2s;
  343. u32 cif_ids[2];
  344. struct resource *mem, *memregion;
  345. void __iomem *regs;
  346. int ret;
  347. i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
  348. if (!i2s) {
  349. dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
  350. ret = -ENOMEM;
  351. goto err;
  352. }
  353. dev_set_drvdata(&pdev->dev, i2s);
  354. i2s->dai = tegra30_i2s_dai_template;
  355. i2s->dai.name = dev_name(&pdev->dev);
  356. ret = of_property_read_u32_array(pdev->dev.of_node,
  357. "nvidia,ahub-cif-ids", cif_ids,
  358. ARRAY_SIZE(cif_ids));
  359. if (ret < 0)
  360. goto err;
  361. i2s->playback_i2s_cif = cif_ids[0];
  362. i2s->capture_i2s_cif = cif_ids[1];
  363. i2s->clk_i2s = clk_get(&pdev->dev, NULL);
  364. if (IS_ERR(i2s->clk_i2s)) {
  365. dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
  366. ret = PTR_ERR(i2s->clk_i2s);
  367. goto err;
  368. }
  369. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  370. if (!mem) {
  371. dev_err(&pdev->dev, "No memory resource\n");
  372. ret = -ENODEV;
  373. goto err_clk_put;
  374. }
  375. memregion = devm_request_mem_region(&pdev->dev, mem->start,
  376. resource_size(mem), DRV_NAME);
  377. if (!memregion) {
  378. dev_err(&pdev->dev, "Memory region already claimed\n");
  379. ret = -EBUSY;
  380. goto err_clk_put;
  381. }
  382. regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
  383. if (!regs) {
  384. dev_err(&pdev->dev, "ioremap failed\n");
  385. ret = -ENOMEM;
  386. goto err_clk_put;
  387. }
  388. i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
  389. &tegra30_i2s_regmap_config);
  390. if (IS_ERR(i2s->regmap)) {
  391. dev_err(&pdev->dev, "regmap init failed\n");
  392. ret = PTR_ERR(i2s->regmap);
  393. goto err_clk_put;
  394. }
  395. regcache_cache_only(i2s->regmap, true);
  396. pm_runtime_enable(&pdev->dev);
  397. if (!pm_runtime_enabled(&pdev->dev)) {
  398. ret = tegra30_i2s_runtime_resume(&pdev->dev);
  399. if (ret)
  400. goto err_pm_disable;
  401. }
  402. ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
  403. if (ret) {
  404. dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
  405. ret = -ENOMEM;
  406. goto err_suspend;
  407. }
  408. ret = tegra_pcm_platform_register(&pdev->dev);
  409. if (ret) {
  410. dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
  411. goto err_unregister_dai;
  412. }
  413. return 0;
  414. err_unregister_dai:
  415. snd_soc_unregister_dai(&pdev->dev);
  416. err_suspend:
  417. if (!pm_runtime_status_suspended(&pdev->dev))
  418. tegra30_i2s_runtime_suspend(&pdev->dev);
  419. err_pm_disable:
  420. pm_runtime_disable(&pdev->dev);
  421. err_clk_put:
  422. clk_put(i2s->clk_i2s);
  423. err:
  424. return ret;
  425. }
  426. static int tegra30_i2s_platform_remove(struct platform_device *pdev)
  427. {
  428. struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
  429. pm_runtime_disable(&pdev->dev);
  430. if (!pm_runtime_status_suspended(&pdev->dev))
  431. tegra30_i2s_runtime_suspend(&pdev->dev);
  432. tegra_pcm_platform_unregister(&pdev->dev);
  433. snd_soc_unregister_dai(&pdev->dev);
  434. clk_put(i2s->clk_i2s);
  435. return 0;
  436. }
  437. static const struct of_device_id tegra30_i2s_of_match[] = {
  438. { .compatible = "nvidia,tegra30-i2s", },
  439. {},
  440. };
  441. static const struct dev_pm_ops tegra30_i2s_pm_ops = {
  442. SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
  443. tegra30_i2s_runtime_resume, NULL)
  444. };
  445. static struct platform_driver tegra30_i2s_driver = {
  446. .driver = {
  447. .name = DRV_NAME,
  448. .owner = THIS_MODULE,
  449. .of_match_table = tegra30_i2s_of_match,
  450. .pm = &tegra30_i2s_pm_ops,
  451. },
  452. .probe = tegra30_i2s_platform_probe,
  453. .remove = tegra30_i2s_platform_remove,
  454. };
  455. module_platform_driver(tegra30_i2s_driver);
  456. MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
  457. MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
  458. MODULE_LICENSE("GPL");
  459. MODULE_ALIAS("platform:" DRV_NAME);
  460. MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);