tegra20_spdif.c 9.6 KB

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  1. /*
  2. * tegra20_spdif.c - Tegra20 SPDIF driver
  3. *
  4. * Author: Stephen Warren <swarren@nvidia.com>
  5. * Copyright (C) 2011-2012 - NVIDIA, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19. * 02110-1301 USA
  20. *
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/device.h>
  24. #include <linux/io.h>
  25. #include <linux/module.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/regmap.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include "tegra20_spdif.h"
  35. #define DRV_NAME "tegra20-spdif"
  36. static int tegra20_spdif_runtime_suspend(struct device *dev)
  37. {
  38. struct tegra20_spdif *spdif = dev_get_drvdata(dev);
  39. clk_disable_unprepare(spdif->clk_spdif_out);
  40. return 0;
  41. }
  42. static int tegra20_spdif_runtime_resume(struct device *dev)
  43. {
  44. struct tegra20_spdif *spdif = dev_get_drvdata(dev);
  45. int ret;
  46. ret = clk_prepare_enable(spdif->clk_spdif_out);
  47. if (ret) {
  48. dev_err(dev, "clk_enable failed: %d\n", ret);
  49. return ret;
  50. }
  51. return 0;
  52. }
  53. static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
  54. struct snd_pcm_hw_params *params,
  55. struct snd_soc_dai *dai)
  56. {
  57. struct device *dev = dai->dev;
  58. struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
  59. unsigned int mask, val;
  60. int ret, spdifclock;
  61. mask = TEGRA20_SPDIF_CTRL_PACK |
  62. TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
  63. switch (params_format(params)) {
  64. case SNDRV_PCM_FORMAT_S16_LE:
  65. val = TEGRA20_SPDIF_CTRL_PACK |
  66. TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
  67. break;
  68. default:
  69. return -EINVAL;
  70. }
  71. regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
  72. switch (params_rate(params)) {
  73. case 32000:
  74. spdifclock = 4096000;
  75. break;
  76. case 44100:
  77. spdifclock = 5644800;
  78. break;
  79. case 48000:
  80. spdifclock = 6144000;
  81. break;
  82. case 88200:
  83. spdifclock = 11289600;
  84. break;
  85. case 96000:
  86. spdifclock = 12288000;
  87. break;
  88. case 176400:
  89. spdifclock = 22579200;
  90. break;
  91. case 192000:
  92. spdifclock = 24576000;
  93. break;
  94. default:
  95. return -EINVAL;
  96. }
  97. ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
  98. if (ret) {
  99. dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
  100. return ret;
  101. }
  102. return 0;
  103. }
  104. static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
  105. {
  106. regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
  107. TEGRA20_SPDIF_CTRL_TX_EN,
  108. TEGRA20_SPDIF_CTRL_TX_EN);
  109. }
  110. static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
  111. {
  112. regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
  113. TEGRA20_SPDIF_CTRL_TX_EN, 0);
  114. }
  115. static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
  116. struct snd_soc_dai *dai)
  117. {
  118. struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
  119. switch (cmd) {
  120. case SNDRV_PCM_TRIGGER_START:
  121. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  122. case SNDRV_PCM_TRIGGER_RESUME:
  123. tegra20_spdif_start_playback(spdif);
  124. break;
  125. case SNDRV_PCM_TRIGGER_STOP:
  126. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  127. case SNDRV_PCM_TRIGGER_SUSPEND:
  128. tegra20_spdif_stop_playback(spdif);
  129. break;
  130. default:
  131. return -EINVAL;
  132. }
  133. return 0;
  134. }
  135. static int tegra20_spdif_probe(struct snd_soc_dai *dai)
  136. {
  137. struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
  138. dai->capture_dma_data = NULL;
  139. dai->playback_dma_data = &spdif->playback_dma_data;
  140. return 0;
  141. }
  142. static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
  143. .hw_params = tegra20_spdif_hw_params,
  144. .trigger = tegra20_spdif_trigger,
  145. };
  146. static struct snd_soc_dai_driver tegra20_spdif_dai = {
  147. .name = DRV_NAME,
  148. .probe = tegra20_spdif_probe,
  149. .playback = {
  150. .stream_name = "Playback",
  151. .channels_min = 2,
  152. .channels_max = 2,
  153. .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
  154. SNDRV_PCM_RATE_48000,
  155. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  156. },
  157. .ops = &tegra20_spdif_dai_ops,
  158. };
  159. static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
  160. {
  161. switch (reg) {
  162. case TEGRA20_SPDIF_CTRL:
  163. case TEGRA20_SPDIF_STATUS:
  164. case TEGRA20_SPDIF_STROBE_CTRL:
  165. case TEGRA20_SPDIF_DATA_FIFO_CSR:
  166. case TEGRA20_SPDIF_DATA_OUT:
  167. case TEGRA20_SPDIF_DATA_IN:
  168. case TEGRA20_SPDIF_CH_STA_RX_A:
  169. case TEGRA20_SPDIF_CH_STA_RX_B:
  170. case TEGRA20_SPDIF_CH_STA_RX_C:
  171. case TEGRA20_SPDIF_CH_STA_RX_D:
  172. case TEGRA20_SPDIF_CH_STA_RX_E:
  173. case TEGRA20_SPDIF_CH_STA_RX_F:
  174. case TEGRA20_SPDIF_CH_STA_TX_A:
  175. case TEGRA20_SPDIF_CH_STA_TX_B:
  176. case TEGRA20_SPDIF_CH_STA_TX_C:
  177. case TEGRA20_SPDIF_CH_STA_TX_D:
  178. case TEGRA20_SPDIF_CH_STA_TX_E:
  179. case TEGRA20_SPDIF_CH_STA_TX_F:
  180. case TEGRA20_SPDIF_USR_STA_RX_A:
  181. case TEGRA20_SPDIF_USR_DAT_TX_A:
  182. return true;
  183. default:
  184. return false;
  185. };
  186. }
  187. static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
  188. {
  189. switch (reg) {
  190. case TEGRA20_SPDIF_STATUS:
  191. case TEGRA20_SPDIF_DATA_FIFO_CSR:
  192. case TEGRA20_SPDIF_DATA_OUT:
  193. case TEGRA20_SPDIF_DATA_IN:
  194. case TEGRA20_SPDIF_CH_STA_RX_A:
  195. case TEGRA20_SPDIF_CH_STA_RX_B:
  196. case TEGRA20_SPDIF_CH_STA_RX_C:
  197. case TEGRA20_SPDIF_CH_STA_RX_D:
  198. case TEGRA20_SPDIF_CH_STA_RX_E:
  199. case TEGRA20_SPDIF_CH_STA_RX_F:
  200. case TEGRA20_SPDIF_USR_STA_RX_A:
  201. case TEGRA20_SPDIF_USR_DAT_TX_A:
  202. return true;
  203. default:
  204. return false;
  205. };
  206. }
  207. static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
  208. {
  209. switch (reg) {
  210. case TEGRA20_SPDIF_DATA_OUT:
  211. case TEGRA20_SPDIF_DATA_IN:
  212. case TEGRA20_SPDIF_USR_STA_RX_A:
  213. case TEGRA20_SPDIF_USR_DAT_TX_A:
  214. return true;
  215. default:
  216. return false;
  217. };
  218. }
  219. static const struct regmap_config tegra20_spdif_regmap_config = {
  220. .reg_bits = 32,
  221. .reg_stride = 4,
  222. .val_bits = 32,
  223. .max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
  224. .writeable_reg = tegra20_spdif_wr_rd_reg,
  225. .readable_reg = tegra20_spdif_wr_rd_reg,
  226. .volatile_reg = tegra20_spdif_volatile_reg,
  227. .precious_reg = tegra20_spdif_precious_reg,
  228. .cache_type = REGCACHE_RBTREE,
  229. };
  230. static int tegra20_spdif_platform_probe(struct platform_device *pdev)
  231. {
  232. struct tegra20_spdif *spdif;
  233. struct resource *mem, *memregion, *dmareq;
  234. void __iomem *regs;
  235. int ret;
  236. spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
  237. GFP_KERNEL);
  238. if (!spdif) {
  239. dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n");
  240. ret = -ENOMEM;
  241. goto err;
  242. }
  243. dev_set_drvdata(&pdev->dev, spdif);
  244. spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
  245. if (IS_ERR(spdif->clk_spdif_out)) {
  246. pr_err("Can't retrieve spdif clock\n");
  247. ret = PTR_ERR(spdif->clk_spdif_out);
  248. goto err;
  249. }
  250. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  251. if (!mem) {
  252. dev_err(&pdev->dev, "No memory resource\n");
  253. ret = -ENODEV;
  254. goto err_clk_put;
  255. }
  256. dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  257. if (!dmareq) {
  258. dev_err(&pdev->dev, "No DMA resource\n");
  259. ret = -ENODEV;
  260. goto err_clk_put;
  261. }
  262. memregion = devm_request_mem_region(&pdev->dev, mem->start,
  263. resource_size(mem), DRV_NAME);
  264. if (!memregion) {
  265. dev_err(&pdev->dev, "Memory region already claimed\n");
  266. ret = -EBUSY;
  267. goto err_clk_put;
  268. }
  269. regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
  270. if (!regs) {
  271. dev_err(&pdev->dev, "ioremap failed\n");
  272. ret = -ENOMEM;
  273. goto err_clk_put;
  274. }
  275. spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
  276. &tegra20_spdif_regmap_config);
  277. if (IS_ERR(spdif->regmap)) {
  278. dev_err(&pdev->dev, "regmap init failed\n");
  279. ret = PTR_ERR(spdif->regmap);
  280. goto err_clk_put;
  281. }
  282. spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
  283. spdif->playback_dma_data.wrap = 4;
  284. spdif->playback_dma_data.width = 32;
  285. spdif->playback_dma_data.req_sel = dmareq->start;
  286. pm_runtime_enable(&pdev->dev);
  287. if (!pm_runtime_enabled(&pdev->dev)) {
  288. ret = tegra20_spdif_runtime_resume(&pdev->dev);
  289. if (ret)
  290. goto err_pm_disable;
  291. }
  292. ret = snd_soc_register_dai(&pdev->dev, &tegra20_spdif_dai);
  293. if (ret) {
  294. dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
  295. ret = -ENOMEM;
  296. goto err_suspend;
  297. }
  298. ret = tegra_pcm_platform_register(&pdev->dev);
  299. if (ret) {
  300. dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
  301. goto err_unregister_dai;
  302. }
  303. return 0;
  304. err_unregister_dai:
  305. snd_soc_unregister_dai(&pdev->dev);
  306. err_suspend:
  307. if (!pm_runtime_status_suspended(&pdev->dev))
  308. tegra20_spdif_runtime_suspend(&pdev->dev);
  309. err_pm_disable:
  310. pm_runtime_disable(&pdev->dev);
  311. err_clk_put:
  312. clk_put(spdif->clk_spdif_out);
  313. err:
  314. return ret;
  315. }
  316. static int tegra20_spdif_platform_remove(struct platform_device *pdev)
  317. {
  318. struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev);
  319. pm_runtime_disable(&pdev->dev);
  320. if (!pm_runtime_status_suspended(&pdev->dev))
  321. tegra20_spdif_runtime_suspend(&pdev->dev);
  322. tegra_pcm_platform_unregister(&pdev->dev);
  323. snd_soc_unregister_dai(&pdev->dev);
  324. clk_put(spdif->clk_spdif_out);
  325. return 0;
  326. }
  327. static const struct dev_pm_ops tegra20_spdif_pm_ops = {
  328. SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
  329. tegra20_spdif_runtime_resume, NULL)
  330. };
  331. static struct platform_driver tegra20_spdif_driver = {
  332. .driver = {
  333. .name = DRV_NAME,
  334. .owner = THIS_MODULE,
  335. .pm = &tegra20_spdif_pm_ops,
  336. },
  337. .probe = tegra20_spdif_platform_probe,
  338. .remove = tegra20_spdif_platform_remove,
  339. };
  340. module_platform_driver(tegra20_spdif_driver);
  341. MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
  342. MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
  343. MODULE_LICENSE("GPL");
  344. MODULE_ALIAS("platform:" DRV_NAME);