omap-mcpdm.c 14 KB

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  1. /*
  2. * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
  3. *
  4. * Copyright (C) 2009 - 2011 Texas Instruments
  5. *
  6. * Author: Misael Lopez Cruz <misael.lopez@ti.com>
  7. * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
  8. * Margarita Olaya <magi.olaya@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/err.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include <linux/slab.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/of_device.h>
  36. #include <sound/core.h>
  37. #include <sound/pcm.h>
  38. #include <sound/pcm_params.h>
  39. #include <sound/soc.h>
  40. #include "omap-mcpdm.h"
  41. #include "omap-pcm.h"
  42. #define OMAP44XX_MCPDM_L3_BASE 0x49032000
  43. struct omap_mcpdm {
  44. struct device *dev;
  45. unsigned long phys_base;
  46. void __iomem *io_base;
  47. int irq;
  48. struct mutex mutex;
  49. /* channel data */
  50. u32 dn_channels;
  51. u32 up_channels;
  52. /* McPDM FIFO thresholds */
  53. u32 dn_threshold;
  54. u32 up_threshold;
  55. /* McPDM dn offsets for rx1, and 2 channels */
  56. u32 dn_rx_offset;
  57. };
  58. /*
  59. * Stream DMA parameters
  60. */
  61. static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
  62. {
  63. .name = "Audio playback",
  64. },
  65. {
  66. .name = "Audio capture",
  67. },
  68. };
  69. static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  70. {
  71. __raw_writel(val, mcpdm->io_base + reg);
  72. }
  73. static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  74. {
  75. return __raw_readl(mcpdm->io_base + reg);
  76. }
  77. #ifdef DEBUG
  78. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  79. {
  80. dev_dbg(mcpdm->dev, "***********************\n");
  81. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  82. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  83. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  84. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  85. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  86. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  87. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  88. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
  89. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  90. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
  91. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  92. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
  93. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  94. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
  95. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  96. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
  97. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  98. omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
  99. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  100. omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
  101. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  102. omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
  103. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  104. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
  105. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  106. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
  107. dev_dbg(mcpdm->dev, "***********************\n");
  108. }
  109. #else
  110. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
  111. #endif
  112. /*
  113. * Enables the transfer through the PDM interface to/from the Phoenix
  114. * codec by enabling the corresponding UP or DN channels.
  115. */
  116. static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
  117. {
  118. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  119. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  120. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  121. ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
  122. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  123. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  124. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  125. }
  126. /*
  127. * Disables the transfer through the PDM interface to/from the Phoenix
  128. * codec by disabling the corresponding UP or DN channels.
  129. */
  130. static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
  131. {
  132. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  133. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  134. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  135. ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
  136. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  137. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  138. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  139. }
  140. /*
  141. * Is the physical McPDM interface active.
  142. */
  143. static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
  144. {
  145. return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
  146. (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
  147. }
  148. /*
  149. * Configures McPDM uplink, and downlink for audio.
  150. * This function should be called before omap_mcpdm_start.
  151. */
  152. static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
  153. {
  154. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
  155. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
  156. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  157. /* Enable DN RX1/2 offset cancellation feature, if configured */
  158. if (mcpdm->dn_rx_offset) {
  159. u32 dn_offset = mcpdm->dn_rx_offset;
  160. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  161. dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
  162. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  163. }
  164. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
  165. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
  166. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
  167. MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
  168. }
  169. /*
  170. * Cleans McPDM uplink, and downlink configuration.
  171. * This function should be called when the stream is closed.
  172. */
  173. static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
  174. {
  175. /* Disable irq request generation for downlink */
  176. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  177. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
  178. /* Disable DMA request generation for downlink */
  179. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
  180. /* Disable irq request generation for uplink */
  181. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  182. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  183. /* Disable DMA request generation for uplink */
  184. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
  185. /* Disable RX1/2 offset cancellation */
  186. if (mcpdm->dn_rx_offset)
  187. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
  188. }
  189. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  190. {
  191. struct omap_mcpdm *mcpdm = dev_id;
  192. int irq_status;
  193. irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
  194. /* Acknowledge irq event */
  195. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
  196. if (irq_status & MCPDM_DN_IRQ_FULL)
  197. dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
  198. if (irq_status & MCPDM_DN_IRQ_EMPTY)
  199. dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
  200. if (irq_status & MCPDM_DN_IRQ)
  201. dev_dbg(mcpdm->dev, "DN (playback) write request\n");
  202. if (irq_status & MCPDM_UP_IRQ_FULL)
  203. dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
  204. if (irq_status & MCPDM_UP_IRQ_EMPTY)
  205. dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
  206. if (irq_status & MCPDM_UP_IRQ)
  207. dev_dbg(mcpdm->dev, "UP (capture) write request\n");
  208. return IRQ_HANDLED;
  209. }
  210. static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
  211. struct snd_soc_dai *dai)
  212. {
  213. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  214. mutex_lock(&mcpdm->mutex);
  215. if (!dai->active) {
  216. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  217. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
  218. omap_mcpdm_open_streams(mcpdm);
  219. }
  220. mutex_unlock(&mcpdm->mutex);
  221. snd_soc_dai_set_dma_data(dai, substream,
  222. &omap_mcpdm_dai_dma_params[substream->stream]);
  223. return 0;
  224. }
  225. static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
  226. struct snd_soc_dai *dai)
  227. {
  228. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  229. mutex_lock(&mcpdm->mutex);
  230. if (!dai->active) {
  231. if (omap_mcpdm_active(mcpdm)) {
  232. omap_mcpdm_stop(mcpdm);
  233. omap_mcpdm_close_streams(mcpdm);
  234. }
  235. }
  236. mutex_unlock(&mcpdm->mutex);
  237. }
  238. static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
  239. struct snd_pcm_hw_params *params,
  240. struct snd_soc_dai *dai)
  241. {
  242. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  243. int stream = substream->stream;
  244. struct omap_pcm_dma_data *dma_data;
  245. int channels;
  246. int link_mask = 0;
  247. channels = params_channels(params);
  248. switch (channels) {
  249. case 5:
  250. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  251. /* up to 3 channels for capture */
  252. return -EINVAL;
  253. link_mask |= 1 << 4;
  254. case 4:
  255. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  256. /* up to 3 channels for capture */
  257. return -EINVAL;
  258. link_mask |= 1 << 3;
  259. case 3:
  260. link_mask |= 1 << 2;
  261. case 2:
  262. link_mask |= 1 << 1;
  263. case 1:
  264. link_mask |= 1 << 0;
  265. break;
  266. default:
  267. /* unsupported number of channels */
  268. return -EINVAL;
  269. }
  270. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  271. /* Configure McPDM channels, and DMA packet size */
  272. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  273. mcpdm->dn_channels = link_mask << 3;
  274. dma_data->packet_size =
  275. (MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
  276. } else {
  277. mcpdm->up_channels = link_mask << 0;
  278. dma_data->packet_size = mcpdm->up_threshold * channels;
  279. }
  280. return 0;
  281. }
  282. static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
  283. struct snd_soc_dai *dai)
  284. {
  285. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  286. if (!omap_mcpdm_active(mcpdm)) {
  287. omap_mcpdm_start(mcpdm);
  288. omap_mcpdm_reg_dump(mcpdm);
  289. }
  290. return 0;
  291. }
  292. static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
  293. .startup = omap_mcpdm_dai_startup,
  294. .shutdown = omap_mcpdm_dai_shutdown,
  295. .hw_params = omap_mcpdm_dai_hw_params,
  296. .prepare = omap_mcpdm_prepare,
  297. };
  298. static int omap_mcpdm_probe(struct snd_soc_dai *dai)
  299. {
  300. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  301. int ret;
  302. pm_runtime_enable(mcpdm->dev);
  303. /* Disable lines while request is ongoing */
  304. pm_runtime_get_sync(mcpdm->dev);
  305. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
  306. ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
  307. 0, "McPDM", (void *)mcpdm);
  308. pm_runtime_put_sync(mcpdm->dev);
  309. if (ret) {
  310. dev_err(mcpdm->dev, "Request for IRQ failed\n");
  311. pm_runtime_disable(mcpdm->dev);
  312. }
  313. /* Configure McPDM threshold values */
  314. mcpdm->dn_threshold = 2;
  315. mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
  316. return ret;
  317. }
  318. static int omap_mcpdm_remove(struct snd_soc_dai *dai)
  319. {
  320. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  321. free_irq(mcpdm->irq, (void *)mcpdm);
  322. pm_runtime_disable(mcpdm->dev);
  323. return 0;
  324. }
  325. #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  326. #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
  327. static struct snd_soc_dai_driver omap_mcpdm_dai = {
  328. .probe = omap_mcpdm_probe,
  329. .remove = omap_mcpdm_remove,
  330. .probe_order = SND_SOC_COMP_ORDER_LATE,
  331. .remove_order = SND_SOC_COMP_ORDER_EARLY,
  332. .playback = {
  333. .channels_min = 1,
  334. .channels_max = 5,
  335. .rates = OMAP_MCPDM_RATES,
  336. .formats = OMAP_MCPDM_FORMATS,
  337. .sig_bits = 24,
  338. },
  339. .capture = {
  340. .channels_min = 1,
  341. .channels_max = 3,
  342. .rates = OMAP_MCPDM_RATES,
  343. .formats = OMAP_MCPDM_FORMATS,
  344. .sig_bits = 24,
  345. },
  346. .ops = &omap_mcpdm_dai_ops,
  347. };
  348. void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
  349. u8 rx1, u8 rx2)
  350. {
  351. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  352. mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
  353. }
  354. EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
  355. static int asoc_mcpdm_probe(struct platform_device *pdev)
  356. {
  357. struct omap_mcpdm *mcpdm;
  358. struct resource *res;
  359. mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
  360. if (!mcpdm)
  361. return -ENOMEM;
  362. platform_set_drvdata(pdev, mcpdm);
  363. mutex_init(&mcpdm->mutex);
  364. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  365. if (res == NULL)
  366. return -ENOMEM;
  367. omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
  368. omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
  369. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
  370. if (!res)
  371. return -ENODEV;
  372. omap_mcpdm_dai_dma_params[0].dma_req = res->start;
  373. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
  374. if (!res)
  375. return -ENODEV;
  376. omap_mcpdm_dai_dma_params[1].dma_req = res->start;
  377. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  378. if (res == NULL)
  379. return -ENOMEM;
  380. if (!devm_request_mem_region(&pdev->dev, res->start,
  381. resource_size(res), "McPDM"))
  382. return -EBUSY;
  383. mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
  384. resource_size(res));
  385. if (!mcpdm->io_base)
  386. return -ENOMEM;
  387. mcpdm->irq = platform_get_irq(pdev, 0);
  388. if (mcpdm->irq < 0)
  389. return mcpdm->irq;
  390. mcpdm->dev = &pdev->dev;
  391. return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
  392. }
  393. static int asoc_mcpdm_remove(struct platform_device *pdev)
  394. {
  395. snd_soc_unregister_dai(&pdev->dev);
  396. return 0;
  397. }
  398. static const struct of_device_id omap_mcpdm_of_match[] = {
  399. { .compatible = "ti,omap4-mcpdm", },
  400. { }
  401. };
  402. MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
  403. static struct platform_driver asoc_mcpdm_driver = {
  404. .driver = {
  405. .name = "omap-mcpdm",
  406. .owner = THIS_MODULE,
  407. .of_match_table = omap_mcpdm_of_match,
  408. },
  409. .probe = asoc_mcpdm_probe,
  410. .remove = asoc_mcpdm_remove,
  411. };
  412. module_platform_driver(asoc_mcpdm_driver);
  413. MODULE_ALIAS("platform:omap-mcpdm");
  414. MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
  415. MODULE_DESCRIPTION("OMAP PDM SoC Interface");
  416. MODULE_LICENSE("GPL");