wm8804.c 19 KB

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  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010-11 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/of_device.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include "wm8804.h"
  30. #define WM8804_NUM_SUPPLIES 2
  31. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  32. "PVDD",
  33. "DVDD"
  34. };
  35. static const struct reg_default wm8804_reg_defaults[] = {
  36. { 3, 0x21 }, /* R3 - PLL1 */
  37. { 4, 0xFD }, /* R4 - PLL2 */
  38. { 5, 0x36 }, /* R5 - PLL3 */
  39. { 6, 0x07 }, /* R6 - PLL4 */
  40. { 7, 0x16 }, /* R7 - PLL5 */
  41. { 8, 0x18 }, /* R8 - PLL6 */
  42. { 9, 0xFF }, /* R9 - SPDMODE */
  43. { 10, 0x00 }, /* R10 - INTMASK */
  44. { 18, 0x00 }, /* R18 - SPDTX1 */
  45. { 19, 0x00 }, /* R19 - SPDTX2 */
  46. { 20, 0x00 }, /* R20 - SPDTX3 */
  47. { 21, 0x71 }, /* R21 - SPDTX4 */
  48. { 22, 0x0B }, /* R22 - SPDTX5 */
  49. { 23, 0x70 }, /* R23 - GPO0 */
  50. { 24, 0x57 }, /* R24 - GPO1 */
  51. { 26, 0x42 }, /* R26 - GPO2 */
  52. { 27, 0x06 }, /* R27 - AIFTX */
  53. { 28, 0x06 }, /* R28 - AIFRX */
  54. { 29, 0x80 }, /* R29 - SPDRX1 */
  55. { 30, 0x07 }, /* R30 - PWRDN */
  56. };
  57. struct wm8804_priv {
  58. struct regmap *regmap;
  59. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  60. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  61. };
  62. static int txsrc_get(struct snd_kcontrol *kcontrol,
  63. struct snd_ctl_elem_value *ucontrol);
  64. static int txsrc_put(struct snd_kcontrol *kcontrol,
  65. struct snd_ctl_elem_value *ucontrol);
  66. /*
  67. * We can't use the same notifier block for more than one supply and
  68. * there's no way I can see to get from a callback to the caller
  69. * except container_of().
  70. */
  71. #define WM8804_REGULATOR_EVENT(n) \
  72. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  73. unsigned long event, void *data) \
  74. { \
  75. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  76. disable_nb[n]); \
  77. if (event & REGULATOR_EVENT_DISABLE) { \
  78. regcache_mark_dirty(wm8804->regmap); \
  79. } \
  80. return 0; \
  81. }
  82. WM8804_REGULATOR_EVENT(0)
  83. WM8804_REGULATOR_EVENT(1)
  84. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  85. static const SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
  86. static const struct snd_kcontrol_new wm8804_snd_controls[] = {
  87. SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
  88. SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
  89. SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
  90. };
  91. static int txsrc_get(struct snd_kcontrol *kcontrol,
  92. struct snd_ctl_elem_value *ucontrol)
  93. {
  94. struct snd_soc_codec *codec;
  95. unsigned int src;
  96. codec = snd_kcontrol_chip(kcontrol);
  97. src = snd_soc_read(codec, WM8804_SPDTX4);
  98. if (src & 0x40)
  99. ucontrol->value.integer.value[0] = 1;
  100. else
  101. ucontrol->value.integer.value[0] = 0;
  102. return 0;
  103. }
  104. static int txsrc_put(struct snd_kcontrol *kcontrol,
  105. struct snd_ctl_elem_value *ucontrol)
  106. {
  107. struct snd_soc_codec *codec;
  108. unsigned int src, txpwr;
  109. codec = snd_kcontrol_chip(kcontrol);
  110. if (ucontrol->value.integer.value[0] != 0
  111. && ucontrol->value.integer.value[0] != 1)
  112. return -EINVAL;
  113. src = snd_soc_read(codec, WM8804_SPDTX4);
  114. switch ((src & 0x40) >> 6) {
  115. case 0:
  116. if (!ucontrol->value.integer.value[0])
  117. return 0;
  118. break;
  119. case 1:
  120. if (ucontrol->value.integer.value[1])
  121. return 0;
  122. break;
  123. }
  124. /* save the current power state of the transmitter */
  125. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  126. /* power down the transmitter */
  127. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  128. /* set the tx source */
  129. snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
  130. ucontrol->value.integer.value[0] << 6);
  131. if (ucontrol->value.integer.value[0]) {
  132. /* power down the receiver */
  133. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
  134. /* power up the AIF */
  135. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
  136. } else {
  137. /* don't power down the AIF -- may be used as an output */
  138. /* power up the receiver */
  139. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
  140. }
  141. /* restore the transmitter's configuration */
  142. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  143. return 0;
  144. }
  145. static bool wm8804_volatile(struct device *dev, unsigned int reg)
  146. {
  147. switch (reg) {
  148. case WM8804_RST_DEVID1:
  149. case WM8804_DEVID2:
  150. case WM8804_DEVREV:
  151. case WM8804_INTSTAT:
  152. case WM8804_SPDSTAT:
  153. case WM8804_RXCHAN1:
  154. case WM8804_RXCHAN2:
  155. case WM8804_RXCHAN3:
  156. case WM8804_RXCHAN4:
  157. case WM8804_RXCHAN5:
  158. return true;
  159. default:
  160. return false;
  161. }
  162. }
  163. static int wm8804_reset(struct snd_soc_codec *codec)
  164. {
  165. return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
  166. }
  167. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  168. {
  169. struct snd_soc_codec *codec;
  170. u16 format, master, bcp, lrp;
  171. codec = dai->codec;
  172. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  173. case SND_SOC_DAIFMT_I2S:
  174. format = 0x2;
  175. break;
  176. case SND_SOC_DAIFMT_RIGHT_J:
  177. format = 0x0;
  178. break;
  179. case SND_SOC_DAIFMT_LEFT_J:
  180. format = 0x1;
  181. break;
  182. case SND_SOC_DAIFMT_DSP_A:
  183. case SND_SOC_DAIFMT_DSP_B:
  184. format = 0x3;
  185. break;
  186. default:
  187. dev_err(dai->dev, "Unknown dai format\n");
  188. return -EINVAL;
  189. }
  190. /* set data format */
  191. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  192. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  193. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  194. case SND_SOC_DAIFMT_CBM_CFM:
  195. master = 1;
  196. break;
  197. case SND_SOC_DAIFMT_CBS_CFS:
  198. master = 0;
  199. break;
  200. default:
  201. dev_err(dai->dev, "Unknown master/slave configuration\n");
  202. return -EINVAL;
  203. }
  204. /* set master/slave mode */
  205. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  206. bcp = lrp = 0;
  207. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  208. case SND_SOC_DAIFMT_NB_NF:
  209. break;
  210. case SND_SOC_DAIFMT_IB_IF:
  211. bcp = lrp = 1;
  212. break;
  213. case SND_SOC_DAIFMT_IB_NF:
  214. bcp = 1;
  215. break;
  216. case SND_SOC_DAIFMT_NB_IF:
  217. lrp = 1;
  218. break;
  219. default:
  220. dev_err(dai->dev, "Unknown polarity configuration\n");
  221. return -EINVAL;
  222. }
  223. /* set frame inversion */
  224. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  225. (bcp << 4) | (lrp << 5));
  226. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  227. (bcp << 4) | (lrp << 5));
  228. return 0;
  229. }
  230. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *params,
  232. struct snd_soc_dai *dai)
  233. {
  234. struct snd_soc_codec *codec;
  235. u16 blen;
  236. codec = dai->codec;
  237. switch (params_format(params)) {
  238. case SNDRV_PCM_FORMAT_S16_LE:
  239. blen = 0x0;
  240. break;
  241. case SNDRV_PCM_FORMAT_S20_3LE:
  242. blen = 0x1;
  243. break;
  244. case SNDRV_PCM_FORMAT_S24_LE:
  245. blen = 0x2;
  246. break;
  247. default:
  248. dev_err(dai->dev, "Unsupported word length: %u\n",
  249. params_format(params));
  250. return -EINVAL;
  251. }
  252. /* set word length */
  253. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  254. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  255. return 0;
  256. }
  257. struct pll_div {
  258. u32 prescale:1;
  259. u32 mclkdiv:1;
  260. u32 freqmode:2;
  261. u32 n:4;
  262. u32 k:22;
  263. };
  264. /* PLL rate to output rate divisions */
  265. static struct {
  266. unsigned int div;
  267. unsigned int freqmode;
  268. unsigned int mclkdiv;
  269. } post_table[] = {
  270. { 2, 0, 0 },
  271. { 4, 0, 1 },
  272. { 4, 1, 0 },
  273. { 8, 1, 1 },
  274. { 8, 2, 0 },
  275. { 16, 2, 1 },
  276. { 12, 3, 0 },
  277. { 24, 3, 1 }
  278. };
  279. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  280. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  281. unsigned int source)
  282. {
  283. u64 Kpart;
  284. unsigned long int K, Ndiv, Nmod, tmp;
  285. int i;
  286. /*
  287. * Scale the output frequency up; the PLL should run in the
  288. * region of 90-100MHz.
  289. */
  290. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  291. tmp = target * post_table[i].div;
  292. if (tmp >= 90000000 && tmp <= 100000000) {
  293. pll_div->freqmode = post_table[i].freqmode;
  294. pll_div->mclkdiv = post_table[i].mclkdiv;
  295. target *= post_table[i].div;
  296. break;
  297. }
  298. }
  299. if (i == ARRAY_SIZE(post_table)) {
  300. pr_err("%s: Unable to scale output frequency: %uHz\n",
  301. __func__, target);
  302. return -EINVAL;
  303. }
  304. pll_div->prescale = 0;
  305. Ndiv = target / source;
  306. if (Ndiv < 5) {
  307. source >>= 1;
  308. pll_div->prescale = 1;
  309. Ndiv = target / source;
  310. }
  311. if (Ndiv < 5 || Ndiv > 13) {
  312. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  313. __func__, Ndiv);
  314. return -EINVAL;
  315. }
  316. pll_div->n = Ndiv;
  317. Nmod = target % source;
  318. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  319. do_div(Kpart, source);
  320. K = Kpart & 0xffffffff;
  321. if ((K % 10) >= 5)
  322. K += 5;
  323. K /= 10;
  324. pll_div->k = K;
  325. return 0;
  326. }
  327. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  328. int source, unsigned int freq_in,
  329. unsigned int freq_out)
  330. {
  331. struct snd_soc_codec *codec;
  332. codec = dai->codec;
  333. if (!freq_in || !freq_out) {
  334. /* disable the PLL */
  335. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  336. return 0;
  337. } else {
  338. int ret;
  339. struct pll_div pll_div;
  340. ret = pll_factors(&pll_div, freq_out, freq_in);
  341. if (ret)
  342. return ret;
  343. /* power down the PLL before reprogramming it */
  344. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  345. /* set PLLN and PRESCALE */
  346. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  347. pll_div.n | (pll_div.prescale << 4));
  348. /* set mclkdiv and freqmode */
  349. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  350. pll_div.freqmode | (pll_div.mclkdiv << 3));
  351. /* set PLLK */
  352. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  353. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  354. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  355. /* power up the PLL */
  356. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  357. }
  358. return 0;
  359. }
  360. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  361. int clk_id, unsigned int freq, int dir)
  362. {
  363. struct snd_soc_codec *codec;
  364. codec = dai->codec;
  365. switch (clk_id) {
  366. case WM8804_TX_CLKSRC_MCLK:
  367. if ((freq >= 10000000 && freq <= 14400000)
  368. || (freq >= 16280000 && freq <= 27000000))
  369. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  370. else {
  371. dev_err(dai->dev, "OSCCLOCK is not within the "
  372. "recommended range: %uHz\n", freq);
  373. return -EINVAL;
  374. }
  375. break;
  376. case WM8804_TX_CLKSRC_PLL:
  377. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  378. break;
  379. case WM8804_CLKOUT_SRC_CLK1:
  380. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  381. break;
  382. case WM8804_CLKOUT_SRC_OSCCLK:
  383. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  384. break;
  385. default:
  386. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  387. return -EINVAL;
  388. }
  389. return 0;
  390. }
  391. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  392. int div_id, int div)
  393. {
  394. struct snd_soc_codec *codec;
  395. codec = dai->codec;
  396. switch (div_id) {
  397. case WM8804_CLKOUT_DIV:
  398. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  399. (div & 0x3) << 4);
  400. break;
  401. default:
  402. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  403. return -EINVAL;
  404. }
  405. return 0;
  406. }
  407. static int wm8804_set_bias_level(struct snd_soc_codec *codec,
  408. enum snd_soc_bias_level level)
  409. {
  410. int ret;
  411. struct wm8804_priv *wm8804;
  412. wm8804 = snd_soc_codec_get_drvdata(codec);
  413. switch (level) {
  414. case SND_SOC_BIAS_ON:
  415. break;
  416. case SND_SOC_BIAS_PREPARE:
  417. /* power up the OSC and the PLL */
  418. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
  419. break;
  420. case SND_SOC_BIAS_STANDBY:
  421. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  422. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  423. wm8804->supplies);
  424. if (ret) {
  425. dev_err(codec->dev,
  426. "Failed to enable supplies: %d\n",
  427. ret);
  428. return ret;
  429. }
  430. regcache_sync(wm8804->regmap);
  431. }
  432. /* power down the OSC and the PLL */
  433. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  434. break;
  435. case SND_SOC_BIAS_OFF:
  436. /* power down the OSC and the PLL */
  437. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  438. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  439. wm8804->supplies);
  440. break;
  441. }
  442. codec->dapm.bias_level = level;
  443. return 0;
  444. }
  445. #ifdef CONFIG_PM
  446. static int wm8804_suspend(struct snd_soc_codec *codec)
  447. {
  448. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  449. return 0;
  450. }
  451. static int wm8804_resume(struct snd_soc_codec *codec)
  452. {
  453. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  454. return 0;
  455. }
  456. #else
  457. #define wm8804_suspend NULL
  458. #define wm8804_resume NULL
  459. #endif
  460. static int wm8804_remove(struct snd_soc_codec *codec)
  461. {
  462. struct wm8804_priv *wm8804;
  463. int i;
  464. wm8804 = snd_soc_codec_get_drvdata(codec);
  465. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  466. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
  467. regulator_unregister_notifier(wm8804->supplies[i].consumer,
  468. &wm8804->disable_nb[i]);
  469. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  470. return 0;
  471. }
  472. static int wm8804_probe(struct snd_soc_codec *codec)
  473. {
  474. struct wm8804_priv *wm8804;
  475. int i, id1, id2, ret;
  476. wm8804 = snd_soc_codec_get_drvdata(codec);
  477. codec->control_data = wm8804->regmap;
  478. ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
  479. if (ret < 0) {
  480. dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
  481. return ret;
  482. }
  483. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  484. wm8804->supplies[i].supply = wm8804_supply_names[i];
  485. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
  486. wm8804->supplies);
  487. if (ret) {
  488. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  489. return ret;
  490. }
  491. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  492. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  493. /* This should really be moved into the regulator core */
  494. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  495. ret = regulator_register_notifier(wm8804->supplies[i].consumer,
  496. &wm8804->disable_nb[i]);
  497. if (ret != 0) {
  498. dev_err(codec->dev,
  499. "Failed to register regulator notifier: %d\n",
  500. ret);
  501. }
  502. }
  503. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  504. wm8804->supplies);
  505. if (ret) {
  506. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  507. goto err_reg_get;
  508. }
  509. id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
  510. if (id1 < 0) {
  511. dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
  512. ret = id1;
  513. goto err_reg_enable;
  514. }
  515. id2 = snd_soc_read(codec, WM8804_DEVID2);
  516. if (id2 < 0) {
  517. dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
  518. ret = id2;
  519. goto err_reg_enable;
  520. }
  521. id2 = (id2 << 8) | id1;
  522. if (id2 != 0x8805) {
  523. dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
  524. ret = -EINVAL;
  525. goto err_reg_enable;
  526. }
  527. ret = snd_soc_read(codec, WM8804_DEVREV);
  528. if (ret < 0) {
  529. dev_err(codec->dev, "Failed to read device revision: %d\n",
  530. ret);
  531. goto err_reg_enable;
  532. }
  533. dev_info(codec->dev, "revision %c\n", ret + 'A');
  534. ret = wm8804_reset(codec);
  535. if (ret < 0) {
  536. dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
  537. goto err_reg_enable;
  538. }
  539. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  540. return 0;
  541. err_reg_enable:
  542. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  543. err_reg_get:
  544. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  545. return ret;
  546. }
  547. static const struct snd_soc_dai_ops wm8804_dai_ops = {
  548. .hw_params = wm8804_hw_params,
  549. .set_fmt = wm8804_set_fmt,
  550. .set_sysclk = wm8804_set_sysclk,
  551. .set_clkdiv = wm8804_set_clkdiv,
  552. .set_pll = wm8804_set_pll
  553. };
  554. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  555. SNDRV_PCM_FMTBIT_S24_LE)
  556. #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  557. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  558. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  559. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  560. static struct snd_soc_dai_driver wm8804_dai = {
  561. .name = "wm8804-spdif",
  562. .playback = {
  563. .stream_name = "Playback",
  564. .channels_min = 2,
  565. .channels_max = 2,
  566. .rates = WM8804_RATES,
  567. .formats = WM8804_FORMATS,
  568. },
  569. .capture = {
  570. .stream_name = "Capture",
  571. .channels_min = 2,
  572. .channels_max = 2,
  573. .rates = WM8804_RATES,
  574. .formats = WM8804_FORMATS,
  575. },
  576. .ops = &wm8804_dai_ops,
  577. .symmetric_rates = 1
  578. };
  579. static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  580. .probe = wm8804_probe,
  581. .remove = wm8804_remove,
  582. .suspend = wm8804_suspend,
  583. .resume = wm8804_resume,
  584. .set_bias_level = wm8804_set_bias_level,
  585. .idle_bias_off = true,
  586. .controls = wm8804_snd_controls,
  587. .num_controls = ARRAY_SIZE(wm8804_snd_controls),
  588. };
  589. static const struct of_device_id wm8804_of_match[] = {
  590. { .compatible = "wlf,wm8804", },
  591. { }
  592. };
  593. MODULE_DEVICE_TABLE(of, wm8804_of_match);
  594. static struct regmap_config wm8804_regmap_config = {
  595. .reg_bits = 8,
  596. .val_bits = 8,
  597. .max_register = WM8804_MAX_REGISTER,
  598. .volatile_reg = wm8804_volatile,
  599. .cache_type = REGCACHE_RBTREE,
  600. .reg_defaults = wm8804_reg_defaults,
  601. .num_reg_defaults = ARRAY_SIZE(wm8804_reg_defaults),
  602. };
  603. #if defined(CONFIG_SPI_MASTER)
  604. static int wm8804_spi_probe(struct spi_device *spi)
  605. {
  606. struct wm8804_priv *wm8804;
  607. int ret;
  608. wm8804 = devm_kzalloc(&spi->dev, sizeof *wm8804, GFP_KERNEL);
  609. if (!wm8804)
  610. return -ENOMEM;
  611. wm8804->regmap = devm_regmap_init_spi(spi, &wm8804_regmap_config);
  612. if (IS_ERR(wm8804->regmap)) {
  613. ret = PTR_ERR(wm8804->regmap);
  614. return ret;
  615. }
  616. spi_set_drvdata(spi, wm8804);
  617. ret = snd_soc_register_codec(&spi->dev,
  618. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  619. return ret;
  620. }
  621. static int wm8804_spi_remove(struct spi_device *spi)
  622. {
  623. snd_soc_unregister_codec(&spi->dev);
  624. return 0;
  625. }
  626. static struct spi_driver wm8804_spi_driver = {
  627. .driver = {
  628. .name = "wm8804",
  629. .owner = THIS_MODULE,
  630. .of_match_table = wm8804_of_match,
  631. },
  632. .probe = wm8804_spi_probe,
  633. .remove = wm8804_spi_remove
  634. };
  635. #endif
  636. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  637. static int wm8804_i2c_probe(struct i2c_client *i2c,
  638. const struct i2c_device_id *id)
  639. {
  640. struct wm8804_priv *wm8804;
  641. int ret;
  642. wm8804 = devm_kzalloc(&i2c->dev, sizeof *wm8804, GFP_KERNEL);
  643. if (!wm8804)
  644. return -ENOMEM;
  645. wm8804->regmap = devm_regmap_init_i2c(i2c, &wm8804_regmap_config);
  646. if (IS_ERR(wm8804->regmap)) {
  647. ret = PTR_ERR(wm8804->regmap);
  648. return ret;
  649. }
  650. i2c_set_clientdata(i2c, wm8804);
  651. ret = snd_soc_register_codec(&i2c->dev,
  652. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  653. return ret;
  654. }
  655. static int wm8804_i2c_remove(struct i2c_client *i2c)
  656. {
  657. snd_soc_unregister_codec(&i2c->dev);
  658. return 0;
  659. }
  660. static const struct i2c_device_id wm8804_i2c_id[] = {
  661. { "wm8804", 0 },
  662. { }
  663. };
  664. MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
  665. static struct i2c_driver wm8804_i2c_driver = {
  666. .driver = {
  667. .name = "wm8804",
  668. .owner = THIS_MODULE,
  669. .of_match_table = wm8804_of_match,
  670. },
  671. .probe = wm8804_i2c_probe,
  672. .remove = wm8804_i2c_remove,
  673. .id_table = wm8804_i2c_id
  674. };
  675. #endif
  676. static int __init wm8804_modinit(void)
  677. {
  678. int ret = 0;
  679. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  680. ret = i2c_add_driver(&wm8804_i2c_driver);
  681. if (ret) {
  682. printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
  683. ret);
  684. }
  685. #endif
  686. #if defined(CONFIG_SPI_MASTER)
  687. ret = spi_register_driver(&wm8804_spi_driver);
  688. if (ret != 0) {
  689. printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
  690. ret);
  691. }
  692. #endif
  693. return ret;
  694. }
  695. module_init(wm8804_modinit);
  696. static void __exit wm8804_exit(void)
  697. {
  698. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  699. i2c_del_driver(&wm8804_i2c_driver);
  700. #endif
  701. #if defined(CONFIG_SPI_MASTER)
  702. spi_unregister_driver(&wm8804_spi_driver);
  703. #endif
  704. }
  705. module_exit(wm8804_exit);
  706. MODULE_DESCRIPTION("ASoC WM8804 driver");
  707. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  708. MODULE_LICENSE("GPL");