lm49453.c 53 KB

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  1. /*
  2. * lm49453.c - LM49453 ALSA Soc Audio driver
  3. *
  4. * Copyright (c) 2012 Texas Instruments, Inc
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * Initially based on sound/soc/codecs/wm8350.c
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/tlv.h>
  27. #include <sound/jack.h>
  28. #include <sound/initval.h>
  29. #include <asm/div64.h>
  30. #include "lm49453.h"
  31. static struct reg_default lm49453_reg_defs[] = {
  32. { 0, 0x00 },
  33. { 1, 0x00 },
  34. { 2, 0x00 },
  35. { 3, 0x00 },
  36. { 4, 0x00 },
  37. { 5, 0x00 },
  38. { 6, 0x00 },
  39. { 7, 0x00 },
  40. { 8, 0x00 },
  41. { 9, 0x00 },
  42. { 10, 0x00 },
  43. { 11, 0x00 },
  44. { 12, 0x00 },
  45. { 13, 0x00 },
  46. { 14, 0x00 },
  47. { 15, 0x00 },
  48. { 16, 0x00 },
  49. { 17, 0x00 },
  50. { 18, 0x00 },
  51. { 19, 0x00 },
  52. { 20, 0x00 },
  53. { 21, 0x00 },
  54. { 22, 0x00 },
  55. { 23, 0x00 },
  56. { 32, 0x00 },
  57. { 33, 0x00 },
  58. { 35, 0x00 },
  59. { 36, 0x00 },
  60. { 37, 0x00 },
  61. { 46, 0x00 },
  62. { 48, 0x00 },
  63. { 49, 0x00 },
  64. { 51, 0x00 },
  65. { 56, 0x00 },
  66. { 58, 0x00 },
  67. { 59, 0x00 },
  68. { 60, 0x00 },
  69. { 61, 0x00 },
  70. { 62, 0x00 },
  71. { 63, 0x00 },
  72. { 64, 0x00 },
  73. { 65, 0x00 },
  74. { 66, 0x00 },
  75. { 67, 0x00 },
  76. { 68, 0x00 },
  77. { 69, 0x00 },
  78. { 70, 0x00 },
  79. { 71, 0x00 },
  80. { 72, 0x00 },
  81. { 73, 0x00 },
  82. { 74, 0x00 },
  83. { 75, 0x00 },
  84. { 76, 0x00 },
  85. { 77, 0x00 },
  86. { 78, 0x00 },
  87. { 79, 0x00 },
  88. { 80, 0x00 },
  89. { 81, 0x00 },
  90. { 82, 0x00 },
  91. { 83, 0x00 },
  92. { 85, 0x00 },
  93. { 85, 0x00 },
  94. { 86, 0x00 },
  95. { 87, 0x00 },
  96. { 88, 0x00 },
  97. { 89, 0x00 },
  98. { 90, 0x00 },
  99. { 91, 0x00 },
  100. { 92, 0x00 },
  101. { 93, 0x00 },
  102. { 94, 0x00 },
  103. { 95, 0x00 },
  104. { 96, 0x01 },
  105. { 97, 0x00 },
  106. { 98, 0x00 },
  107. { 99, 0x00 },
  108. { 100, 0x00 },
  109. { 101, 0x00 },
  110. { 102, 0x00 },
  111. { 103, 0x01 },
  112. { 104, 0x01 },
  113. { 105, 0x00 },
  114. { 106, 0x01 },
  115. { 107, 0x00 },
  116. { 108, 0x00 },
  117. { 109, 0x00 },
  118. { 110, 0x00 },
  119. { 111, 0x02 },
  120. { 112, 0x02 },
  121. { 113, 0x00 },
  122. { 121, 0x80 },
  123. { 122, 0xBB },
  124. { 123, 0x80 },
  125. { 124, 0xBB },
  126. { 128, 0x00 },
  127. { 130, 0x00 },
  128. { 131, 0x00 },
  129. { 132, 0x00 },
  130. { 133, 0x0A },
  131. { 134, 0x0A },
  132. { 135, 0x0A },
  133. { 136, 0x0F },
  134. { 137, 0x00 },
  135. { 138, 0x73 },
  136. { 139, 0x33 },
  137. { 140, 0x73 },
  138. { 141, 0x33 },
  139. { 142, 0x73 },
  140. { 143, 0x33 },
  141. { 144, 0x73 },
  142. { 145, 0x33 },
  143. { 146, 0x73 },
  144. { 147, 0x33 },
  145. { 148, 0x73 },
  146. { 149, 0x33 },
  147. { 150, 0x73 },
  148. { 151, 0x33 },
  149. { 152, 0x00 },
  150. { 153, 0x00 },
  151. { 154, 0x00 },
  152. { 155, 0x00 },
  153. { 176, 0x00 },
  154. { 177, 0x00 },
  155. { 178, 0x00 },
  156. { 179, 0x00 },
  157. { 180, 0x00 },
  158. { 181, 0x00 },
  159. { 182, 0x00 },
  160. { 183, 0x00 },
  161. { 184, 0x00 },
  162. { 185, 0x00 },
  163. { 186, 0x00 },
  164. { 187, 0x00 },
  165. { 188, 0x00 },
  166. { 189, 0x00 },
  167. { 208, 0x06 },
  168. { 209, 0x00 },
  169. { 210, 0x08 },
  170. { 211, 0x54 },
  171. { 212, 0x14 },
  172. { 213, 0x0d },
  173. { 214, 0x0d },
  174. { 215, 0x14 },
  175. { 216, 0x60 },
  176. { 221, 0x00 },
  177. { 222, 0x00 },
  178. { 223, 0x00 },
  179. { 224, 0x00 },
  180. { 248, 0x00 },
  181. { 249, 0x00 },
  182. { 250, 0x00 },
  183. { 255, 0x00 },
  184. };
  185. /* codec private data */
  186. struct lm49453_priv {
  187. struct regmap *regmap;
  188. int fs_rate;
  189. };
  190. /* capture path controls */
  191. static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
  192. static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
  193. lm49453_mic2mode_text);
  194. static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
  195. static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
  196. LM49453_P0_DIGITAL_MIC1_CONFIG_REG,
  197. 7, lm49453_dmic_cfg_text);
  198. static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
  199. LM49453_P0_DIGITAL_MIC2_CONFIG_REG,
  200. 7, lm49453_dmic_cfg_text);
  201. /* MUX Controls */
  202. static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
  203. static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
  204. static const struct soc_enum lm49453_adcl_enum =
  205. SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
  206. ARRAY_SIZE(lm49453_adcl_mux_text),
  207. lm49453_adcl_mux_text);
  208. static const struct soc_enum lm49453_adcr_enum =
  209. SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
  210. ARRAY_SIZE(lm49453_adcr_mux_text),
  211. lm49453_adcr_mux_text);
  212. static const struct snd_kcontrol_new lm49453_adcl_mux_control =
  213. SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
  214. static const struct snd_kcontrol_new lm49453_adcr_mux_control =
  215. SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
  216. static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
  217. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
  218. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
  219. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
  220. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
  221. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
  222. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
  223. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
  224. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
  225. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
  226. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
  227. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
  228. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
  229. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
  230. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
  231. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
  232. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
  233. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
  234. };
  235. static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
  236. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
  237. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
  238. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
  239. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
  240. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
  241. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
  242. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
  243. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
  244. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
  245. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
  246. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
  247. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
  248. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
  249. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
  250. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
  251. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
  252. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
  253. };
  254. static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
  255. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
  256. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
  257. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
  258. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
  259. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
  260. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
  261. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
  262. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
  263. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
  264. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
  265. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
  266. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
  267. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
  268. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
  269. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
  270. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
  271. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
  272. };
  273. static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
  274. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
  275. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
  276. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
  277. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
  278. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
  279. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
  280. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
  281. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
  282. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
  283. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
  284. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
  285. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
  286. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
  287. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
  288. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
  289. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
  290. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
  291. };
  292. static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
  293. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
  294. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
  295. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
  296. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
  297. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
  298. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
  299. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
  300. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
  301. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
  302. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
  303. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
  304. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
  305. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
  306. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
  307. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
  308. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
  309. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
  310. };
  311. static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
  312. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
  313. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
  314. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
  315. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
  316. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
  317. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
  318. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
  319. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
  320. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
  321. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
  322. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
  323. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
  324. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
  325. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
  326. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
  327. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
  328. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
  329. };
  330. static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
  331. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
  332. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
  333. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
  334. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
  335. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
  336. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
  337. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
  338. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
  339. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
  340. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
  341. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
  342. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
  343. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
  344. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
  345. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
  346. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
  347. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
  348. };
  349. static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
  350. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
  351. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
  352. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
  353. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
  354. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
  355. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
  356. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
  357. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
  358. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
  359. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
  360. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
  361. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
  362. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
  363. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
  364. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
  365. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
  366. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
  367. };
  368. static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
  369. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
  370. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
  371. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
  372. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
  373. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
  374. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
  375. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
  376. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
  377. };
  378. static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
  379. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
  380. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
  381. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
  382. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
  383. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
  384. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
  385. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
  386. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
  387. };
  388. static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
  389. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
  390. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
  391. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
  392. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
  393. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
  394. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
  395. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
  396. };
  397. static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
  398. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
  399. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
  400. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
  401. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
  402. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
  403. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
  404. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
  405. };
  406. static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
  407. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
  408. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
  409. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
  410. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
  411. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
  412. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
  413. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
  414. };
  415. static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
  416. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
  417. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
  418. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
  419. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
  420. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
  421. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
  422. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
  423. };
  424. static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
  425. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
  426. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
  427. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
  428. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
  429. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
  430. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
  431. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
  432. };
  433. static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
  434. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
  435. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
  436. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
  437. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
  438. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
  439. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
  440. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
  441. };
  442. static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
  443. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
  444. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
  445. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
  446. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
  447. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
  448. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
  449. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
  450. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
  451. };
  452. static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
  453. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
  454. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
  455. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
  456. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
  457. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
  458. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
  459. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
  460. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
  461. };
  462. /* TLV Declarations */
  463. static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
  464. static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
  465. static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
  466. static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
  467. static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
  468. /* Sidetone supports mono only */
  469. SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
  470. 0, 0x3F, 0, stn_tlv),
  471. SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
  472. 0, 0x3F, 0, stn_tlv),
  473. SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
  474. 0, 0x3F, 0, stn_tlv),
  475. SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
  476. 0, 0x3F, 0, stn_tlv),
  477. SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
  478. 0, 0x3F, 0, stn_tlv),
  479. SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
  480. 0, 0x3F, 0, stn_tlv),
  481. };
  482. static const struct snd_kcontrol_new lm49453_snd_controls[] = {
  483. /* mic1 and mic2 supports mono only */
  484. SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
  485. SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
  486. SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
  487. 0, adc_dac_tlv),
  488. SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
  489. 0, adc_dac_tlv),
  490. SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
  491. LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  492. SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
  493. LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  494. SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
  495. SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
  496. SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
  497. /* Capture path filter enable */
  498. SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
  499. 0, 1, 0),
  500. SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
  501. 1, 1, 0),
  502. SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
  503. 2, 1, 0),
  504. SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
  505. LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  506. SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
  507. LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  508. SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
  509. LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  510. SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
  511. LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  512. SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
  513. 0, 63, 0, adc_dac_tlv),
  514. SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  515. 0, 3, 0, port_tlv),
  516. SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  517. 2, 3, 0, port_tlv),
  518. SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  519. 4, 3, 0, port_tlv),
  520. SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  521. 6, 3, 0, port_tlv),
  522. SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  523. 0, 3, 0, port_tlv),
  524. SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  525. 2, 3, 0, port_tlv),
  526. SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  527. 4, 3, 0, port_tlv),
  528. SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  529. 6, 3, 0, port_tlv),
  530. SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
  531. 0, 3, 0, port_tlv),
  532. SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
  533. 2, 3, 0, port_tlv),
  534. SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
  535. 1, 1, 0),
  536. SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
  537. 1, 1, 0),
  538. SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
  539. 2, 1, 0),
  540. SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
  541. 2, 1, 0)
  542. };
  543. /* DAPM widgets */
  544. static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
  545. /* All end points HP,EP, LS, Lineout and Haptic */
  546. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  547. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  548. SND_SOC_DAPM_OUTPUT("EPOUT"),
  549. SND_SOC_DAPM_OUTPUT("LSOUTL"),
  550. SND_SOC_DAPM_OUTPUT("LSOUTR"),
  551. SND_SOC_DAPM_OUTPUT("LOOUTR"),
  552. SND_SOC_DAPM_OUTPUT("LOOUTL"),
  553. SND_SOC_DAPM_OUTPUT("HAOUTL"),
  554. SND_SOC_DAPM_OUTPUT("HAOUTR"),
  555. SND_SOC_DAPM_INPUT("AMIC1"),
  556. SND_SOC_DAPM_INPUT("AMIC2"),
  557. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  558. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  559. SND_SOC_DAPM_INPUT("AUXL"),
  560. SND_SOC_DAPM_INPUT("AUXR"),
  561. SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  562. SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  563. SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  564. SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  565. SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  566. SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  567. SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  568. SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  569. SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  570. SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  571. SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
  572. SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
  573. /* playback path driver enables */
  574. SND_SOC_DAPM_OUT_DRV("Headset Switch",
  575. LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
  576. SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
  577. LM49453_P0_EP_REG, 0, 0, NULL, 0),
  578. SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
  579. LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
  580. SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
  581. LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
  582. SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
  583. LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
  584. SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
  585. LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
  586. /* DAC */
  587. SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
  588. SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
  589. SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
  590. SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
  591. SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
  592. SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
  593. SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
  594. SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
  595. SND_SOC_DAPM_PGA("AUXL Input",
  596. LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
  597. SND_SOC_DAPM_PGA("AUXR Input",
  598. LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
  599. SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
  600. /* ADC */
  601. SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
  602. SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
  603. SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
  604. SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
  605. SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
  606. SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
  607. SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
  608. &lm49453_adcl_mux_control),
  609. SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
  610. &lm49453_adcr_mux_control),
  611. SND_SOC_DAPM_MUX("Mic1 Input",
  612. SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
  613. SND_SOC_DAPM_MUX("Mic2 Input",
  614. SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
  615. /* AIF */
  616. SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
  617. LM49453_P0_PULL_CONFIG1_REG, 2, 0),
  618. SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
  619. LM49453_P0_PULL_CONFIG1_REG, 6, 0),
  620. SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
  621. LM49453_P0_PULL_CONFIG1_REG, 3, 0),
  622. SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
  623. LM49453_P0_PULL_CONFIG1_REG, 7, 0),
  624. /* Port1 TX controls */
  625. SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  626. SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  627. SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  628. SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  629. SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  630. SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  631. SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  632. SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  633. /* Port2 TX controls */
  634. SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  635. SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  636. /* Sidetone Mixer */
  637. SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
  638. lm49453_sidetone_mixer_controls,
  639. ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
  640. /* DAC MIXERS */
  641. SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
  642. lm49453_headset_left_mixer,
  643. ARRAY_SIZE(lm49453_headset_left_mixer)),
  644. SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
  645. lm49453_headset_right_mixer,
  646. ARRAY_SIZE(lm49453_headset_right_mixer)),
  647. SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
  648. lm49453_lineout_left_mixer,
  649. ARRAY_SIZE(lm49453_lineout_left_mixer)),
  650. SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
  651. lm49453_lineout_right_mixer,
  652. ARRAY_SIZE(lm49453_lineout_right_mixer)),
  653. SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
  654. lm49453_speaker_left_mixer,
  655. ARRAY_SIZE(lm49453_speaker_left_mixer)),
  656. SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
  657. lm49453_speaker_right_mixer,
  658. ARRAY_SIZE(lm49453_speaker_right_mixer)),
  659. SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
  660. lm49453_haptic_left_mixer,
  661. ARRAY_SIZE(lm49453_haptic_left_mixer)),
  662. SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
  663. lm49453_haptic_right_mixer,
  664. ARRAY_SIZE(lm49453_haptic_right_mixer)),
  665. /* Capture Mixer */
  666. SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
  667. lm49453_port1_tx1_mixer,
  668. ARRAY_SIZE(lm49453_port1_tx1_mixer)),
  669. SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
  670. lm49453_port1_tx2_mixer,
  671. ARRAY_SIZE(lm49453_port1_tx2_mixer)),
  672. SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
  673. lm49453_port1_tx3_mixer,
  674. ARRAY_SIZE(lm49453_port1_tx3_mixer)),
  675. SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
  676. lm49453_port1_tx4_mixer,
  677. ARRAY_SIZE(lm49453_port1_tx4_mixer)),
  678. SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
  679. lm49453_port1_tx5_mixer,
  680. ARRAY_SIZE(lm49453_port1_tx5_mixer)),
  681. SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
  682. lm49453_port1_tx6_mixer,
  683. ARRAY_SIZE(lm49453_port1_tx6_mixer)),
  684. SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
  685. lm49453_port1_tx7_mixer,
  686. ARRAY_SIZE(lm49453_port1_tx7_mixer)),
  687. SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
  688. lm49453_port1_tx8_mixer,
  689. ARRAY_SIZE(lm49453_port1_tx8_mixer)),
  690. SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
  691. lm49453_port2_tx1_mixer,
  692. ARRAY_SIZE(lm49453_port2_tx1_mixer)),
  693. SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
  694. lm49453_port2_tx2_mixer,
  695. ARRAY_SIZE(lm49453_port2_tx2_mixer)),
  696. };
  697. static const struct snd_soc_dapm_route lm49453_audio_map[] = {
  698. /* Port SDI mapping */
  699. { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
  700. { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
  701. { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
  702. { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
  703. { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
  704. { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
  705. { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
  706. { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
  707. { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
  708. { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
  709. /* HP mapping */
  710. { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  711. { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  712. { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  713. { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  714. { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  715. { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  716. { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  717. { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  718. { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  719. { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  720. { "HPL Mixer", "ADCL Switch", "ADC Left" },
  721. { "HPL Mixer", "ADCR Switch", "ADC Right" },
  722. { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  723. { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  724. { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  725. { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  726. { "HPL Mixer", "Sidetone Switch", "Sidetone" },
  727. { "HPL DAC", NULL, "HPL Mixer" },
  728. { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  729. { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  730. { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  731. { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  732. { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  733. { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  734. { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  735. { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  736. /* Port 2 */
  737. { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  738. { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  739. { "HPR Mixer", "ADCL Switch", "ADC Left" },
  740. { "HPR Mixer", "ADCR Switch", "ADC Right" },
  741. { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  742. { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  743. { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  744. { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
  745. { "HPR Mixer", "Sidetone Switch", "Sidetone" },
  746. { "HPR DAC", NULL, "HPR Mixer" },
  747. { "HPOUTL", "Headset Switch", "HPL DAC"},
  748. { "HPOUTR", "Headset Switch", "HPR DAC"},
  749. /* EP map */
  750. { "EPOUT", "Earpiece Switch", "HPL DAC" },
  751. /* Speaker map */
  752. { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  753. { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  754. { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  755. { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  756. { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  757. { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  758. { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  759. { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  760. /* Port 2 */
  761. { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  762. { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  763. { "LSL Mixer", "ADCL Switch", "ADC Left" },
  764. { "LSL Mixer", "ADCR Switch", "ADC Right" },
  765. { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  766. { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  767. { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  768. { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  769. { "LSL Mixer", "Sidetone Switch", "Sidetone" },
  770. { "LSL DAC", NULL, "LSL Mixer" },
  771. { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  772. { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  773. { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  774. { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  775. { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  776. { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  777. { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  778. { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  779. /* Port 2 */
  780. { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  781. { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  782. { "LSR Mixer", "ADCL Switch", "ADC Left" },
  783. { "LSR Mixer", "ADCR Switch", "ADC Right" },
  784. { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  785. { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  786. { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  787. { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
  788. { "LSR Mixer", "Sidetone Switch", "Sidetone" },
  789. { "LSR DAC", NULL, "LSR Mixer" },
  790. { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
  791. { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
  792. /* Haptic map */
  793. { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  794. { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  795. { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  796. { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  797. { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  798. { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  799. { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  800. { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  801. /* Port 2 */
  802. { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  803. { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  804. { "HAL Mixer", "ADCL Switch", "ADC Left" },
  805. { "HAL Mixer", "ADCR Switch", "ADC Right" },
  806. { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  807. { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  808. { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  809. { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  810. { "HAL Mixer", "Sidetone Switch", "Sidetone" },
  811. { "HAL DAC", NULL, "HAL Mixer" },
  812. { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  813. { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  814. { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  815. { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  816. { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  817. { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  818. { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  819. { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  820. /* Port 2 */
  821. { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  822. { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  823. { "HAR Mixer", "ADCL Switch", "ADC Left" },
  824. { "HAR Mixer", "ADCR Switch", "ADC Right" },
  825. { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  826. { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  827. { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  828. { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
  829. { "HAR Mixer", "Sideton Switch", "Sidetone" },
  830. { "HAR DAC", NULL, "HAR Mixer" },
  831. { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
  832. { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
  833. /* Lineout map */
  834. { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  835. { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  836. { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  837. { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  838. { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  839. { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  840. { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  841. { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  842. /* Port 2 */
  843. { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  844. { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  845. { "LOL Mixer", "ADCL Switch", "ADC Left" },
  846. { "LOL Mixer", "ADCR Switch", "ADC Right" },
  847. { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  848. { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  849. { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  850. { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  851. { "LOL Mixer", "Sidetone Switch", "Sidetone" },
  852. { "LOL DAC", NULL, "LOL Mixer" },
  853. { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  854. { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  855. { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  856. { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  857. { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  858. { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  859. { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  860. { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  861. /* Port 2 */
  862. { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  863. { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  864. { "LOR Mixer", "ADCL Switch", "ADC Left" },
  865. { "LOR Mixer", "ADCR Switch", "ADC Right" },
  866. { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  867. { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  868. { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  869. { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
  870. { "LOR Mixer", "Sidetone Switch", "Sidetone" },
  871. { "LOR DAC", NULL, "LOR Mixer" },
  872. { "LOOUTL", NULL, "LOL DAC" },
  873. { "LOOUTR", NULL, "LOR DAC" },
  874. /* TX map */
  875. /* Port1 mappings */
  876. { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
  877. { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
  878. { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  879. { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  880. { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  881. { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  882. { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
  883. { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
  884. { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  885. { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  886. { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  887. { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  888. { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
  889. { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
  890. { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  891. { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  892. { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  893. { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  894. { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
  895. { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
  896. { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  897. { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  898. { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  899. { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  900. { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
  901. { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
  902. { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  903. { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  904. { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  905. { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  906. { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
  907. { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
  908. { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  909. { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  910. { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  911. { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  912. { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
  913. { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
  914. { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  915. { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  916. { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  917. { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  918. { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
  919. { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
  920. { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  921. { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  922. { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  923. { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  924. { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
  925. { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
  926. { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  927. { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  928. { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  929. { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  930. { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
  931. { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
  932. { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  933. { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  934. { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  935. { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  936. { "P1_1_TX", NULL, "Port1_1 Mixer" },
  937. { "P1_2_TX", NULL, "Port1_2 Mixer" },
  938. { "P1_3_TX", NULL, "Port1_3 Mixer" },
  939. { "P1_4_TX", NULL, "Port1_4 Mixer" },
  940. { "P1_5_TX", NULL, "Port1_5 Mixer" },
  941. { "P1_6_TX", NULL, "Port1_6 Mixer" },
  942. { "P1_7_TX", NULL, "Port1_7 Mixer" },
  943. { "P1_8_TX", NULL, "Port1_8 Mixer" },
  944. { "P2_1_TX", NULL, "Port2_1 Mixer" },
  945. { "P2_2_TX", NULL, "Port2_2 Mixer" },
  946. { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
  947. { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
  948. { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
  949. { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
  950. { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
  951. { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
  952. { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
  953. { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
  954. { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
  955. { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
  956. { "Mic1 Input", NULL, "AMIC1" },
  957. { "Mic2 Input", NULL, "AMIC2" },
  958. { "AUXL Input", NULL, "AUXL" },
  959. { "AUXR Input", NULL, "AUXR" },
  960. /* AUX connections */
  961. { "ADCL Mux", "Aux_L", "AUXL Input" },
  962. { "ADCL Mux", "MIC1", "Mic1 Input" },
  963. { "ADCR Mux", "Aux_R", "AUXR Input" },
  964. { "ADCR Mux", "MIC2", "Mic2 Input" },
  965. /* ADC connection */
  966. { "ADC Left", NULL, "ADCL Mux"},
  967. { "ADC Right", NULL, "ADCR Mux"},
  968. { "DMIC1 Left", NULL, "DMIC1DAT"},
  969. { "DMIC1 Right", NULL, "DMIC1DAT"},
  970. { "DMIC2 Left", NULL, "DMIC2DAT"},
  971. { "DMIC2 Right", NULL, "DMIC2DAT"},
  972. /* Sidetone map */
  973. { "Sidetone Mixer", NULL, "ADC Left" },
  974. { "Sidetone Mixer", NULL, "ADC Right" },
  975. { "Sidetone Mixer", NULL, "DMIC1 Left" },
  976. { "Sidetone Mixer", NULL, "DMIC1 Right" },
  977. { "Sidetone Mixer", NULL, "DMIC2 Left" },
  978. { "Sidetone Mixer", NULL, "DMIC2 Right" },
  979. { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
  980. };
  981. static int lm49453_hw_params(struct snd_pcm_substream *substream,
  982. struct snd_pcm_hw_params *params,
  983. struct snd_soc_dai *dai)
  984. {
  985. struct snd_soc_codec *codec = dai->codec;
  986. struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
  987. u16 clk_div = 0;
  988. lm49453->fs_rate = params_rate(params);
  989. /* Setting DAC clock dividers based on substream sample rate. */
  990. switch (lm49453->fs_rate) {
  991. case 8000:
  992. case 16000:
  993. case 32000:
  994. case 24000:
  995. case 48000:
  996. clk_div = 256;
  997. break;
  998. case 11025:
  999. case 22050:
  1000. case 44100:
  1001. clk_div = 216;
  1002. break;
  1003. case 96000:
  1004. clk_div = 127;
  1005. break;
  1006. default:
  1007. return -EINVAL;
  1008. }
  1009. snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
  1010. snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
  1011. return 0;
  1012. }
  1013. static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  1014. {
  1015. struct snd_soc_codec *codec = codec_dai->codec;
  1016. u16 aif_val;
  1017. int mode = 0;
  1018. int clk_phase = 0;
  1019. int clk_shift = 0;
  1020. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1021. case SND_SOC_DAIFMT_CBS_CFS:
  1022. aif_val = 0;
  1023. break;
  1024. case SND_SOC_DAIFMT_CBS_CFM:
  1025. aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
  1026. break;
  1027. case SND_SOC_DAIFMT_CBM_CFS:
  1028. aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
  1029. break;
  1030. case SND_SOC_DAIFMT_CBM_CFM:
  1031. aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
  1032. LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
  1033. break;
  1034. default:
  1035. return -EINVAL;
  1036. }
  1037. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1038. case SND_SOC_DAIFMT_I2S:
  1039. break;
  1040. case SND_SOC_DAIFMT_DSP_A:
  1041. mode = 1;
  1042. clk_phase = (1 << 5);
  1043. clk_shift = 1;
  1044. break;
  1045. case SND_SOC_DAIFMT_DSP_B:
  1046. mode = 1;
  1047. clk_phase = (1 << 5);
  1048. clk_shift = 0;
  1049. break;
  1050. default:
  1051. return -EINVAL;
  1052. }
  1053. snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
  1054. LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
  1055. (aif_val | mode | clk_phase));
  1056. snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
  1057. return 0;
  1058. }
  1059. static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  1060. unsigned int freq, int dir)
  1061. {
  1062. struct snd_soc_codec *codec = dai->codec;
  1063. u16 pll_clk = 0;
  1064. switch (freq) {
  1065. case 12288000:
  1066. case 26000000:
  1067. case 19200000:
  1068. /* pll clk slection */
  1069. pll_clk = 0;
  1070. break;
  1071. case 48000:
  1072. case 32576:
  1073. /* fll clk slection */
  1074. pll_clk = BIT(4);
  1075. return 0;
  1076. default:
  1077. return -EINVAL;
  1078. }
  1079. snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
  1080. return 0;
  1081. }
  1082. static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
  1083. {
  1084. snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
  1085. (mute ? (BIT(1)|BIT(0)) : 0));
  1086. return 0;
  1087. }
  1088. static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
  1089. {
  1090. snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
  1091. (mute ? (BIT(3)|BIT(2)) : 0));
  1092. return 0;
  1093. }
  1094. static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
  1095. {
  1096. snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
  1097. (mute ? (BIT(5)|BIT(4)) : 0));
  1098. return 0;
  1099. }
  1100. static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
  1101. {
  1102. snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
  1103. (mute ? BIT(4) : 0));
  1104. return 0;
  1105. }
  1106. static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
  1107. {
  1108. snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
  1109. (mute ? (BIT(7)|BIT(6)) : 0));
  1110. return 0;
  1111. }
  1112. static int lm49453_set_bias_level(struct snd_soc_codec *codec,
  1113. enum snd_soc_bias_level level)
  1114. {
  1115. struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
  1116. switch (level) {
  1117. case SND_SOC_BIAS_ON:
  1118. case SND_SOC_BIAS_PREPARE:
  1119. break;
  1120. case SND_SOC_BIAS_STANDBY:
  1121. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
  1122. regcache_sync(lm49453->regmap);
  1123. snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
  1124. LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
  1125. break;
  1126. case SND_SOC_BIAS_OFF:
  1127. snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
  1128. LM49453_PMC_SETUP_CHIP_EN, 0);
  1129. break;
  1130. }
  1131. codec->dapm.bias_level = level;
  1132. return 0;
  1133. }
  1134. /* Formates supported by LM49453 driver. */
  1135. #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1136. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1137. static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
  1138. .hw_params = lm49453_hw_params,
  1139. .set_sysclk = lm49453_set_dai_sysclk,
  1140. .set_fmt = lm49453_set_dai_fmt,
  1141. .digital_mute = lm49453_hp_mute,
  1142. };
  1143. static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
  1144. .hw_params = lm49453_hw_params,
  1145. .set_sysclk = lm49453_set_dai_sysclk,
  1146. .set_fmt = lm49453_set_dai_fmt,
  1147. .digital_mute = lm49453_ls_mute,
  1148. };
  1149. static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
  1150. .hw_params = lm49453_hw_params,
  1151. .set_sysclk = lm49453_set_dai_sysclk,
  1152. .set_fmt = lm49453_set_dai_fmt,
  1153. .digital_mute = lm49453_ha_mute,
  1154. };
  1155. static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
  1156. .hw_params = lm49453_hw_params,
  1157. .set_sysclk = lm49453_set_dai_sysclk,
  1158. .set_fmt = lm49453_set_dai_fmt,
  1159. .digital_mute = lm49453_ep_mute,
  1160. };
  1161. static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
  1162. .hw_params = lm49453_hw_params,
  1163. .set_sysclk = lm49453_set_dai_sysclk,
  1164. .set_fmt = lm49453_set_dai_fmt,
  1165. .digital_mute = lm49453_lo_mute,
  1166. };
  1167. /* LM49453 dai structure. */
  1168. static struct snd_soc_dai_driver lm49453_dai[] = {
  1169. {
  1170. .name = "LM49453 Headset",
  1171. .playback = {
  1172. .stream_name = "Headset",
  1173. .channels_min = 2,
  1174. .channels_max = 2,
  1175. .rates = SNDRV_PCM_RATE_8000_192000,
  1176. .formats = LM49453_FORMATS,
  1177. },
  1178. .capture = {
  1179. .stream_name = "Capture",
  1180. .channels_min = 1,
  1181. .channels_max = 5,
  1182. .rates = SNDRV_PCM_RATE_8000_192000,
  1183. .formats = LM49453_FORMATS,
  1184. },
  1185. .ops = &lm49453_headset_dai_ops,
  1186. .symmetric_rates = 1,
  1187. },
  1188. {
  1189. .name = "LM49453 Speaker",
  1190. .playback = {
  1191. .stream_name = "Speaker",
  1192. .channels_min = 2,
  1193. .channels_max = 2,
  1194. .rates = SNDRV_PCM_RATE_8000_192000,
  1195. .formats = LM49453_FORMATS,
  1196. },
  1197. .ops = &lm49453_speaker_dai_ops,
  1198. },
  1199. {
  1200. .name = "LM49453 Haptic",
  1201. .playback = {
  1202. .stream_name = "Haptic",
  1203. .channels_min = 2,
  1204. .channels_max = 2,
  1205. .rates = SNDRV_PCM_RATE_8000_192000,
  1206. .formats = LM49453_FORMATS,
  1207. },
  1208. .ops = &lm49453_haptic_dai_ops,
  1209. },
  1210. {
  1211. .name = "LM49453 Earpiece",
  1212. .playback = {
  1213. .stream_name = "Earpiece",
  1214. .channels_min = 1,
  1215. .channels_max = 1,
  1216. .rates = SNDRV_PCM_RATE_8000_192000,
  1217. .formats = LM49453_FORMATS,
  1218. },
  1219. .ops = &lm49453_ep_dai_ops,
  1220. },
  1221. {
  1222. .name = "LM49453 line out",
  1223. .playback = {
  1224. .stream_name = "Lineout",
  1225. .channels_min = 2,
  1226. .channels_max = 2,
  1227. .rates = SNDRV_PCM_RATE_8000_192000,
  1228. .formats = LM49453_FORMATS,
  1229. },
  1230. .ops = &lm49453_lineout_dai_ops,
  1231. },
  1232. };
  1233. static int lm49453_suspend(struct snd_soc_codec *codec)
  1234. {
  1235. lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1236. return 0;
  1237. }
  1238. static int lm49453_resume(struct snd_soc_codec *codec)
  1239. {
  1240. lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1241. return 0;
  1242. }
  1243. static int lm49453_probe(struct snd_soc_codec *codec)
  1244. {
  1245. struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
  1246. int ret = 0;
  1247. codec->control_data = lm49453->regmap;
  1248. ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
  1249. if (ret < 0) {
  1250. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1251. return ret;
  1252. }
  1253. return 0;
  1254. }
  1255. /* power down chip */
  1256. static int lm49453_remove(struct snd_soc_codec *codec)
  1257. {
  1258. lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1259. return 0;
  1260. }
  1261. static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
  1262. .probe = lm49453_probe,
  1263. .remove = lm49453_remove,
  1264. .suspend = lm49453_suspend,
  1265. .resume = lm49453_resume,
  1266. .set_bias_level = lm49453_set_bias_level,
  1267. .controls = lm49453_snd_controls,
  1268. .num_controls = ARRAY_SIZE(lm49453_snd_controls),
  1269. .dapm_widgets = lm49453_dapm_widgets,
  1270. .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
  1271. .dapm_routes = lm49453_audio_map,
  1272. .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
  1273. .idle_bias_off = true,
  1274. };
  1275. static const struct regmap_config lm49453_regmap_config = {
  1276. .reg_bits = 8,
  1277. .val_bits = 8,
  1278. .max_register = LM49453_MAX_REGISTER,
  1279. .reg_defaults = lm49453_reg_defs,
  1280. .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
  1281. .cache_type = REGCACHE_RBTREE,
  1282. };
  1283. static int lm49453_i2c_probe(struct i2c_client *i2c,
  1284. const struct i2c_device_id *id)
  1285. {
  1286. struct lm49453_priv *lm49453;
  1287. int ret = 0;
  1288. lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
  1289. GFP_KERNEL);
  1290. if (lm49453 == NULL)
  1291. return -ENOMEM;
  1292. i2c_set_clientdata(i2c, lm49453);
  1293. lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
  1294. if (IS_ERR(lm49453->regmap)) {
  1295. ret = PTR_ERR(lm49453->regmap);
  1296. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1297. ret);
  1298. return ret;
  1299. }
  1300. ret = snd_soc_register_codec(&i2c->dev,
  1301. &soc_codec_dev_lm49453,
  1302. lm49453_dai, ARRAY_SIZE(lm49453_dai));
  1303. if (ret < 0)
  1304. dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
  1305. return ret;
  1306. }
  1307. static int lm49453_i2c_remove(struct i2c_client *client)
  1308. {
  1309. snd_soc_unregister_codec(&client->dev);
  1310. return 0;
  1311. }
  1312. static const struct i2c_device_id lm49453_i2c_id[] = {
  1313. { "lm49453", 0 },
  1314. { }
  1315. };
  1316. MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
  1317. static struct i2c_driver lm49453_i2c_driver = {
  1318. .driver = {
  1319. .name = "lm49453",
  1320. .owner = THIS_MODULE,
  1321. },
  1322. .probe = lm49453_i2c_probe,
  1323. .remove = lm49453_i2c_remove,
  1324. .id_table = lm49453_i2c_id,
  1325. };
  1326. module_i2c_driver(lm49453_i2c_driver);
  1327. MODULE_DESCRIPTION("ASoC LM49453 driver");
  1328. MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
  1329. MODULE_LICENSE("GPL v2");