ymfpci_main.c 72 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/firmware.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/sched.h>
  26. #include <linux/slab.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <sound/core.h>
  30. #include <sound/control.h>
  31. #include <sound/info.h>
  32. #include <sound/tlv.h>
  33. #include "ymfpci.h"
  34. #include <sound/asoundef.h>
  35. #include <sound/mpu401.h>
  36. #include <asm/io.h>
  37. #include <asm/byteorder.h>
  38. /*
  39. * common I/O routines
  40. */
  41. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  42. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  43. {
  44. return readb(chip->reg_area_virt + offset);
  45. }
  46. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  47. {
  48. writeb(val, chip->reg_area_virt + offset);
  49. }
  50. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  51. {
  52. return readw(chip->reg_area_virt + offset);
  53. }
  54. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  55. {
  56. writew(val, chip->reg_area_virt + offset);
  57. }
  58. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  59. {
  60. return readl(chip->reg_area_virt + offset);
  61. }
  62. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  63. {
  64. writel(val, chip->reg_area_virt + offset);
  65. }
  66. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  67. {
  68. unsigned long end_time;
  69. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  70. end_time = jiffies + msecs_to_jiffies(750);
  71. do {
  72. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  73. return 0;
  74. schedule_timeout_uninterruptible(1);
  75. } while (time_before(jiffies, end_time));
  76. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  77. return -EBUSY;
  78. }
  79. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  80. {
  81. struct snd_ymfpci *chip = ac97->private_data;
  82. u32 cmd;
  83. snd_ymfpci_codec_ready(chip, 0);
  84. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  85. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  86. }
  87. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  88. {
  89. struct snd_ymfpci *chip = ac97->private_data;
  90. if (snd_ymfpci_codec_ready(chip, 0))
  91. return ~0;
  92. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  93. if (snd_ymfpci_codec_ready(chip, 0))
  94. return ~0;
  95. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  96. int i;
  97. for (i = 0; i < 600; i++)
  98. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  99. }
  100. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  101. }
  102. /*
  103. * Misc routines
  104. */
  105. static u32 snd_ymfpci_calc_delta(u32 rate)
  106. {
  107. switch (rate) {
  108. case 8000: return 0x02aaab00;
  109. case 11025: return 0x03accd00;
  110. case 16000: return 0x05555500;
  111. case 22050: return 0x07599a00;
  112. case 32000: return 0x0aaaab00;
  113. case 44100: return 0x0eb33300;
  114. default: return ((rate << 16) / 375) << 5;
  115. }
  116. }
  117. static u32 def_rate[8] = {
  118. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  119. };
  120. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  121. {
  122. u32 i;
  123. static u32 val[8] = {
  124. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  125. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  126. };
  127. if (rate == 44100)
  128. return 0x40000000; /* FIXME: What's the right value? */
  129. for (i = 0; i < 8; i++)
  130. if (rate <= def_rate[i])
  131. return val[i];
  132. return val[0];
  133. }
  134. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  135. {
  136. u32 i;
  137. static u32 val[8] = {
  138. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  139. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  140. };
  141. if (rate == 44100)
  142. return 0x370A0000;
  143. for (i = 0; i < 8; i++)
  144. if (rate <= def_rate[i])
  145. return val[i];
  146. return val[0];
  147. }
  148. /*
  149. * Hardware start management
  150. */
  151. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  152. {
  153. unsigned long flags;
  154. spin_lock_irqsave(&chip->reg_lock, flags);
  155. if (chip->start_count++ > 0)
  156. goto __end;
  157. snd_ymfpci_writel(chip, YDSXGR_MODE,
  158. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  159. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  160. __end:
  161. spin_unlock_irqrestore(&chip->reg_lock, flags);
  162. }
  163. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  164. {
  165. unsigned long flags;
  166. long timeout = 1000;
  167. spin_lock_irqsave(&chip->reg_lock, flags);
  168. if (--chip->start_count > 0)
  169. goto __end;
  170. snd_ymfpci_writel(chip, YDSXGR_MODE,
  171. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  172. while (timeout-- > 0) {
  173. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  174. break;
  175. }
  176. if (atomic_read(&chip->interrupt_sleep_count)) {
  177. atomic_set(&chip->interrupt_sleep_count, 0);
  178. wake_up(&chip->interrupt_sleep);
  179. }
  180. __end:
  181. spin_unlock_irqrestore(&chip->reg_lock, flags);
  182. }
  183. /*
  184. * Playback voice management
  185. */
  186. static int voice_alloc(struct snd_ymfpci *chip,
  187. enum snd_ymfpci_voice_type type, int pair,
  188. struct snd_ymfpci_voice **rvoice)
  189. {
  190. struct snd_ymfpci_voice *voice, *voice2;
  191. int idx;
  192. *rvoice = NULL;
  193. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  194. voice = &chip->voices[idx];
  195. voice2 = pair ? &chip->voices[idx+1] : NULL;
  196. if (voice->use || (voice2 && voice2->use))
  197. continue;
  198. voice->use = 1;
  199. if (voice2)
  200. voice2->use = 1;
  201. switch (type) {
  202. case YMFPCI_PCM:
  203. voice->pcm = 1;
  204. if (voice2)
  205. voice2->pcm = 1;
  206. break;
  207. case YMFPCI_SYNTH:
  208. voice->synth = 1;
  209. break;
  210. case YMFPCI_MIDI:
  211. voice->midi = 1;
  212. break;
  213. }
  214. snd_ymfpci_hw_start(chip);
  215. if (voice2)
  216. snd_ymfpci_hw_start(chip);
  217. *rvoice = voice;
  218. return 0;
  219. }
  220. return -ENOMEM;
  221. }
  222. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  223. enum snd_ymfpci_voice_type type, int pair,
  224. struct snd_ymfpci_voice **rvoice)
  225. {
  226. unsigned long flags;
  227. int result;
  228. if (snd_BUG_ON(!rvoice))
  229. return -EINVAL;
  230. if (snd_BUG_ON(pair && type != YMFPCI_PCM))
  231. return -EINVAL;
  232. spin_lock_irqsave(&chip->voice_lock, flags);
  233. for (;;) {
  234. result = voice_alloc(chip, type, pair, rvoice);
  235. if (result == 0 || type != YMFPCI_PCM)
  236. break;
  237. /* TODO: synth/midi voice deallocation */
  238. break;
  239. }
  240. spin_unlock_irqrestore(&chip->voice_lock, flags);
  241. return result;
  242. }
  243. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  244. {
  245. unsigned long flags;
  246. if (snd_BUG_ON(!pvoice))
  247. return -EINVAL;
  248. snd_ymfpci_hw_stop(chip);
  249. spin_lock_irqsave(&chip->voice_lock, flags);
  250. if (pvoice->number == chip->src441_used) {
  251. chip->src441_used = -1;
  252. pvoice->ypcm->use_441_slot = 0;
  253. }
  254. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  255. pvoice->ypcm = NULL;
  256. pvoice->interrupt = NULL;
  257. spin_unlock_irqrestore(&chip->voice_lock, flags);
  258. return 0;
  259. }
  260. /*
  261. * PCM part
  262. */
  263. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  264. {
  265. struct snd_ymfpci_pcm *ypcm;
  266. u32 pos, delta;
  267. if ((ypcm = voice->ypcm) == NULL)
  268. return;
  269. if (ypcm->substream == NULL)
  270. return;
  271. spin_lock(&chip->reg_lock);
  272. if (ypcm->running) {
  273. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  274. if (pos < ypcm->last_pos)
  275. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  276. else
  277. delta = pos - ypcm->last_pos;
  278. ypcm->period_pos += delta;
  279. ypcm->last_pos = pos;
  280. if (ypcm->period_pos >= ypcm->period_size) {
  281. /*
  282. printk(KERN_DEBUG
  283. "done - active_bank = 0x%x, start = 0x%x\n",
  284. chip->active_bank,
  285. voice->bank[chip->active_bank].start);
  286. */
  287. ypcm->period_pos %= ypcm->period_size;
  288. spin_unlock(&chip->reg_lock);
  289. snd_pcm_period_elapsed(ypcm->substream);
  290. spin_lock(&chip->reg_lock);
  291. }
  292. if (unlikely(ypcm->update_pcm_vol)) {
  293. unsigned int subs = ypcm->substream->number;
  294. unsigned int next_bank = 1 - chip->active_bank;
  295. struct snd_ymfpci_playback_bank *bank;
  296. u32 volume;
  297. bank = &voice->bank[next_bank];
  298. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  299. bank->left_gain_end = volume;
  300. if (ypcm->output_rear)
  301. bank->eff2_gain_end = volume;
  302. if (ypcm->voices[1])
  303. bank = &ypcm->voices[1]->bank[next_bank];
  304. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  305. bank->right_gain_end = volume;
  306. if (ypcm->output_rear)
  307. bank->eff3_gain_end = volume;
  308. ypcm->update_pcm_vol--;
  309. }
  310. }
  311. spin_unlock(&chip->reg_lock);
  312. }
  313. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  314. {
  315. struct snd_pcm_runtime *runtime = substream->runtime;
  316. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  317. struct snd_ymfpci *chip = ypcm->chip;
  318. u32 pos, delta;
  319. spin_lock(&chip->reg_lock);
  320. if (ypcm->running) {
  321. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  322. if (pos < ypcm->last_pos)
  323. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  324. else
  325. delta = pos - ypcm->last_pos;
  326. ypcm->period_pos += delta;
  327. ypcm->last_pos = pos;
  328. if (ypcm->period_pos >= ypcm->period_size) {
  329. ypcm->period_pos %= ypcm->period_size;
  330. /*
  331. printk(KERN_DEBUG
  332. "done - active_bank = 0x%x, start = 0x%x\n",
  333. chip->active_bank,
  334. voice->bank[chip->active_bank].start);
  335. */
  336. spin_unlock(&chip->reg_lock);
  337. snd_pcm_period_elapsed(substream);
  338. spin_lock(&chip->reg_lock);
  339. }
  340. }
  341. spin_unlock(&chip->reg_lock);
  342. }
  343. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  344. int cmd)
  345. {
  346. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  347. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  348. struct snd_kcontrol *kctl = NULL;
  349. int result = 0;
  350. spin_lock(&chip->reg_lock);
  351. if (ypcm->voices[0] == NULL) {
  352. result = -EINVAL;
  353. goto __unlock;
  354. }
  355. switch (cmd) {
  356. case SNDRV_PCM_TRIGGER_START:
  357. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  358. case SNDRV_PCM_TRIGGER_RESUME:
  359. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  360. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  361. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  362. ypcm->running = 1;
  363. break;
  364. case SNDRV_PCM_TRIGGER_STOP:
  365. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  366. kctl = chip->pcm_mixer[substream->number].ctl;
  367. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  368. }
  369. /* fall through */
  370. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  371. case SNDRV_PCM_TRIGGER_SUSPEND:
  372. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  373. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  374. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  375. ypcm->running = 0;
  376. break;
  377. default:
  378. result = -EINVAL;
  379. break;
  380. }
  381. __unlock:
  382. spin_unlock(&chip->reg_lock);
  383. if (kctl)
  384. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  385. return result;
  386. }
  387. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  388. int cmd)
  389. {
  390. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  391. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  392. int result = 0;
  393. u32 tmp;
  394. spin_lock(&chip->reg_lock);
  395. switch (cmd) {
  396. case SNDRV_PCM_TRIGGER_START:
  397. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  398. case SNDRV_PCM_TRIGGER_RESUME:
  399. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  400. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  401. ypcm->running = 1;
  402. break;
  403. case SNDRV_PCM_TRIGGER_STOP:
  404. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  405. case SNDRV_PCM_TRIGGER_SUSPEND:
  406. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  407. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  408. ypcm->running = 0;
  409. break;
  410. default:
  411. result = -EINVAL;
  412. break;
  413. }
  414. spin_unlock(&chip->reg_lock);
  415. return result;
  416. }
  417. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  418. {
  419. int err;
  420. if (ypcm->voices[1] != NULL && voices < 2) {
  421. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  422. ypcm->voices[1] = NULL;
  423. }
  424. if (voices == 1 && ypcm->voices[0] != NULL)
  425. return 0; /* already allocated */
  426. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  427. return 0; /* already allocated */
  428. if (voices > 1) {
  429. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  430. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  431. ypcm->voices[0] = NULL;
  432. }
  433. }
  434. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  435. if (err < 0)
  436. return err;
  437. ypcm->voices[0]->ypcm = ypcm;
  438. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  439. if (voices > 1) {
  440. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  441. ypcm->voices[1]->ypcm = ypcm;
  442. }
  443. return 0;
  444. }
  445. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  446. struct snd_pcm_runtime *runtime,
  447. int has_pcm_volume)
  448. {
  449. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  450. u32 format;
  451. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  452. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  453. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  454. struct snd_ymfpci_playback_bank *bank;
  455. unsigned int nbank;
  456. u32 vol_left, vol_right;
  457. u8 use_left, use_right;
  458. unsigned long flags;
  459. if (snd_BUG_ON(!voice))
  460. return;
  461. if (runtime->channels == 1) {
  462. use_left = 1;
  463. use_right = 1;
  464. } else {
  465. use_left = (voiceidx & 1) == 0;
  466. use_right = !use_left;
  467. }
  468. if (has_pcm_volume) {
  469. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  470. [ypcm->substream->number].left << 15);
  471. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  472. [ypcm->substream->number].right << 15);
  473. } else {
  474. vol_left = cpu_to_le32(0x40000000);
  475. vol_right = cpu_to_le32(0x40000000);
  476. }
  477. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  478. format = runtime->channels == 2 ? 0x00010000 : 0;
  479. if (snd_pcm_format_width(runtime->format) == 8)
  480. format |= 0x80000000;
  481. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  482. runtime->rate == 44100 && runtime->channels == 2 &&
  483. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  484. ypcm->chip->src441_used == voice->number)) {
  485. ypcm->chip->src441_used = voice->number;
  486. ypcm->use_441_slot = 1;
  487. format |= 0x10000000;
  488. }
  489. if (ypcm->chip->src441_used == voice->number &&
  490. (format & 0x10000000) == 0) {
  491. ypcm->chip->src441_used = -1;
  492. ypcm->use_441_slot = 0;
  493. }
  494. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  495. format |= 1;
  496. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  497. for (nbank = 0; nbank < 2; nbank++) {
  498. bank = &voice->bank[nbank];
  499. memset(bank, 0, sizeof(*bank));
  500. bank->format = cpu_to_le32(format);
  501. bank->base = cpu_to_le32(runtime->dma_addr);
  502. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  503. bank->lpfQ = cpu_to_le32(lpfQ);
  504. bank->delta =
  505. bank->delta_end = cpu_to_le32(delta);
  506. bank->lpfK =
  507. bank->lpfK_end = cpu_to_le32(lpfK);
  508. bank->eg_gain =
  509. bank->eg_gain_end = cpu_to_le32(0x40000000);
  510. if (ypcm->output_front) {
  511. if (use_left) {
  512. bank->left_gain =
  513. bank->left_gain_end = vol_left;
  514. }
  515. if (use_right) {
  516. bank->right_gain =
  517. bank->right_gain_end = vol_right;
  518. }
  519. }
  520. if (ypcm->output_rear) {
  521. if (!ypcm->swap_rear) {
  522. if (use_left) {
  523. bank->eff2_gain =
  524. bank->eff2_gain_end = vol_left;
  525. }
  526. if (use_right) {
  527. bank->eff3_gain =
  528. bank->eff3_gain_end = vol_right;
  529. }
  530. } else {
  531. /* The SPDIF out channels seem to be swapped, so we have
  532. * to swap them here, too. The rear analog out channels
  533. * will be wrong, but otherwise AC3 would not work.
  534. */
  535. if (use_left) {
  536. bank->eff3_gain =
  537. bank->eff3_gain_end = vol_left;
  538. }
  539. if (use_right) {
  540. bank->eff2_gain =
  541. bank->eff2_gain_end = vol_right;
  542. }
  543. }
  544. }
  545. }
  546. }
  547. static int snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  548. {
  549. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  550. 4096, &chip->ac3_tmp_base) < 0)
  551. return -ENOMEM;
  552. chip->bank_effect[3][0]->base =
  553. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  554. chip->bank_effect[3][0]->loop_end =
  555. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  556. chip->bank_effect[4][0]->base =
  557. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  558. chip->bank_effect[4][0]->loop_end =
  559. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  560. spin_lock_irq(&chip->reg_lock);
  561. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  562. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  563. spin_unlock_irq(&chip->reg_lock);
  564. return 0;
  565. }
  566. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  567. {
  568. spin_lock_irq(&chip->reg_lock);
  569. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  570. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  571. spin_unlock_irq(&chip->reg_lock);
  572. // snd_ymfpci_irq_wait(chip);
  573. if (chip->ac3_tmp_base.area) {
  574. snd_dma_free_pages(&chip->ac3_tmp_base);
  575. chip->ac3_tmp_base.area = NULL;
  576. }
  577. return 0;
  578. }
  579. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  580. struct snd_pcm_hw_params *hw_params)
  581. {
  582. struct snd_pcm_runtime *runtime = substream->runtime;
  583. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  584. int err;
  585. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  586. return err;
  587. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  588. return err;
  589. return 0;
  590. }
  591. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  592. {
  593. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  594. struct snd_pcm_runtime *runtime = substream->runtime;
  595. struct snd_ymfpci_pcm *ypcm;
  596. if (runtime->private_data == NULL)
  597. return 0;
  598. ypcm = runtime->private_data;
  599. /* wait, until the PCI operations are not finished */
  600. snd_ymfpci_irq_wait(chip);
  601. snd_pcm_lib_free_pages(substream);
  602. if (ypcm->voices[1]) {
  603. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  604. ypcm->voices[1] = NULL;
  605. }
  606. if (ypcm->voices[0]) {
  607. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  608. ypcm->voices[0] = NULL;
  609. }
  610. return 0;
  611. }
  612. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  613. {
  614. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  615. struct snd_pcm_runtime *runtime = substream->runtime;
  616. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  617. struct snd_kcontrol *kctl;
  618. unsigned int nvoice;
  619. ypcm->period_size = runtime->period_size;
  620. ypcm->buffer_size = runtime->buffer_size;
  621. ypcm->period_pos = 0;
  622. ypcm->last_pos = 0;
  623. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  624. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  625. substream->pcm == chip->pcm);
  626. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  627. kctl = chip->pcm_mixer[substream->number].ctl;
  628. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  629. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  630. }
  631. return 0;
  632. }
  633. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  634. struct snd_pcm_hw_params *hw_params)
  635. {
  636. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  637. }
  638. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  639. {
  640. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  641. /* wait, until the PCI operations are not finished */
  642. snd_ymfpci_irq_wait(chip);
  643. return snd_pcm_lib_free_pages(substream);
  644. }
  645. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  646. {
  647. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  648. struct snd_pcm_runtime *runtime = substream->runtime;
  649. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  650. struct snd_ymfpci_capture_bank * bank;
  651. int nbank;
  652. u32 rate, format;
  653. ypcm->period_size = runtime->period_size;
  654. ypcm->buffer_size = runtime->buffer_size;
  655. ypcm->period_pos = 0;
  656. ypcm->last_pos = 0;
  657. ypcm->shift = 0;
  658. rate = ((48000 * 4096) / runtime->rate) - 1;
  659. format = 0;
  660. if (runtime->channels == 2) {
  661. format |= 2;
  662. ypcm->shift++;
  663. }
  664. if (snd_pcm_format_width(runtime->format) == 8)
  665. format |= 1;
  666. else
  667. ypcm->shift++;
  668. switch (ypcm->capture_bank_number) {
  669. case 0:
  670. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  671. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  672. break;
  673. case 1:
  674. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  675. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  676. break;
  677. }
  678. for (nbank = 0; nbank < 2; nbank++) {
  679. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  680. bank->base = cpu_to_le32(runtime->dma_addr);
  681. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  682. bank->start = 0;
  683. bank->num_of_loops = 0;
  684. }
  685. return 0;
  686. }
  687. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  688. {
  689. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  690. struct snd_pcm_runtime *runtime = substream->runtime;
  691. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  692. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  693. if (!(ypcm->running && voice))
  694. return 0;
  695. return le32_to_cpu(voice->bank[chip->active_bank].start);
  696. }
  697. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  698. {
  699. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  700. struct snd_pcm_runtime *runtime = substream->runtime;
  701. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  702. if (!ypcm->running)
  703. return 0;
  704. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  705. }
  706. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  707. {
  708. wait_queue_t wait;
  709. int loops = 4;
  710. while (loops-- > 0) {
  711. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  712. continue;
  713. init_waitqueue_entry(&wait, current);
  714. add_wait_queue(&chip->interrupt_sleep, &wait);
  715. atomic_inc(&chip->interrupt_sleep_count);
  716. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  717. remove_wait_queue(&chip->interrupt_sleep, &wait);
  718. }
  719. }
  720. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  721. {
  722. struct snd_ymfpci *chip = dev_id;
  723. u32 status, nvoice, mode;
  724. struct snd_ymfpci_voice *voice;
  725. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  726. if (status & 0x80000000) {
  727. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  728. spin_lock(&chip->voice_lock);
  729. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  730. voice = &chip->voices[nvoice];
  731. if (voice->interrupt)
  732. voice->interrupt(chip, voice);
  733. }
  734. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  735. if (chip->capture_substream[nvoice])
  736. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  737. }
  738. #if 0
  739. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  740. if (chip->effect_substream[nvoice])
  741. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  742. }
  743. #endif
  744. spin_unlock(&chip->voice_lock);
  745. spin_lock(&chip->reg_lock);
  746. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  747. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  748. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  749. spin_unlock(&chip->reg_lock);
  750. if (atomic_read(&chip->interrupt_sleep_count)) {
  751. atomic_set(&chip->interrupt_sleep_count, 0);
  752. wake_up(&chip->interrupt_sleep);
  753. }
  754. }
  755. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  756. if (status & 1) {
  757. if (chip->timer)
  758. snd_timer_interrupt(chip->timer, chip->timer_ticks);
  759. }
  760. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  761. if (chip->rawmidi)
  762. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  763. return IRQ_HANDLED;
  764. }
  765. static struct snd_pcm_hardware snd_ymfpci_playback =
  766. {
  767. .info = (SNDRV_PCM_INFO_MMAP |
  768. SNDRV_PCM_INFO_MMAP_VALID |
  769. SNDRV_PCM_INFO_INTERLEAVED |
  770. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  771. SNDRV_PCM_INFO_PAUSE |
  772. SNDRV_PCM_INFO_RESUME),
  773. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  774. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  775. .rate_min = 8000,
  776. .rate_max = 48000,
  777. .channels_min = 1,
  778. .channels_max = 2,
  779. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  780. .period_bytes_min = 64,
  781. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  782. .periods_min = 3,
  783. .periods_max = 1024,
  784. .fifo_size = 0,
  785. };
  786. static struct snd_pcm_hardware snd_ymfpci_capture =
  787. {
  788. .info = (SNDRV_PCM_INFO_MMAP |
  789. SNDRV_PCM_INFO_MMAP_VALID |
  790. SNDRV_PCM_INFO_INTERLEAVED |
  791. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  792. SNDRV_PCM_INFO_PAUSE |
  793. SNDRV_PCM_INFO_RESUME),
  794. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  795. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  796. .rate_min = 8000,
  797. .rate_max = 48000,
  798. .channels_min = 1,
  799. .channels_max = 2,
  800. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  801. .period_bytes_min = 64,
  802. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  803. .periods_min = 3,
  804. .periods_max = 1024,
  805. .fifo_size = 0,
  806. };
  807. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  808. {
  809. kfree(runtime->private_data);
  810. }
  811. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  812. {
  813. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  814. struct snd_pcm_runtime *runtime = substream->runtime;
  815. struct snd_ymfpci_pcm *ypcm;
  816. int err;
  817. runtime->hw = snd_ymfpci_playback;
  818. /* FIXME? True value is 256/48 = 5.33333 ms */
  819. err = snd_pcm_hw_constraint_minmax(runtime,
  820. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  821. 5334, UINT_MAX);
  822. if (err < 0)
  823. return err;
  824. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  825. if (err < 0)
  826. return err;
  827. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  828. if (ypcm == NULL)
  829. return -ENOMEM;
  830. ypcm->chip = chip;
  831. ypcm->type = PLAYBACK_VOICE;
  832. ypcm->substream = substream;
  833. runtime->private_data = ypcm;
  834. runtime->private_free = snd_ymfpci_pcm_free_substream;
  835. return 0;
  836. }
  837. /* call with spinlock held */
  838. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  839. {
  840. if (! chip->rear_opened) {
  841. if (! chip->spdif_opened) /* set AC3 */
  842. snd_ymfpci_writel(chip, YDSXGR_MODE,
  843. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  844. /* enable second codec (4CHEN) */
  845. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  846. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  847. }
  848. }
  849. /* call with spinlock held */
  850. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  851. {
  852. if (! chip->rear_opened) {
  853. if (! chip->spdif_opened)
  854. snd_ymfpci_writel(chip, YDSXGR_MODE,
  855. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  856. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  857. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  858. }
  859. }
  860. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  861. {
  862. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  863. struct snd_pcm_runtime *runtime = substream->runtime;
  864. struct snd_ymfpci_pcm *ypcm;
  865. int err;
  866. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  867. return err;
  868. ypcm = runtime->private_data;
  869. ypcm->output_front = 1;
  870. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  871. ypcm->swap_rear = 0;
  872. spin_lock_irq(&chip->reg_lock);
  873. if (ypcm->output_rear) {
  874. ymfpci_open_extension(chip);
  875. chip->rear_opened++;
  876. }
  877. spin_unlock_irq(&chip->reg_lock);
  878. return 0;
  879. }
  880. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  881. {
  882. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  883. struct snd_pcm_runtime *runtime = substream->runtime;
  884. struct snd_ymfpci_pcm *ypcm;
  885. int err;
  886. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  887. return err;
  888. ypcm = runtime->private_data;
  889. ypcm->output_front = 0;
  890. ypcm->output_rear = 1;
  891. ypcm->swap_rear = 1;
  892. spin_lock_irq(&chip->reg_lock);
  893. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  894. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  895. ymfpci_open_extension(chip);
  896. chip->spdif_pcm_bits = chip->spdif_bits;
  897. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  898. chip->spdif_opened++;
  899. spin_unlock_irq(&chip->reg_lock);
  900. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  901. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  902. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  903. return 0;
  904. }
  905. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  906. {
  907. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  908. struct snd_pcm_runtime *runtime = substream->runtime;
  909. struct snd_ymfpci_pcm *ypcm;
  910. int err;
  911. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  912. return err;
  913. ypcm = runtime->private_data;
  914. ypcm->output_front = 0;
  915. ypcm->output_rear = 1;
  916. ypcm->swap_rear = 0;
  917. spin_lock_irq(&chip->reg_lock);
  918. ymfpci_open_extension(chip);
  919. chip->rear_opened++;
  920. spin_unlock_irq(&chip->reg_lock);
  921. return 0;
  922. }
  923. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  924. u32 capture_bank_number)
  925. {
  926. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  927. struct snd_pcm_runtime *runtime = substream->runtime;
  928. struct snd_ymfpci_pcm *ypcm;
  929. int err;
  930. runtime->hw = snd_ymfpci_capture;
  931. /* FIXME? True value is 256/48 = 5.33333 ms */
  932. err = snd_pcm_hw_constraint_minmax(runtime,
  933. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  934. 5334, UINT_MAX);
  935. if (err < 0)
  936. return err;
  937. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  938. if (err < 0)
  939. return err;
  940. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  941. if (ypcm == NULL)
  942. return -ENOMEM;
  943. ypcm->chip = chip;
  944. ypcm->type = capture_bank_number + CAPTURE_REC;
  945. ypcm->substream = substream;
  946. ypcm->capture_bank_number = capture_bank_number;
  947. chip->capture_substream[capture_bank_number] = substream;
  948. runtime->private_data = ypcm;
  949. runtime->private_free = snd_ymfpci_pcm_free_substream;
  950. snd_ymfpci_hw_start(chip);
  951. return 0;
  952. }
  953. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  954. {
  955. return snd_ymfpci_capture_open(substream, 0);
  956. }
  957. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  958. {
  959. return snd_ymfpci_capture_open(substream, 1);
  960. }
  961. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  962. {
  963. return 0;
  964. }
  965. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  966. {
  967. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  968. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  969. spin_lock_irq(&chip->reg_lock);
  970. if (ypcm->output_rear && chip->rear_opened > 0) {
  971. chip->rear_opened--;
  972. ymfpci_close_extension(chip);
  973. }
  974. spin_unlock_irq(&chip->reg_lock);
  975. return snd_ymfpci_playback_close_1(substream);
  976. }
  977. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  978. {
  979. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  980. spin_lock_irq(&chip->reg_lock);
  981. chip->spdif_opened = 0;
  982. ymfpci_close_extension(chip);
  983. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  984. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  985. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  986. spin_unlock_irq(&chip->reg_lock);
  987. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  988. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  989. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  990. return snd_ymfpci_playback_close_1(substream);
  991. }
  992. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  993. {
  994. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  995. spin_lock_irq(&chip->reg_lock);
  996. if (chip->rear_opened > 0) {
  997. chip->rear_opened--;
  998. ymfpci_close_extension(chip);
  999. }
  1000. spin_unlock_irq(&chip->reg_lock);
  1001. return snd_ymfpci_playback_close_1(substream);
  1002. }
  1003. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  1004. {
  1005. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  1006. struct snd_pcm_runtime *runtime = substream->runtime;
  1007. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  1008. if (ypcm != NULL) {
  1009. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  1010. snd_ymfpci_hw_stop(chip);
  1011. }
  1012. return 0;
  1013. }
  1014. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  1015. .open = snd_ymfpci_playback_open,
  1016. .close = snd_ymfpci_playback_close,
  1017. .ioctl = snd_pcm_lib_ioctl,
  1018. .hw_params = snd_ymfpci_playback_hw_params,
  1019. .hw_free = snd_ymfpci_playback_hw_free,
  1020. .prepare = snd_ymfpci_playback_prepare,
  1021. .trigger = snd_ymfpci_playback_trigger,
  1022. .pointer = snd_ymfpci_playback_pointer,
  1023. };
  1024. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  1025. .open = snd_ymfpci_capture_rec_open,
  1026. .close = snd_ymfpci_capture_close,
  1027. .ioctl = snd_pcm_lib_ioctl,
  1028. .hw_params = snd_ymfpci_capture_hw_params,
  1029. .hw_free = snd_ymfpci_capture_hw_free,
  1030. .prepare = snd_ymfpci_capture_prepare,
  1031. .trigger = snd_ymfpci_capture_trigger,
  1032. .pointer = snd_ymfpci_capture_pointer,
  1033. };
  1034. int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm)
  1035. {
  1036. struct snd_pcm *pcm;
  1037. int err;
  1038. if (rpcm)
  1039. *rpcm = NULL;
  1040. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  1041. return err;
  1042. pcm->private_data = chip;
  1043. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1044. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1045. /* global setup */
  1046. pcm->info_flags = 0;
  1047. strcpy(pcm->name, "YMFPCI");
  1048. chip->pcm = pcm;
  1049. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1050. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1051. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1052. snd_pcm_std_chmaps, 2, 0, NULL);
  1053. if (err < 0)
  1054. return err;
  1055. if (rpcm)
  1056. *rpcm = pcm;
  1057. return 0;
  1058. }
  1059. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1060. .open = snd_ymfpci_capture_ac97_open,
  1061. .close = snd_ymfpci_capture_close,
  1062. .ioctl = snd_pcm_lib_ioctl,
  1063. .hw_params = snd_ymfpci_capture_hw_params,
  1064. .hw_free = snd_ymfpci_capture_hw_free,
  1065. .prepare = snd_ymfpci_capture_prepare,
  1066. .trigger = snd_ymfpci_capture_trigger,
  1067. .pointer = snd_ymfpci_capture_pointer,
  1068. };
  1069. int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm)
  1070. {
  1071. struct snd_pcm *pcm;
  1072. int err;
  1073. if (rpcm)
  1074. *rpcm = NULL;
  1075. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1076. return err;
  1077. pcm->private_data = chip;
  1078. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1079. /* global setup */
  1080. pcm->info_flags = 0;
  1081. sprintf(pcm->name, "YMFPCI - %s",
  1082. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1083. chip->pcm2 = pcm;
  1084. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1085. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1086. if (rpcm)
  1087. *rpcm = pcm;
  1088. return 0;
  1089. }
  1090. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1091. .open = snd_ymfpci_playback_spdif_open,
  1092. .close = snd_ymfpci_playback_spdif_close,
  1093. .ioctl = snd_pcm_lib_ioctl,
  1094. .hw_params = snd_ymfpci_playback_hw_params,
  1095. .hw_free = snd_ymfpci_playback_hw_free,
  1096. .prepare = snd_ymfpci_playback_prepare,
  1097. .trigger = snd_ymfpci_playback_trigger,
  1098. .pointer = snd_ymfpci_playback_pointer,
  1099. };
  1100. int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device,
  1101. struct snd_pcm **rpcm)
  1102. {
  1103. struct snd_pcm *pcm;
  1104. int err;
  1105. if (rpcm)
  1106. *rpcm = NULL;
  1107. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1108. return err;
  1109. pcm->private_data = chip;
  1110. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1111. /* global setup */
  1112. pcm->info_flags = 0;
  1113. strcpy(pcm->name, "YMFPCI - IEC958");
  1114. chip->pcm_spdif = pcm;
  1115. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1116. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1117. if (rpcm)
  1118. *rpcm = pcm;
  1119. return 0;
  1120. }
  1121. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1122. .open = snd_ymfpci_playback_4ch_open,
  1123. .close = snd_ymfpci_playback_4ch_close,
  1124. .ioctl = snd_pcm_lib_ioctl,
  1125. .hw_params = snd_ymfpci_playback_hw_params,
  1126. .hw_free = snd_ymfpci_playback_hw_free,
  1127. .prepare = snd_ymfpci_playback_prepare,
  1128. .trigger = snd_ymfpci_playback_trigger,
  1129. .pointer = snd_ymfpci_playback_pointer,
  1130. };
  1131. static const struct snd_pcm_chmap_elem surround_map[] = {
  1132. { .channels = 1,
  1133. .map = { SNDRV_CHMAP_MONO } },
  1134. { .channels = 2,
  1135. .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  1136. { }
  1137. };
  1138. int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device,
  1139. struct snd_pcm **rpcm)
  1140. {
  1141. struct snd_pcm *pcm;
  1142. int err;
  1143. if (rpcm)
  1144. *rpcm = NULL;
  1145. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1146. return err;
  1147. pcm->private_data = chip;
  1148. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1149. /* global setup */
  1150. pcm->info_flags = 0;
  1151. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1152. chip->pcm_4ch = pcm;
  1153. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1154. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1155. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1156. surround_map, 2, 0, NULL);
  1157. if (err < 0)
  1158. return err;
  1159. if (rpcm)
  1160. *rpcm = pcm;
  1161. return 0;
  1162. }
  1163. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1164. {
  1165. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1166. uinfo->count = 1;
  1167. return 0;
  1168. }
  1169. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1170. struct snd_ctl_elem_value *ucontrol)
  1171. {
  1172. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1173. spin_lock_irq(&chip->reg_lock);
  1174. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1175. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1176. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1177. spin_unlock_irq(&chip->reg_lock);
  1178. return 0;
  1179. }
  1180. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1181. struct snd_ctl_elem_value *ucontrol)
  1182. {
  1183. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1184. unsigned int val;
  1185. int change;
  1186. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1187. (ucontrol->value.iec958.status[1] << 8);
  1188. spin_lock_irq(&chip->reg_lock);
  1189. change = chip->spdif_bits != val;
  1190. chip->spdif_bits = val;
  1191. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1192. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1193. spin_unlock_irq(&chip->reg_lock);
  1194. return change;
  1195. }
  1196. static struct snd_kcontrol_new snd_ymfpci_spdif_default =
  1197. {
  1198. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1199. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1200. .info = snd_ymfpci_spdif_default_info,
  1201. .get = snd_ymfpci_spdif_default_get,
  1202. .put = snd_ymfpci_spdif_default_put
  1203. };
  1204. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1205. {
  1206. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1207. uinfo->count = 1;
  1208. return 0;
  1209. }
  1210. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1211. struct snd_ctl_elem_value *ucontrol)
  1212. {
  1213. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1214. spin_lock_irq(&chip->reg_lock);
  1215. ucontrol->value.iec958.status[0] = 0x3e;
  1216. ucontrol->value.iec958.status[1] = 0xff;
  1217. spin_unlock_irq(&chip->reg_lock);
  1218. return 0;
  1219. }
  1220. static struct snd_kcontrol_new snd_ymfpci_spdif_mask =
  1221. {
  1222. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1223. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1224. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1225. .info = snd_ymfpci_spdif_mask_info,
  1226. .get = snd_ymfpci_spdif_mask_get,
  1227. };
  1228. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1229. {
  1230. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1231. uinfo->count = 1;
  1232. return 0;
  1233. }
  1234. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1235. struct snd_ctl_elem_value *ucontrol)
  1236. {
  1237. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1238. spin_lock_irq(&chip->reg_lock);
  1239. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1240. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1241. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1242. spin_unlock_irq(&chip->reg_lock);
  1243. return 0;
  1244. }
  1245. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1246. struct snd_ctl_elem_value *ucontrol)
  1247. {
  1248. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1249. unsigned int val;
  1250. int change;
  1251. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1252. (ucontrol->value.iec958.status[1] << 8);
  1253. spin_lock_irq(&chip->reg_lock);
  1254. change = chip->spdif_pcm_bits != val;
  1255. chip->spdif_pcm_bits = val;
  1256. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1257. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1258. spin_unlock_irq(&chip->reg_lock);
  1259. return change;
  1260. }
  1261. static struct snd_kcontrol_new snd_ymfpci_spdif_stream =
  1262. {
  1263. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1264. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1265. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1266. .info = snd_ymfpci_spdif_stream_info,
  1267. .get = snd_ymfpci_spdif_stream_get,
  1268. .put = snd_ymfpci_spdif_stream_put
  1269. };
  1270. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1271. {
  1272. static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1273. return snd_ctl_enum_info(info, 1, 3, texts);
  1274. }
  1275. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1276. {
  1277. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1278. u16 reg;
  1279. spin_lock_irq(&chip->reg_lock);
  1280. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1281. spin_unlock_irq(&chip->reg_lock);
  1282. if (!(reg & 0x100))
  1283. value->value.enumerated.item[0] = 0;
  1284. else
  1285. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1286. return 0;
  1287. }
  1288. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1289. {
  1290. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1291. u16 reg, old_reg;
  1292. spin_lock_irq(&chip->reg_lock);
  1293. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1294. if (value->value.enumerated.item[0] == 0)
  1295. reg = old_reg & ~0x100;
  1296. else
  1297. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1298. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1299. spin_unlock_irq(&chip->reg_lock);
  1300. return reg != old_reg;
  1301. }
  1302. static struct snd_kcontrol_new snd_ymfpci_drec_source = {
  1303. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1304. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1305. .name = "Direct Recording Source",
  1306. .info = snd_ymfpci_drec_source_info,
  1307. .get = snd_ymfpci_drec_source_get,
  1308. .put = snd_ymfpci_drec_source_put
  1309. };
  1310. /*
  1311. * Mixer controls
  1312. */
  1313. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1314. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1315. .info = snd_ymfpci_info_single, \
  1316. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1317. .private_value = ((reg) | ((shift) << 16)) }
  1318. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1319. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1320. struct snd_ctl_elem_value *ucontrol)
  1321. {
  1322. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1323. int reg = kcontrol->private_value & 0xffff;
  1324. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1325. unsigned int mask = 1;
  1326. switch (reg) {
  1327. case YDSXGR_SPDIFOUTCTRL: break;
  1328. case YDSXGR_SPDIFINCTRL: break;
  1329. default: return -EINVAL;
  1330. }
  1331. ucontrol->value.integer.value[0] =
  1332. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1333. return 0;
  1334. }
  1335. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1336. struct snd_ctl_elem_value *ucontrol)
  1337. {
  1338. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1339. int reg = kcontrol->private_value & 0xffff;
  1340. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1341. unsigned int mask = 1;
  1342. int change;
  1343. unsigned int val, oval;
  1344. switch (reg) {
  1345. case YDSXGR_SPDIFOUTCTRL: break;
  1346. case YDSXGR_SPDIFINCTRL: break;
  1347. default: return -EINVAL;
  1348. }
  1349. val = (ucontrol->value.integer.value[0] & mask);
  1350. val <<= shift;
  1351. spin_lock_irq(&chip->reg_lock);
  1352. oval = snd_ymfpci_readl(chip, reg);
  1353. val = (oval & ~(mask << shift)) | val;
  1354. change = val != oval;
  1355. snd_ymfpci_writel(chip, reg, val);
  1356. spin_unlock_irq(&chip->reg_lock);
  1357. return change;
  1358. }
  1359. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1360. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1361. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1362. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1363. .info = snd_ymfpci_info_double, \
  1364. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1365. .private_value = reg, \
  1366. .tlv = { .p = db_scale_native } }
  1367. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1368. {
  1369. unsigned int reg = kcontrol->private_value;
  1370. if (reg < 0x80 || reg >= 0xc0)
  1371. return -EINVAL;
  1372. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1373. uinfo->count = 2;
  1374. uinfo->value.integer.min = 0;
  1375. uinfo->value.integer.max = 16383;
  1376. return 0;
  1377. }
  1378. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1379. {
  1380. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1381. unsigned int reg = kcontrol->private_value;
  1382. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1383. unsigned int val;
  1384. if (reg < 0x80 || reg >= 0xc0)
  1385. return -EINVAL;
  1386. spin_lock_irq(&chip->reg_lock);
  1387. val = snd_ymfpci_readl(chip, reg);
  1388. spin_unlock_irq(&chip->reg_lock);
  1389. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1390. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1391. return 0;
  1392. }
  1393. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1394. {
  1395. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1396. unsigned int reg = kcontrol->private_value;
  1397. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1398. int change;
  1399. unsigned int val1, val2, oval;
  1400. if (reg < 0x80 || reg >= 0xc0)
  1401. return -EINVAL;
  1402. val1 = ucontrol->value.integer.value[0] & mask;
  1403. val2 = ucontrol->value.integer.value[1] & mask;
  1404. val1 <<= shift_left;
  1405. val2 <<= shift_right;
  1406. spin_lock_irq(&chip->reg_lock);
  1407. oval = snd_ymfpci_readl(chip, reg);
  1408. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1409. change = val1 != oval;
  1410. snd_ymfpci_writel(chip, reg, val1);
  1411. spin_unlock_irq(&chip->reg_lock);
  1412. return change;
  1413. }
  1414. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1415. struct snd_ctl_elem_value *ucontrol)
  1416. {
  1417. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1418. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1419. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1420. int change;
  1421. unsigned int value, oval;
  1422. value = ucontrol->value.integer.value[0] & 0x3fff;
  1423. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1424. spin_lock_irq(&chip->reg_lock);
  1425. oval = snd_ymfpci_readl(chip, reg);
  1426. change = value != oval;
  1427. snd_ymfpci_writel(chip, reg, value);
  1428. snd_ymfpci_writel(chip, reg2, value);
  1429. spin_unlock_irq(&chip->reg_lock);
  1430. return change;
  1431. }
  1432. /*
  1433. * 4ch duplication
  1434. */
  1435. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1436. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1437. {
  1438. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1439. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1440. return 0;
  1441. }
  1442. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1443. {
  1444. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1445. int change;
  1446. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1447. if (change)
  1448. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1449. return change;
  1450. }
  1451. static struct snd_kcontrol_new snd_ymfpci_dup4ch = {
  1452. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1453. .name = "4ch Duplication",
  1454. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1455. .info = snd_ymfpci_info_dup4ch,
  1456. .get = snd_ymfpci_get_dup4ch,
  1457. .put = snd_ymfpci_put_dup4ch,
  1458. };
  1459. static struct snd_kcontrol_new snd_ymfpci_controls[] = {
  1460. {
  1461. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1462. .name = "Wave Playback Volume",
  1463. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1464. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1465. .info = snd_ymfpci_info_double,
  1466. .get = snd_ymfpci_get_double,
  1467. .put = snd_ymfpci_put_nativedacvol,
  1468. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1469. .tlv = { .p = db_scale_native },
  1470. },
  1471. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1472. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1473. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1474. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1475. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1476. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1477. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1478. YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
  1479. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1480. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1481. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1482. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1483. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1484. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1485. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1486. };
  1487. /*
  1488. * GPIO
  1489. */
  1490. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1491. {
  1492. u16 reg, mode;
  1493. unsigned long flags;
  1494. spin_lock_irqsave(&chip->reg_lock, flags);
  1495. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1496. reg &= ~(1 << (pin + 8));
  1497. reg |= (1 << pin);
  1498. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1499. /* set the level mode for input line */
  1500. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1501. mode &= ~(3 << (pin * 2));
  1502. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1503. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1504. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1505. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1506. return (mode >> pin) & 1;
  1507. }
  1508. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1509. {
  1510. u16 reg;
  1511. unsigned long flags;
  1512. spin_lock_irqsave(&chip->reg_lock, flags);
  1513. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1514. reg &= ~(1 << pin);
  1515. reg &= ~(1 << (pin + 8));
  1516. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1517. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1518. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1519. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1520. return 0;
  1521. }
  1522. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1523. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1524. {
  1525. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1526. int pin = (int)kcontrol->private_value;
  1527. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1528. return 0;
  1529. }
  1530. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1531. {
  1532. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1533. int pin = (int)kcontrol->private_value;
  1534. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1535. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1536. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1537. return 1;
  1538. }
  1539. return 0;
  1540. }
  1541. static struct snd_kcontrol_new snd_ymfpci_rear_shared = {
  1542. .name = "Shared Rear/Line-In Switch",
  1543. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1544. .info = snd_ymfpci_gpio_sw_info,
  1545. .get = snd_ymfpci_gpio_sw_get,
  1546. .put = snd_ymfpci_gpio_sw_put,
  1547. .private_value = 2,
  1548. };
  1549. /*
  1550. * PCM voice volume
  1551. */
  1552. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1553. struct snd_ctl_elem_info *uinfo)
  1554. {
  1555. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1556. uinfo->count = 2;
  1557. uinfo->value.integer.min = 0;
  1558. uinfo->value.integer.max = 0x8000;
  1559. return 0;
  1560. }
  1561. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1562. struct snd_ctl_elem_value *ucontrol)
  1563. {
  1564. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1565. unsigned int subs = kcontrol->id.subdevice;
  1566. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1567. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1568. return 0;
  1569. }
  1570. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1571. struct snd_ctl_elem_value *ucontrol)
  1572. {
  1573. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1574. unsigned int subs = kcontrol->id.subdevice;
  1575. struct snd_pcm_substream *substream;
  1576. unsigned long flags;
  1577. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1578. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1579. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1580. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1581. if (chip->pcm_mixer[subs].left > 0x8000)
  1582. chip->pcm_mixer[subs].left = 0x8000;
  1583. if (chip->pcm_mixer[subs].right > 0x8000)
  1584. chip->pcm_mixer[subs].right = 0x8000;
  1585. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1586. spin_lock_irqsave(&chip->voice_lock, flags);
  1587. if (substream->runtime && substream->runtime->private_data) {
  1588. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1589. if (!ypcm->use_441_slot)
  1590. ypcm->update_pcm_vol = 2;
  1591. }
  1592. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1593. return 1;
  1594. }
  1595. return 0;
  1596. }
  1597. static struct snd_kcontrol_new snd_ymfpci_pcm_volume = {
  1598. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1599. .name = "PCM Playback Volume",
  1600. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1601. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1602. .info = snd_ymfpci_pcm_vol_info,
  1603. .get = snd_ymfpci_pcm_vol_get,
  1604. .put = snd_ymfpci_pcm_vol_put,
  1605. };
  1606. /*
  1607. * Mixer routines
  1608. */
  1609. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1610. {
  1611. struct snd_ymfpci *chip = bus->private_data;
  1612. chip->ac97_bus = NULL;
  1613. }
  1614. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1615. {
  1616. struct snd_ymfpci *chip = ac97->private_data;
  1617. chip->ac97 = NULL;
  1618. }
  1619. int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1620. {
  1621. struct snd_ac97_template ac97;
  1622. struct snd_kcontrol *kctl;
  1623. struct snd_pcm_substream *substream;
  1624. unsigned int idx;
  1625. int err;
  1626. static struct snd_ac97_bus_ops ops = {
  1627. .write = snd_ymfpci_codec_write,
  1628. .read = snd_ymfpci_codec_read,
  1629. };
  1630. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1631. return err;
  1632. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1633. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1634. memset(&ac97, 0, sizeof(ac97));
  1635. ac97.private_data = chip;
  1636. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1637. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1638. return err;
  1639. /* to be sure */
  1640. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1641. AC97_EA_VRA|AC97_EA_VRM, 0);
  1642. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1643. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1644. return err;
  1645. }
  1646. if (chip->ac97->ext_id & AC97_EI_SDAC) {
  1647. kctl = snd_ctl_new1(&snd_ymfpci_dup4ch, chip);
  1648. err = snd_ctl_add(chip->card, kctl);
  1649. if (err < 0)
  1650. return err;
  1651. }
  1652. /* add S/PDIF control */
  1653. if (snd_BUG_ON(!chip->pcm_spdif))
  1654. return -ENXIO;
  1655. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1656. return err;
  1657. kctl->id.device = chip->pcm_spdif->device;
  1658. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1659. return err;
  1660. kctl->id.device = chip->pcm_spdif->device;
  1661. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1662. return err;
  1663. kctl->id.device = chip->pcm_spdif->device;
  1664. chip->spdif_pcm_ctl = kctl;
  1665. /* direct recording source */
  1666. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1667. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1668. return err;
  1669. /*
  1670. * shared rear/line-in
  1671. */
  1672. if (rear_switch) {
  1673. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1674. return err;
  1675. }
  1676. /* per-voice volume */
  1677. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1678. for (idx = 0; idx < 32; ++idx) {
  1679. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1680. if (!kctl)
  1681. return -ENOMEM;
  1682. kctl->id.device = chip->pcm->device;
  1683. kctl->id.subdevice = idx;
  1684. kctl->private_value = (unsigned long)substream;
  1685. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1686. return err;
  1687. chip->pcm_mixer[idx].left = 0x8000;
  1688. chip->pcm_mixer[idx].right = 0x8000;
  1689. chip->pcm_mixer[idx].ctl = kctl;
  1690. substream = substream->next;
  1691. }
  1692. return 0;
  1693. }
  1694. /*
  1695. * timer
  1696. */
  1697. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1698. {
  1699. struct snd_ymfpci *chip;
  1700. unsigned long flags;
  1701. unsigned int count;
  1702. chip = snd_timer_chip(timer);
  1703. spin_lock_irqsave(&chip->reg_lock, flags);
  1704. if (timer->sticks > 1) {
  1705. chip->timer_ticks = timer->sticks;
  1706. count = timer->sticks - 1;
  1707. } else {
  1708. /*
  1709. * Divisor 1 is not allowed; fake it by using divisor 2 and
  1710. * counting two ticks for each interrupt.
  1711. */
  1712. chip->timer_ticks = 2;
  1713. count = 2 - 1;
  1714. }
  1715. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1716. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1717. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1718. return 0;
  1719. }
  1720. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1721. {
  1722. struct snd_ymfpci *chip;
  1723. unsigned long flags;
  1724. chip = snd_timer_chip(timer);
  1725. spin_lock_irqsave(&chip->reg_lock, flags);
  1726. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1727. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1728. return 0;
  1729. }
  1730. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1731. unsigned long *num, unsigned long *den)
  1732. {
  1733. *num = 1;
  1734. *den = 96000;
  1735. return 0;
  1736. }
  1737. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1738. .flags = SNDRV_TIMER_HW_AUTO,
  1739. .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
  1740. .ticks = 0x10000,
  1741. .start = snd_ymfpci_timer_start,
  1742. .stop = snd_ymfpci_timer_stop,
  1743. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1744. };
  1745. int snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1746. {
  1747. struct snd_timer *timer = NULL;
  1748. struct snd_timer_id tid;
  1749. int err;
  1750. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1751. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1752. tid.card = chip->card->number;
  1753. tid.device = device;
  1754. tid.subdevice = 0;
  1755. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1756. strcpy(timer->name, "YMFPCI timer");
  1757. timer->private_data = chip;
  1758. timer->hw = snd_ymfpci_timer_hw;
  1759. }
  1760. chip->timer = timer;
  1761. return err;
  1762. }
  1763. /*
  1764. * proc interface
  1765. */
  1766. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1767. struct snd_info_buffer *buffer)
  1768. {
  1769. struct snd_ymfpci *chip = entry->private_data;
  1770. int i;
  1771. snd_iprintf(buffer, "YMFPCI\n\n");
  1772. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1773. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1774. }
  1775. static int snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1776. {
  1777. struct snd_info_entry *entry;
  1778. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1779. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1780. return 0;
  1781. }
  1782. /*
  1783. * initialization routines
  1784. */
  1785. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1786. {
  1787. u8 cmd;
  1788. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1789. #if 0 // force to reset
  1790. if (cmd & 0x03) {
  1791. #endif
  1792. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1793. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1794. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1795. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1796. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1797. #if 0
  1798. }
  1799. #endif
  1800. }
  1801. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1802. {
  1803. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1804. }
  1805. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1806. {
  1807. u32 val;
  1808. int timeout = 1000;
  1809. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1810. if (val)
  1811. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1812. while (timeout-- > 0) {
  1813. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1814. if ((val & 0x00000002) == 0)
  1815. break;
  1816. }
  1817. }
  1818. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1819. {
  1820. int err, is_1e;
  1821. const char *name;
  1822. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1823. &chip->pci->dev);
  1824. if (err >= 0) {
  1825. if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
  1826. snd_printk(KERN_ERR "DSP microcode has wrong size\n");
  1827. err = -EINVAL;
  1828. }
  1829. }
  1830. if (err < 0)
  1831. return err;
  1832. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1833. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1834. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1835. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1836. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1837. err = request_firmware(&chip->controller_microcode, name,
  1838. &chip->pci->dev);
  1839. if (err >= 0) {
  1840. if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
  1841. snd_printk(KERN_ERR "controller microcode"
  1842. " has wrong size\n");
  1843. err = -EINVAL;
  1844. }
  1845. }
  1846. if (err < 0)
  1847. return err;
  1848. return 0;
  1849. }
  1850. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1851. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1852. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1853. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1854. {
  1855. int i;
  1856. u16 ctrl;
  1857. const __le32 *inst;
  1858. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1859. snd_ymfpci_disable_dsp(chip);
  1860. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1861. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1862. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1863. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1864. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1865. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1866. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1867. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1868. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1869. /* setup DSP instruction code */
  1870. inst = (const __le32 *)chip->dsp_microcode->data;
  1871. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1872. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
  1873. le32_to_cpu(inst[i]));
  1874. /* setup control instruction code */
  1875. inst = (const __le32 *)chip->controller_microcode->data;
  1876. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1877. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
  1878. le32_to_cpu(inst[i]));
  1879. snd_ymfpci_enable_dsp(chip);
  1880. }
  1881. static int snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1882. {
  1883. long size, playback_ctrl_size;
  1884. int voice, bank, reg;
  1885. u8 *ptr;
  1886. dma_addr_t ptr_addr;
  1887. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1888. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1889. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1890. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1891. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1892. size = ALIGN(playback_ctrl_size, 0x100) +
  1893. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1894. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1895. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1896. chip->work_size;
  1897. /* work_ptr must be aligned to 256 bytes, but it's already
  1898. covered with the kernel page allocation mechanism */
  1899. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1900. size, &chip->work_ptr) < 0)
  1901. return -ENOMEM;
  1902. ptr = chip->work_ptr.area;
  1903. ptr_addr = chip->work_ptr.addr;
  1904. memset(ptr, 0, size); /* for sure */
  1905. chip->bank_base_playback = ptr;
  1906. chip->bank_base_playback_addr = ptr_addr;
  1907. chip->ctrl_playback = (u32 *)ptr;
  1908. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1909. ptr += ALIGN(playback_ctrl_size, 0x100);
  1910. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1911. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1912. chip->voices[voice].number = voice;
  1913. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1914. chip->voices[voice].bank_addr = ptr_addr;
  1915. for (bank = 0; bank < 2; bank++) {
  1916. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1917. ptr += chip->bank_size_playback;
  1918. ptr_addr += chip->bank_size_playback;
  1919. }
  1920. }
  1921. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1922. ptr_addr = ALIGN(ptr_addr, 0x100);
  1923. chip->bank_base_capture = ptr;
  1924. chip->bank_base_capture_addr = ptr_addr;
  1925. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1926. for (bank = 0; bank < 2; bank++) {
  1927. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1928. ptr += chip->bank_size_capture;
  1929. ptr_addr += chip->bank_size_capture;
  1930. }
  1931. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1932. ptr_addr = ALIGN(ptr_addr, 0x100);
  1933. chip->bank_base_effect = ptr;
  1934. chip->bank_base_effect_addr = ptr_addr;
  1935. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1936. for (bank = 0; bank < 2; bank++) {
  1937. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1938. ptr += chip->bank_size_effect;
  1939. ptr_addr += chip->bank_size_effect;
  1940. }
  1941. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1942. ptr_addr = ALIGN(ptr_addr, 0x100);
  1943. chip->work_base = ptr;
  1944. chip->work_base_addr = ptr_addr;
  1945. snd_BUG_ON(ptr + chip->work_size !=
  1946. chip->work_ptr.area + chip->work_ptr.bytes);
  1947. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1948. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1949. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1950. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1951. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1952. /* S/PDIF output initialization */
  1953. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1954. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1955. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1956. /* S/PDIF input initialization */
  1957. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1958. /* digital mixer setup */
  1959. for (reg = 0x80; reg < 0xc0; reg += 4)
  1960. snd_ymfpci_writel(chip, reg, 0);
  1961. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1962. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1963. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1964. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1965. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1966. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1967. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1968. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1969. return 0;
  1970. }
  1971. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1972. {
  1973. u16 ctrl;
  1974. if (snd_BUG_ON(!chip))
  1975. return -EINVAL;
  1976. if (chip->res_reg_area) { /* don't touch busy hardware */
  1977. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1978. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1979. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1980. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1981. snd_ymfpci_disable_dsp(chip);
  1982. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1983. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1984. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1985. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1986. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1987. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1988. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1989. }
  1990. snd_ymfpci_ac3_done(chip);
  1991. /* Set PCI device to D3 state */
  1992. #if 0
  1993. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1994. * the chip again unless reboot. ACPI bug?
  1995. */
  1996. pci_set_power_state(chip->pci, 3);
  1997. #endif
  1998. #ifdef CONFIG_PM_SLEEP
  1999. kfree(chip->saved_regs);
  2000. #endif
  2001. if (chip->irq >= 0)
  2002. free_irq(chip->irq, chip);
  2003. release_and_free_resource(chip->mpu_res);
  2004. release_and_free_resource(chip->fm_res);
  2005. snd_ymfpci_free_gameport(chip);
  2006. if (chip->reg_area_virt)
  2007. iounmap(chip->reg_area_virt);
  2008. if (chip->work_ptr.area)
  2009. snd_dma_free_pages(&chip->work_ptr);
  2010. release_and_free_resource(chip->res_reg_area);
  2011. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  2012. pci_disable_device(chip->pci);
  2013. release_firmware(chip->dsp_microcode);
  2014. release_firmware(chip->controller_microcode);
  2015. kfree(chip);
  2016. return 0;
  2017. }
  2018. static int snd_ymfpci_dev_free(struct snd_device *device)
  2019. {
  2020. struct snd_ymfpci *chip = device->device_data;
  2021. return snd_ymfpci_free(chip);
  2022. }
  2023. #ifdef CONFIG_PM_SLEEP
  2024. static int saved_regs_index[] = {
  2025. /* spdif */
  2026. YDSXGR_SPDIFOUTCTRL,
  2027. YDSXGR_SPDIFOUTSTATUS,
  2028. YDSXGR_SPDIFINCTRL,
  2029. /* volumes */
  2030. YDSXGR_PRIADCLOOPVOL,
  2031. YDSXGR_NATIVEDACINVOL,
  2032. YDSXGR_NATIVEDACOUTVOL,
  2033. YDSXGR_BUF441OUTVOL,
  2034. YDSXGR_NATIVEADCINVOL,
  2035. YDSXGR_SPDIFLOOPVOL,
  2036. YDSXGR_SPDIFOUTVOL,
  2037. YDSXGR_ZVOUTVOL,
  2038. YDSXGR_LEGACYOUTVOL,
  2039. /* address bases */
  2040. YDSXGR_PLAYCTRLBASE,
  2041. YDSXGR_RECCTRLBASE,
  2042. YDSXGR_EFFCTRLBASE,
  2043. YDSXGR_WORKBASE,
  2044. /* capture set up */
  2045. YDSXGR_MAPOFREC,
  2046. YDSXGR_RECFORMAT,
  2047. YDSXGR_RECSLOTSR,
  2048. YDSXGR_ADCFORMAT,
  2049. YDSXGR_ADCSLOTSR,
  2050. };
  2051. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  2052. static int snd_ymfpci_suspend(struct device *dev)
  2053. {
  2054. struct pci_dev *pci = to_pci_dev(dev);
  2055. struct snd_card *card = dev_get_drvdata(dev);
  2056. struct snd_ymfpci *chip = card->private_data;
  2057. unsigned int i;
  2058. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2059. snd_pcm_suspend_all(chip->pcm);
  2060. snd_pcm_suspend_all(chip->pcm2);
  2061. snd_pcm_suspend_all(chip->pcm_spdif);
  2062. snd_pcm_suspend_all(chip->pcm_4ch);
  2063. snd_ac97_suspend(chip->ac97);
  2064. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2065. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2066. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2067. pci_read_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2068. &chip->saved_dsxg_legacy);
  2069. pci_read_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2070. &chip->saved_dsxg_elegacy);
  2071. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2072. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2073. snd_ymfpci_disable_dsp(chip);
  2074. pci_disable_device(pci);
  2075. pci_save_state(pci);
  2076. pci_set_power_state(pci, PCI_D3hot);
  2077. return 0;
  2078. }
  2079. static int snd_ymfpci_resume(struct device *dev)
  2080. {
  2081. struct pci_dev *pci = to_pci_dev(dev);
  2082. struct snd_card *card = dev_get_drvdata(dev);
  2083. struct snd_ymfpci *chip = card->private_data;
  2084. unsigned int i;
  2085. pci_set_power_state(pci, PCI_D0);
  2086. pci_restore_state(pci);
  2087. if (pci_enable_device(pci) < 0) {
  2088. printk(KERN_ERR "ymfpci: pci_enable_device failed, "
  2089. "disabling device\n");
  2090. snd_card_disconnect(card);
  2091. return -EIO;
  2092. }
  2093. pci_set_master(pci);
  2094. snd_ymfpci_aclink_reset(pci);
  2095. snd_ymfpci_codec_ready(chip, 0);
  2096. snd_ymfpci_download_image(chip);
  2097. udelay(100);
  2098. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2099. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2100. snd_ac97_resume(chip->ac97);
  2101. pci_write_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2102. chip->saved_dsxg_legacy);
  2103. pci_write_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2104. chip->saved_dsxg_elegacy);
  2105. /* start hw again */
  2106. if (chip->start_count > 0) {
  2107. spin_lock_irq(&chip->reg_lock);
  2108. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2109. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2110. spin_unlock_irq(&chip->reg_lock);
  2111. }
  2112. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2113. return 0;
  2114. }
  2115. SIMPLE_DEV_PM_OPS(snd_ymfpci_pm, snd_ymfpci_suspend, snd_ymfpci_resume);
  2116. #endif /* CONFIG_PM_SLEEP */
  2117. int snd_ymfpci_create(struct snd_card *card,
  2118. struct pci_dev *pci,
  2119. unsigned short old_legacy_ctrl,
  2120. struct snd_ymfpci **rchip)
  2121. {
  2122. struct snd_ymfpci *chip;
  2123. int err;
  2124. static struct snd_device_ops ops = {
  2125. .dev_free = snd_ymfpci_dev_free,
  2126. };
  2127. *rchip = NULL;
  2128. /* enable PCI device */
  2129. if ((err = pci_enable_device(pci)) < 0)
  2130. return err;
  2131. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2132. if (chip == NULL) {
  2133. pci_disable_device(pci);
  2134. return -ENOMEM;
  2135. }
  2136. chip->old_legacy_ctrl = old_legacy_ctrl;
  2137. spin_lock_init(&chip->reg_lock);
  2138. spin_lock_init(&chip->voice_lock);
  2139. init_waitqueue_head(&chip->interrupt_sleep);
  2140. atomic_set(&chip->interrupt_sleep_count, 0);
  2141. chip->card = card;
  2142. chip->pci = pci;
  2143. chip->irq = -1;
  2144. chip->device_id = pci->device;
  2145. chip->rev = pci->revision;
  2146. chip->reg_area_phys = pci_resource_start(pci, 0);
  2147. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2148. pci_set_master(pci);
  2149. chip->src441_used = -1;
  2150. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2151. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2152. snd_ymfpci_free(chip);
  2153. return -EBUSY;
  2154. }
  2155. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2156. KBUILD_MODNAME, chip)) {
  2157. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2158. snd_ymfpci_free(chip);
  2159. return -EBUSY;
  2160. }
  2161. chip->irq = pci->irq;
  2162. snd_ymfpci_aclink_reset(pci);
  2163. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2164. snd_ymfpci_free(chip);
  2165. return -EIO;
  2166. }
  2167. err = snd_ymfpci_request_firmware(chip);
  2168. if (err < 0) {
  2169. snd_printk(KERN_ERR "firmware request failed: %d\n", err);
  2170. snd_ymfpci_free(chip);
  2171. return err;
  2172. }
  2173. snd_ymfpci_download_image(chip);
  2174. udelay(100); /* seems we need a delay after downloading image.. */
  2175. if (snd_ymfpci_memalloc(chip) < 0) {
  2176. snd_ymfpci_free(chip);
  2177. return -EIO;
  2178. }
  2179. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2180. snd_ymfpci_free(chip);
  2181. return err;
  2182. }
  2183. #ifdef CONFIG_PM_SLEEP
  2184. chip->saved_regs = kmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32),
  2185. GFP_KERNEL);
  2186. if (chip->saved_regs == NULL) {
  2187. snd_ymfpci_free(chip);
  2188. return -ENOMEM;
  2189. }
  2190. #endif
  2191. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2192. snd_ymfpci_free(chip);
  2193. return err;
  2194. }
  2195. snd_ymfpci_proc_init(card, chip);
  2196. snd_card_set_dev(card, &pci->dev);
  2197. *rchip = chip;
  2198. return 0;
  2199. }