ice1712.c 82 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <linux/delay.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/init.h>
  49. #include <linux/pci.h>
  50. #include <linux/dma-mapping.h>
  51. #include <linux/slab.h>
  52. #include <linux/module.h>
  53. #include <linux/mutex.h>
  54. #include <sound/core.h>
  55. #include <sound/cs8427.h>
  56. #include <sound/info.h>
  57. #include <sound/initval.h>
  58. #include <sound/tlv.h>
  59. #include <sound/asoundef.h>
  60. #include "ice1712.h"
  61. /* lowlevel routines */
  62. #include "delta.h"
  63. #include "ews.h"
  64. #include "hoontech.h"
  65. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  66. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  67. MODULE_LICENSE("GPL");
  68. MODULE_SUPPORTED_DEVICE("{"
  69. HOONTECH_DEVICE_DESC
  70. DELTA_DEVICE_DESC
  71. EWS_DEVICE_DESC
  72. "{ICEnsemble,Generic ICE1712},"
  73. "{ICEnsemble,Generic Envy24}}");
  74. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  75. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  76. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  77. static char *model[SNDRV_CARDS];
  78. static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  79. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
  80. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  81. module_param_array(index, int, NULL, 0444);
  82. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  83. module_param_array(id, charp, NULL, 0444);
  84. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  85. module_param_array(enable, bool, NULL, 0444);
  86. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  87. module_param_array(omni, bool, NULL, 0444);
  88. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  89. module_param_array(cs8427_timeout, int, NULL, 0444);
  90. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  91. module_param_array(model, charp, NULL, 0444);
  92. MODULE_PARM_DESC(model, "Use the given board model.");
  93. module_param_array(dxr_enable, int, NULL, 0444);
  94. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  95. static DEFINE_PCI_DEVICE_TABLE(snd_ice1712_ids) = {
  96. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
  97. { 0, }
  98. };
  99. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  100. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  101. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  102. static int PRO_RATE_LOCKED;
  103. static int PRO_RATE_RESET = 1;
  104. static unsigned int PRO_RATE_DEFAULT = 44100;
  105. /*
  106. * Basic I/O
  107. */
  108. /* check whether the clock mode is spdif-in */
  109. static inline int is_spdif_master(struct snd_ice1712 *ice)
  110. {
  111. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  112. }
  113. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  114. {
  115. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  116. }
  117. static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
  118. {
  119. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  120. outl(data, ICEDS(ice, DATA));
  121. }
  122. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
  123. {
  124. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  125. return inl(ICEDS(ice, DATA));
  126. }
  127. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  128. unsigned short reg,
  129. unsigned short val)
  130. {
  131. struct snd_ice1712 *ice = ac97->private_data;
  132. int tm;
  133. unsigned char old_cmd = 0;
  134. for (tm = 0; tm < 0x10000; tm++) {
  135. old_cmd = inb(ICEREG(ice, AC97_CMD));
  136. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  137. continue;
  138. if (!(old_cmd & ICE1712_AC97_READY))
  139. continue;
  140. break;
  141. }
  142. outb(reg, ICEREG(ice, AC97_INDEX));
  143. outw(val, ICEREG(ice, AC97_DATA));
  144. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  145. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  146. for (tm = 0; tm < 0x10000; tm++)
  147. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  148. break;
  149. }
  150. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  151. unsigned short reg)
  152. {
  153. struct snd_ice1712 *ice = ac97->private_data;
  154. int tm;
  155. unsigned char old_cmd = 0;
  156. for (tm = 0; tm < 0x10000; tm++) {
  157. old_cmd = inb(ICEREG(ice, AC97_CMD));
  158. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  159. continue;
  160. if (!(old_cmd & ICE1712_AC97_READY))
  161. continue;
  162. break;
  163. }
  164. outb(reg, ICEREG(ice, AC97_INDEX));
  165. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  166. for (tm = 0; tm < 0x10000; tm++)
  167. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  168. break;
  169. if (tm >= 0x10000) /* timeout */
  170. return ~0;
  171. return inw(ICEREG(ice, AC97_DATA));
  172. }
  173. /*
  174. * pro ac97 section
  175. */
  176. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  177. unsigned short reg,
  178. unsigned short val)
  179. {
  180. struct snd_ice1712 *ice = ac97->private_data;
  181. int tm;
  182. unsigned char old_cmd = 0;
  183. for (tm = 0; tm < 0x10000; tm++) {
  184. old_cmd = inb(ICEMT(ice, AC97_CMD));
  185. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  186. continue;
  187. if (!(old_cmd & ICE1712_AC97_READY))
  188. continue;
  189. break;
  190. }
  191. outb(reg, ICEMT(ice, AC97_INDEX));
  192. outw(val, ICEMT(ice, AC97_DATA));
  193. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  194. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  195. for (tm = 0; tm < 0x10000; tm++)
  196. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  197. break;
  198. }
  199. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  200. unsigned short reg)
  201. {
  202. struct snd_ice1712 *ice = ac97->private_data;
  203. int tm;
  204. unsigned char old_cmd = 0;
  205. for (tm = 0; tm < 0x10000; tm++) {
  206. old_cmd = inb(ICEMT(ice, AC97_CMD));
  207. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  208. continue;
  209. if (!(old_cmd & ICE1712_AC97_READY))
  210. continue;
  211. break;
  212. }
  213. outb(reg, ICEMT(ice, AC97_INDEX));
  214. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  215. for (tm = 0; tm < 0x10000; tm++)
  216. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  217. break;
  218. if (tm >= 0x10000) /* timeout */
  219. return ~0;
  220. return inw(ICEMT(ice, AC97_DATA));
  221. }
  222. /*
  223. * consumer ac97 digital mix
  224. */
  225. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  226. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  227. {
  228. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  229. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  230. return 0;
  231. }
  232. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  233. {
  234. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  235. unsigned char val, nval;
  236. spin_lock_irq(&ice->reg_lock);
  237. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  238. nval = val & ~ICE1712_ROUTE_AC97;
  239. if (ucontrol->value.integer.value[0])
  240. nval |= ICE1712_ROUTE_AC97;
  241. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  242. spin_unlock_irq(&ice->reg_lock);
  243. return val != nval;
  244. }
  245. static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
  246. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  247. .name = "Digital Mixer To AC97",
  248. .info = snd_ice1712_digmix_route_ac97_info,
  249. .get = snd_ice1712_digmix_route_ac97_get,
  250. .put = snd_ice1712_digmix_route_ac97_put,
  251. };
  252. /*
  253. * gpio operations
  254. */
  255. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  256. {
  257. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  258. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  259. }
  260. static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
  261. {
  262. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
  263. }
  264. static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
  265. {
  266. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
  267. }
  268. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  269. {
  270. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  271. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  272. }
  273. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  274. {
  275. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  276. }
  277. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  278. {
  279. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  280. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  281. }
  282. /*
  283. *
  284. * CS8427 interface
  285. *
  286. */
  287. /*
  288. * change the input clock selection
  289. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  290. */
  291. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  292. {
  293. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  294. unsigned char val, nval;
  295. int res = 0;
  296. snd_i2c_lock(ice->i2c);
  297. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  298. snd_i2c_unlock(ice->i2c);
  299. return -EIO;
  300. }
  301. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  302. snd_i2c_unlock(ice->i2c);
  303. return -EIO;
  304. }
  305. nval = val & 0xf0;
  306. if (spdif_clock)
  307. nval |= 0x01;
  308. else
  309. nval |= 0x04;
  310. if (val != nval) {
  311. reg[1] = nval;
  312. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  313. res = -EIO;
  314. } else {
  315. res++;
  316. }
  317. }
  318. snd_i2c_unlock(ice->i2c);
  319. return res;
  320. }
  321. /*
  322. * spdif callbacks
  323. */
  324. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  325. {
  326. snd_cs8427_iec958_active(ice->cs8427, 1);
  327. }
  328. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  329. {
  330. snd_cs8427_iec958_active(ice->cs8427, 0);
  331. }
  332. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  333. {
  334. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  335. }
  336. /*
  337. * create and initialize callbacks for cs8427 interface
  338. */
  339. int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  340. {
  341. int err;
  342. err = snd_cs8427_create(ice->i2c, addr,
  343. (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
  344. if (err < 0) {
  345. snd_printk(KERN_ERR "CS8427 initialization failed\n");
  346. return err;
  347. }
  348. ice->spdif.ops.open = open_cs8427;
  349. ice->spdif.ops.close = close_cs8427;
  350. ice->spdif.ops.setup_rate = setup_cs8427;
  351. return 0;
  352. }
  353. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  354. {
  355. /* change CS8427 clock source too */
  356. if (ice->cs8427)
  357. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  358. /* notify ak4524 chip as well */
  359. if (spdif_is_master) {
  360. unsigned int i;
  361. for (i = 0; i < ice->akm_codecs; i++) {
  362. if (ice->akm[i].ops.set_rate_val)
  363. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  364. }
  365. }
  366. }
  367. /*
  368. * Interrupt handler
  369. */
  370. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  371. {
  372. struct snd_ice1712 *ice = dev_id;
  373. unsigned char status;
  374. int handled = 0;
  375. while (1) {
  376. status = inb(ICEREG(ice, IRQSTAT));
  377. if (status == 0)
  378. break;
  379. handled = 1;
  380. if (status & ICE1712_IRQ_MPU1) {
  381. if (ice->rmidi[0])
  382. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  383. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  384. status &= ~ICE1712_IRQ_MPU1;
  385. }
  386. if (status & ICE1712_IRQ_TIMER)
  387. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  388. if (status & ICE1712_IRQ_MPU2) {
  389. if (ice->rmidi[1])
  390. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  391. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  392. status &= ~ICE1712_IRQ_MPU2;
  393. }
  394. if (status & ICE1712_IRQ_PROPCM) {
  395. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  396. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  397. if (ice->playback_pro_substream)
  398. snd_pcm_period_elapsed(ice->playback_pro_substream);
  399. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  400. }
  401. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  402. if (ice->capture_pro_substream)
  403. snd_pcm_period_elapsed(ice->capture_pro_substream);
  404. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  405. }
  406. }
  407. if (status & ICE1712_IRQ_FM)
  408. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  409. if (status & ICE1712_IRQ_PBKDS) {
  410. u32 idx;
  411. u16 pbkstatus;
  412. struct snd_pcm_substream *substream;
  413. pbkstatus = inw(ICEDS(ice, INTSTAT));
  414. /* printk(KERN_DEBUG "pbkstatus = 0x%x\n", pbkstatus); */
  415. for (idx = 0; idx < 6; idx++) {
  416. if ((pbkstatus & (3 << (idx * 2))) == 0)
  417. continue;
  418. substream = ice->playback_con_substream_ds[idx];
  419. if (substream != NULL)
  420. snd_pcm_period_elapsed(substream);
  421. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  422. }
  423. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  424. }
  425. if (status & ICE1712_IRQ_CONCAP) {
  426. if (ice->capture_con_substream)
  427. snd_pcm_period_elapsed(ice->capture_con_substream);
  428. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  429. }
  430. if (status & ICE1712_IRQ_CONPBK) {
  431. if (ice->playback_con_substream)
  432. snd_pcm_period_elapsed(ice->playback_con_substream);
  433. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  434. }
  435. }
  436. return IRQ_RETVAL(handled);
  437. }
  438. /*
  439. * PCM part - misc
  440. */
  441. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  442. struct snd_pcm_hw_params *hw_params)
  443. {
  444. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  445. }
  446. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  447. {
  448. return snd_pcm_lib_free_pages(substream);
  449. }
  450. /*
  451. * PCM part - consumer I/O
  452. */
  453. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  454. int cmd)
  455. {
  456. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  457. int result = 0;
  458. u32 tmp;
  459. spin_lock(&ice->reg_lock);
  460. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  461. if (cmd == SNDRV_PCM_TRIGGER_START) {
  462. tmp |= 1;
  463. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  464. tmp &= ~1;
  465. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  466. tmp |= 2;
  467. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  468. tmp &= ~2;
  469. } else {
  470. result = -EINVAL;
  471. }
  472. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  473. spin_unlock(&ice->reg_lock);
  474. return result;
  475. }
  476. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  477. int cmd)
  478. {
  479. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  480. int result = 0;
  481. u32 tmp;
  482. spin_lock(&ice->reg_lock);
  483. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  484. if (cmd == SNDRV_PCM_TRIGGER_START) {
  485. tmp |= 1;
  486. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  487. tmp &= ~1;
  488. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  489. tmp |= 2;
  490. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  491. tmp &= ~2;
  492. } else {
  493. result = -EINVAL;
  494. }
  495. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  496. spin_unlock(&ice->reg_lock);
  497. return result;
  498. }
  499. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  500. int cmd)
  501. {
  502. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  503. int result = 0;
  504. u8 tmp;
  505. spin_lock(&ice->reg_lock);
  506. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  507. if (cmd == SNDRV_PCM_TRIGGER_START) {
  508. tmp |= 1;
  509. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  510. tmp &= ~1;
  511. } else {
  512. result = -EINVAL;
  513. }
  514. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  515. spin_unlock(&ice->reg_lock);
  516. return result;
  517. }
  518. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  519. {
  520. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  521. struct snd_pcm_runtime *runtime = substream->runtime;
  522. u32 period_size, buf_size, rate, tmp;
  523. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  524. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  525. tmp = 0x0000;
  526. if (snd_pcm_format_width(runtime->format) == 16)
  527. tmp |= 0x10;
  528. if (runtime->channels == 2)
  529. tmp |= 0x08;
  530. rate = (runtime->rate * 8192) / 375;
  531. if (rate > 0x000fffff)
  532. rate = 0x000fffff;
  533. spin_lock_irq(&ice->reg_lock);
  534. outb(0, ice->ddma_port + 15);
  535. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  536. outl(runtime->dma_addr, ice->ddma_port + 0);
  537. outw(buf_size, ice->ddma_port + 4);
  538. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  539. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  540. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  541. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  542. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  543. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  544. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  545. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  546. spin_unlock_irq(&ice->reg_lock);
  547. return 0;
  548. }
  549. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  550. {
  551. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  552. struct snd_pcm_runtime *runtime = substream->runtime;
  553. u32 period_size, buf_size, rate, tmp, chn;
  554. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  555. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  556. tmp = 0x0064;
  557. if (snd_pcm_format_width(runtime->format) == 16)
  558. tmp &= ~0x04;
  559. if (runtime->channels == 2)
  560. tmp |= 0x08;
  561. rate = (runtime->rate * 8192) / 375;
  562. if (rate > 0x000fffff)
  563. rate = 0x000fffff;
  564. ice->playback_con_active_buf[substream->number] = 0;
  565. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  566. chn = substream->number * 2;
  567. spin_lock_irq(&ice->reg_lock);
  568. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  569. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  570. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  571. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  572. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  573. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  574. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  575. if (runtime->channels == 2) {
  576. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  577. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  578. }
  579. spin_unlock_irq(&ice->reg_lock);
  580. return 0;
  581. }
  582. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  583. {
  584. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  585. struct snd_pcm_runtime *runtime = substream->runtime;
  586. u32 period_size, buf_size;
  587. u8 tmp;
  588. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  589. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  590. tmp = 0x06;
  591. if (snd_pcm_format_width(runtime->format) == 16)
  592. tmp &= ~0x04;
  593. if (runtime->channels == 2)
  594. tmp &= ~0x02;
  595. spin_lock_irq(&ice->reg_lock);
  596. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  597. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  598. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  599. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  600. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  601. spin_unlock_irq(&ice->reg_lock);
  602. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  603. return 0;
  604. }
  605. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  606. {
  607. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  608. struct snd_pcm_runtime *runtime = substream->runtime;
  609. size_t ptr;
  610. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  611. return 0;
  612. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  613. if (ptr == runtime->buffer_size)
  614. ptr = 0;
  615. return bytes_to_frames(substream->runtime, ptr);
  616. }
  617. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  618. {
  619. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  620. u8 addr;
  621. size_t ptr;
  622. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  623. return 0;
  624. if (ice->playback_con_active_buf[substream->number])
  625. addr = ICE1712_DSC_ADDR1;
  626. else
  627. addr = ICE1712_DSC_ADDR0;
  628. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  629. ice->playback_con_virt_addr[substream->number];
  630. if (ptr == substream->runtime->buffer_size)
  631. ptr = 0;
  632. return bytes_to_frames(substream->runtime, ptr);
  633. }
  634. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  635. {
  636. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  637. size_t ptr;
  638. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  639. return 0;
  640. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  641. if (ptr == substream->runtime->buffer_size)
  642. ptr = 0;
  643. return bytes_to_frames(substream->runtime, ptr);
  644. }
  645. static const struct snd_pcm_hardware snd_ice1712_playback = {
  646. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  647. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  648. SNDRV_PCM_INFO_MMAP_VALID |
  649. SNDRV_PCM_INFO_PAUSE),
  650. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  651. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  652. .rate_min = 4000,
  653. .rate_max = 48000,
  654. .channels_min = 1,
  655. .channels_max = 2,
  656. .buffer_bytes_max = (64*1024),
  657. .period_bytes_min = 64,
  658. .period_bytes_max = (64*1024),
  659. .periods_min = 1,
  660. .periods_max = 1024,
  661. .fifo_size = 0,
  662. };
  663. static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
  664. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  665. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  666. SNDRV_PCM_INFO_MMAP_VALID |
  667. SNDRV_PCM_INFO_PAUSE),
  668. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  669. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  670. .rate_min = 4000,
  671. .rate_max = 48000,
  672. .channels_min = 1,
  673. .channels_max = 2,
  674. .buffer_bytes_max = (128*1024),
  675. .period_bytes_min = 64,
  676. .period_bytes_max = (128*1024),
  677. .periods_min = 2,
  678. .periods_max = 2,
  679. .fifo_size = 0,
  680. };
  681. static const struct snd_pcm_hardware snd_ice1712_capture = {
  682. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  683. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  684. SNDRV_PCM_INFO_MMAP_VALID),
  685. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  686. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  687. .rate_min = 4000,
  688. .rate_max = 48000,
  689. .channels_min = 1,
  690. .channels_max = 2,
  691. .buffer_bytes_max = (64*1024),
  692. .period_bytes_min = 64,
  693. .period_bytes_max = (64*1024),
  694. .periods_min = 1,
  695. .periods_max = 1024,
  696. .fifo_size = 0,
  697. };
  698. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  699. {
  700. struct snd_pcm_runtime *runtime = substream->runtime;
  701. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  702. ice->playback_con_substream = substream;
  703. runtime->hw = snd_ice1712_playback;
  704. return 0;
  705. }
  706. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  707. {
  708. struct snd_pcm_runtime *runtime = substream->runtime;
  709. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  710. u32 tmp;
  711. ice->playback_con_substream_ds[substream->number] = substream;
  712. runtime->hw = snd_ice1712_playback_ds;
  713. spin_lock_irq(&ice->reg_lock);
  714. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  715. outw(tmp, ICEDS(ice, INTMASK));
  716. spin_unlock_irq(&ice->reg_lock);
  717. return 0;
  718. }
  719. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  720. {
  721. struct snd_pcm_runtime *runtime = substream->runtime;
  722. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  723. ice->capture_con_substream = substream;
  724. runtime->hw = snd_ice1712_capture;
  725. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  726. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  727. runtime->hw.rate_min = 48000;
  728. return 0;
  729. }
  730. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  731. {
  732. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  733. ice->playback_con_substream = NULL;
  734. return 0;
  735. }
  736. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  737. {
  738. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  739. u32 tmp;
  740. spin_lock_irq(&ice->reg_lock);
  741. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  742. outw(tmp, ICEDS(ice, INTMASK));
  743. spin_unlock_irq(&ice->reg_lock);
  744. ice->playback_con_substream_ds[substream->number] = NULL;
  745. return 0;
  746. }
  747. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  748. {
  749. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  750. ice->capture_con_substream = NULL;
  751. return 0;
  752. }
  753. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  754. .open = snd_ice1712_playback_open,
  755. .close = snd_ice1712_playback_close,
  756. .ioctl = snd_pcm_lib_ioctl,
  757. .hw_params = snd_ice1712_hw_params,
  758. .hw_free = snd_ice1712_hw_free,
  759. .prepare = snd_ice1712_playback_prepare,
  760. .trigger = snd_ice1712_playback_trigger,
  761. .pointer = snd_ice1712_playback_pointer,
  762. };
  763. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  764. .open = snd_ice1712_playback_ds_open,
  765. .close = snd_ice1712_playback_ds_close,
  766. .ioctl = snd_pcm_lib_ioctl,
  767. .hw_params = snd_ice1712_hw_params,
  768. .hw_free = snd_ice1712_hw_free,
  769. .prepare = snd_ice1712_playback_ds_prepare,
  770. .trigger = snd_ice1712_playback_ds_trigger,
  771. .pointer = snd_ice1712_playback_ds_pointer,
  772. };
  773. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  774. .open = snd_ice1712_capture_open,
  775. .close = snd_ice1712_capture_close,
  776. .ioctl = snd_pcm_lib_ioctl,
  777. .hw_params = snd_ice1712_hw_params,
  778. .hw_free = snd_ice1712_hw_free,
  779. .prepare = snd_ice1712_capture_prepare,
  780. .trigger = snd_ice1712_capture_trigger,
  781. .pointer = snd_ice1712_capture_pointer,
  782. };
  783. static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  784. {
  785. struct snd_pcm *pcm;
  786. int err;
  787. if (rpcm)
  788. *rpcm = NULL;
  789. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  790. if (err < 0)
  791. return err;
  792. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  793. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  794. pcm->private_data = ice;
  795. pcm->info_flags = 0;
  796. strcpy(pcm->name, "ICE1712 consumer");
  797. ice->pcm = pcm;
  798. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  799. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  800. if (rpcm)
  801. *rpcm = pcm;
  802. printk(KERN_WARNING "Consumer PCM code does not work well at the moment --jk\n");
  803. return 0;
  804. }
  805. static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  806. {
  807. struct snd_pcm *pcm;
  808. int err;
  809. if (rpcm)
  810. *rpcm = NULL;
  811. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  812. if (err < 0)
  813. return err;
  814. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  815. pcm->private_data = ice;
  816. pcm->info_flags = 0;
  817. strcpy(pcm->name, "ICE1712 consumer (DS)");
  818. ice->pcm_ds = pcm;
  819. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  820. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  821. if (rpcm)
  822. *rpcm = pcm;
  823. return 0;
  824. }
  825. /*
  826. * PCM code - professional part (multitrack)
  827. */
  828. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  829. 32000, 44100, 48000, 64000, 88200, 96000 };
  830. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  831. .count = ARRAY_SIZE(rates),
  832. .list = rates,
  833. .mask = 0,
  834. };
  835. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  836. int cmd)
  837. {
  838. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  839. switch (cmd) {
  840. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  841. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  842. {
  843. unsigned int what;
  844. unsigned int old;
  845. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  846. return -EINVAL;
  847. what = ICE1712_PLAYBACK_PAUSE;
  848. snd_pcm_trigger_done(substream, substream);
  849. spin_lock(&ice->reg_lock);
  850. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  851. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  852. old |= what;
  853. else
  854. old &= ~what;
  855. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  856. spin_unlock(&ice->reg_lock);
  857. break;
  858. }
  859. case SNDRV_PCM_TRIGGER_START:
  860. case SNDRV_PCM_TRIGGER_STOP:
  861. {
  862. unsigned int what = 0;
  863. unsigned int old;
  864. struct snd_pcm_substream *s;
  865. snd_pcm_group_for_each_entry(s, substream) {
  866. if (s == ice->playback_pro_substream) {
  867. what |= ICE1712_PLAYBACK_START;
  868. snd_pcm_trigger_done(s, substream);
  869. } else if (s == ice->capture_pro_substream) {
  870. what |= ICE1712_CAPTURE_START_SHADOW;
  871. snd_pcm_trigger_done(s, substream);
  872. }
  873. }
  874. spin_lock(&ice->reg_lock);
  875. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  876. if (cmd == SNDRV_PCM_TRIGGER_START)
  877. old |= what;
  878. else
  879. old &= ~what;
  880. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  881. spin_unlock(&ice->reg_lock);
  882. break;
  883. }
  884. default:
  885. return -EINVAL;
  886. }
  887. return 0;
  888. }
  889. /*
  890. */
  891. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  892. {
  893. unsigned long flags;
  894. unsigned char val, old;
  895. unsigned int i;
  896. switch (rate) {
  897. case 8000: val = 6; break;
  898. case 9600: val = 3; break;
  899. case 11025: val = 10; break;
  900. case 12000: val = 2; break;
  901. case 16000: val = 5; break;
  902. case 22050: val = 9; break;
  903. case 24000: val = 1; break;
  904. case 32000: val = 4; break;
  905. case 44100: val = 8; break;
  906. case 48000: val = 0; break;
  907. case 64000: val = 15; break;
  908. case 88200: val = 11; break;
  909. case 96000: val = 7; break;
  910. default:
  911. snd_BUG();
  912. val = 0;
  913. rate = 48000;
  914. break;
  915. }
  916. spin_lock_irqsave(&ice->reg_lock, flags);
  917. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  918. ICE1712_PLAYBACK_PAUSE|
  919. ICE1712_PLAYBACK_START)) {
  920. __out:
  921. spin_unlock_irqrestore(&ice->reg_lock, flags);
  922. return;
  923. }
  924. if (!force && is_pro_rate_locked(ice))
  925. goto __out;
  926. old = inb(ICEMT(ice, RATE));
  927. if (!force && old == val)
  928. goto __out;
  929. outb(val, ICEMT(ice, RATE));
  930. spin_unlock_irqrestore(&ice->reg_lock, flags);
  931. if (ice->gpio.set_pro_rate)
  932. ice->gpio.set_pro_rate(ice, rate);
  933. for (i = 0; i < ice->akm_codecs; i++) {
  934. if (ice->akm[i].ops.set_rate_val)
  935. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  936. }
  937. if (ice->spdif.ops.setup_rate)
  938. ice->spdif.ops.setup_rate(ice, rate);
  939. }
  940. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  941. {
  942. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  943. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  944. spin_lock_irq(&ice->reg_lock);
  945. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  946. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  947. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  948. spin_unlock_irq(&ice->reg_lock);
  949. return 0;
  950. }
  951. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  952. struct snd_pcm_hw_params *hw_params)
  953. {
  954. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  955. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  956. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  957. }
  958. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  959. {
  960. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  961. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  962. spin_lock_irq(&ice->reg_lock);
  963. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  964. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  965. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  966. spin_unlock_irq(&ice->reg_lock);
  967. return 0;
  968. }
  969. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  970. struct snd_pcm_hw_params *hw_params)
  971. {
  972. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  973. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  974. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  975. }
  976. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  977. {
  978. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  979. size_t ptr;
  980. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  981. return 0;
  982. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  983. if (ptr == substream->runtime->buffer_size)
  984. ptr = 0;
  985. return bytes_to_frames(substream->runtime, ptr);
  986. }
  987. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  988. {
  989. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  990. size_t ptr;
  991. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  992. return 0;
  993. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  994. if (ptr == substream->runtime->buffer_size)
  995. ptr = 0;
  996. return bytes_to_frames(substream->runtime, ptr);
  997. }
  998. static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
  999. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1000. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1001. SNDRV_PCM_INFO_MMAP_VALID |
  1002. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1003. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1004. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1005. .rate_min = 4000,
  1006. .rate_max = 96000,
  1007. .channels_min = 10,
  1008. .channels_max = 10,
  1009. .buffer_bytes_max = (256*1024),
  1010. .period_bytes_min = 10 * 4 * 2,
  1011. .period_bytes_max = 131040,
  1012. .periods_min = 1,
  1013. .periods_max = 1024,
  1014. .fifo_size = 0,
  1015. };
  1016. static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
  1017. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1018. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1019. SNDRV_PCM_INFO_MMAP_VALID |
  1020. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1021. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1022. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1023. .rate_min = 4000,
  1024. .rate_max = 96000,
  1025. .channels_min = 12,
  1026. .channels_max = 12,
  1027. .buffer_bytes_max = (256*1024),
  1028. .period_bytes_min = 12 * 4 * 2,
  1029. .period_bytes_max = 131040,
  1030. .periods_min = 1,
  1031. .periods_max = 1024,
  1032. .fifo_size = 0,
  1033. };
  1034. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1035. {
  1036. struct snd_pcm_runtime *runtime = substream->runtime;
  1037. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1038. ice->playback_pro_substream = substream;
  1039. runtime->hw = snd_ice1712_playback_pro;
  1040. snd_pcm_set_sync(substream);
  1041. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1042. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1043. if (is_pro_rate_locked(ice)) {
  1044. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1045. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1046. }
  1047. if (ice->spdif.ops.open)
  1048. ice->spdif.ops.open(ice, substream);
  1049. return 0;
  1050. }
  1051. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1052. {
  1053. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1054. struct snd_pcm_runtime *runtime = substream->runtime;
  1055. ice->capture_pro_substream = substream;
  1056. runtime->hw = snd_ice1712_capture_pro;
  1057. snd_pcm_set_sync(substream);
  1058. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1059. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1060. if (is_pro_rate_locked(ice)) {
  1061. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1062. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1063. }
  1064. return 0;
  1065. }
  1066. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1067. {
  1068. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1069. if (PRO_RATE_RESET)
  1070. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1071. ice->playback_pro_substream = NULL;
  1072. if (ice->spdif.ops.close)
  1073. ice->spdif.ops.close(ice, substream);
  1074. return 0;
  1075. }
  1076. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1077. {
  1078. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1079. if (PRO_RATE_RESET)
  1080. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1081. ice->capture_pro_substream = NULL;
  1082. return 0;
  1083. }
  1084. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1085. .open = snd_ice1712_playback_pro_open,
  1086. .close = snd_ice1712_playback_pro_close,
  1087. .ioctl = snd_pcm_lib_ioctl,
  1088. .hw_params = snd_ice1712_playback_pro_hw_params,
  1089. .hw_free = snd_ice1712_hw_free,
  1090. .prepare = snd_ice1712_playback_pro_prepare,
  1091. .trigger = snd_ice1712_pro_trigger,
  1092. .pointer = snd_ice1712_playback_pro_pointer,
  1093. };
  1094. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1095. .open = snd_ice1712_capture_pro_open,
  1096. .close = snd_ice1712_capture_pro_close,
  1097. .ioctl = snd_pcm_lib_ioctl,
  1098. .hw_params = snd_ice1712_capture_pro_hw_params,
  1099. .hw_free = snd_ice1712_hw_free,
  1100. .prepare = snd_ice1712_capture_pro_prepare,
  1101. .trigger = snd_ice1712_pro_trigger,
  1102. .pointer = snd_ice1712_capture_pro_pointer,
  1103. };
  1104. static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  1105. {
  1106. struct snd_pcm *pcm;
  1107. int err;
  1108. if (rpcm)
  1109. *rpcm = NULL;
  1110. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1111. if (err < 0)
  1112. return err;
  1113. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1114. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1115. pcm->private_data = ice;
  1116. pcm->info_flags = 0;
  1117. strcpy(pcm->name, "ICE1712 multi");
  1118. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1119. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1120. ice->pcm_pro = pcm;
  1121. if (rpcm)
  1122. *rpcm = pcm;
  1123. if (ice->cs8427) {
  1124. /* assign channels to iec958 */
  1125. err = snd_cs8427_iec958_build(ice->cs8427,
  1126. pcm->streams[0].substream,
  1127. pcm->streams[1].substream);
  1128. if (err < 0)
  1129. return err;
  1130. }
  1131. err = snd_ice1712_build_pro_mixer(ice);
  1132. if (err < 0)
  1133. return err;
  1134. return 0;
  1135. }
  1136. /*
  1137. * Mixer section
  1138. */
  1139. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1140. {
  1141. unsigned int vol = ice->pro_volumes[index];
  1142. unsigned short val = 0;
  1143. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1144. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1145. outb(index, ICEMT(ice, MONITOR_INDEX));
  1146. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1147. }
  1148. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1149. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1150. {
  1151. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1152. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1153. kcontrol->private_value;
  1154. spin_lock_irq(&ice->reg_lock);
  1155. ucontrol->value.integer.value[0] =
  1156. !((ice->pro_volumes[priv_idx] >> 15) & 1);
  1157. ucontrol->value.integer.value[1] =
  1158. !((ice->pro_volumes[priv_idx] >> 31) & 1);
  1159. spin_unlock_irq(&ice->reg_lock);
  1160. return 0;
  1161. }
  1162. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1163. {
  1164. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1165. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1166. kcontrol->private_value;
  1167. unsigned int nval, change;
  1168. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1169. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1170. spin_lock_irq(&ice->reg_lock);
  1171. nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
  1172. change = nval != ice->pro_volumes[priv_idx];
  1173. ice->pro_volumes[priv_idx] = nval;
  1174. snd_ice1712_update_volume(ice, priv_idx);
  1175. spin_unlock_irq(&ice->reg_lock);
  1176. return change;
  1177. }
  1178. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1179. {
  1180. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1181. uinfo->count = 2;
  1182. uinfo->value.integer.min = 0;
  1183. uinfo->value.integer.max = 96;
  1184. return 0;
  1185. }
  1186. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1189. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1190. kcontrol->private_value;
  1191. spin_lock_irq(&ice->reg_lock);
  1192. ucontrol->value.integer.value[0] =
  1193. (ice->pro_volumes[priv_idx] >> 0) & 127;
  1194. ucontrol->value.integer.value[1] =
  1195. (ice->pro_volumes[priv_idx] >> 16) & 127;
  1196. spin_unlock_irq(&ice->reg_lock);
  1197. return 0;
  1198. }
  1199. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1200. {
  1201. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1202. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1203. kcontrol->private_value;
  1204. unsigned int nval, change;
  1205. nval = (ucontrol->value.integer.value[0] & 127) |
  1206. ((ucontrol->value.integer.value[1] & 127) << 16);
  1207. spin_lock_irq(&ice->reg_lock);
  1208. nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
  1209. change = nval != ice->pro_volumes[priv_idx];
  1210. ice->pro_volumes[priv_idx] = nval;
  1211. snd_ice1712_update_volume(ice, priv_idx);
  1212. spin_unlock_irq(&ice->reg_lock);
  1213. return change;
  1214. }
  1215. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1216. static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
  1217. {
  1218. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1219. .name = "Multi Playback Switch",
  1220. .info = snd_ice1712_pro_mixer_switch_info,
  1221. .get = snd_ice1712_pro_mixer_switch_get,
  1222. .put = snd_ice1712_pro_mixer_switch_put,
  1223. .private_value = 0,
  1224. .count = 10,
  1225. },
  1226. {
  1227. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1228. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1229. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1230. .name = "Multi Playback Volume",
  1231. .info = snd_ice1712_pro_mixer_volume_info,
  1232. .get = snd_ice1712_pro_mixer_volume_get,
  1233. .put = snd_ice1712_pro_mixer_volume_put,
  1234. .private_value = 0,
  1235. .count = 10,
  1236. .tlv = { .p = db_scale_playback }
  1237. },
  1238. };
  1239. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
  1240. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1241. .name = "H/W Multi Capture Switch",
  1242. .info = snd_ice1712_pro_mixer_switch_info,
  1243. .get = snd_ice1712_pro_mixer_switch_get,
  1244. .put = snd_ice1712_pro_mixer_switch_put,
  1245. .private_value = 10,
  1246. };
  1247. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
  1248. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1249. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
  1250. .info = snd_ice1712_pro_mixer_switch_info,
  1251. .get = snd_ice1712_pro_mixer_switch_get,
  1252. .put = snd_ice1712_pro_mixer_switch_put,
  1253. .private_value = 18,
  1254. .count = 2,
  1255. };
  1256. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
  1257. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1258. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1259. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1260. .name = "H/W Multi Capture Volume",
  1261. .info = snd_ice1712_pro_mixer_volume_info,
  1262. .get = snd_ice1712_pro_mixer_volume_get,
  1263. .put = snd_ice1712_pro_mixer_volume_put,
  1264. .private_value = 10,
  1265. .tlv = { .p = db_scale_playback }
  1266. };
  1267. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
  1268. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1269. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
  1270. .info = snd_ice1712_pro_mixer_volume_info,
  1271. .get = snd_ice1712_pro_mixer_volume_get,
  1272. .put = snd_ice1712_pro_mixer_volume_put,
  1273. .private_value = 18,
  1274. .count = 2,
  1275. };
  1276. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1277. {
  1278. struct snd_card *card = ice->card;
  1279. unsigned int idx;
  1280. int err;
  1281. /* multi-channel mixer */
  1282. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1283. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1284. if (err < 0)
  1285. return err;
  1286. }
  1287. if (ice->num_total_adcs > 0) {
  1288. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1289. tmp.count = ice->num_total_adcs;
  1290. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1291. if (err < 0)
  1292. return err;
  1293. }
  1294. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1295. if (err < 0)
  1296. return err;
  1297. if (ice->num_total_adcs > 0) {
  1298. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1299. tmp.count = ice->num_total_adcs;
  1300. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1301. if (err < 0)
  1302. return err;
  1303. }
  1304. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1305. if (err < 0)
  1306. return err;
  1307. /* initialize volumes */
  1308. for (idx = 0; idx < 10; idx++) {
  1309. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1310. snd_ice1712_update_volume(ice, idx);
  1311. }
  1312. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1313. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1314. snd_ice1712_update_volume(ice, idx);
  1315. }
  1316. for (idx = 18; idx < 20; idx++) {
  1317. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1318. snd_ice1712_update_volume(ice, idx);
  1319. }
  1320. return 0;
  1321. }
  1322. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1323. {
  1324. struct snd_ice1712 *ice = ac97->private_data;
  1325. ice->ac97 = NULL;
  1326. }
  1327. static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
  1328. {
  1329. int err, bus_num = 0;
  1330. struct snd_ac97_template ac97;
  1331. struct snd_ac97_bus *pbus;
  1332. static struct snd_ac97_bus_ops con_ops = {
  1333. .write = snd_ice1712_ac97_write,
  1334. .read = snd_ice1712_ac97_read,
  1335. };
  1336. static struct snd_ac97_bus_ops pro_ops = {
  1337. .write = snd_ice1712_pro_ac97_write,
  1338. .read = snd_ice1712_pro_ac97_read,
  1339. };
  1340. if (ice_has_con_ac97(ice)) {
  1341. err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
  1342. if (err < 0)
  1343. return err;
  1344. memset(&ac97, 0, sizeof(ac97));
  1345. ac97.private_data = ice;
  1346. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1347. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1348. if (err < 0)
  1349. printk(KERN_WARNING "ice1712: cannot initialize ac97 for consumer, skipped\n");
  1350. else {
  1351. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice));
  1352. if (err < 0)
  1353. return err;
  1354. return 0;
  1355. }
  1356. }
  1357. if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1358. err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
  1359. if (err < 0)
  1360. return err;
  1361. memset(&ac97, 0, sizeof(ac97));
  1362. ac97.private_data = ice;
  1363. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1364. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1365. if (err < 0)
  1366. printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n");
  1367. else
  1368. return 0;
  1369. }
  1370. /* I2S mixer only */
  1371. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1372. return 0;
  1373. }
  1374. /*
  1375. *
  1376. */
  1377. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1378. {
  1379. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1380. }
  1381. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1382. struct snd_info_buffer *buffer)
  1383. {
  1384. struct snd_ice1712 *ice = entry->private_data;
  1385. unsigned int idx;
  1386. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1387. snd_iprintf(buffer, "EEPROM:\n");
  1388. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1389. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1390. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1391. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1392. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1393. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1394. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1395. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1396. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1397. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1398. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1399. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1400. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1401. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1402. for (idx = 0; idx < 4; idx++)
  1403. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1404. for (idx = 0; idx < 4; idx++)
  1405. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1406. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1407. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1408. snd_iprintf(buffer, "\nRegisters:\n");
  1409. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1410. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1411. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1412. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1413. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1414. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1415. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1416. }
  1417. static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
  1418. {
  1419. struct snd_info_entry *entry;
  1420. if (!snd_card_proc_new(ice->card, "ice1712", &entry))
  1421. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1422. }
  1423. /*
  1424. *
  1425. */
  1426. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1427. struct snd_ctl_elem_info *uinfo)
  1428. {
  1429. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1430. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1431. return 0;
  1432. }
  1433. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1434. struct snd_ctl_elem_value *ucontrol)
  1435. {
  1436. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1437. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1438. return 0;
  1439. }
  1440. static struct snd_kcontrol_new snd_ice1712_eeprom = {
  1441. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1442. .name = "ICE1712 EEPROM",
  1443. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1444. .info = snd_ice1712_eeprom_info,
  1445. .get = snd_ice1712_eeprom_get
  1446. };
  1447. /*
  1448. */
  1449. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1450. struct snd_ctl_elem_info *uinfo)
  1451. {
  1452. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1453. uinfo->count = 1;
  1454. return 0;
  1455. }
  1456. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1457. struct snd_ctl_elem_value *ucontrol)
  1458. {
  1459. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1460. if (ice->spdif.ops.default_get)
  1461. ice->spdif.ops.default_get(ice, ucontrol);
  1462. return 0;
  1463. }
  1464. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1465. struct snd_ctl_elem_value *ucontrol)
  1466. {
  1467. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1468. if (ice->spdif.ops.default_put)
  1469. return ice->spdif.ops.default_put(ice, ucontrol);
  1470. return 0;
  1471. }
  1472. static struct snd_kcontrol_new snd_ice1712_spdif_default =
  1473. {
  1474. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1475. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1476. .info = snd_ice1712_spdif_info,
  1477. .get = snd_ice1712_spdif_default_get,
  1478. .put = snd_ice1712_spdif_default_put
  1479. };
  1480. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1481. struct snd_ctl_elem_value *ucontrol)
  1482. {
  1483. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1484. if (ice->spdif.ops.default_get) {
  1485. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1486. IEC958_AES0_PROFESSIONAL |
  1487. IEC958_AES0_CON_NOT_COPYRIGHT |
  1488. IEC958_AES0_CON_EMPHASIS;
  1489. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1490. IEC958_AES1_CON_CATEGORY;
  1491. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1492. } else {
  1493. ucontrol->value.iec958.status[0] = 0xff;
  1494. ucontrol->value.iec958.status[1] = 0xff;
  1495. ucontrol->value.iec958.status[2] = 0xff;
  1496. ucontrol->value.iec958.status[3] = 0xff;
  1497. ucontrol->value.iec958.status[4] = 0xff;
  1498. }
  1499. return 0;
  1500. }
  1501. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1502. struct snd_ctl_elem_value *ucontrol)
  1503. {
  1504. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1505. if (ice->spdif.ops.default_get) {
  1506. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1507. IEC958_AES0_PROFESSIONAL |
  1508. IEC958_AES0_PRO_FS |
  1509. IEC958_AES0_PRO_EMPHASIS;
  1510. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1511. } else {
  1512. ucontrol->value.iec958.status[0] = 0xff;
  1513. ucontrol->value.iec958.status[1] = 0xff;
  1514. ucontrol->value.iec958.status[2] = 0xff;
  1515. ucontrol->value.iec958.status[3] = 0xff;
  1516. ucontrol->value.iec958.status[4] = 0xff;
  1517. }
  1518. return 0;
  1519. }
  1520. static struct snd_kcontrol_new snd_ice1712_spdif_maskc =
  1521. {
  1522. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1523. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1524. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1525. .info = snd_ice1712_spdif_info,
  1526. .get = snd_ice1712_spdif_maskc_get,
  1527. };
  1528. static struct snd_kcontrol_new snd_ice1712_spdif_maskp =
  1529. {
  1530. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1531. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1532. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1533. .info = snd_ice1712_spdif_info,
  1534. .get = snd_ice1712_spdif_maskp_get,
  1535. };
  1536. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1540. if (ice->spdif.ops.stream_get)
  1541. ice->spdif.ops.stream_get(ice, ucontrol);
  1542. return 0;
  1543. }
  1544. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1548. if (ice->spdif.ops.stream_put)
  1549. return ice->spdif.ops.stream_put(ice, ucontrol);
  1550. return 0;
  1551. }
  1552. static struct snd_kcontrol_new snd_ice1712_spdif_stream =
  1553. {
  1554. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1555. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1556. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1557. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1558. .info = snd_ice1712_spdif_info,
  1559. .get = snd_ice1712_spdif_stream_get,
  1560. .put = snd_ice1712_spdif_stream_put
  1561. };
  1562. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1563. struct snd_ctl_elem_value *ucontrol)
  1564. {
  1565. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1566. unsigned char mask = kcontrol->private_value & 0xff;
  1567. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1568. snd_ice1712_save_gpio_status(ice);
  1569. ucontrol->value.integer.value[0] =
  1570. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1571. snd_ice1712_restore_gpio_status(ice);
  1572. return 0;
  1573. }
  1574. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1575. struct snd_ctl_elem_value *ucontrol)
  1576. {
  1577. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1578. unsigned char mask = kcontrol->private_value & 0xff;
  1579. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1580. unsigned int val, nval;
  1581. if (kcontrol->private_value & (1 << 31))
  1582. return -EPERM;
  1583. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1584. snd_ice1712_save_gpio_status(ice);
  1585. val = snd_ice1712_gpio_read(ice);
  1586. nval |= val & ~mask;
  1587. if (val != nval)
  1588. snd_ice1712_gpio_write(ice, nval);
  1589. snd_ice1712_restore_gpio_status(ice);
  1590. return val != nval;
  1591. }
  1592. /*
  1593. * rate
  1594. */
  1595. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_info *uinfo)
  1597. {
  1598. static const char * const texts[] = {
  1599. "8000", /* 0: 6 */
  1600. "9600", /* 1: 3 */
  1601. "11025", /* 2: 10 */
  1602. "12000", /* 3: 2 */
  1603. "16000", /* 4: 5 */
  1604. "22050", /* 5: 9 */
  1605. "24000", /* 6: 1 */
  1606. "32000", /* 7: 4 */
  1607. "44100", /* 8: 8 */
  1608. "48000", /* 9: 0 */
  1609. "64000", /* 10: 15 */
  1610. "88200", /* 11: 11 */
  1611. "96000", /* 12: 7 */
  1612. "IEC958 Input", /* 13: -- */
  1613. };
  1614. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1615. uinfo->count = 1;
  1616. uinfo->value.enumerated.items = 14;
  1617. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1618. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1619. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1620. return 0;
  1621. }
  1622. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1623. struct snd_ctl_elem_value *ucontrol)
  1624. {
  1625. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1626. static const unsigned char xlate[16] = {
  1627. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1628. };
  1629. unsigned char val;
  1630. spin_lock_irq(&ice->reg_lock);
  1631. if (is_spdif_master(ice)) {
  1632. ucontrol->value.enumerated.item[0] = 13;
  1633. } else {
  1634. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1635. if (val == 255) {
  1636. snd_BUG();
  1637. val = 0;
  1638. }
  1639. ucontrol->value.enumerated.item[0] = val;
  1640. }
  1641. spin_unlock_irq(&ice->reg_lock);
  1642. return 0;
  1643. }
  1644. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1645. struct snd_ctl_elem_value *ucontrol)
  1646. {
  1647. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1648. static const unsigned int xrate[13] = {
  1649. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1650. 32000, 44100, 48000, 64000, 88200, 96000
  1651. };
  1652. unsigned char oval;
  1653. int change = 0;
  1654. spin_lock_irq(&ice->reg_lock);
  1655. oval = inb(ICEMT(ice, RATE));
  1656. if (ucontrol->value.enumerated.item[0] == 13) {
  1657. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1658. } else {
  1659. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1660. spin_unlock_irq(&ice->reg_lock);
  1661. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1662. spin_lock_irq(&ice->reg_lock);
  1663. }
  1664. change = inb(ICEMT(ice, RATE)) != oval;
  1665. spin_unlock_irq(&ice->reg_lock);
  1666. if ((oval & ICE1712_SPDIF_MASTER) !=
  1667. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1668. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1669. return change;
  1670. }
  1671. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
  1672. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1673. .name = "Multi Track Internal Clock",
  1674. .info = snd_ice1712_pro_internal_clock_info,
  1675. .get = snd_ice1712_pro_internal_clock_get,
  1676. .put = snd_ice1712_pro_internal_clock_put
  1677. };
  1678. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1679. struct snd_ctl_elem_info *uinfo)
  1680. {
  1681. static const char * const texts[] = {
  1682. "8000", /* 0: 6 */
  1683. "9600", /* 1: 3 */
  1684. "11025", /* 2: 10 */
  1685. "12000", /* 3: 2 */
  1686. "16000", /* 4: 5 */
  1687. "22050", /* 5: 9 */
  1688. "24000", /* 6: 1 */
  1689. "32000", /* 7: 4 */
  1690. "44100", /* 8: 8 */
  1691. "48000", /* 9: 0 */
  1692. "64000", /* 10: 15 */
  1693. "88200", /* 11: 11 */
  1694. "96000", /* 12: 7 */
  1695. /* "IEC958 Input", 13: -- */
  1696. };
  1697. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1698. uinfo->count = 1;
  1699. uinfo->value.enumerated.items = 13;
  1700. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1701. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1702. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1703. return 0;
  1704. }
  1705. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1706. struct snd_ctl_elem_value *ucontrol)
  1707. {
  1708. int val;
  1709. static const unsigned int xrate[13] = {
  1710. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1711. 32000, 44100, 48000, 64000, 88200, 96000
  1712. };
  1713. for (val = 0; val < 13; val++) {
  1714. if (xrate[val] == PRO_RATE_DEFAULT)
  1715. break;
  1716. }
  1717. ucontrol->value.enumerated.item[0] = val;
  1718. return 0;
  1719. }
  1720. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1721. struct snd_ctl_elem_value *ucontrol)
  1722. {
  1723. static const unsigned int xrate[13] = {
  1724. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1725. 32000, 44100, 48000, 64000, 88200, 96000
  1726. };
  1727. unsigned char oval;
  1728. int change = 0;
  1729. oval = PRO_RATE_DEFAULT;
  1730. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1731. change = PRO_RATE_DEFAULT != oval;
  1732. return change;
  1733. }
  1734. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
  1735. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1736. .name = "Multi Track Internal Clock Default",
  1737. .info = snd_ice1712_pro_internal_clock_default_info,
  1738. .get = snd_ice1712_pro_internal_clock_default_get,
  1739. .put = snd_ice1712_pro_internal_clock_default_put
  1740. };
  1741. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1742. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1743. struct snd_ctl_elem_value *ucontrol)
  1744. {
  1745. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1746. return 0;
  1747. }
  1748. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1749. struct snd_ctl_elem_value *ucontrol)
  1750. {
  1751. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1752. int change = 0, nval;
  1753. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1754. spin_lock_irq(&ice->reg_lock);
  1755. change = PRO_RATE_LOCKED != nval;
  1756. PRO_RATE_LOCKED = nval;
  1757. spin_unlock_irq(&ice->reg_lock);
  1758. return change;
  1759. }
  1760. static struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
  1761. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1762. .name = "Multi Track Rate Locking",
  1763. .info = snd_ice1712_pro_rate_locking_info,
  1764. .get = snd_ice1712_pro_rate_locking_get,
  1765. .put = snd_ice1712_pro_rate_locking_put
  1766. };
  1767. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1768. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1769. struct snd_ctl_elem_value *ucontrol)
  1770. {
  1771. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1772. return 0;
  1773. }
  1774. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1775. struct snd_ctl_elem_value *ucontrol)
  1776. {
  1777. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1778. int change = 0, nval;
  1779. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1780. spin_lock_irq(&ice->reg_lock);
  1781. change = PRO_RATE_RESET != nval;
  1782. PRO_RATE_RESET = nval;
  1783. spin_unlock_irq(&ice->reg_lock);
  1784. return change;
  1785. }
  1786. static struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
  1787. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1788. .name = "Multi Track Rate Reset",
  1789. .info = snd_ice1712_pro_rate_reset_info,
  1790. .get = snd_ice1712_pro_rate_reset_get,
  1791. .put = snd_ice1712_pro_rate_reset_put
  1792. };
  1793. /*
  1794. * routing
  1795. */
  1796. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1797. struct snd_ctl_elem_info *uinfo)
  1798. {
  1799. static const char * const texts[] = {
  1800. "PCM Out", /* 0 */
  1801. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1802. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1803. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1804. "Digital Mixer", /* 11 - optional */
  1805. };
  1806. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1807. uinfo->count = 1;
  1808. uinfo->value.enumerated.items =
  1809. snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1810. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1811. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1812. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1813. return 0;
  1814. }
  1815. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1816. struct snd_ctl_elem_value *ucontrol)
  1817. {
  1818. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1819. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1820. unsigned int val, cval;
  1821. spin_lock_irq(&ice->reg_lock);
  1822. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1823. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1824. spin_unlock_irq(&ice->reg_lock);
  1825. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1826. val &= 3;
  1827. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1828. if (val == 1 && idx < 2)
  1829. ucontrol->value.enumerated.item[0] = 11;
  1830. else if (val == 2)
  1831. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1832. else if (val == 3)
  1833. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1834. else
  1835. ucontrol->value.enumerated.item[0] = 0;
  1836. return 0;
  1837. }
  1838. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1839. struct snd_ctl_elem_value *ucontrol)
  1840. {
  1841. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1842. int change, shift;
  1843. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1844. unsigned int val, old_val, nval;
  1845. /* update PSDOUT */
  1846. if (ucontrol->value.enumerated.item[0] >= 11)
  1847. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1848. else if (ucontrol->value.enumerated.item[0] >= 9)
  1849. nval = 3; /* spdif in */
  1850. else if (ucontrol->value.enumerated.item[0] >= 1)
  1851. nval = 2; /* analog in */
  1852. else
  1853. nval = 0; /* pcm */
  1854. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1855. spin_lock_irq(&ice->reg_lock);
  1856. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1857. val &= ~(0x03 << shift);
  1858. val |= nval << shift;
  1859. change = val != old_val;
  1860. if (change)
  1861. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1862. spin_unlock_irq(&ice->reg_lock);
  1863. if (nval < 2) /* dig mixer of pcm */
  1864. return change;
  1865. /* update CAPTURE */
  1866. spin_lock_irq(&ice->reg_lock);
  1867. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1868. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1869. if (nval == 2) { /* analog in */
  1870. nval = ucontrol->value.enumerated.item[0] - 1;
  1871. val &= ~(0x07 << shift);
  1872. val |= nval << shift;
  1873. } else { /* spdif in */
  1874. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1875. val &= ~(0x08 << shift);
  1876. val |= nval << shift;
  1877. }
  1878. if (val != old_val) {
  1879. change = 1;
  1880. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1881. }
  1882. spin_unlock_irq(&ice->reg_lock);
  1883. return change;
  1884. }
  1885. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1886. struct snd_ctl_elem_value *ucontrol)
  1887. {
  1888. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1889. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1890. unsigned int val, cval;
  1891. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1892. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1893. val = (val >> (idx * 2)) & 0x03;
  1894. if (val == 1)
  1895. ucontrol->value.enumerated.item[0] = 11;
  1896. else if (val == 2)
  1897. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1898. else if (val == 3)
  1899. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1900. else
  1901. ucontrol->value.enumerated.item[0] = 0;
  1902. return 0;
  1903. }
  1904. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1905. struct snd_ctl_elem_value *ucontrol)
  1906. {
  1907. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1908. int change, shift;
  1909. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1910. unsigned int val, old_val, nval;
  1911. /* update SPDOUT */
  1912. spin_lock_irq(&ice->reg_lock);
  1913. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1914. if (ucontrol->value.enumerated.item[0] >= 11)
  1915. nval = 1;
  1916. else if (ucontrol->value.enumerated.item[0] >= 9)
  1917. nval = 3;
  1918. else if (ucontrol->value.enumerated.item[0] >= 1)
  1919. nval = 2;
  1920. else
  1921. nval = 0;
  1922. shift = idx * 2;
  1923. val &= ~(0x03 << shift);
  1924. val |= nval << shift;
  1925. shift = idx * 4 + 8;
  1926. if (nval == 2) {
  1927. nval = ucontrol->value.enumerated.item[0] - 1;
  1928. val &= ~(0x07 << shift);
  1929. val |= nval << shift;
  1930. } else if (nval == 3) {
  1931. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1932. val &= ~(0x08 << shift);
  1933. val |= nval << shift;
  1934. }
  1935. change = val != old_val;
  1936. if (change)
  1937. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1938. spin_unlock_irq(&ice->reg_lock);
  1939. return change;
  1940. }
  1941. static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
  1942. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1943. .name = "H/W Playback Route",
  1944. .info = snd_ice1712_pro_route_info,
  1945. .get = snd_ice1712_pro_route_analog_get,
  1946. .put = snd_ice1712_pro_route_analog_put,
  1947. };
  1948. static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
  1949. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1950. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1951. .info = snd_ice1712_pro_route_info,
  1952. .get = snd_ice1712_pro_route_spdif_get,
  1953. .put = snd_ice1712_pro_route_spdif_put,
  1954. .count = 2,
  1955. };
  1956. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1957. struct snd_ctl_elem_info *uinfo)
  1958. {
  1959. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1960. uinfo->count = 1;
  1961. uinfo->value.integer.min = 0;
  1962. uinfo->value.integer.max = 255;
  1963. return 0;
  1964. }
  1965. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1966. struct snd_ctl_elem_value *ucontrol)
  1967. {
  1968. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1969. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1970. return 0;
  1971. }
  1972. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1973. struct snd_ctl_elem_value *ucontrol)
  1974. {
  1975. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1976. int change;
  1977. spin_lock_irq(&ice->reg_lock);
  1978. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1979. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1980. spin_unlock_irq(&ice->reg_lock);
  1981. return change;
  1982. }
  1983. static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
  1984. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1985. .name = "Multi Track Volume Rate",
  1986. .info = snd_ice1712_pro_volume_rate_info,
  1987. .get = snd_ice1712_pro_volume_rate_get,
  1988. .put = snd_ice1712_pro_volume_rate_put
  1989. };
  1990. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  1991. struct snd_ctl_elem_info *uinfo)
  1992. {
  1993. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1994. uinfo->count = 22;
  1995. uinfo->value.integer.min = 0;
  1996. uinfo->value.integer.max = 255;
  1997. return 0;
  1998. }
  1999. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  2000. struct snd_ctl_elem_value *ucontrol)
  2001. {
  2002. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  2003. int idx;
  2004. spin_lock_irq(&ice->reg_lock);
  2005. for (idx = 0; idx < 22; idx++) {
  2006. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  2007. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  2008. }
  2009. spin_unlock_irq(&ice->reg_lock);
  2010. return 0;
  2011. }
  2012. static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
  2013. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2014. .name = "Multi Track Peak",
  2015. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  2016. .info = snd_ice1712_pro_peak_info,
  2017. .get = snd_ice1712_pro_peak_get
  2018. };
  2019. /*
  2020. *
  2021. */
  2022. /*
  2023. * list of available boards
  2024. */
  2025. static struct snd_ice1712_card_info *card_tables[] = {
  2026. snd_ice1712_hoontech_cards,
  2027. snd_ice1712_delta_cards,
  2028. snd_ice1712_ews_cards,
  2029. NULL,
  2030. };
  2031. static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2032. unsigned char dev,
  2033. unsigned char addr)
  2034. {
  2035. long t = 0x10000;
  2036. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2037. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2038. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2039. return inb(ICEREG(ice, I2C_DATA));
  2040. }
  2041. static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2042. const char *modelname)
  2043. {
  2044. int dev = 0xa0; /* EEPROM device address */
  2045. unsigned int i, size;
  2046. struct snd_ice1712_card_info * const *tbl, *c;
  2047. if (!modelname || !*modelname) {
  2048. ice->eeprom.subvendor = 0;
  2049. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2050. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2051. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2052. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2053. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2054. if (ice->eeprom.subvendor == 0 ||
  2055. ice->eeprom.subvendor == (unsigned int)-1) {
  2056. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2057. u16 vendor, device;
  2058. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2059. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2060. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2061. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2062. printk(KERN_ERR "ice1712: No valid ID is found\n");
  2063. return -ENXIO;
  2064. }
  2065. }
  2066. }
  2067. for (tbl = card_tables; *tbl; tbl++) {
  2068. for (c = *tbl; c->subvendor; c++) {
  2069. if (modelname && c->model && !strcmp(modelname, c->model)) {
  2070. printk(KERN_INFO "ice1712: Using board model %s\n", c->name);
  2071. ice->eeprom.subvendor = c->subvendor;
  2072. } else if (c->subvendor != ice->eeprom.subvendor)
  2073. continue;
  2074. if (!c->eeprom_size || !c->eeprom_data)
  2075. goto found;
  2076. /* if the EEPROM is given by the driver, use it */
  2077. snd_printdd("using the defined eeprom..\n");
  2078. ice->eeprom.version = 1;
  2079. ice->eeprom.size = c->eeprom_size + 6;
  2080. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2081. goto read_skipped;
  2082. }
  2083. }
  2084. printk(KERN_WARNING "ice1712: No matching model found for ID 0x%x\n",
  2085. ice->eeprom.subvendor);
  2086. found:
  2087. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2088. if (ice->eeprom.size < 6)
  2089. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2090. else if (ice->eeprom.size > 32) {
  2091. snd_printk(KERN_ERR "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2092. return -EIO;
  2093. }
  2094. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2095. if (ice->eeprom.version != 1) {
  2096. snd_printk(KERN_ERR "invalid EEPROM version %i\n",
  2097. ice->eeprom.version);
  2098. /* return -EIO; */
  2099. }
  2100. size = ice->eeprom.size - 6;
  2101. for (i = 0; i < size; i++)
  2102. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2103. read_skipped:
  2104. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2105. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2106. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2107. return 0;
  2108. }
  2109. static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2110. {
  2111. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2112. udelay(200);
  2113. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2114. udelay(200);
  2115. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2116. !ice->dxr_enable)
  2117. /* Set eeprom value to limit active ADCs and DACs to 6;
  2118. * Also disable AC97 as no hardware in standard 6fire card/box
  2119. * Note: DXR extensions are not currently supported
  2120. */
  2121. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2122. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2123. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2124. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2125. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2126. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2127. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2128. ice->gpio.direction = ice->eeprom.gpiodir;
  2129. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2130. ice->eeprom.gpiomask);
  2131. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2132. ice->eeprom.gpiodir);
  2133. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2134. ice->eeprom.gpiostate);
  2135. } else {
  2136. ice->gpio.write_mask = 0xc0;
  2137. ice->gpio.direction = 0xff;
  2138. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2139. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2140. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2141. ICE1712_STDSP24_CLOCK_BIT);
  2142. }
  2143. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2144. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2145. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2146. udelay(100);
  2147. outb(0, ICEREG(ice, AC97_CMD));
  2148. udelay(200);
  2149. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2150. }
  2151. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2152. return 0;
  2153. }
  2154. int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2155. {
  2156. int err;
  2157. struct snd_kcontrol *kctl;
  2158. if (snd_BUG_ON(!ice->pcm_pro))
  2159. return -EIO;
  2160. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2161. if (err < 0)
  2162. return err;
  2163. kctl->id.device = ice->pcm_pro->device;
  2164. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2165. if (err < 0)
  2166. return err;
  2167. kctl->id.device = ice->pcm_pro->device;
  2168. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2169. if (err < 0)
  2170. return err;
  2171. kctl->id.device = ice->pcm_pro->device;
  2172. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2173. if (err < 0)
  2174. return err;
  2175. kctl->id.device = ice->pcm_pro->device;
  2176. ice->spdif.stream_ctl = kctl;
  2177. return 0;
  2178. }
  2179. static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2180. {
  2181. int err;
  2182. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2183. if (err < 0)
  2184. return err;
  2185. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2186. if (err < 0)
  2187. return err;
  2188. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2189. if (err < 0)
  2190. return err;
  2191. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2192. if (err < 0)
  2193. return err;
  2194. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2195. if (err < 0)
  2196. return err;
  2197. if (ice->num_total_dacs > 0) {
  2198. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2199. tmp.count = ice->num_total_dacs;
  2200. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2201. if (err < 0)
  2202. return err;
  2203. }
  2204. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2205. if (err < 0)
  2206. return err;
  2207. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2208. if (err < 0)
  2209. return err;
  2210. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2211. if (err < 0)
  2212. return err;
  2213. return 0;
  2214. }
  2215. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2216. {
  2217. if (!ice->port)
  2218. goto __hw_end;
  2219. /* mask all interrupts */
  2220. outb(0xc0, ICEMT(ice, IRQ));
  2221. outb(0xff, ICEREG(ice, IRQMASK));
  2222. /* --- */
  2223. __hw_end:
  2224. if (ice->irq >= 0)
  2225. free_irq(ice->irq, ice);
  2226. if (ice->port)
  2227. pci_release_regions(ice->pci);
  2228. snd_ice1712_akm4xxx_free(ice);
  2229. pci_disable_device(ice->pci);
  2230. kfree(ice->spec);
  2231. kfree(ice);
  2232. return 0;
  2233. }
  2234. static int snd_ice1712_dev_free(struct snd_device *device)
  2235. {
  2236. struct snd_ice1712 *ice = device->device_data;
  2237. return snd_ice1712_free(ice);
  2238. }
  2239. static int snd_ice1712_create(struct snd_card *card,
  2240. struct pci_dev *pci,
  2241. const char *modelname,
  2242. int omni,
  2243. int cs8427_timeout,
  2244. int dxr_enable,
  2245. struct snd_ice1712 **r_ice1712)
  2246. {
  2247. struct snd_ice1712 *ice;
  2248. int err;
  2249. static struct snd_device_ops ops = {
  2250. .dev_free = snd_ice1712_dev_free,
  2251. };
  2252. *r_ice1712 = NULL;
  2253. /* enable PCI device */
  2254. err = pci_enable_device(pci);
  2255. if (err < 0)
  2256. return err;
  2257. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2258. if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
  2259. pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
  2260. snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
  2261. pci_disable_device(pci);
  2262. return -ENXIO;
  2263. }
  2264. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2265. if (ice == NULL) {
  2266. pci_disable_device(pci);
  2267. return -ENOMEM;
  2268. }
  2269. ice->omni = omni ? 1 : 0;
  2270. if (cs8427_timeout < 1)
  2271. cs8427_timeout = 1;
  2272. else if (cs8427_timeout > 1000)
  2273. cs8427_timeout = 1000;
  2274. ice->cs8427_timeout = cs8427_timeout;
  2275. ice->dxr_enable = dxr_enable;
  2276. spin_lock_init(&ice->reg_lock);
  2277. mutex_init(&ice->gpio_mutex);
  2278. mutex_init(&ice->i2c_mutex);
  2279. mutex_init(&ice->open_mutex);
  2280. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2281. ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
  2282. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2283. ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
  2284. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2285. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2286. ice->spdif.cs8403_bits =
  2287. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2288. 0x10 | /* no emphasis */
  2289. 0x20); /* PCM encoder/decoder */
  2290. ice->card = card;
  2291. ice->pci = pci;
  2292. ice->irq = -1;
  2293. pci_set_master(pci);
  2294. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2295. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2296. snd_ice1712_proc_init(ice);
  2297. synchronize_irq(pci->irq);
  2298. card->private_data = ice;
  2299. err = pci_request_regions(pci, "ICE1712");
  2300. if (err < 0) {
  2301. kfree(ice);
  2302. pci_disable_device(pci);
  2303. return err;
  2304. }
  2305. ice->port = pci_resource_start(pci, 0);
  2306. ice->ddma_port = pci_resource_start(pci, 1);
  2307. ice->dmapath_port = pci_resource_start(pci, 2);
  2308. ice->profi_port = pci_resource_start(pci, 3);
  2309. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2310. KBUILD_MODNAME, ice)) {
  2311. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2312. snd_ice1712_free(ice);
  2313. return -EIO;
  2314. }
  2315. ice->irq = pci->irq;
  2316. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2317. snd_ice1712_free(ice);
  2318. return -EIO;
  2319. }
  2320. if (snd_ice1712_chip_init(ice) < 0) {
  2321. snd_ice1712_free(ice);
  2322. return -EIO;
  2323. }
  2324. /* unmask used interrupts */
  2325. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2326. ICE1712_IRQ_MPU2 : 0) |
  2327. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2328. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2329. ICEREG(ice, IRQMASK));
  2330. outb(0x00, ICEMT(ice, IRQ));
  2331. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2332. if (err < 0) {
  2333. snd_ice1712_free(ice);
  2334. return err;
  2335. }
  2336. snd_card_set_dev(card, &pci->dev);
  2337. *r_ice1712 = ice;
  2338. return 0;
  2339. }
  2340. /*
  2341. *
  2342. * Registration
  2343. *
  2344. */
  2345. static struct snd_ice1712_card_info no_matched;
  2346. static int snd_ice1712_probe(struct pci_dev *pci,
  2347. const struct pci_device_id *pci_id)
  2348. {
  2349. static int dev;
  2350. struct snd_card *card;
  2351. struct snd_ice1712 *ice;
  2352. int pcm_dev = 0, err;
  2353. struct snd_ice1712_card_info * const *tbl, *c;
  2354. if (dev >= SNDRV_CARDS)
  2355. return -ENODEV;
  2356. if (!enable[dev]) {
  2357. dev++;
  2358. return -ENOENT;
  2359. }
  2360. err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
  2361. if (err < 0)
  2362. return err;
  2363. strcpy(card->driver, "ICE1712");
  2364. strcpy(card->shortname, "ICEnsemble ICE1712");
  2365. err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2366. cs8427_timeout[dev], dxr_enable[dev], &ice);
  2367. if (err < 0) {
  2368. snd_card_free(card);
  2369. return err;
  2370. }
  2371. for (tbl = card_tables; *tbl; tbl++) {
  2372. for (c = *tbl; c->subvendor; c++) {
  2373. if (c->subvendor == ice->eeprom.subvendor) {
  2374. ice->card_info = c;
  2375. strcpy(card->shortname, c->name);
  2376. if (c->driver) /* specific driver? */
  2377. strcpy(card->driver, c->driver);
  2378. if (c->chip_init) {
  2379. err = c->chip_init(ice);
  2380. if (err < 0) {
  2381. snd_card_free(card);
  2382. return err;
  2383. }
  2384. }
  2385. goto __found;
  2386. }
  2387. }
  2388. }
  2389. c = &no_matched;
  2390. __found:
  2391. err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL);
  2392. if (err < 0) {
  2393. snd_card_free(card);
  2394. return err;
  2395. }
  2396. if (ice_has_con_ac97(ice)) {
  2397. err = snd_ice1712_pcm(ice, pcm_dev++, NULL);
  2398. if (err < 0) {
  2399. snd_card_free(card);
  2400. return err;
  2401. }
  2402. }
  2403. err = snd_ice1712_ac97_mixer(ice);
  2404. if (err < 0) {
  2405. snd_card_free(card);
  2406. return err;
  2407. }
  2408. err = snd_ice1712_build_controls(ice);
  2409. if (err < 0) {
  2410. snd_card_free(card);
  2411. return err;
  2412. }
  2413. if (c->build_controls) {
  2414. err = c->build_controls(ice);
  2415. if (err < 0) {
  2416. snd_card_free(card);
  2417. return err;
  2418. }
  2419. }
  2420. if (ice_has_con_ac97(ice)) {
  2421. err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL);
  2422. if (err < 0) {
  2423. snd_card_free(card);
  2424. return err;
  2425. }
  2426. }
  2427. if (!c->no_mpu401) {
  2428. err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2429. ICEREG(ice, MPU1_CTRL),
  2430. c->mpu401_1_info_flags |
  2431. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2432. -1, &ice->rmidi[0]);
  2433. if (err < 0) {
  2434. snd_card_free(card);
  2435. return err;
  2436. }
  2437. if (c->mpu401_1_name)
  2438. /* Preferred name available in card_info */
  2439. snprintf(ice->rmidi[0]->name,
  2440. sizeof(ice->rmidi[0]->name),
  2441. "%s %d", c->mpu401_1_name, card->number);
  2442. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2443. /* 2nd port used */
  2444. err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2445. ICEREG(ice, MPU2_CTRL),
  2446. c->mpu401_2_info_flags |
  2447. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2448. -1, &ice->rmidi[1]);
  2449. if (err < 0) {
  2450. snd_card_free(card);
  2451. return err;
  2452. }
  2453. if (c->mpu401_2_name)
  2454. /* Preferred name available in card_info */
  2455. snprintf(ice->rmidi[1]->name,
  2456. sizeof(ice->rmidi[1]->name),
  2457. "%s %d", c->mpu401_2_name,
  2458. card->number);
  2459. }
  2460. }
  2461. snd_ice1712_set_input_clock_source(ice, 0);
  2462. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2463. card->shortname, ice->port, ice->irq);
  2464. err = snd_card_register(card);
  2465. if (err < 0) {
  2466. snd_card_free(card);
  2467. return err;
  2468. }
  2469. pci_set_drvdata(pci, card);
  2470. dev++;
  2471. return 0;
  2472. }
  2473. static void snd_ice1712_remove(struct pci_dev *pci)
  2474. {
  2475. struct snd_card *card = pci_get_drvdata(pci);
  2476. struct snd_ice1712 *ice = card->private_data;
  2477. if (ice->card_info && ice->card_info->chip_exit)
  2478. ice->card_info->chip_exit(ice);
  2479. snd_card_free(card);
  2480. pci_set_drvdata(pci, NULL);
  2481. }
  2482. static struct pci_driver ice1712_driver = {
  2483. .name = KBUILD_MODNAME,
  2484. .id_table = snd_ice1712_ids,
  2485. .probe = snd_ice1712_probe,
  2486. .remove = snd_ice1712_remove,
  2487. };
  2488. module_pci_driver(ice1712_driver);