adv7604.h 4.4 KB

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  1. /*
  2. * adv7604 - Analog Devices ADV7604 video decoder driver
  3. *
  4. * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
  5. *
  6. * This program is free software; you may redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17. * SOFTWARE.
  18. *
  19. */
  20. #ifndef _ADV7604_
  21. #define _ADV7604_
  22. /* Analog input muxing modes (AFE register 0x02, [2:0]) */
  23. enum adv7604_ain_sel {
  24. ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
  25. ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
  26. ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
  27. ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
  28. ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
  29. };
  30. /* Bus rotation and reordering (IO register 0x04, [7:5]) */
  31. enum adv7604_op_ch_sel {
  32. ADV7604_OP_CH_SEL_GBR = 0,
  33. ADV7604_OP_CH_SEL_GRB = 1,
  34. ADV7604_OP_CH_SEL_BGR = 2,
  35. ADV7604_OP_CH_SEL_RGB = 3,
  36. ADV7604_OP_CH_SEL_BRG = 4,
  37. ADV7604_OP_CH_SEL_RBG = 5,
  38. };
  39. /* Input Color Space (IO register 0x02, [7:4]) */
  40. enum adv7604_inp_color_space {
  41. ADV7604_INP_COLOR_SPACE_LIM_RGB = 0,
  42. ADV7604_INP_COLOR_SPACE_FULL_RGB = 1,
  43. ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
  44. ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
  45. ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4,
  46. ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5,
  47. ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
  48. ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
  49. ADV7604_INP_COLOR_SPACE_AUTO = 0xf,
  50. };
  51. /* Select output format (IO register 0x03, [7:0]) */
  52. enum adv7604_op_format_sel {
  53. ADV7604_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
  54. ADV7604_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
  55. ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
  56. ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
  57. ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
  58. ADV7604_OP_FORMAT_SEL_DDR_422_8 = 0x20,
  59. ADV7604_OP_FORMAT_SEL_DDR_422_10 = 0x21,
  60. ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
  61. ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
  62. ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
  63. ADV7604_OP_FORMAT_SEL_SDR_444_24 = 0x40,
  64. ADV7604_OP_FORMAT_SEL_SDR_444_30 = 0x41,
  65. ADV7604_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
  66. ADV7604_OP_FORMAT_SEL_DDR_444_24 = 0x60,
  67. ADV7604_OP_FORMAT_SEL_DDR_444_30 = 0x61,
  68. ADV7604_OP_FORMAT_SEL_DDR_444_36 = 0x62,
  69. ADV7604_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
  70. ADV7604_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
  71. ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
  72. ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
  73. ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
  74. };
  75. /* Platform dependent definition */
  76. struct adv7604_platform_data {
  77. /* connector - HDMI or DVI? */
  78. unsigned connector_hdmi:1;
  79. /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
  80. unsigned disable_pwrdnb:1;
  81. /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
  82. unsigned disable_cable_det_rst:1;
  83. /* Analog input muxing mode */
  84. enum adv7604_ain_sel ain_sel;
  85. /* Bus rotation and reordering */
  86. enum adv7604_op_ch_sel op_ch_sel;
  87. /* Select output format */
  88. enum adv7604_op_format_sel op_format_sel;
  89. /* IO register 0x02 */
  90. unsigned alt_gamma:1;
  91. unsigned op_656_range:1;
  92. unsigned rgb_out:1;
  93. unsigned alt_data_sat:1;
  94. /* IO register 0x05 */
  95. unsigned blank_data:1;
  96. unsigned insert_av_codes:1;
  97. unsigned replicate_av_codes:1;
  98. unsigned invert_cbcr:1;
  99. /* IO register 0x30 */
  100. unsigned output_bus_lsb_to_msb:1;
  101. /* Free run */
  102. unsigned hdmi_free_run_mode;
  103. /* i2c addresses: 0 == use default */
  104. u8 i2c_avlink;
  105. u8 i2c_cec;
  106. u8 i2c_infoframe;
  107. u8 i2c_esdp;
  108. u8 i2c_dpp;
  109. u8 i2c_afe;
  110. u8 i2c_repeater;
  111. u8 i2c_edid;
  112. u8 i2c_hdmi;
  113. u8 i2c_test;
  114. u8 i2c_cp;
  115. u8 i2c_vdp;
  116. };
  117. /*
  118. * Mode of operation.
  119. * This is used as the input argument of the s_routing video op.
  120. */
  121. enum adv7604_mode {
  122. ADV7604_MODE_COMP,
  123. ADV7604_MODE_GR,
  124. ADV7604_MODE_HDMI,
  125. };
  126. #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
  127. #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
  128. #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
  129. /* notify events */
  130. #define ADV7604_HOTPLUG 1
  131. #define ADV7604_FMT_CHANGE 2
  132. #endif