events.c 43 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882
  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #ifdef CONFIG_X86
  33. #include <asm/desc.h>
  34. #include <asm/ptrace.h>
  35. #include <asm/irq.h>
  36. #include <asm/idle.h>
  37. #include <asm/io_apic.h>
  38. #include <asm/xen/page.h>
  39. #include <asm/xen/pci.h>
  40. #endif
  41. #include <asm/sync_bitops.h>
  42. #include <asm/xen/hypercall.h>
  43. #include <asm/xen/hypervisor.h>
  44. #include <xen/xen.h>
  45. #include <xen/hvm.h>
  46. #include <xen/xen-ops.h>
  47. #include <xen/events.h>
  48. #include <xen/interface/xen.h>
  49. #include <xen/interface/event_channel.h>
  50. #include <xen/interface/hvm/hvm_op.h>
  51. #include <xen/interface/hvm/params.h>
  52. #include <xen/interface/physdev.h>
  53. #include <xen/interface/sched.h>
  54. #include <asm/hw_irq.h>
  55. /*
  56. * This lock protects updates to the following mapping and reference-count
  57. * arrays. The lock does not need to be acquired to read the mapping tables.
  58. */
  59. static DEFINE_MUTEX(irq_mapping_update_lock);
  60. static LIST_HEAD(xen_irq_list_head);
  61. /* IRQ <-> VIRQ mapping. */
  62. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  63. /* IRQ <-> IPI mapping */
  64. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  65. /* Interrupt types. */
  66. enum xen_irq_type {
  67. IRQT_UNBOUND = 0,
  68. IRQT_PIRQ,
  69. IRQT_VIRQ,
  70. IRQT_IPI,
  71. IRQT_EVTCHN
  72. };
  73. /*
  74. * Packed IRQ information:
  75. * type - enum xen_irq_type
  76. * event channel - irq->event channel mapping
  77. * cpu - cpu this event channel is bound to
  78. * index - type-specific information:
  79. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  80. * guest, or GSI (real passthrough IRQ) of the device.
  81. * VIRQ - virq number
  82. * IPI - IPI vector
  83. * EVTCHN -
  84. */
  85. struct irq_info {
  86. struct list_head list;
  87. int refcnt;
  88. enum xen_irq_type type; /* type */
  89. unsigned irq;
  90. unsigned short evtchn; /* event channel */
  91. unsigned short cpu; /* cpu bound */
  92. union {
  93. unsigned short virq;
  94. enum ipi_vector ipi;
  95. struct {
  96. unsigned short pirq;
  97. unsigned short gsi;
  98. unsigned char vector;
  99. unsigned char flags;
  100. uint16_t domid;
  101. } pirq;
  102. } u;
  103. };
  104. #define PIRQ_NEEDS_EOI (1 << 0)
  105. #define PIRQ_SHAREABLE (1 << 1)
  106. static int *evtchn_to_irq;
  107. #ifdef CONFIG_X86
  108. static unsigned long *pirq_eoi_map;
  109. #endif
  110. static bool (*pirq_needs_eoi)(unsigned irq);
  111. /*
  112. * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
  113. * careful to only use bitops which allow for this (e.g
  114. * test_bit/find_first_bit and friends but not __ffs) and to pass
  115. * BITS_PER_EVTCHN_WORD as the bitmask length.
  116. */
  117. #define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
  118. /*
  119. * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
  120. * array. Primarily to avoid long lines (hence the terse name).
  121. */
  122. #define BM(x) (unsigned long *)(x)
  123. /* Find the first set bit in a evtchn mask */
  124. #define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
  125. static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
  126. cpu_evtchn_mask);
  127. /* Xen will never allocate port zero for any purpose. */
  128. #define VALID_EVTCHN(chn) ((chn) != 0)
  129. static struct irq_chip xen_dynamic_chip;
  130. static struct irq_chip xen_percpu_chip;
  131. static struct irq_chip xen_pirq_chip;
  132. static void enable_dynirq(struct irq_data *data);
  133. static void disable_dynirq(struct irq_data *data);
  134. /* Get info for IRQ */
  135. static struct irq_info *info_for_irq(unsigned irq)
  136. {
  137. return irq_get_handler_data(irq);
  138. }
  139. /* Constructors for packed IRQ information. */
  140. static void xen_irq_info_common_init(struct irq_info *info,
  141. unsigned irq,
  142. enum xen_irq_type type,
  143. unsigned short evtchn,
  144. unsigned short cpu)
  145. {
  146. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  147. info->type = type;
  148. info->irq = irq;
  149. info->evtchn = evtchn;
  150. info->cpu = cpu;
  151. evtchn_to_irq[evtchn] = irq;
  152. }
  153. static void xen_irq_info_evtchn_init(unsigned irq,
  154. unsigned short evtchn)
  155. {
  156. struct irq_info *info = info_for_irq(irq);
  157. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  158. }
  159. static void xen_irq_info_ipi_init(unsigned cpu,
  160. unsigned irq,
  161. unsigned short evtchn,
  162. enum ipi_vector ipi)
  163. {
  164. struct irq_info *info = info_for_irq(irq);
  165. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  166. info->u.ipi = ipi;
  167. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  168. }
  169. static void xen_irq_info_virq_init(unsigned cpu,
  170. unsigned irq,
  171. unsigned short evtchn,
  172. unsigned short virq)
  173. {
  174. struct irq_info *info = info_for_irq(irq);
  175. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  176. info->u.virq = virq;
  177. per_cpu(virq_to_irq, cpu)[virq] = irq;
  178. }
  179. static void xen_irq_info_pirq_init(unsigned irq,
  180. unsigned short evtchn,
  181. unsigned short pirq,
  182. unsigned short gsi,
  183. unsigned short vector,
  184. uint16_t domid,
  185. unsigned char flags)
  186. {
  187. struct irq_info *info = info_for_irq(irq);
  188. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  189. info->u.pirq.pirq = pirq;
  190. info->u.pirq.gsi = gsi;
  191. info->u.pirq.vector = vector;
  192. info->u.pirq.domid = domid;
  193. info->u.pirq.flags = flags;
  194. }
  195. /*
  196. * Accessors for packed IRQ information.
  197. */
  198. static unsigned int evtchn_from_irq(unsigned irq)
  199. {
  200. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  201. return 0;
  202. return info_for_irq(irq)->evtchn;
  203. }
  204. unsigned irq_from_evtchn(unsigned int evtchn)
  205. {
  206. return evtchn_to_irq[evtchn];
  207. }
  208. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  209. static enum ipi_vector ipi_from_irq(unsigned irq)
  210. {
  211. struct irq_info *info = info_for_irq(irq);
  212. BUG_ON(info == NULL);
  213. BUG_ON(info->type != IRQT_IPI);
  214. return info->u.ipi;
  215. }
  216. static unsigned virq_from_irq(unsigned irq)
  217. {
  218. struct irq_info *info = info_for_irq(irq);
  219. BUG_ON(info == NULL);
  220. BUG_ON(info->type != IRQT_VIRQ);
  221. return info->u.virq;
  222. }
  223. static unsigned pirq_from_irq(unsigned irq)
  224. {
  225. struct irq_info *info = info_for_irq(irq);
  226. BUG_ON(info == NULL);
  227. BUG_ON(info->type != IRQT_PIRQ);
  228. return info->u.pirq.pirq;
  229. }
  230. static enum xen_irq_type type_from_irq(unsigned irq)
  231. {
  232. return info_for_irq(irq)->type;
  233. }
  234. static unsigned cpu_from_irq(unsigned irq)
  235. {
  236. return info_for_irq(irq)->cpu;
  237. }
  238. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  239. {
  240. int irq = evtchn_to_irq[evtchn];
  241. unsigned ret = 0;
  242. if (irq != -1)
  243. ret = cpu_from_irq(irq);
  244. return ret;
  245. }
  246. #ifdef CONFIG_X86
  247. static bool pirq_check_eoi_map(unsigned irq)
  248. {
  249. return test_bit(pirq_from_irq(irq), pirq_eoi_map);
  250. }
  251. #endif
  252. static bool pirq_needs_eoi_flag(unsigned irq)
  253. {
  254. struct irq_info *info = info_for_irq(irq);
  255. BUG_ON(info->type != IRQT_PIRQ);
  256. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  257. }
  258. static inline xen_ulong_t active_evtchns(unsigned int cpu,
  259. struct shared_info *sh,
  260. unsigned int idx)
  261. {
  262. return sh->evtchn_pending[idx] &
  263. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  264. ~sh->evtchn_mask[idx];
  265. }
  266. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  267. {
  268. int irq = evtchn_to_irq[chn];
  269. BUG_ON(irq == -1);
  270. #ifdef CONFIG_SMP
  271. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  272. #endif
  273. clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
  274. set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
  275. info_for_irq(irq)->cpu = cpu;
  276. }
  277. static void init_evtchn_cpu_bindings(void)
  278. {
  279. int i;
  280. #ifdef CONFIG_SMP
  281. struct irq_info *info;
  282. /* By default all event channels notify CPU#0. */
  283. list_for_each_entry(info, &xen_irq_list_head, list) {
  284. struct irq_desc *desc = irq_to_desc(info->irq);
  285. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  286. }
  287. #endif
  288. for_each_possible_cpu(i)
  289. memset(per_cpu(cpu_evtchn_mask, i),
  290. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  291. }
  292. static inline void clear_evtchn(int port)
  293. {
  294. struct shared_info *s = HYPERVISOR_shared_info;
  295. sync_clear_bit(port, BM(&s->evtchn_pending[0]));
  296. }
  297. static inline void set_evtchn(int port)
  298. {
  299. struct shared_info *s = HYPERVISOR_shared_info;
  300. sync_set_bit(port, BM(&s->evtchn_pending[0]));
  301. }
  302. static inline int test_evtchn(int port)
  303. {
  304. struct shared_info *s = HYPERVISOR_shared_info;
  305. return sync_test_bit(port, BM(&s->evtchn_pending[0]));
  306. }
  307. /**
  308. * notify_remote_via_irq - send event to remote end of event channel via irq
  309. * @irq: irq of event channel to send event to
  310. *
  311. * Unlike notify_remote_via_evtchn(), this is safe to use across
  312. * save/restore. Notifications on a broken connection are silently
  313. * dropped.
  314. */
  315. void notify_remote_via_irq(int irq)
  316. {
  317. int evtchn = evtchn_from_irq(irq);
  318. if (VALID_EVTCHN(evtchn))
  319. notify_remote_via_evtchn(evtchn);
  320. }
  321. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  322. static void mask_evtchn(int port)
  323. {
  324. struct shared_info *s = HYPERVISOR_shared_info;
  325. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  326. }
  327. static void unmask_evtchn(int port)
  328. {
  329. struct shared_info *s = HYPERVISOR_shared_info;
  330. unsigned int cpu = get_cpu();
  331. int do_hypercall = 0, evtchn_pending = 0;
  332. BUG_ON(!irqs_disabled());
  333. if (unlikely((cpu != cpu_from_evtchn(port))))
  334. do_hypercall = 1;
  335. else {
  336. /*
  337. * Need to clear the mask before checking pending to
  338. * avoid a race with an event becoming pending.
  339. *
  340. * EVTCHNOP_unmask will only trigger an upcall if the
  341. * mask bit was set, so if a hypercall is needed
  342. * remask the event.
  343. */
  344. sync_clear_bit(port, BM(&s->evtchn_mask[0]));
  345. evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
  346. if (unlikely(evtchn_pending && xen_hvm_domain())) {
  347. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  348. do_hypercall = 1;
  349. }
  350. }
  351. /* Slow path (hypercall) if this is a non-local port or if this is
  352. * an hvm domain and an event is pending (hvm domains don't have
  353. * their own implementation of irq_enable). */
  354. if (do_hypercall) {
  355. struct evtchn_unmask unmask = { .port = port };
  356. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  357. } else {
  358. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  359. /*
  360. * The following is basically the equivalent of
  361. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  362. * the interrupt edge' if the channel is masked.
  363. */
  364. if (evtchn_pending &&
  365. !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
  366. BM(&vcpu_info->evtchn_pending_sel)))
  367. vcpu_info->evtchn_upcall_pending = 1;
  368. }
  369. put_cpu();
  370. }
  371. static void xen_irq_init(unsigned irq)
  372. {
  373. struct irq_info *info;
  374. #ifdef CONFIG_SMP
  375. struct irq_desc *desc = irq_to_desc(irq);
  376. /* By default all event channels notify CPU#0. */
  377. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  378. #endif
  379. info = kzalloc(sizeof(*info), GFP_KERNEL);
  380. if (info == NULL)
  381. panic("Unable to allocate metadata for IRQ%d\n", irq);
  382. info->type = IRQT_UNBOUND;
  383. info->refcnt = -1;
  384. irq_set_handler_data(irq, info);
  385. list_add_tail(&info->list, &xen_irq_list_head);
  386. }
  387. static int __must_check xen_allocate_irq_dynamic(void)
  388. {
  389. int first = 0;
  390. int irq;
  391. #ifdef CONFIG_X86_IO_APIC
  392. /*
  393. * For an HVM guest or domain 0 which see "real" (emulated or
  394. * actual respectively) GSIs we allocate dynamic IRQs
  395. * e.g. those corresponding to event channels or MSIs
  396. * etc. from the range above those "real" GSIs to avoid
  397. * collisions.
  398. */
  399. if (xen_initial_domain() || xen_hvm_domain())
  400. first = get_nr_irqs_gsi();
  401. #endif
  402. irq = irq_alloc_desc_from(first, -1);
  403. if (irq >= 0)
  404. xen_irq_init(irq);
  405. return irq;
  406. }
  407. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  408. {
  409. int irq;
  410. /*
  411. * A PV guest has no concept of a GSI (since it has no ACPI
  412. * nor access to/knowledge of the physical APICs). Therefore
  413. * all IRQs are dynamically allocated from the entire IRQ
  414. * space.
  415. */
  416. if (xen_pv_domain() && !xen_initial_domain())
  417. return xen_allocate_irq_dynamic();
  418. /* Legacy IRQ descriptors are already allocated by the arch. */
  419. if (gsi < NR_IRQS_LEGACY)
  420. irq = gsi;
  421. else
  422. irq = irq_alloc_desc_at(gsi, -1);
  423. xen_irq_init(irq);
  424. return irq;
  425. }
  426. static void xen_free_irq(unsigned irq)
  427. {
  428. struct irq_info *info = irq_get_handler_data(irq);
  429. list_del(&info->list);
  430. irq_set_handler_data(irq, NULL);
  431. WARN_ON(info->refcnt > 0);
  432. kfree(info);
  433. /* Legacy IRQ descriptors are managed by the arch. */
  434. if (irq < NR_IRQS_LEGACY)
  435. return;
  436. irq_free_desc(irq);
  437. }
  438. static void pirq_query_unmask(int irq)
  439. {
  440. struct physdev_irq_status_query irq_status;
  441. struct irq_info *info = info_for_irq(irq);
  442. BUG_ON(info->type != IRQT_PIRQ);
  443. irq_status.irq = pirq_from_irq(irq);
  444. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  445. irq_status.flags = 0;
  446. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  447. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  448. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  449. }
  450. static bool probing_irq(int irq)
  451. {
  452. struct irq_desc *desc = irq_to_desc(irq);
  453. return desc && desc->action == NULL;
  454. }
  455. static void eoi_pirq(struct irq_data *data)
  456. {
  457. int evtchn = evtchn_from_irq(data->irq);
  458. struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
  459. int rc = 0;
  460. irq_move_irq(data);
  461. if (VALID_EVTCHN(evtchn))
  462. clear_evtchn(evtchn);
  463. if (pirq_needs_eoi(data->irq)) {
  464. rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  465. WARN_ON(rc);
  466. }
  467. }
  468. static void mask_ack_pirq(struct irq_data *data)
  469. {
  470. disable_dynirq(data);
  471. eoi_pirq(data);
  472. }
  473. static unsigned int __startup_pirq(unsigned int irq)
  474. {
  475. struct evtchn_bind_pirq bind_pirq;
  476. struct irq_info *info = info_for_irq(irq);
  477. int evtchn = evtchn_from_irq(irq);
  478. int rc;
  479. BUG_ON(info->type != IRQT_PIRQ);
  480. if (VALID_EVTCHN(evtchn))
  481. goto out;
  482. bind_pirq.pirq = pirq_from_irq(irq);
  483. /* NB. We are happy to share unless we are probing. */
  484. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  485. BIND_PIRQ__WILL_SHARE : 0;
  486. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  487. if (rc != 0) {
  488. if (!probing_irq(irq))
  489. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  490. irq);
  491. return 0;
  492. }
  493. evtchn = bind_pirq.port;
  494. pirq_query_unmask(irq);
  495. evtchn_to_irq[evtchn] = irq;
  496. bind_evtchn_to_cpu(evtchn, 0);
  497. info->evtchn = evtchn;
  498. out:
  499. unmask_evtchn(evtchn);
  500. eoi_pirq(irq_get_irq_data(irq));
  501. return 0;
  502. }
  503. static unsigned int startup_pirq(struct irq_data *data)
  504. {
  505. return __startup_pirq(data->irq);
  506. }
  507. static void shutdown_pirq(struct irq_data *data)
  508. {
  509. struct evtchn_close close;
  510. unsigned int irq = data->irq;
  511. struct irq_info *info = info_for_irq(irq);
  512. int evtchn = evtchn_from_irq(irq);
  513. BUG_ON(info->type != IRQT_PIRQ);
  514. if (!VALID_EVTCHN(evtchn))
  515. return;
  516. mask_evtchn(evtchn);
  517. close.port = evtchn;
  518. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  519. BUG();
  520. bind_evtchn_to_cpu(evtchn, 0);
  521. evtchn_to_irq[evtchn] = -1;
  522. info->evtchn = 0;
  523. }
  524. static void enable_pirq(struct irq_data *data)
  525. {
  526. startup_pirq(data);
  527. }
  528. static void disable_pirq(struct irq_data *data)
  529. {
  530. disable_dynirq(data);
  531. }
  532. int xen_irq_from_gsi(unsigned gsi)
  533. {
  534. struct irq_info *info;
  535. list_for_each_entry(info, &xen_irq_list_head, list) {
  536. if (info->type != IRQT_PIRQ)
  537. continue;
  538. if (info->u.pirq.gsi == gsi)
  539. return info->irq;
  540. }
  541. return -1;
  542. }
  543. EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
  544. /*
  545. * Do not make any assumptions regarding the relationship between the
  546. * IRQ number returned here and the Xen pirq argument.
  547. *
  548. * Note: We don't assign an event channel until the irq actually started
  549. * up. Return an existing irq if we've already got one for the gsi.
  550. *
  551. * Shareable implies level triggered, not shareable implies edge
  552. * triggered here.
  553. */
  554. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  555. unsigned pirq, int shareable, char *name)
  556. {
  557. int irq = -1;
  558. struct physdev_irq irq_op;
  559. mutex_lock(&irq_mapping_update_lock);
  560. irq = xen_irq_from_gsi(gsi);
  561. if (irq != -1) {
  562. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  563. irq, gsi);
  564. goto out;
  565. }
  566. irq = xen_allocate_irq_gsi(gsi);
  567. if (irq < 0)
  568. goto out;
  569. irq_op.irq = irq;
  570. irq_op.vector = 0;
  571. /* Only the privileged domain can do this. For non-priv, the pcifront
  572. * driver provides a PCI bus that does the call to do exactly
  573. * this in the priv domain. */
  574. if (xen_initial_domain() &&
  575. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  576. xen_free_irq(irq);
  577. irq = -ENOSPC;
  578. goto out;
  579. }
  580. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
  581. shareable ? PIRQ_SHAREABLE : 0);
  582. pirq_query_unmask(irq);
  583. /* We try to use the handler with the appropriate semantic for the
  584. * type of interrupt: if the interrupt is an edge triggered
  585. * interrupt we use handle_edge_irq.
  586. *
  587. * On the other hand if the interrupt is level triggered we use
  588. * handle_fasteoi_irq like the native code does for this kind of
  589. * interrupts.
  590. *
  591. * Depending on the Xen version, pirq_needs_eoi might return true
  592. * not only for level triggered interrupts but for edge triggered
  593. * interrupts too. In any case Xen always honors the eoi mechanism,
  594. * not injecting any more pirqs of the same kind if the first one
  595. * hasn't received an eoi yet. Therefore using the fasteoi handler
  596. * is the right choice either way.
  597. */
  598. if (shareable)
  599. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  600. handle_fasteoi_irq, name);
  601. else
  602. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  603. handle_edge_irq, name);
  604. out:
  605. mutex_unlock(&irq_mapping_update_lock);
  606. return irq;
  607. }
  608. #ifdef CONFIG_PCI_MSI
  609. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  610. {
  611. int rc;
  612. struct physdev_get_free_pirq op_get_free_pirq;
  613. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  614. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  615. WARN_ONCE(rc == -ENOSYS,
  616. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  617. return rc ? -1 : op_get_free_pirq.pirq;
  618. }
  619. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  620. int pirq, int vector, const char *name,
  621. domid_t domid)
  622. {
  623. int irq, ret;
  624. mutex_lock(&irq_mapping_update_lock);
  625. irq = xen_allocate_irq_dynamic();
  626. if (irq < 0)
  627. goto out;
  628. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
  629. name);
  630. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
  631. ret = irq_set_msi_desc(irq, msidesc);
  632. if (ret < 0)
  633. goto error_irq;
  634. out:
  635. mutex_unlock(&irq_mapping_update_lock);
  636. return irq;
  637. error_irq:
  638. mutex_unlock(&irq_mapping_update_lock);
  639. xen_free_irq(irq);
  640. return ret;
  641. }
  642. #endif
  643. int xen_destroy_irq(int irq)
  644. {
  645. struct irq_desc *desc;
  646. struct physdev_unmap_pirq unmap_irq;
  647. struct irq_info *info = info_for_irq(irq);
  648. int rc = -ENOENT;
  649. mutex_lock(&irq_mapping_update_lock);
  650. desc = irq_to_desc(irq);
  651. if (!desc)
  652. goto out;
  653. if (xen_initial_domain()) {
  654. unmap_irq.pirq = info->u.pirq.pirq;
  655. unmap_irq.domid = info->u.pirq.domid;
  656. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  657. /* If another domain quits without making the pci_disable_msix
  658. * call, the Xen hypervisor takes care of freeing the PIRQs
  659. * (free_domain_pirqs).
  660. */
  661. if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
  662. printk(KERN_INFO "domain %d does not have %d anymore\n",
  663. info->u.pirq.domid, info->u.pirq.pirq);
  664. else if (rc) {
  665. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  666. goto out;
  667. }
  668. }
  669. xen_free_irq(irq);
  670. out:
  671. mutex_unlock(&irq_mapping_update_lock);
  672. return rc;
  673. }
  674. int xen_irq_from_pirq(unsigned pirq)
  675. {
  676. int irq;
  677. struct irq_info *info;
  678. mutex_lock(&irq_mapping_update_lock);
  679. list_for_each_entry(info, &xen_irq_list_head, list) {
  680. if (info->type != IRQT_PIRQ)
  681. continue;
  682. irq = info->irq;
  683. if (info->u.pirq.pirq == pirq)
  684. goto out;
  685. }
  686. irq = -1;
  687. out:
  688. mutex_unlock(&irq_mapping_update_lock);
  689. return irq;
  690. }
  691. int xen_pirq_from_irq(unsigned irq)
  692. {
  693. return pirq_from_irq(irq);
  694. }
  695. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  696. int bind_evtchn_to_irq(unsigned int evtchn)
  697. {
  698. int irq;
  699. mutex_lock(&irq_mapping_update_lock);
  700. irq = evtchn_to_irq[evtchn];
  701. if (irq == -1) {
  702. irq = xen_allocate_irq_dynamic();
  703. if (irq < 0)
  704. goto out;
  705. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  706. handle_edge_irq, "event");
  707. xen_irq_info_evtchn_init(irq, evtchn);
  708. } else {
  709. struct irq_info *info = info_for_irq(irq);
  710. WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
  711. }
  712. irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
  713. out:
  714. mutex_unlock(&irq_mapping_update_lock);
  715. return irq;
  716. }
  717. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  718. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  719. {
  720. struct evtchn_bind_ipi bind_ipi;
  721. int evtchn, irq;
  722. mutex_lock(&irq_mapping_update_lock);
  723. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  724. if (irq == -1) {
  725. irq = xen_allocate_irq_dynamic();
  726. if (irq < 0)
  727. goto out;
  728. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  729. handle_percpu_irq, "ipi");
  730. bind_ipi.vcpu = cpu;
  731. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  732. &bind_ipi) != 0)
  733. BUG();
  734. evtchn = bind_ipi.port;
  735. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  736. bind_evtchn_to_cpu(evtchn, cpu);
  737. } else {
  738. struct irq_info *info = info_for_irq(irq);
  739. WARN_ON(info == NULL || info->type != IRQT_IPI);
  740. }
  741. out:
  742. mutex_unlock(&irq_mapping_update_lock);
  743. return irq;
  744. }
  745. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  746. unsigned int remote_port)
  747. {
  748. struct evtchn_bind_interdomain bind_interdomain;
  749. int err;
  750. bind_interdomain.remote_dom = remote_domain;
  751. bind_interdomain.remote_port = remote_port;
  752. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  753. &bind_interdomain);
  754. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  755. }
  756. static int find_virq(unsigned int virq, unsigned int cpu)
  757. {
  758. struct evtchn_status status;
  759. int port, rc = -ENOENT;
  760. memset(&status, 0, sizeof(status));
  761. for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
  762. status.dom = DOMID_SELF;
  763. status.port = port;
  764. rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
  765. if (rc < 0)
  766. continue;
  767. if (status.status != EVTCHNSTAT_virq)
  768. continue;
  769. if (status.u.virq == virq && status.vcpu == cpu) {
  770. rc = port;
  771. break;
  772. }
  773. }
  774. return rc;
  775. }
  776. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  777. {
  778. struct evtchn_bind_virq bind_virq;
  779. int evtchn, irq, ret;
  780. mutex_lock(&irq_mapping_update_lock);
  781. irq = per_cpu(virq_to_irq, cpu)[virq];
  782. if (irq == -1) {
  783. irq = xen_allocate_irq_dynamic();
  784. if (irq < 0)
  785. goto out;
  786. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  787. handle_percpu_irq, "virq");
  788. bind_virq.virq = virq;
  789. bind_virq.vcpu = cpu;
  790. ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  791. &bind_virq);
  792. if (ret == 0)
  793. evtchn = bind_virq.port;
  794. else {
  795. if (ret == -EEXIST)
  796. ret = find_virq(virq, cpu);
  797. BUG_ON(ret < 0);
  798. evtchn = ret;
  799. }
  800. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  801. bind_evtchn_to_cpu(evtchn, cpu);
  802. } else {
  803. struct irq_info *info = info_for_irq(irq);
  804. WARN_ON(info == NULL || info->type != IRQT_VIRQ);
  805. }
  806. out:
  807. mutex_unlock(&irq_mapping_update_lock);
  808. return irq;
  809. }
  810. static void unbind_from_irq(unsigned int irq)
  811. {
  812. struct evtchn_close close;
  813. int evtchn = evtchn_from_irq(irq);
  814. struct irq_info *info = irq_get_handler_data(irq);
  815. mutex_lock(&irq_mapping_update_lock);
  816. if (info->refcnt > 0) {
  817. info->refcnt--;
  818. if (info->refcnt != 0)
  819. goto done;
  820. }
  821. if (VALID_EVTCHN(evtchn)) {
  822. close.port = evtchn;
  823. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  824. BUG();
  825. switch (type_from_irq(irq)) {
  826. case IRQT_VIRQ:
  827. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  828. [virq_from_irq(irq)] = -1;
  829. break;
  830. case IRQT_IPI:
  831. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  832. [ipi_from_irq(irq)] = -1;
  833. break;
  834. default:
  835. break;
  836. }
  837. /* Closed ports are implicitly re-bound to VCPU0. */
  838. bind_evtchn_to_cpu(evtchn, 0);
  839. evtchn_to_irq[evtchn] = -1;
  840. }
  841. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  842. xen_free_irq(irq);
  843. done:
  844. mutex_unlock(&irq_mapping_update_lock);
  845. }
  846. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  847. irq_handler_t handler,
  848. unsigned long irqflags,
  849. const char *devname, void *dev_id)
  850. {
  851. int irq, retval;
  852. irq = bind_evtchn_to_irq(evtchn);
  853. if (irq < 0)
  854. return irq;
  855. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  856. if (retval != 0) {
  857. unbind_from_irq(irq);
  858. return retval;
  859. }
  860. return irq;
  861. }
  862. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  863. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  864. unsigned int remote_port,
  865. irq_handler_t handler,
  866. unsigned long irqflags,
  867. const char *devname,
  868. void *dev_id)
  869. {
  870. int irq, retval;
  871. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  872. if (irq < 0)
  873. return irq;
  874. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  875. if (retval != 0) {
  876. unbind_from_irq(irq);
  877. return retval;
  878. }
  879. return irq;
  880. }
  881. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  882. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  883. irq_handler_t handler,
  884. unsigned long irqflags, const char *devname, void *dev_id)
  885. {
  886. int irq, retval;
  887. irq = bind_virq_to_irq(virq, cpu);
  888. if (irq < 0)
  889. return irq;
  890. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  891. if (retval != 0) {
  892. unbind_from_irq(irq);
  893. return retval;
  894. }
  895. return irq;
  896. }
  897. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  898. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  899. unsigned int cpu,
  900. irq_handler_t handler,
  901. unsigned long irqflags,
  902. const char *devname,
  903. void *dev_id)
  904. {
  905. int irq, retval;
  906. irq = bind_ipi_to_irq(ipi, cpu);
  907. if (irq < 0)
  908. return irq;
  909. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
  910. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  911. if (retval != 0) {
  912. unbind_from_irq(irq);
  913. return retval;
  914. }
  915. return irq;
  916. }
  917. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  918. {
  919. free_irq(irq, dev_id);
  920. unbind_from_irq(irq);
  921. }
  922. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  923. int evtchn_make_refcounted(unsigned int evtchn)
  924. {
  925. int irq = evtchn_to_irq[evtchn];
  926. struct irq_info *info;
  927. if (irq == -1)
  928. return -ENOENT;
  929. info = irq_get_handler_data(irq);
  930. if (!info)
  931. return -ENOENT;
  932. WARN_ON(info->refcnt != -1);
  933. info->refcnt = 1;
  934. return 0;
  935. }
  936. EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
  937. int evtchn_get(unsigned int evtchn)
  938. {
  939. int irq;
  940. struct irq_info *info;
  941. int err = -ENOENT;
  942. if (evtchn >= NR_EVENT_CHANNELS)
  943. return -EINVAL;
  944. mutex_lock(&irq_mapping_update_lock);
  945. irq = evtchn_to_irq[evtchn];
  946. if (irq == -1)
  947. goto done;
  948. info = irq_get_handler_data(irq);
  949. if (!info)
  950. goto done;
  951. err = -EINVAL;
  952. if (info->refcnt <= 0)
  953. goto done;
  954. info->refcnt++;
  955. err = 0;
  956. done:
  957. mutex_unlock(&irq_mapping_update_lock);
  958. return err;
  959. }
  960. EXPORT_SYMBOL_GPL(evtchn_get);
  961. void evtchn_put(unsigned int evtchn)
  962. {
  963. int irq = evtchn_to_irq[evtchn];
  964. if (WARN_ON(irq == -1))
  965. return;
  966. unbind_from_irq(irq);
  967. }
  968. EXPORT_SYMBOL_GPL(evtchn_put);
  969. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  970. {
  971. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  972. BUG_ON(irq < 0);
  973. notify_remote_via_irq(irq);
  974. }
  975. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  976. {
  977. struct shared_info *sh = HYPERVISOR_shared_info;
  978. int cpu = smp_processor_id();
  979. xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  980. int i;
  981. unsigned long flags;
  982. static DEFINE_SPINLOCK(debug_lock);
  983. struct vcpu_info *v;
  984. spin_lock_irqsave(&debug_lock, flags);
  985. printk("\nvcpu %d\n ", cpu);
  986. for_each_online_cpu(i) {
  987. int pending;
  988. v = per_cpu(xen_vcpu, i);
  989. pending = (get_irq_regs() && i == cpu)
  990. ? xen_irqs_disabled(get_irq_regs())
  991. : v->evtchn_upcall_mask;
  992. printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
  993. pending, v->evtchn_upcall_pending,
  994. (int)(sizeof(v->evtchn_pending_sel)*2),
  995. v->evtchn_pending_sel);
  996. }
  997. v = per_cpu(xen_vcpu, cpu);
  998. printk("\npending:\n ");
  999. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  1000. printk("%0*"PRI_xen_ulong"%s",
  1001. (int)sizeof(sh->evtchn_pending[0])*2,
  1002. sh->evtchn_pending[i],
  1003. i % 8 == 0 ? "\n " : " ");
  1004. printk("\nglobal mask:\n ");
  1005. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  1006. printk("%0*"PRI_xen_ulong"%s",
  1007. (int)(sizeof(sh->evtchn_mask[0])*2),
  1008. sh->evtchn_mask[i],
  1009. i % 8 == 0 ? "\n " : " ");
  1010. printk("\nglobally unmasked:\n ");
  1011. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  1012. printk("%0*"PRI_xen_ulong"%s",
  1013. (int)(sizeof(sh->evtchn_mask[0])*2),
  1014. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  1015. i % 8 == 0 ? "\n " : " ");
  1016. printk("\nlocal cpu%d mask:\n ", cpu);
  1017. for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
  1018. printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
  1019. cpu_evtchn[i],
  1020. i % 8 == 0 ? "\n " : " ");
  1021. printk("\nlocally unmasked:\n ");
  1022. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  1023. xen_ulong_t pending = sh->evtchn_pending[i]
  1024. & ~sh->evtchn_mask[i]
  1025. & cpu_evtchn[i];
  1026. printk("%0*"PRI_xen_ulong"%s",
  1027. (int)(sizeof(sh->evtchn_mask[0])*2),
  1028. pending, i % 8 == 0 ? "\n " : " ");
  1029. }
  1030. printk("\npending list:\n");
  1031. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  1032. if (sync_test_bit(i, BM(sh->evtchn_pending))) {
  1033. int word_idx = i / BITS_PER_EVTCHN_WORD;
  1034. printk(" %d: event %d -> irq %d%s%s%s\n",
  1035. cpu_from_evtchn(i), i,
  1036. evtchn_to_irq[i],
  1037. sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
  1038. ? "" : " l2-clear",
  1039. !sync_test_bit(i, BM(sh->evtchn_mask))
  1040. ? "" : " globally-masked",
  1041. sync_test_bit(i, BM(cpu_evtchn))
  1042. ? "" : " locally-masked");
  1043. }
  1044. }
  1045. spin_unlock_irqrestore(&debug_lock, flags);
  1046. return IRQ_HANDLED;
  1047. }
  1048. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  1049. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  1050. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  1051. /*
  1052. * Mask out the i least significant bits of w
  1053. */
  1054. #define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
  1055. /*
  1056. * Search the CPUs pending events bitmasks. For each one found, map
  1057. * the event number to an irq, and feed it into do_IRQ() for
  1058. * handling.
  1059. *
  1060. * Xen uses a two-level bitmap to speed searching. The first level is
  1061. * a bitset of words which contain pending event bits. The second
  1062. * level is a bitset of pending events themselves.
  1063. */
  1064. static void __xen_evtchn_do_upcall(void)
  1065. {
  1066. int start_word_idx, start_bit_idx;
  1067. int word_idx, bit_idx;
  1068. int i;
  1069. int cpu = get_cpu();
  1070. struct shared_info *s = HYPERVISOR_shared_info;
  1071. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  1072. unsigned count;
  1073. do {
  1074. xen_ulong_t pending_words;
  1075. vcpu_info->evtchn_upcall_pending = 0;
  1076. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  1077. goto out;
  1078. /*
  1079. * Master flag must be cleared /before/ clearing
  1080. * selector flag. xchg_xen_ulong must contain an
  1081. * appropriate barrier.
  1082. */
  1083. pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
  1084. start_word_idx = __this_cpu_read(current_word_idx);
  1085. start_bit_idx = __this_cpu_read(current_bit_idx);
  1086. word_idx = start_word_idx;
  1087. for (i = 0; pending_words != 0; i++) {
  1088. xen_ulong_t pending_bits;
  1089. xen_ulong_t words;
  1090. words = MASK_LSBS(pending_words, word_idx);
  1091. /*
  1092. * If we masked out all events, wrap to beginning.
  1093. */
  1094. if (words == 0) {
  1095. word_idx = 0;
  1096. bit_idx = 0;
  1097. continue;
  1098. }
  1099. word_idx = EVTCHN_FIRST_BIT(words);
  1100. pending_bits = active_evtchns(cpu, s, word_idx);
  1101. bit_idx = 0; /* usually scan entire word from start */
  1102. if (word_idx == start_word_idx) {
  1103. /* We scan the starting word in two parts */
  1104. if (i == 0)
  1105. /* 1st time: start in the middle */
  1106. bit_idx = start_bit_idx;
  1107. else
  1108. /* 2nd time: mask bits done already */
  1109. bit_idx &= (1UL << start_bit_idx) - 1;
  1110. }
  1111. do {
  1112. xen_ulong_t bits;
  1113. int port, irq;
  1114. struct irq_desc *desc;
  1115. bits = MASK_LSBS(pending_bits, bit_idx);
  1116. /* If we masked out all events, move on. */
  1117. if (bits == 0)
  1118. break;
  1119. bit_idx = EVTCHN_FIRST_BIT(bits);
  1120. /* Process port. */
  1121. port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
  1122. irq = evtchn_to_irq[port];
  1123. if (irq != -1) {
  1124. desc = irq_to_desc(irq);
  1125. if (desc)
  1126. generic_handle_irq_desc(irq, desc);
  1127. }
  1128. bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
  1129. /* Next caller starts at last processed + 1 */
  1130. __this_cpu_write(current_word_idx,
  1131. bit_idx ? word_idx :
  1132. (word_idx+1) % BITS_PER_EVTCHN_WORD);
  1133. __this_cpu_write(current_bit_idx, bit_idx);
  1134. } while (bit_idx != 0);
  1135. /* Scan start_l1i twice; all others once. */
  1136. if ((word_idx != start_word_idx) || (i != 0))
  1137. pending_words &= ~(1UL << word_idx);
  1138. word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
  1139. }
  1140. BUG_ON(!irqs_disabled());
  1141. count = __this_cpu_read(xed_nesting_count);
  1142. __this_cpu_write(xed_nesting_count, 0);
  1143. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  1144. out:
  1145. put_cpu();
  1146. }
  1147. void xen_evtchn_do_upcall(struct pt_regs *regs)
  1148. {
  1149. struct pt_regs *old_regs = set_irq_regs(regs);
  1150. irq_enter();
  1151. #ifdef CONFIG_X86
  1152. exit_idle();
  1153. #endif
  1154. __xen_evtchn_do_upcall();
  1155. irq_exit();
  1156. set_irq_regs(old_regs);
  1157. }
  1158. void xen_hvm_evtchn_do_upcall(void)
  1159. {
  1160. __xen_evtchn_do_upcall();
  1161. }
  1162. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  1163. /* Rebind a new event channel to an existing irq. */
  1164. void rebind_evtchn_irq(int evtchn, int irq)
  1165. {
  1166. struct irq_info *info = info_for_irq(irq);
  1167. /* Make sure the irq is masked, since the new event channel
  1168. will also be masked. */
  1169. disable_irq(irq);
  1170. mutex_lock(&irq_mapping_update_lock);
  1171. /* After resume the irq<->evtchn mappings are all cleared out */
  1172. BUG_ON(evtchn_to_irq[evtchn] != -1);
  1173. /* Expect irq to have been bound before,
  1174. so there should be a proper type */
  1175. BUG_ON(info->type == IRQT_UNBOUND);
  1176. xen_irq_info_evtchn_init(irq, evtchn);
  1177. mutex_unlock(&irq_mapping_update_lock);
  1178. /* new event channels are always bound to cpu 0 */
  1179. irq_set_affinity(irq, cpumask_of(0));
  1180. /* Unmask the event channel. */
  1181. enable_irq(irq);
  1182. }
  1183. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1184. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1185. {
  1186. struct evtchn_bind_vcpu bind_vcpu;
  1187. int evtchn = evtchn_from_irq(irq);
  1188. if (!VALID_EVTCHN(evtchn))
  1189. return -1;
  1190. /*
  1191. * Events delivered via platform PCI interrupts are always
  1192. * routed to vcpu 0 and hence cannot be rebound.
  1193. */
  1194. if (xen_hvm_domain() && !xen_have_vector_callback)
  1195. return -1;
  1196. /* Send future instances of this interrupt to other vcpu. */
  1197. bind_vcpu.port = evtchn;
  1198. bind_vcpu.vcpu = tcpu;
  1199. /*
  1200. * If this fails, it usually just indicates that we're dealing with a
  1201. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1202. * it, but don't do the xenlinux-level rebind in that case.
  1203. */
  1204. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1205. bind_evtchn_to_cpu(evtchn, tcpu);
  1206. return 0;
  1207. }
  1208. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1209. bool force)
  1210. {
  1211. unsigned tcpu = cpumask_first(dest);
  1212. return rebind_irq_to_cpu(data->irq, tcpu);
  1213. }
  1214. int resend_irq_on_evtchn(unsigned int irq)
  1215. {
  1216. int masked, evtchn = evtchn_from_irq(irq);
  1217. struct shared_info *s = HYPERVISOR_shared_info;
  1218. if (!VALID_EVTCHN(evtchn))
  1219. return 1;
  1220. masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
  1221. sync_set_bit(evtchn, BM(s->evtchn_pending));
  1222. if (!masked)
  1223. unmask_evtchn(evtchn);
  1224. return 1;
  1225. }
  1226. static void enable_dynirq(struct irq_data *data)
  1227. {
  1228. int evtchn = evtchn_from_irq(data->irq);
  1229. if (VALID_EVTCHN(evtchn))
  1230. unmask_evtchn(evtchn);
  1231. }
  1232. static void disable_dynirq(struct irq_data *data)
  1233. {
  1234. int evtchn = evtchn_from_irq(data->irq);
  1235. if (VALID_EVTCHN(evtchn))
  1236. mask_evtchn(evtchn);
  1237. }
  1238. static void ack_dynirq(struct irq_data *data)
  1239. {
  1240. int evtchn = evtchn_from_irq(data->irq);
  1241. irq_move_irq(data);
  1242. if (VALID_EVTCHN(evtchn))
  1243. clear_evtchn(evtchn);
  1244. }
  1245. static void mask_ack_dynirq(struct irq_data *data)
  1246. {
  1247. disable_dynirq(data);
  1248. ack_dynirq(data);
  1249. }
  1250. static int retrigger_dynirq(struct irq_data *data)
  1251. {
  1252. int evtchn = evtchn_from_irq(data->irq);
  1253. struct shared_info *sh = HYPERVISOR_shared_info;
  1254. int ret = 0;
  1255. if (VALID_EVTCHN(evtchn)) {
  1256. int masked;
  1257. masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
  1258. sync_set_bit(evtchn, BM(sh->evtchn_pending));
  1259. if (!masked)
  1260. unmask_evtchn(evtchn);
  1261. ret = 1;
  1262. }
  1263. return ret;
  1264. }
  1265. static void restore_pirqs(void)
  1266. {
  1267. int pirq, rc, irq, gsi;
  1268. struct physdev_map_pirq map_irq;
  1269. struct irq_info *info;
  1270. list_for_each_entry(info, &xen_irq_list_head, list) {
  1271. if (info->type != IRQT_PIRQ)
  1272. continue;
  1273. pirq = info->u.pirq.pirq;
  1274. gsi = info->u.pirq.gsi;
  1275. irq = info->irq;
  1276. /* save/restore of PT devices doesn't work, so at this point the
  1277. * only devices present are GSI based emulated devices */
  1278. if (!gsi)
  1279. continue;
  1280. map_irq.domid = DOMID_SELF;
  1281. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1282. map_irq.index = gsi;
  1283. map_irq.pirq = pirq;
  1284. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1285. if (rc) {
  1286. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1287. gsi, irq, pirq, rc);
  1288. xen_free_irq(irq);
  1289. continue;
  1290. }
  1291. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1292. __startup_pirq(irq);
  1293. }
  1294. }
  1295. static void restore_cpu_virqs(unsigned int cpu)
  1296. {
  1297. struct evtchn_bind_virq bind_virq;
  1298. int virq, irq, evtchn;
  1299. for (virq = 0; virq < NR_VIRQS; virq++) {
  1300. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1301. continue;
  1302. BUG_ON(virq_from_irq(irq) != virq);
  1303. /* Get a new binding from Xen. */
  1304. bind_virq.virq = virq;
  1305. bind_virq.vcpu = cpu;
  1306. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1307. &bind_virq) != 0)
  1308. BUG();
  1309. evtchn = bind_virq.port;
  1310. /* Record the new mapping. */
  1311. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1312. bind_evtchn_to_cpu(evtchn, cpu);
  1313. }
  1314. }
  1315. static void restore_cpu_ipis(unsigned int cpu)
  1316. {
  1317. struct evtchn_bind_ipi bind_ipi;
  1318. int ipi, irq, evtchn;
  1319. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1320. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1321. continue;
  1322. BUG_ON(ipi_from_irq(irq) != ipi);
  1323. /* Get a new binding from Xen. */
  1324. bind_ipi.vcpu = cpu;
  1325. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1326. &bind_ipi) != 0)
  1327. BUG();
  1328. evtchn = bind_ipi.port;
  1329. /* Record the new mapping. */
  1330. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1331. bind_evtchn_to_cpu(evtchn, cpu);
  1332. }
  1333. }
  1334. /* Clear an irq's pending state, in preparation for polling on it */
  1335. void xen_clear_irq_pending(int irq)
  1336. {
  1337. int evtchn = evtchn_from_irq(irq);
  1338. if (VALID_EVTCHN(evtchn))
  1339. clear_evtchn(evtchn);
  1340. }
  1341. EXPORT_SYMBOL(xen_clear_irq_pending);
  1342. void xen_set_irq_pending(int irq)
  1343. {
  1344. int evtchn = evtchn_from_irq(irq);
  1345. if (VALID_EVTCHN(evtchn))
  1346. set_evtchn(evtchn);
  1347. }
  1348. bool xen_test_irq_pending(int irq)
  1349. {
  1350. int evtchn = evtchn_from_irq(irq);
  1351. bool ret = false;
  1352. if (VALID_EVTCHN(evtchn))
  1353. ret = test_evtchn(evtchn);
  1354. return ret;
  1355. }
  1356. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1357. * the irq will be disabled so it won't deliver an interrupt. */
  1358. void xen_poll_irq_timeout(int irq, u64 timeout)
  1359. {
  1360. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1361. if (VALID_EVTCHN(evtchn)) {
  1362. struct sched_poll poll;
  1363. poll.nr_ports = 1;
  1364. poll.timeout = timeout;
  1365. set_xen_guest_handle(poll.ports, &evtchn);
  1366. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1367. BUG();
  1368. }
  1369. }
  1370. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1371. /* Poll waiting for an irq to become pending. In the usual case, the
  1372. * irq will be disabled so it won't deliver an interrupt. */
  1373. void xen_poll_irq(int irq)
  1374. {
  1375. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1376. }
  1377. /* Check whether the IRQ line is shared with other guests. */
  1378. int xen_test_irq_shared(int irq)
  1379. {
  1380. struct irq_info *info = info_for_irq(irq);
  1381. struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
  1382. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1383. return 0;
  1384. return !(irq_status.flags & XENIRQSTAT_shared);
  1385. }
  1386. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1387. void xen_irq_resume(void)
  1388. {
  1389. unsigned int cpu, evtchn;
  1390. struct irq_info *info;
  1391. init_evtchn_cpu_bindings();
  1392. /* New event-channel space is not 'live' yet. */
  1393. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1394. mask_evtchn(evtchn);
  1395. /* No IRQ <-> event-channel mappings. */
  1396. list_for_each_entry(info, &xen_irq_list_head, list)
  1397. info->evtchn = 0; /* zap event-channel binding */
  1398. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1399. evtchn_to_irq[evtchn] = -1;
  1400. for_each_possible_cpu(cpu) {
  1401. restore_cpu_virqs(cpu);
  1402. restore_cpu_ipis(cpu);
  1403. }
  1404. restore_pirqs();
  1405. }
  1406. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1407. .name = "xen-dyn",
  1408. .irq_disable = disable_dynirq,
  1409. .irq_mask = disable_dynirq,
  1410. .irq_unmask = enable_dynirq,
  1411. .irq_ack = ack_dynirq,
  1412. .irq_mask_ack = mask_ack_dynirq,
  1413. .irq_set_affinity = set_affinity_irq,
  1414. .irq_retrigger = retrigger_dynirq,
  1415. };
  1416. static struct irq_chip xen_pirq_chip __read_mostly = {
  1417. .name = "xen-pirq",
  1418. .irq_startup = startup_pirq,
  1419. .irq_shutdown = shutdown_pirq,
  1420. .irq_enable = enable_pirq,
  1421. .irq_disable = disable_pirq,
  1422. .irq_mask = disable_dynirq,
  1423. .irq_unmask = enable_dynirq,
  1424. .irq_ack = eoi_pirq,
  1425. .irq_eoi = eoi_pirq,
  1426. .irq_mask_ack = mask_ack_pirq,
  1427. .irq_set_affinity = set_affinity_irq,
  1428. .irq_retrigger = retrigger_dynirq,
  1429. };
  1430. static struct irq_chip xen_percpu_chip __read_mostly = {
  1431. .name = "xen-percpu",
  1432. .irq_disable = disable_dynirq,
  1433. .irq_mask = disable_dynirq,
  1434. .irq_unmask = enable_dynirq,
  1435. .irq_ack = ack_dynirq,
  1436. };
  1437. int xen_set_callback_via(uint64_t via)
  1438. {
  1439. struct xen_hvm_param a;
  1440. a.domid = DOMID_SELF;
  1441. a.index = HVM_PARAM_CALLBACK_IRQ;
  1442. a.value = via;
  1443. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1444. }
  1445. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1446. #ifdef CONFIG_XEN_PVHVM
  1447. /* Vector callbacks are better than PCI interrupts to receive event
  1448. * channel notifications because we can receive vector callbacks on any
  1449. * vcpu and we don't need PCI support or APIC interactions. */
  1450. void xen_callback_vector(void)
  1451. {
  1452. int rc;
  1453. uint64_t callback_via;
  1454. if (xen_have_vector_callback) {
  1455. callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
  1456. rc = xen_set_callback_via(callback_via);
  1457. if (rc) {
  1458. printk(KERN_ERR "Request for Xen HVM callback vector"
  1459. " failed.\n");
  1460. xen_have_vector_callback = 0;
  1461. return;
  1462. }
  1463. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1464. "enabled\n");
  1465. /* in the restore case the vector has already been allocated */
  1466. if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
  1467. alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
  1468. xen_hvm_callback_vector);
  1469. }
  1470. }
  1471. #else
  1472. void xen_callback_vector(void) {}
  1473. #endif
  1474. void __init xen_init_IRQ(void)
  1475. {
  1476. int i;
  1477. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1478. GFP_KERNEL);
  1479. BUG_ON(!evtchn_to_irq);
  1480. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1481. evtchn_to_irq[i] = -1;
  1482. init_evtchn_cpu_bindings();
  1483. /* No event channels are 'live' right now. */
  1484. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1485. mask_evtchn(i);
  1486. pirq_needs_eoi = pirq_needs_eoi_flag;
  1487. #ifdef CONFIG_X86
  1488. if (xen_hvm_domain()) {
  1489. xen_callback_vector();
  1490. native_init_IRQ();
  1491. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1492. * __acpi_register_gsi can point at the right function */
  1493. pci_xen_hvm_init();
  1494. } else {
  1495. int rc;
  1496. struct physdev_pirq_eoi_gmfn eoi_gmfn;
  1497. irq_ctx_init(smp_processor_id());
  1498. if (xen_initial_domain())
  1499. pci_xen_initial_domain();
  1500. pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
  1501. eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
  1502. rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
  1503. if (rc != 0) {
  1504. free_page((unsigned long) pirq_eoi_map);
  1505. pirq_eoi_map = NULL;
  1506. } else
  1507. pirq_needs_eoi = pirq_check_eoi_map;
  1508. }
  1509. #endif
  1510. }