davinci_wdt.c 6.4 KB

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  1. /*
  2. * drivers/char/watchdog/davinci_wdt.c
  3. *
  4. * Watchdog driver for DaVinci DM644x/DM646x processors
  5. *
  6. * Copyright (C) 2006 Texas Instruments.
  7. *
  8. * 2007 (c) MontaVista Software, Inc. This file is licensed under
  9. * the terms of the GNU General Public License version 2. This program
  10. * is licensed "as is" without any warranty of any kind, whether express
  11. * or implied.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/fs.h>
  18. #include <linux/miscdevice.h>
  19. #include <linux/watchdog.h>
  20. #include <linux/init.h>
  21. #include <linux/bitops.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/uaccess.h>
  25. #include <linux/io.h>
  26. #include <linux/device.h>
  27. #include <linux/clk.h>
  28. #include <linux/slab.h>
  29. #define MODULE_NAME "DAVINCI-WDT: "
  30. #define DEFAULT_HEARTBEAT 60
  31. #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
  32. /* Timer register set definition */
  33. #define PID12 (0x0)
  34. #define EMUMGT (0x4)
  35. #define TIM12 (0x10)
  36. #define TIM34 (0x14)
  37. #define PRD12 (0x18)
  38. #define PRD34 (0x1C)
  39. #define TCR (0x20)
  40. #define TGCR (0x24)
  41. #define WDTCR (0x28)
  42. /* TCR bit definitions */
  43. #define ENAMODE12_DISABLED (0 << 6)
  44. #define ENAMODE12_ONESHOT (1 << 6)
  45. #define ENAMODE12_PERIODIC (2 << 6)
  46. /* TGCR bit definitions */
  47. #define TIM12RS_UNRESET (1 << 0)
  48. #define TIM34RS_UNRESET (1 << 1)
  49. #define TIMMODE_64BIT_WDOG (2 << 2)
  50. /* WDTCR bit definitions */
  51. #define WDEN (1 << 14)
  52. #define WDFLAG (1 << 15)
  53. #define WDKEY_SEQ0 (0xa5c6 << 16)
  54. #define WDKEY_SEQ1 (0xda7e << 16)
  55. static int heartbeat = DEFAULT_HEARTBEAT;
  56. static DEFINE_SPINLOCK(io_lock);
  57. static unsigned long wdt_status;
  58. #define WDT_IN_USE 0
  59. #define WDT_OK_TO_CLOSE 1
  60. #define WDT_REGION_INITED 2
  61. #define WDT_DEVICE_INITED 3
  62. static void __iomem *wdt_base;
  63. struct clk *wdt_clk;
  64. static void wdt_service(void)
  65. {
  66. spin_lock(&io_lock);
  67. /* put watchdog in service state */
  68. iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
  69. /* put watchdog in active state */
  70. iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
  71. spin_unlock(&io_lock);
  72. }
  73. static void wdt_enable(void)
  74. {
  75. u32 tgcr;
  76. u32 timer_margin;
  77. unsigned long wdt_freq;
  78. wdt_freq = clk_get_rate(wdt_clk);
  79. spin_lock(&io_lock);
  80. /* disable, internal clock source */
  81. iowrite32(0, wdt_base + TCR);
  82. /* reset timer, set mode to 64-bit watchdog, and unreset */
  83. iowrite32(0, wdt_base + TGCR);
  84. tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
  85. iowrite32(tgcr, wdt_base + TGCR);
  86. /* clear counter regs */
  87. iowrite32(0, wdt_base + TIM12);
  88. iowrite32(0, wdt_base + TIM34);
  89. /* set timeout period */
  90. timer_margin = (((u64)heartbeat * wdt_freq) & 0xffffffff);
  91. iowrite32(timer_margin, wdt_base + PRD12);
  92. timer_margin = (((u64)heartbeat * wdt_freq) >> 32);
  93. iowrite32(timer_margin, wdt_base + PRD34);
  94. /* enable run continuously */
  95. iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
  96. /* Once the WDT is in pre-active state write to
  97. * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
  98. * write protected (except for the WDKEY field)
  99. */
  100. /* put watchdog in pre-active state */
  101. iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
  102. /* put watchdog in active state */
  103. iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
  104. spin_unlock(&io_lock);
  105. }
  106. static int davinci_wdt_open(struct inode *inode, struct file *file)
  107. {
  108. if (test_and_set_bit(WDT_IN_USE, &wdt_status))
  109. return -EBUSY;
  110. wdt_enable();
  111. return nonseekable_open(inode, file);
  112. }
  113. static ssize_t
  114. davinci_wdt_write(struct file *file, const char *data, size_t len,
  115. loff_t *ppos)
  116. {
  117. if (len)
  118. wdt_service();
  119. return len;
  120. }
  121. static const struct watchdog_info ident = {
  122. .options = WDIOF_KEEPALIVEPING,
  123. .identity = "DaVinci Watchdog",
  124. };
  125. static long davinci_wdt_ioctl(struct file *file,
  126. unsigned int cmd, unsigned long arg)
  127. {
  128. int ret = -ENOTTY;
  129. switch (cmd) {
  130. case WDIOC_GETSUPPORT:
  131. ret = copy_to_user((struct watchdog_info *)arg, &ident,
  132. sizeof(ident)) ? -EFAULT : 0;
  133. break;
  134. case WDIOC_GETSTATUS:
  135. case WDIOC_GETBOOTSTATUS:
  136. ret = put_user(0, (int *)arg);
  137. break;
  138. case WDIOC_KEEPALIVE:
  139. wdt_service();
  140. ret = 0;
  141. break;
  142. case WDIOC_GETTIMEOUT:
  143. ret = put_user(heartbeat, (int *)arg);
  144. break;
  145. }
  146. return ret;
  147. }
  148. static int davinci_wdt_release(struct inode *inode, struct file *file)
  149. {
  150. wdt_service();
  151. clear_bit(WDT_IN_USE, &wdt_status);
  152. return 0;
  153. }
  154. static const struct file_operations davinci_wdt_fops = {
  155. .owner = THIS_MODULE,
  156. .llseek = no_llseek,
  157. .write = davinci_wdt_write,
  158. .unlocked_ioctl = davinci_wdt_ioctl,
  159. .open = davinci_wdt_open,
  160. .release = davinci_wdt_release,
  161. };
  162. static struct miscdevice davinci_wdt_miscdev = {
  163. .minor = WATCHDOG_MINOR,
  164. .name = "watchdog",
  165. .fops = &davinci_wdt_fops,
  166. };
  167. static int davinci_wdt_probe(struct platform_device *pdev)
  168. {
  169. int ret = 0;
  170. struct device *dev = &pdev->dev;
  171. struct resource *wdt_mem;
  172. wdt_clk = devm_clk_get(dev, NULL);
  173. if (WARN_ON(IS_ERR(wdt_clk)))
  174. return PTR_ERR(wdt_clk);
  175. clk_prepare_enable(wdt_clk);
  176. if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
  177. heartbeat = DEFAULT_HEARTBEAT;
  178. dev_info(dev, "heartbeat %d sec\n", heartbeat);
  179. wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  180. if (wdt_mem == NULL) {
  181. dev_err(dev, "failed to get memory region resource\n");
  182. return -ENOENT;
  183. }
  184. wdt_base = devm_request_and_ioremap(dev, wdt_mem);
  185. if (!wdt_base) {
  186. dev_err(dev, "ioremap failed\n");
  187. return -EADDRNOTAVAIL;
  188. }
  189. ret = misc_register(&davinci_wdt_miscdev);
  190. if (ret < 0) {
  191. dev_err(dev, "cannot register misc device\n");
  192. } else {
  193. set_bit(WDT_DEVICE_INITED, &wdt_status);
  194. }
  195. return ret;
  196. }
  197. static int davinci_wdt_remove(struct platform_device *pdev)
  198. {
  199. misc_deregister(&davinci_wdt_miscdev);
  200. clk_disable_unprepare(wdt_clk);
  201. return 0;
  202. }
  203. static const struct of_device_id davinci_wdt_of_match[] = {
  204. { .compatible = "ti,davinci-wdt", },
  205. {},
  206. };
  207. MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
  208. static struct platform_driver platform_wdt_driver = {
  209. .driver = {
  210. .name = "watchdog",
  211. .owner = THIS_MODULE,
  212. .of_match_table = davinci_wdt_of_match,
  213. },
  214. .probe = davinci_wdt_probe,
  215. .remove = davinci_wdt_remove,
  216. };
  217. module_platform_driver(platform_wdt_driver);
  218. MODULE_AUTHOR("Texas Instruments");
  219. MODULE_DESCRIPTION("DaVinci Watchdog Driver");
  220. module_param(heartbeat, int, 0);
  221. MODULE_PARM_DESC(heartbeat,
  222. "Watchdog heartbeat period in seconds from 1 to "
  223. __MODULE_STRING(MAX_HEARTBEAT) ", default "
  224. __MODULE_STRING(DEFAULT_HEARTBEAT));
  225. MODULE_LICENSE("GPL");
  226. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  227. MODULE_ALIAS("platform:watchdog");