mv_otg.c 21 KB

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  1. /*
  2. * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
  3. * Author: Chao Xie <chao.xie@marvell.com>
  4. * Neil Zhang <zhangwm@marvell.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/device.h>
  17. #include <linux/proc_fs.h>
  18. #include <linux/clk.h>
  19. #include <linux/workqueue.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/usb.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/otg.h>
  24. #include <linux/usb/gadget.h>
  25. #include <linux/usb/hcd.h>
  26. #include <linux/platform_data/mv_usb.h>
  27. #include "mv_otg.h"
  28. #define DRIVER_DESC "Marvell USB OTG transceiver driver"
  29. #define DRIVER_VERSION "Jan 20, 2010"
  30. MODULE_DESCRIPTION(DRIVER_DESC);
  31. MODULE_VERSION(DRIVER_VERSION);
  32. MODULE_LICENSE("GPL");
  33. static const char driver_name[] = "mv-otg";
  34. static char *state_string[] = {
  35. "undefined",
  36. "b_idle",
  37. "b_srp_init",
  38. "b_peripheral",
  39. "b_wait_acon",
  40. "b_host",
  41. "a_idle",
  42. "a_wait_vrise",
  43. "a_wait_bcon",
  44. "a_host",
  45. "a_suspend",
  46. "a_peripheral",
  47. "a_wait_vfall",
  48. "a_vbus_err"
  49. };
  50. static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
  51. {
  52. struct mv_otg *mvotg = container_of(otg->phy, struct mv_otg, phy);
  53. if (mvotg->pdata->set_vbus == NULL)
  54. return -ENODEV;
  55. return mvotg->pdata->set_vbus(on);
  56. }
  57. static int mv_otg_set_host(struct usb_otg *otg,
  58. struct usb_bus *host)
  59. {
  60. otg->host = host;
  61. return 0;
  62. }
  63. static int mv_otg_set_peripheral(struct usb_otg *otg,
  64. struct usb_gadget *gadget)
  65. {
  66. otg->gadget = gadget;
  67. return 0;
  68. }
  69. static void mv_otg_run_state_machine(struct mv_otg *mvotg,
  70. unsigned long delay)
  71. {
  72. dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
  73. if (!mvotg->qwork)
  74. return;
  75. queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
  76. }
  77. static void mv_otg_timer_await_bcon(unsigned long data)
  78. {
  79. struct mv_otg *mvotg = (struct mv_otg *) data;
  80. mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
  81. dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
  82. if (spin_trylock(&mvotg->wq_lock)) {
  83. mv_otg_run_state_machine(mvotg, 0);
  84. spin_unlock(&mvotg->wq_lock);
  85. }
  86. }
  87. static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
  88. {
  89. struct timer_list *timer;
  90. if (id >= OTG_TIMER_NUM)
  91. return -EINVAL;
  92. timer = &mvotg->otg_ctrl.timer[id];
  93. if (timer_pending(timer))
  94. del_timer(timer);
  95. return 0;
  96. }
  97. static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
  98. unsigned long interval,
  99. void (*callback) (unsigned long))
  100. {
  101. struct timer_list *timer;
  102. if (id >= OTG_TIMER_NUM)
  103. return -EINVAL;
  104. timer = &mvotg->otg_ctrl.timer[id];
  105. if (timer_pending(timer)) {
  106. dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
  107. return -EBUSY;
  108. }
  109. init_timer(timer);
  110. timer->data = (unsigned long) mvotg;
  111. timer->function = callback;
  112. timer->expires = jiffies + interval;
  113. add_timer(timer);
  114. return 0;
  115. }
  116. static int mv_otg_reset(struct mv_otg *mvotg)
  117. {
  118. unsigned int loops;
  119. u32 tmp;
  120. /* Stop the controller */
  121. tmp = readl(&mvotg->op_regs->usbcmd);
  122. tmp &= ~USBCMD_RUN_STOP;
  123. writel(tmp, &mvotg->op_regs->usbcmd);
  124. /* Reset the controller to get default values */
  125. writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
  126. loops = 500;
  127. while (readl(&mvotg->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
  128. if (loops == 0) {
  129. dev_err(&mvotg->pdev->dev,
  130. "Wait for RESET completed TIMEOUT\n");
  131. return -ETIMEDOUT;
  132. }
  133. loops--;
  134. udelay(20);
  135. }
  136. writel(0x0, &mvotg->op_regs->usbintr);
  137. tmp = readl(&mvotg->op_regs->usbsts);
  138. writel(tmp, &mvotg->op_regs->usbsts);
  139. return 0;
  140. }
  141. static void mv_otg_init_irq(struct mv_otg *mvotg)
  142. {
  143. u32 otgsc;
  144. mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
  145. | OTGSC_INTR_A_VBUS_VALID;
  146. mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
  147. | OTGSC_INTSTS_A_VBUS_VALID;
  148. if (mvotg->pdata->vbus == NULL) {
  149. mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
  150. | OTGSC_INTR_B_SESSION_END;
  151. mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
  152. | OTGSC_INTSTS_B_SESSION_END;
  153. }
  154. if (mvotg->pdata->id == NULL) {
  155. mvotg->irq_en |= OTGSC_INTR_USB_ID;
  156. mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
  157. }
  158. otgsc = readl(&mvotg->op_regs->otgsc);
  159. otgsc |= mvotg->irq_en;
  160. writel(otgsc, &mvotg->op_regs->otgsc);
  161. }
  162. static void mv_otg_start_host(struct mv_otg *mvotg, int on)
  163. {
  164. #ifdef CONFIG_USB
  165. struct usb_otg *otg = mvotg->phy.otg;
  166. struct usb_hcd *hcd;
  167. if (!otg->host)
  168. return;
  169. dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
  170. hcd = bus_to_hcd(otg->host);
  171. if (on)
  172. usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
  173. else
  174. usb_remove_hcd(hcd);
  175. #endif /* CONFIG_USB */
  176. }
  177. static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
  178. {
  179. struct usb_otg *otg = mvotg->phy.otg;
  180. if (!otg->gadget)
  181. return;
  182. dev_info(mvotg->phy.dev, "gadget %s\n", on ? "on" : "off");
  183. if (on)
  184. usb_gadget_vbus_connect(otg->gadget);
  185. else
  186. usb_gadget_vbus_disconnect(otg->gadget);
  187. }
  188. static void otg_clock_enable(struct mv_otg *mvotg)
  189. {
  190. unsigned int i;
  191. for (i = 0; i < mvotg->clknum; i++)
  192. clk_prepare_enable(mvotg->clk[i]);
  193. }
  194. static void otg_clock_disable(struct mv_otg *mvotg)
  195. {
  196. unsigned int i;
  197. for (i = 0; i < mvotg->clknum; i++)
  198. clk_disable_unprepare(mvotg->clk[i]);
  199. }
  200. static int mv_otg_enable_internal(struct mv_otg *mvotg)
  201. {
  202. int retval = 0;
  203. if (mvotg->active)
  204. return 0;
  205. dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
  206. otg_clock_enable(mvotg);
  207. if (mvotg->pdata->phy_init) {
  208. retval = mvotg->pdata->phy_init(mvotg->phy_regs);
  209. if (retval) {
  210. dev_err(&mvotg->pdev->dev,
  211. "init phy error %d\n", retval);
  212. otg_clock_disable(mvotg);
  213. return retval;
  214. }
  215. }
  216. mvotg->active = 1;
  217. return 0;
  218. }
  219. static int mv_otg_enable(struct mv_otg *mvotg)
  220. {
  221. if (mvotg->clock_gating)
  222. return mv_otg_enable_internal(mvotg);
  223. return 0;
  224. }
  225. static void mv_otg_disable_internal(struct mv_otg *mvotg)
  226. {
  227. if (mvotg->active) {
  228. dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
  229. if (mvotg->pdata->phy_deinit)
  230. mvotg->pdata->phy_deinit(mvotg->phy_regs);
  231. otg_clock_disable(mvotg);
  232. mvotg->active = 0;
  233. }
  234. }
  235. static void mv_otg_disable(struct mv_otg *mvotg)
  236. {
  237. if (mvotg->clock_gating)
  238. mv_otg_disable_internal(mvotg);
  239. }
  240. static void mv_otg_update_inputs(struct mv_otg *mvotg)
  241. {
  242. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  243. u32 otgsc;
  244. otgsc = readl(&mvotg->op_regs->otgsc);
  245. if (mvotg->pdata->vbus) {
  246. if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
  247. otg_ctrl->b_sess_vld = 1;
  248. otg_ctrl->b_sess_end = 0;
  249. } else {
  250. otg_ctrl->b_sess_vld = 0;
  251. otg_ctrl->b_sess_end = 1;
  252. }
  253. } else {
  254. otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
  255. otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
  256. }
  257. if (mvotg->pdata->id)
  258. otg_ctrl->id = !!mvotg->pdata->id->poll();
  259. else
  260. otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
  261. if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
  262. otg_ctrl->a_bus_req = 1;
  263. otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
  264. otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
  265. dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
  266. dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
  267. dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
  268. dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
  269. dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
  270. dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
  271. }
  272. static void mv_otg_update_state(struct mv_otg *mvotg)
  273. {
  274. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  275. struct usb_phy *phy = &mvotg->phy;
  276. int old_state = phy->state;
  277. switch (old_state) {
  278. case OTG_STATE_UNDEFINED:
  279. phy->state = OTG_STATE_B_IDLE;
  280. /* FALL THROUGH */
  281. case OTG_STATE_B_IDLE:
  282. if (otg_ctrl->id == 0)
  283. phy->state = OTG_STATE_A_IDLE;
  284. else if (otg_ctrl->b_sess_vld)
  285. phy->state = OTG_STATE_B_PERIPHERAL;
  286. break;
  287. case OTG_STATE_B_PERIPHERAL:
  288. if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
  289. phy->state = OTG_STATE_B_IDLE;
  290. break;
  291. case OTG_STATE_A_IDLE:
  292. if (otg_ctrl->id)
  293. phy->state = OTG_STATE_B_IDLE;
  294. else if (!(otg_ctrl->a_bus_drop) &&
  295. (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
  296. phy->state = OTG_STATE_A_WAIT_VRISE;
  297. break;
  298. case OTG_STATE_A_WAIT_VRISE:
  299. if (otg_ctrl->a_vbus_vld)
  300. phy->state = OTG_STATE_A_WAIT_BCON;
  301. break;
  302. case OTG_STATE_A_WAIT_BCON:
  303. if (otg_ctrl->id || otg_ctrl->a_bus_drop
  304. || otg_ctrl->a_wait_bcon_timeout) {
  305. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  306. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  307. phy->state = OTG_STATE_A_WAIT_VFALL;
  308. otg_ctrl->a_bus_req = 0;
  309. } else if (!otg_ctrl->a_vbus_vld) {
  310. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  311. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  312. phy->state = OTG_STATE_A_VBUS_ERR;
  313. } else if (otg_ctrl->b_conn) {
  314. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  315. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  316. phy->state = OTG_STATE_A_HOST;
  317. }
  318. break;
  319. case OTG_STATE_A_HOST:
  320. if (otg_ctrl->id || !otg_ctrl->b_conn
  321. || otg_ctrl->a_bus_drop)
  322. phy->state = OTG_STATE_A_WAIT_BCON;
  323. else if (!otg_ctrl->a_vbus_vld)
  324. phy->state = OTG_STATE_A_VBUS_ERR;
  325. break;
  326. case OTG_STATE_A_WAIT_VFALL:
  327. if (otg_ctrl->id
  328. || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
  329. || otg_ctrl->a_bus_req)
  330. phy->state = OTG_STATE_A_IDLE;
  331. break;
  332. case OTG_STATE_A_VBUS_ERR:
  333. if (otg_ctrl->id || otg_ctrl->a_clr_err
  334. || otg_ctrl->a_bus_drop) {
  335. otg_ctrl->a_clr_err = 0;
  336. phy->state = OTG_STATE_A_WAIT_VFALL;
  337. }
  338. break;
  339. default:
  340. break;
  341. }
  342. }
  343. static void mv_otg_work(struct work_struct *work)
  344. {
  345. struct mv_otg *mvotg;
  346. struct usb_phy *phy;
  347. struct usb_otg *otg;
  348. int old_state;
  349. mvotg = container_of(to_delayed_work(work), struct mv_otg, work);
  350. run:
  351. /* work queue is single thread, or we need spin_lock to protect */
  352. phy = &mvotg->phy;
  353. otg = phy->otg;
  354. old_state = phy->state;
  355. if (!mvotg->active)
  356. return;
  357. mv_otg_update_inputs(mvotg);
  358. mv_otg_update_state(mvotg);
  359. if (old_state != phy->state) {
  360. dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
  361. state_string[old_state],
  362. state_string[phy->state]);
  363. switch (phy->state) {
  364. case OTG_STATE_B_IDLE:
  365. otg->default_a = 0;
  366. if (old_state == OTG_STATE_B_PERIPHERAL)
  367. mv_otg_start_periphrals(mvotg, 0);
  368. mv_otg_reset(mvotg);
  369. mv_otg_disable(mvotg);
  370. break;
  371. case OTG_STATE_B_PERIPHERAL:
  372. mv_otg_enable(mvotg);
  373. mv_otg_start_periphrals(mvotg, 1);
  374. break;
  375. case OTG_STATE_A_IDLE:
  376. otg->default_a = 1;
  377. mv_otg_enable(mvotg);
  378. if (old_state == OTG_STATE_A_WAIT_VFALL)
  379. mv_otg_start_host(mvotg, 0);
  380. mv_otg_reset(mvotg);
  381. break;
  382. case OTG_STATE_A_WAIT_VRISE:
  383. mv_otg_set_vbus(otg, 1);
  384. break;
  385. case OTG_STATE_A_WAIT_BCON:
  386. if (old_state != OTG_STATE_A_HOST)
  387. mv_otg_start_host(mvotg, 1);
  388. mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
  389. T_A_WAIT_BCON,
  390. mv_otg_timer_await_bcon);
  391. /*
  392. * Now, we directly enter A_HOST. So set b_conn = 1
  393. * here. In fact, it need host driver to notify us.
  394. */
  395. mvotg->otg_ctrl.b_conn = 1;
  396. break;
  397. case OTG_STATE_A_HOST:
  398. break;
  399. case OTG_STATE_A_WAIT_VFALL:
  400. /*
  401. * Now, we has exited A_HOST. So set b_conn = 0
  402. * here. In fact, it need host driver to notify us.
  403. */
  404. mvotg->otg_ctrl.b_conn = 0;
  405. mv_otg_set_vbus(otg, 0);
  406. break;
  407. case OTG_STATE_A_VBUS_ERR:
  408. break;
  409. default:
  410. break;
  411. }
  412. goto run;
  413. }
  414. }
  415. static irqreturn_t mv_otg_irq(int irq, void *dev)
  416. {
  417. struct mv_otg *mvotg = dev;
  418. u32 otgsc;
  419. otgsc = readl(&mvotg->op_regs->otgsc);
  420. writel(otgsc, &mvotg->op_regs->otgsc);
  421. /*
  422. * if we have vbus, then the vbus detection for B-device
  423. * will be done by mv_otg_inputs_irq().
  424. */
  425. if (mvotg->pdata->vbus)
  426. if ((otgsc & OTGSC_STS_USB_ID) &&
  427. !(otgsc & OTGSC_INTSTS_USB_ID))
  428. return IRQ_NONE;
  429. if ((otgsc & mvotg->irq_status) == 0)
  430. return IRQ_NONE;
  431. mv_otg_run_state_machine(mvotg, 0);
  432. return IRQ_HANDLED;
  433. }
  434. static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
  435. {
  436. struct mv_otg *mvotg = dev;
  437. /* The clock may disabled at this time */
  438. if (!mvotg->active) {
  439. mv_otg_enable(mvotg);
  440. mv_otg_init_irq(mvotg);
  441. }
  442. mv_otg_run_state_machine(mvotg, 0);
  443. return IRQ_HANDLED;
  444. }
  445. static ssize_t
  446. get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  447. {
  448. struct mv_otg *mvotg = dev_get_drvdata(dev);
  449. return scnprintf(buf, PAGE_SIZE, "%d\n",
  450. mvotg->otg_ctrl.a_bus_req);
  451. }
  452. static ssize_t
  453. set_a_bus_req(struct device *dev, struct device_attribute *attr,
  454. const char *buf, size_t count)
  455. {
  456. struct mv_otg *mvotg = dev_get_drvdata(dev);
  457. if (count > 2)
  458. return -1;
  459. /* We will use this interface to change to A device */
  460. if (mvotg->phy.state != OTG_STATE_B_IDLE
  461. && mvotg->phy.state != OTG_STATE_A_IDLE)
  462. return -1;
  463. /* The clock may disabled and we need to set irq for ID detected */
  464. mv_otg_enable(mvotg);
  465. mv_otg_init_irq(mvotg);
  466. if (buf[0] == '1') {
  467. mvotg->otg_ctrl.a_bus_req = 1;
  468. mvotg->otg_ctrl.a_bus_drop = 0;
  469. dev_dbg(&mvotg->pdev->dev,
  470. "User request: a_bus_req = 1\n");
  471. if (spin_trylock(&mvotg->wq_lock)) {
  472. mv_otg_run_state_machine(mvotg, 0);
  473. spin_unlock(&mvotg->wq_lock);
  474. }
  475. }
  476. return count;
  477. }
  478. static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req,
  479. set_a_bus_req);
  480. static ssize_t
  481. set_a_clr_err(struct device *dev, struct device_attribute *attr,
  482. const char *buf, size_t count)
  483. {
  484. struct mv_otg *mvotg = dev_get_drvdata(dev);
  485. if (!mvotg->phy.otg->default_a)
  486. return -1;
  487. if (count > 2)
  488. return -1;
  489. if (buf[0] == '1') {
  490. mvotg->otg_ctrl.a_clr_err = 1;
  491. dev_dbg(&mvotg->pdev->dev,
  492. "User request: a_clr_err = 1\n");
  493. }
  494. if (spin_trylock(&mvotg->wq_lock)) {
  495. mv_otg_run_state_machine(mvotg, 0);
  496. spin_unlock(&mvotg->wq_lock);
  497. }
  498. return count;
  499. }
  500. static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
  501. static ssize_t
  502. get_a_bus_drop(struct device *dev, struct device_attribute *attr,
  503. char *buf)
  504. {
  505. struct mv_otg *mvotg = dev_get_drvdata(dev);
  506. return scnprintf(buf, PAGE_SIZE, "%d\n",
  507. mvotg->otg_ctrl.a_bus_drop);
  508. }
  509. static ssize_t
  510. set_a_bus_drop(struct device *dev, struct device_attribute *attr,
  511. const char *buf, size_t count)
  512. {
  513. struct mv_otg *mvotg = dev_get_drvdata(dev);
  514. if (!mvotg->phy.otg->default_a)
  515. return -1;
  516. if (count > 2)
  517. return -1;
  518. if (buf[0] == '0') {
  519. mvotg->otg_ctrl.a_bus_drop = 0;
  520. dev_dbg(&mvotg->pdev->dev,
  521. "User request: a_bus_drop = 0\n");
  522. } else if (buf[0] == '1') {
  523. mvotg->otg_ctrl.a_bus_drop = 1;
  524. mvotg->otg_ctrl.a_bus_req = 0;
  525. dev_dbg(&mvotg->pdev->dev,
  526. "User request: a_bus_drop = 1\n");
  527. dev_dbg(&mvotg->pdev->dev,
  528. "User request: and a_bus_req = 0\n");
  529. }
  530. if (spin_trylock(&mvotg->wq_lock)) {
  531. mv_otg_run_state_machine(mvotg, 0);
  532. spin_unlock(&mvotg->wq_lock);
  533. }
  534. return count;
  535. }
  536. static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR,
  537. get_a_bus_drop, set_a_bus_drop);
  538. static struct attribute *inputs_attrs[] = {
  539. &dev_attr_a_bus_req.attr,
  540. &dev_attr_a_clr_err.attr,
  541. &dev_attr_a_bus_drop.attr,
  542. NULL,
  543. };
  544. static struct attribute_group inputs_attr_group = {
  545. .name = "inputs",
  546. .attrs = inputs_attrs,
  547. };
  548. int mv_otg_remove(struct platform_device *pdev)
  549. {
  550. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  551. sysfs_remove_group(&mvotg->pdev->dev.kobj, &inputs_attr_group);
  552. if (mvotg->qwork) {
  553. flush_workqueue(mvotg->qwork);
  554. destroy_workqueue(mvotg->qwork);
  555. }
  556. mv_otg_disable(mvotg);
  557. usb_remove_phy(&mvotg->phy);
  558. platform_set_drvdata(pdev, NULL);
  559. return 0;
  560. }
  561. static int mv_otg_probe(struct platform_device *pdev)
  562. {
  563. struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
  564. struct mv_otg *mvotg;
  565. struct usb_otg *otg;
  566. struct resource *r;
  567. int retval = 0, clk_i, i;
  568. size_t size;
  569. if (pdata == NULL) {
  570. dev_err(&pdev->dev, "failed to get platform data\n");
  571. return -ENODEV;
  572. }
  573. size = sizeof(*mvotg) + sizeof(struct clk *) * pdata->clknum;
  574. mvotg = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
  575. if (!mvotg) {
  576. dev_err(&pdev->dev, "failed to allocate memory!\n");
  577. return -ENOMEM;
  578. }
  579. otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
  580. if (!otg)
  581. return -ENOMEM;
  582. platform_set_drvdata(pdev, mvotg);
  583. mvotg->pdev = pdev;
  584. mvotg->pdata = pdata;
  585. mvotg->clknum = pdata->clknum;
  586. for (clk_i = 0; clk_i < mvotg->clknum; clk_i++) {
  587. mvotg->clk[clk_i] = devm_clk_get(&pdev->dev,
  588. pdata->clkname[clk_i]);
  589. if (IS_ERR(mvotg->clk[clk_i])) {
  590. retval = PTR_ERR(mvotg->clk[clk_i]);
  591. return retval;
  592. }
  593. }
  594. mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
  595. if (!mvotg->qwork) {
  596. dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
  597. return -ENOMEM;
  598. }
  599. INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
  600. /* OTG common part */
  601. mvotg->pdev = pdev;
  602. mvotg->phy.dev = &pdev->dev;
  603. mvotg->phy.otg = otg;
  604. mvotg->phy.label = driver_name;
  605. mvotg->phy.state = OTG_STATE_UNDEFINED;
  606. otg->phy = &mvotg->phy;
  607. otg->set_host = mv_otg_set_host;
  608. otg->set_peripheral = mv_otg_set_peripheral;
  609. otg->set_vbus = mv_otg_set_vbus;
  610. for (i = 0; i < OTG_TIMER_NUM; i++)
  611. init_timer(&mvotg->otg_ctrl.timer[i]);
  612. r = platform_get_resource_byname(mvotg->pdev,
  613. IORESOURCE_MEM, "phyregs");
  614. if (r == NULL) {
  615. dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
  616. retval = -ENODEV;
  617. goto err_destroy_workqueue;
  618. }
  619. mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  620. if (mvotg->phy_regs == NULL) {
  621. dev_err(&pdev->dev, "failed to map phy I/O memory\n");
  622. retval = -EFAULT;
  623. goto err_destroy_workqueue;
  624. }
  625. r = platform_get_resource_byname(mvotg->pdev,
  626. IORESOURCE_MEM, "capregs");
  627. if (r == NULL) {
  628. dev_err(&pdev->dev, "no I/O memory resource defined\n");
  629. retval = -ENODEV;
  630. goto err_destroy_workqueue;
  631. }
  632. mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  633. if (mvotg->cap_regs == NULL) {
  634. dev_err(&pdev->dev, "failed to map I/O memory\n");
  635. retval = -EFAULT;
  636. goto err_destroy_workqueue;
  637. }
  638. /* we will acces controller register, so enable the udc controller */
  639. retval = mv_otg_enable_internal(mvotg);
  640. if (retval) {
  641. dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
  642. goto err_destroy_workqueue;
  643. }
  644. mvotg->op_regs =
  645. (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
  646. + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
  647. if (pdata->id) {
  648. retval = devm_request_threaded_irq(&pdev->dev, pdata->id->irq,
  649. NULL, mv_otg_inputs_irq,
  650. IRQF_ONESHOT, "id", mvotg);
  651. if (retval) {
  652. dev_info(&pdev->dev,
  653. "Failed to request irq for ID\n");
  654. pdata->id = NULL;
  655. }
  656. }
  657. if (pdata->vbus) {
  658. mvotg->clock_gating = 1;
  659. retval = devm_request_threaded_irq(&pdev->dev, pdata->vbus->irq,
  660. NULL, mv_otg_inputs_irq,
  661. IRQF_ONESHOT, "vbus", mvotg);
  662. if (retval) {
  663. dev_info(&pdev->dev,
  664. "Failed to request irq for VBUS, "
  665. "disable clock gating\n");
  666. mvotg->clock_gating = 0;
  667. pdata->vbus = NULL;
  668. }
  669. }
  670. if (pdata->disable_otg_clock_gating)
  671. mvotg->clock_gating = 0;
  672. mv_otg_reset(mvotg);
  673. mv_otg_init_irq(mvotg);
  674. r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
  675. if (r == NULL) {
  676. dev_err(&pdev->dev, "no IRQ resource defined\n");
  677. retval = -ENODEV;
  678. goto err_disable_clk;
  679. }
  680. mvotg->irq = r->start;
  681. if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED,
  682. driver_name, mvotg)) {
  683. dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
  684. mvotg->irq);
  685. mvotg->irq = 0;
  686. retval = -ENODEV;
  687. goto err_disable_clk;
  688. }
  689. retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
  690. if (retval < 0) {
  691. dev_err(&pdev->dev, "can't register transceiver, %d\n",
  692. retval);
  693. goto err_disable_clk;
  694. }
  695. retval = sysfs_create_group(&pdev->dev.kobj, &inputs_attr_group);
  696. if (retval < 0) {
  697. dev_dbg(&pdev->dev,
  698. "Can't register sysfs attr group: %d\n", retval);
  699. goto err_remove_phy;
  700. }
  701. spin_lock_init(&mvotg->wq_lock);
  702. if (spin_trylock(&mvotg->wq_lock)) {
  703. mv_otg_run_state_machine(mvotg, 2 * HZ);
  704. spin_unlock(&mvotg->wq_lock);
  705. }
  706. dev_info(&pdev->dev,
  707. "successful probe OTG device %s clock gating.\n",
  708. mvotg->clock_gating ? "with" : "without");
  709. return 0;
  710. err_remove_phy:
  711. usb_remove_phy(&mvotg->phy);
  712. err_disable_clk:
  713. mv_otg_disable_internal(mvotg);
  714. err_destroy_workqueue:
  715. flush_workqueue(mvotg->qwork);
  716. destroy_workqueue(mvotg->qwork);
  717. platform_set_drvdata(pdev, NULL);
  718. return retval;
  719. }
  720. #ifdef CONFIG_PM
  721. static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
  722. {
  723. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  724. if (mvotg->phy.state != OTG_STATE_B_IDLE) {
  725. dev_info(&pdev->dev,
  726. "OTG state is not B_IDLE, it is %d!\n",
  727. mvotg->phy.state);
  728. return -EAGAIN;
  729. }
  730. if (!mvotg->clock_gating)
  731. mv_otg_disable_internal(mvotg);
  732. return 0;
  733. }
  734. static int mv_otg_resume(struct platform_device *pdev)
  735. {
  736. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  737. u32 otgsc;
  738. if (!mvotg->clock_gating) {
  739. mv_otg_enable_internal(mvotg);
  740. otgsc = readl(&mvotg->op_regs->otgsc);
  741. otgsc |= mvotg->irq_en;
  742. writel(otgsc, &mvotg->op_regs->otgsc);
  743. if (spin_trylock(&mvotg->wq_lock)) {
  744. mv_otg_run_state_machine(mvotg, 0);
  745. spin_unlock(&mvotg->wq_lock);
  746. }
  747. }
  748. return 0;
  749. }
  750. #endif
  751. static struct platform_driver mv_otg_driver = {
  752. .probe = mv_otg_probe,
  753. .remove = __exit_p(mv_otg_remove),
  754. .driver = {
  755. .owner = THIS_MODULE,
  756. .name = driver_name,
  757. },
  758. #ifdef CONFIG_PM
  759. .suspend = mv_otg_suspend,
  760. .resume = mv_otg_resume,
  761. #endif
  762. };
  763. module_platform_driver(mv_otg_driver);