xhci-pci.c 10 KB

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  1. /*
  2. * xHCI host controller driver PCI Bus Glue.
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/slab.h>
  24. #include <linux/module.h>
  25. #include "xhci.h"
  26. /* Device for a quirk */
  27. #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
  28. #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
  29. #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
  30. #define PCI_VENDOR_ID_ETRON 0x1b6f
  31. #define PCI_DEVICE_ID_ASROCK_P67 0x7023
  32. static const char hcd_name[] = "xhci_hcd";
  33. /* called after powerup, by probe or system-pm "wakeup" */
  34. static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  35. {
  36. /*
  37. * TODO: Implement finding debug ports later.
  38. * TODO: see if there are any quirks that need to be added to handle
  39. * new extended capabilities.
  40. */
  41. /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  42. if (!pci_set_mwi(pdev))
  43. xhci_dbg(xhci, "MWI active\n");
  44. xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  45. return 0;
  46. }
  47. static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  48. {
  49. struct pci_dev *pdev = to_pci_dev(dev);
  50. /* Look for vendor-specific quirks */
  51. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  52. (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  53. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  54. if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  55. pdev->revision == 0x0) {
  56. xhci->quirks |= XHCI_RESET_EP_QUIRK;
  57. xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
  58. " endpoint cmd after reset endpoint\n");
  59. }
  60. /* Fresco Logic confirms: all revisions of this chip do not
  61. * support MSI, even though some of them claim to in their PCI
  62. * capabilities.
  63. */
  64. xhci->quirks |= XHCI_BROKEN_MSI;
  65. xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
  66. "has broken MSI implementation\n",
  67. pdev->revision);
  68. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  69. }
  70. if (pdev->vendor == PCI_VENDOR_ID_NEC)
  71. xhci->quirks |= XHCI_NEC_HOST;
  72. if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
  73. xhci->quirks |= XHCI_AMD_0x96_HOST;
  74. /* AMD PLL quirk */
  75. if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
  76. xhci->quirks |= XHCI_AMD_PLL_FIX;
  77. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  78. xhci->quirks |= XHCI_LPM_SUPPORT;
  79. xhci->quirks |= XHCI_INTEL_HOST;
  80. }
  81. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  82. pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
  83. xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
  84. xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
  85. xhci->limit_active_eps = 64;
  86. xhci->quirks |= XHCI_SW_BW_CHECKING;
  87. /*
  88. * PPT desktop boards DH77EB and DH77DF will power back on after
  89. * a few seconds of being shutdown. The fix for this is to
  90. * switch the ports from xHCI to EHCI on shutdown. We can't use
  91. * DMI information to find those particular boards (since each
  92. * vendor will change the board name), so we have to key off all
  93. * PPT chipsets.
  94. */
  95. xhci->quirks |= XHCI_SPURIOUS_REBOOT;
  96. xhci->quirks |= XHCI_AVOID_BEI;
  97. }
  98. if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
  99. pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
  100. xhci->quirks |= XHCI_RESET_ON_RESUME;
  101. xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
  102. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  103. }
  104. if (pdev->vendor == PCI_VENDOR_ID_VIA)
  105. xhci->quirks |= XHCI_RESET_ON_RESUME;
  106. }
  107. /* called during probe() after chip reset completes */
  108. static int xhci_pci_setup(struct usb_hcd *hcd)
  109. {
  110. struct xhci_hcd *xhci;
  111. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  112. int retval;
  113. retval = xhci_gen_setup(hcd, xhci_pci_quirks);
  114. if (retval)
  115. return retval;
  116. xhci = hcd_to_xhci(hcd);
  117. if (!usb_hcd_is_primary_hcd(hcd))
  118. return 0;
  119. pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
  120. xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
  121. /* Find any debug ports */
  122. retval = xhci_pci_reinit(xhci, pdev);
  123. if (!retval)
  124. return retval;
  125. kfree(xhci);
  126. return retval;
  127. }
  128. /*
  129. * We need to register our own PCI probe function (instead of the USB core's
  130. * function) in order to create a second roothub under xHCI.
  131. */
  132. static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  133. {
  134. int retval;
  135. struct xhci_hcd *xhci;
  136. struct hc_driver *driver;
  137. struct usb_hcd *hcd;
  138. driver = (struct hc_driver *)id->driver_data;
  139. /* Register the USB 2.0 roothub.
  140. * FIXME: USB core must know to register the USB 2.0 roothub first.
  141. * This is sort of silly, because we could just set the HCD driver flags
  142. * to say USB 2.0, but I'm not sure what the implications would be in
  143. * the other parts of the HCD code.
  144. */
  145. retval = usb_hcd_pci_probe(dev, id);
  146. if (retval)
  147. return retval;
  148. /* USB 2.0 roothub is stored in the PCI device now. */
  149. hcd = dev_get_drvdata(&dev->dev);
  150. xhci = hcd_to_xhci(hcd);
  151. xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
  152. pci_name(dev), hcd);
  153. if (!xhci->shared_hcd) {
  154. retval = -ENOMEM;
  155. goto dealloc_usb2_hcd;
  156. }
  157. /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
  158. * is called by usb_add_hcd().
  159. */
  160. *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
  161. retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
  162. IRQF_SHARED);
  163. if (retval)
  164. goto put_usb3_hcd;
  165. /* Roothub already marked as USB 3.0 speed */
  166. /* We know the LPM timeout algorithms for this host, let the USB core
  167. * enable and disable LPM for devices under the USB 3.0 roothub.
  168. */
  169. if (xhci->quirks & XHCI_LPM_SUPPORT)
  170. hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
  171. return 0;
  172. put_usb3_hcd:
  173. usb_put_hcd(xhci->shared_hcd);
  174. dealloc_usb2_hcd:
  175. usb_hcd_pci_remove(dev);
  176. return retval;
  177. }
  178. static void xhci_pci_remove(struct pci_dev *dev)
  179. {
  180. struct xhci_hcd *xhci;
  181. xhci = hcd_to_xhci(pci_get_drvdata(dev));
  182. if (xhci->shared_hcd) {
  183. usb_remove_hcd(xhci->shared_hcd);
  184. usb_put_hcd(xhci->shared_hcd);
  185. }
  186. usb_hcd_pci_remove(dev);
  187. kfree(xhci);
  188. }
  189. #ifdef CONFIG_PM
  190. static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  191. {
  192. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  193. return xhci_suspend(xhci);
  194. }
  195. static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  196. {
  197. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  198. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  199. int retval = 0;
  200. /* The BIOS on systems with the Intel Panther Point chipset may or may
  201. * not support xHCI natively. That means that during system resume, it
  202. * may switch the ports back to EHCI so that users can use their
  203. * keyboard to select a kernel from GRUB after resume from hibernate.
  204. *
  205. * The BIOS is supposed to remember whether the OS had xHCI ports
  206. * enabled before resume, and switch the ports back to xHCI when the
  207. * BIOS/OS semaphore is written, but we all know we can't trust BIOS
  208. * writers.
  209. *
  210. * Unconditionally switch the ports back to xHCI after a system resume.
  211. * We can't tell whether the EHCI or xHCI controller will be resumed
  212. * first, so we have to do the port switchover in both drivers. Writing
  213. * a '1' to the port switchover registers should have no effect if the
  214. * port was already switched over.
  215. */
  216. if (usb_is_intel_switchable_xhci(pdev))
  217. usb_enable_xhci_ports(pdev);
  218. retval = xhci_resume(xhci, hibernated);
  219. return retval;
  220. }
  221. #endif /* CONFIG_PM */
  222. static const struct hc_driver xhci_pci_hc_driver = {
  223. .description = hcd_name,
  224. .product_desc = "xHCI Host Controller",
  225. .hcd_priv_size = sizeof(struct xhci_hcd *),
  226. /*
  227. * generic hardware linkage
  228. */
  229. .irq = xhci_irq,
  230. .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
  231. /*
  232. * basic lifecycle operations
  233. */
  234. .reset = xhci_pci_setup,
  235. .start = xhci_run,
  236. #ifdef CONFIG_PM
  237. .pci_suspend = xhci_pci_suspend,
  238. .pci_resume = xhci_pci_resume,
  239. #endif
  240. .stop = xhci_stop,
  241. .shutdown = xhci_shutdown,
  242. /*
  243. * managing i/o requests and associated device resources
  244. */
  245. .urb_enqueue = xhci_urb_enqueue,
  246. .urb_dequeue = xhci_urb_dequeue,
  247. .alloc_dev = xhci_alloc_dev,
  248. .free_dev = xhci_free_dev,
  249. .alloc_streams = xhci_alloc_streams,
  250. .free_streams = xhci_free_streams,
  251. .add_endpoint = xhci_add_endpoint,
  252. .drop_endpoint = xhci_drop_endpoint,
  253. .endpoint_reset = xhci_endpoint_reset,
  254. .check_bandwidth = xhci_check_bandwidth,
  255. .reset_bandwidth = xhci_reset_bandwidth,
  256. .address_device = xhci_address_device,
  257. .update_hub_device = xhci_update_hub_device,
  258. .reset_device = xhci_discover_or_reset_device,
  259. /*
  260. * scheduling support
  261. */
  262. .get_frame_number = xhci_get_frame,
  263. /* Root hub support */
  264. .hub_control = xhci_hub_control,
  265. .hub_status_data = xhci_hub_status_data,
  266. .bus_suspend = xhci_bus_suspend,
  267. .bus_resume = xhci_bus_resume,
  268. /*
  269. * call back when device connected and addressed
  270. */
  271. .update_device = xhci_update_device,
  272. .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
  273. .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
  274. .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
  275. .find_raw_port_number = xhci_find_raw_port_number,
  276. };
  277. /*-------------------------------------------------------------------------*/
  278. /* PCI driver selection metadata; PCI hotplugging uses this */
  279. static const struct pci_device_id pci_ids[] = { {
  280. /* handle any USB 3.0 xHCI controller */
  281. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
  282. .driver_data = (unsigned long) &xhci_pci_hc_driver,
  283. },
  284. { /* end: all zeroes */ }
  285. };
  286. MODULE_DEVICE_TABLE(pci, pci_ids);
  287. /* pci driver glue; this is a "new style" PCI driver module */
  288. static struct pci_driver xhci_pci_driver = {
  289. .name = (char *) hcd_name,
  290. .id_table = pci_ids,
  291. .probe = xhci_pci_probe,
  292. .remove = xhci_pci_remove,
  293. /* suspend and resume implemented later */
  294. .shutdown = usb_hcd_pci_shutdown,
  295. #ifdef CONFIG_PM_SLEEP
  296. .driver = {
  297. .pm = &usb_hcd_pci_pm_ops
  298. },
  299. #endif
  300. };
  301. int __init xhci_register_pci(void)
  302. {
  303. return pci_register_driver(&xhci_pci_driver);
  304. }
  305. void xhci_unregister_pci(void)
  306. {
  307. pci_unregister_driver(&xhci_pci_driver);
  308. }