ehci-mem.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2001 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. /*-------------------------------------------------------------------------*/
  20. /*
  21. * There's basically three types of memory:
  22. * - data used only by the HCD ... kmalloc is fine
  23. * - async and periodic schedules, shared by HC and HCD ... these
  24. * need to use dma_pool or dma_alloc_coherent
  25. * - driver buffers, read/written by HC ... single shot DMA mapped
  26. *
  27. * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
  28. * No memory seen by this driver is pageable.
  29. */
  30. /*-------------------------------------------------------------------------*/
  31. /* Allocate the key transfer structures from the previously allocated pool */
  32. static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
  33. dma_addr_t dma)
  34. {
  35. memset (qtd, 0, sizeof *qtd);
  36. qtd->qtd_dma = dma;
  37. qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
  38. qtd->hw_next = EHCI_LIST_END(ehci);
  39. qtd->hw_alt_next = EHCI_LIST_END(ehci);
  40. INIT_LIST_HEAD (&qtd->qtd_list);
  41. }
  42. static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
  43. {
  44. struct ehci_qtd *qtd;
  45. dma_addr_t dma;
  46. qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
  47. if (qtd != NULL) {
  48. ehci_qtd_init(ehci, qtd, dma);
  49. }
  50. return qtd;
  51. }
  52. static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  53. {
  54. dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
  55. }
  56. static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh)
  57. {
  58. /* clean qtds first, and know this is not linked */
  59. if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
  60. ehci_dbg (ehci, "unused qh not empty!\n");
  61. BUG ();
  62. }
  63. if (qh->dummy)
  64. ehci_qtd_free (ehci, qh->dummy);
  65. dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
  66. kfree(qh);
  67. }
  68. static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
  69. {
  70. struct ehci_qh *qh;
  71. dma_addr_t dma;
  72. qh = kzalloc(sizeof *qh, GFP_ATOMIC);
  73. if (!qh)
  74. goto done;
  75. qh->hw = (struct ehci_qh_hw *)
  76. dma_pool_alloc(ehci->qh_pool, flags, &dma);
  77. if (!qh->hw)
  78. goto fail;
  79. memset(qh->hw, 0, sizeof *qh->hw);
  80. qh->qh_dma = dma;
  81. // INIT_LIST_HEAD (&qh->qh_list);
  82. INIT_LIST_HEAD (&qh->qtd_list);
  83. /* dummy td enables safe urb queuing */
  84. qh->dummy = ehci_qtd_alloc (ehci, flags);
  85. if (qh->dummy == NULL) {
  86. ehci_dbg (ehci, "no dummy td\n");
  87. goto fail1;
  88. }
  89. done:
  90. return qh;
  91. fail1:
  92. dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
  93. fail:
  94. kfree(qh);
  95. return NULL;
  96. }
  97. /*-------------------------------------------------------------------------*/
  98. /* The queue heads and transfer descriptors are managed from pools tied
  99. * to each of the "per device" structures.
  100. * This is the initialisation and cleanup code.
  101. */
  102. static void ehci_mem_cleanup (struct ehci_hcd *ehci)
  103. {
  104. if (ehci->async)
  105. qh_destroy(ehci, ehci->async);
  106. ehci->async = NULL;
  107. if (ehci->dummy)
  108. qh_destroy(ehci, ehci->dummy);
  109. ehci->dummy = NULL;
  110. /* DMA consistent memory and pools */
  111. if (ehci->qtd_pool)
  112. dma_pool_destroy (ehci->qtd_pool);
  113. ehci->qtd_pool = NULL;
  114. if (ehci->qh_pool) {
  115. dma_pool_destroy (ehci->qh_pool);
  116. ehci->qh_pool = NULL;
  117. }
  118. if (ehci->itd_pool)
  119. dma_pool_destroy (ehci->itd_pool);
  120. ehci->itd_pool = NULL;
  121. if (ehci->sitd_pool)
  122. dma_pool_destroy (ehci->sitd_pool);
  123. ehci->sitd_pool = NULL;
  124. if (ehci->periodic)
  125. dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
  126. ehci->periodic_size * sizeof (u32),
  127. ehci->periodic, ehci->periodic_dma);
  128. ehci->periodic = NULL;
  129. /* shadow periodic table */
  130. kfree(ehci->pshadow);
  131. ehci->pshadow = NULL;
  132. }
  133. /* remember to add cleanup code (above) if you add anything here */
  134. static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
  135. {
  136. int i;
  137. /* QTDs for control/bulk/intr transfers */
  138. ehci->qtd_pool = dma_pool_create ("ehci_qtd",
  139. ehci_to_hcd(ehci)->self.controller,
  140. sizeof (struct ehci_qtd),
  141. 32 /* byte alignment (for hw parts) */,
  142. 4096 /* can't cross 4K */);
  143. if (!ehci->qtd_pool) {
  144. goto fail;
  145. }
  146. /* QHs for control/bulk/intr transfers */
  147. ehci->qh_pool = dma_pool_create ("ehci_qh",
  148. ehci_to_hcd(ehci)->self.controller,
  149. sizeof(struct ehci_qh_hw),
  150. 32 /* byte alignment (for hw parts) */,
  151. 4096 /* can't cross 4K */);
  152. if (!ehci->qh_pool) {
  153. goto fail;
  154. }
  155. ehci->async = ehci_qh_alloc (ehci, flags);
  156. if (!ehci->async) {
  157. goto fail;
  158. }
  159. /* ITD for high speed ISO transfers */
  160. ehci->itd_pool = dma_pool_create ("ehci_itd",
  161. ehci_to_hcd(ehci)->self.controller,
  162. sizeof (struct ehci_itd),
  163. 32 /* byte alignment (for hw parts) */,
  164. 4096 /* can't cross 4K */);
  165. if (!ehci->itd_pool) {
  166. goto fail;
  167. }
  168. /* SITD for full/low speed split ISO transfers */
  169. ehci->sitd_pool = dma_pool_create ("ehci_sitd",
  170. ehci_to_hcd(ehci)->self.controller,
  171. sizeof (struct ehci_sitd),
  172. 32 /* byte alignment (for hw parts) */,
  173. 4096 /* can't cross 4K */);
  174. if (!ehci->sitd_pool) {
  175. goto fail;
  176. }
  177. /* Hardware periodic table */
  178. ehci->periodic = (__le32 *)
  179. dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
  180. ehci->periodic_size * sizeof(__le32),
  181. &ehci->periodic_dma, 0);
  182. if (ehci->periodic == NULL) {
  183. goto fail;
  184. }
  185. if (ehci->use_dummy_qh) {
  186. struct ehci_qh_hw *hw;
  187. ehci->dummy = ehci_qh_alloc(ehci, flags);
  188. if (!ehci->dummy)
  189. goto fail;
  190. hw = ehci->dummy->hw;
  191. hw->hw_next = EHCI_LIST_END(ehci);
  192. hw->hw_qtd_next = EHCI_LIST_END(ehci);
  193. hw->hw_alt_next = EHCI_LIST_END(ehci);
  194. hw->hw_token &= ~QTD_STS_ACTIVE;
  195. ehci->dummy->hw = hw;
  196. for (i = 0; i < ehci->periodic_size; i++)
  197. ehci->periodic[i] = ehci->dummy->qh_dma;
  198. } else {
  199. for (i = 0; i < ehci->periodic_size; i++)
  200. ehci->periodic[i] = EHCI_LIST_END(ehci);
  201. }
  202. /* software shadow of hardware table */
  203. ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
  204. if (ehci->pshadow != NULL)
  205. return 0;
  206. fail:
  207. ehci_dbg (ehci, "couldn't init memory\n");
  208. ehci_mem_cleanup (ehci);
  209. return -ENOMEM;
  210. }