s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #define pr_fmt(fmt) "s3c2410_udc: " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/delay.h>
  18. #include <linux/ioport.h>
  19. #include <linux/sched.h>
  20. #include <linux/slab.h>
  21. #include <linux/errno.h>
  22. #include <linux/init.h>
  23. #include <linux/timer.h>
  24. #include <linux/list.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/gpio.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/io.h>
  31. #include <linux/debugfs.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/usb.h>
  34. #include <linux/usb/gadget.h>
  35. #include <asm/byteorder.h>
  36. #include <asm/irq.h>
  37. #include <asm/unaligned.h>
  38. #include <mach/irqs.h>
  39. #include <mach/hardware.h>
  40. #include <plat/regs-udc.h>
  41. #include <linux/platform_data/usb-s3c2410_udc.h>
  42. #include "s3c2410_udc.h"
  43. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  44. #define DRIVER_VERSION "29 Apr 2007"
  45. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  46. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  47. static const char gadget_name[] = "s3c2410_udc";
  48. static const char driver_desc[] = DRIVER_DESC;
  49. static struct s3c2410_udc *the_controller;
  50. static struct clk *udc_clock;
  51. static struct clk *usb_bus_clock;
  52. static void __iomem *base_addr;
  53. static u64 rsrc_start;
  54. static u64 rsrc_len;
  55. static struct dentry *s3c2410_udc_debugfs_root;
  56. static inline u32 udc_read(u32 reg)
  57. {
  58. return readb(base_addr + reg);
  59. }
  60. static inline void udc_write(u32 value, u32 reg)
  61. {
  62. writeb(value, base_addr + reg);
  63. }
  64. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  65. {
  66. writeb(value, base + reg);
  67. }
  68. static struct s3c2410_udc_mach_info *udc_info;
  69. /*************************** DEBUG FUNCTION ***************************/
  70. #define DEBUG_NORMAL 1
  71. #define DEBUG_VERBOSE 2
  72. #ifdef CONFIG_USB_S3C2410_DEBUG
  73. #define USB_S3C2410_DEBUG_LEVEL 0
  74. static uint32_t s3c2410_ticks = 0;
  75. static int dprintk(int level, const char *fmt, ...)
  76. {
  77. static char printk_buf[1024];
  78. static long prevticks;
  79. static int invocation;
  80. va_list args;
  81. int len;
  82. if (level > USB_S3C2410_DEBUG_LEVEL)
  83. return 0;
  84. if (s3c2410_ticks != prevticks) {
  85. prevticks = s3c2410_ticks;
  86. invocation = 0;
  87. }
  88. len = scnprintf(printk_buf,
  89. sizeof(printk_buf), "%1lu.%02d USB: ",
  90. prevticks, invocation++);
  91. va_start(args, fmt);
  92. len = vscnprintf(printk_buf+len,
  93. sizeof(printk_buf)-len, fmt, args);
  94. va_end(args);
  95. return pr_debug("%s", printk_buf);
  96. }
  97. #else
  98. static int dprintk(int level, const char *fmt, ...)
  99. {
  100. return 0;
  101. }
  102. #endif
  103. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  104. {
  105. u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
  106. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  107. u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
  108. u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
  109. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  110. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  111. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  112. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  113. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  114. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  115. udc_write(0, S3C2410_UDC_INDEX_REG);
  116. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  117. udc_write(1, S3C2410_UDC_INDEX_REG);
  118. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  119. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  120. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  121. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  122. udc_write(2, S3C2410_UDC_INDEX_REG);
  123. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  124. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  125. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  126. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  127. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  128. "PWR_REG : 0x%04X\n"
  129. "EP_INT_REG : 0x%04X\n"
  130. "USB_INT_REG : 0x%04X\n"
  131. "EP_INT_EN_REG : 0x%04X\n"
  132. "USB_INT_EN_REG : 0x%04X\n"
  133. "EP0_CSR : 0x%04X\n"
  134. "EP1_I_CSR1 : 0x%04X\n"
  135. "EP1_I_CSR2 : 0x%04X\n"
  136. "EP1_O_CSR1 : 0x%04X\n"
  137. "EP1_O_CSR2 : 0x%04X\n"
  138. "EP2_I_CSR1 : 0x%04X\n"
  139. "EP2_I_CSR2 : 0x%04X\n"
  140. "EP2_O_CSR1 : 0x%04X\n"
  141. "EP2_O_CSR2 : 0x%04X\n",
  142. addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
  143. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  144. ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
  145. ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
  146. );
  147. return 0;
  148. }
  149. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  150. struct file *file)
  151. {
  152. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  153. }
  154. static const struct file_operations s3c2410_udc_debugfs_fops = {
  155. .open = s3c2410_udc_debugfs_fops_open,
  156. .read = seq_read,
  157. .llseek = seq_lseek,
  158. .release = single_release,
  159. .owner = THIS_MODULE,
  160. };
  161. /* io macros */
  162. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  163. {
  164. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  165. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  166. S3C2410_UDC_EP0_CSR_REG);
  167. }
  168. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  169. {
  170. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  171. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  172. }
  173. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  174. {
  175. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  176. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  177. }
  178. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  179. {
  180. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  181. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  182. }
  183. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  184. {
  185. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  186. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  187. }
  188. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  189. {
  190. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  191. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  192. }
  193. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  194. {
  195. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  196. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  197. | S3C2410_UDC_EP0_CSR_DE),
  198. S3C2410_UDC_EP0_CSR_REG);
  199. }
  200. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  201. {
  202. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  203. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  204. | S3C2410_UDC_EP0_CSR_SSE),
  205. S3C2410_UDC_EP0_CSR_REG);
  206. }
  207. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  208. {
  209. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  210. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  211. | S3C2410_UDC_EP0_CSR_DE),
  212. S3C2410_UDC_EP0_CSR_REG);
  213. }
  214. /*------------------------- I/O ----------------------------------*/
  215. /*
  216. * s3c2410_udc_done
  217. */
  218. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  219. struct s3c2410_request *req, int status)
  220. {
  221. unsigned halted = ep->halted;
  222. list_del_init(&req->queue);
  223. if (likely(req->req.status == -EINPROGRESS))
  224. req->req.status = status;
  225. else
  226. status = req->req.status;
  227. ep->halted = 1;
  228. req->req.complete(&ep->ep, &req->req);
  229. ep->halted = halted;
  230. }
  231. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  232. struct s3c2410_ep *ep, int status)
  233. {
  234. /* Sanity check */
  235. if (&ep->queue == NULL)
  236. return;
  237. while (!list_empty(&ep->queue)) {
  238. struct s3c2410_request *req;
  239. req = list_entry(ep->queue.next, struct s3c2410_request,
  240. queue);
  241. s3c2410_udc_done(ep, req, status);
  242. }
  243. }
  244. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  245. {
  246. unsigned i;
  247. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  248. * fifos, and pending transactions mustn't be continued in any case.
  249. */
  250. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  251. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  252. }
  253. static inline int s3c2410_udc_fifo_count_out(void)
  254. {
  255. int tmp;
  256. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  257. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  258. return tmp;
  259. }
  260. /*
  261. * s3c2410_udc_write_packet
  262. */
  263. static inline int s3c2410_udc_write_packet(int fifo,
  264. struct s3c2410_request *req,
  265. unsigned max)
  266. {
  267. unsigned len = min(req->req.length - req->req.actual, max);
  268. u8 *buf = req->req.buf + req->req.actual;
  269. prefetch(buf);
  270. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  271. req->req.actual, req->req.length, len, req->req.actual + len);
  272. req->req.actual += len;
  273. udelay(5);
  274. writesb(base_addr + fifo, buf, len);
  275. return len;
  276. }
  277. /*
  278. * s3c2410_udc_write_fifo
  279. *
  280. * return: 0 = still running, 1 = completed, negative = errno
  281. */
  282. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  283. struct s3c2410_request *req)
  284. {
  285. unsigned count;
  286. int is_last;
  287. u32 idx;
  288. int fifo_reg;
  289. u32 ep_csr;
  290. idx = ep->bEndpointAddress & 0x7F;
  291. switch (idx) {
  292. default:
  293. idx = 0;
  294. case 0:
  295. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  296. break;
  297. case 1:
  298. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  299. break;
  300. case 2:
  301. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  302. break;
  303. case 3:
  304. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  305. break;
  306. case 4:
  307. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  308. break;
  309. }
  310. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  311. /* last packet is often short (sometimes a zlp) */
  312. if (count != ep->ep.maxpacket)
  313. is_last = 1;
  314. else if (req->req.length != req->req.actual || req->req.zero)
  315. is_last = 0;
  316. else
  317. is_last = 2;
  318. /* Only ep0 debug messages are interesting */
  319. if (idx == 0)
  320. dprintk(DEBUG_NORMAL,
  321. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  322. idx, count, req->req.actual, req->req.length,
  323. is_last, req->req.zero);
  324. if (is_last) {
  325. /* The order is important. It prevents sending 2 packets
  326. * at the same time */
  327. if (idx == 0) {
  328. /* Reset signal => no need to say 'data sent' */
  329. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  330. & S3C2410_UDC_USBINT_RESET))
  331. s3c2410_udc_set_ep0_de_in(base_addr);
  332. ep->dev->ep0state = EP0_IDLE;
  333. } else {
  334. udc_write(idx, S3C2410_UDC_INDEX_REG);
  335. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  336. udc_write(idx, S3C2410_UDC_INDEX_REG);
  337. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  338. S3C2410_UDC_IN_CSR1_REG);
  339. }
  340. s3c2410_udc_done(ep, req, 0);
  341. is_last = 1;
  342. } else {
  343. if (idx == 0) {
  344. /* Reset signal => no need to say 'data sent' */
  345. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  346. & S3C2410_UDC_USBINT_RESET))
  347. s3c2410_udc_set_ep0_ipr(base_addr);
  348. } else {
  349. udc_write(idx, S3C2410_UDC_INDEX_REG);
  350. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  351. udc_write(idx, S3C2410_UDC_INDEX_REG);
  352. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  353. S3C2410_UDC_IN_CSR1_REG);
  354. }
  355. }
  356. return is_last;
  357. }
  358. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  359. struct s3c2410_request *req, unsigned avail)
  360. {
  361. unsigned len;
  362. len = min(req->req.length - req->req.actual, avail);
  363. req->req.actual += len;
  364. readsb(fifo + base_addr, buf, len);
  365. return len;
  366. }
  367. /*
  368. * return: 0 = still running, 1 = queue empty, negative = errno
  369. */
  370. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  371. struct s3c2410_request *req)
  372. {
  373. u8 *buf;
  374. u32 ep_csr;
  375. unsigned bufferspace;
  376. int is_last = 1;
  377. unsigned avail;
  378. int fifo_count = 0;
  379. u32 idx;
  380. int fifo_reg;
  381. idx = ep->bEndpointAddress & 0x7F;
  382. switch (idx) {
  383. default:
  384. idx = 0;
  385. case 0:
  386. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  387. break;
  388. case 1:
  389. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  390. break;
  391. case 2:
  392. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  393. break;
  394. case 3:
  395. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  396. break;
  397. case 4:
  398. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  399. break;
  400. }
  401. if (!req->req.length)
  402. return 1;
  403. buf = req->req.buf + req->req.actual;
  404. bufferspace = req->req.length - req->req.actual;
  405. if (!bufferspace) {
  406. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  407. return -1;
  408. }
  409. udc_write(idx, S3C2410_UDC_INDEX_REG);
  410. fifo_count = s3c2410_udc_fifo_count_out();
  411. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  412. if (fifo_count > ep->ep.maxpacket)
  413. avail = ep->ep.maxpacket;
  414. else
  415. avail = fifo_count;
  416. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  417. /* checking this with ep0 is not accurate as we already
  418. * read a control request
  419. **/
  420. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  421. is_last = 1;
  422. /* overflowed this request? flush extra data */
  423. if (fifo_count != avail)
  424. req->req.status = -EOVERFLOW;
  425. } else {
  426. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  427. }
  428. udc_write(idx, S3C2410_UDC_INDEX_REG);
  429. fifo_count = s3c2410_udc_fifo_count_out();
  430. /* Only ep0 debug messages are interesting */
  431. if (idx == 0)
  432. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  433. __func__, fifo_count, is_last);
  434. if (is_last) {
  435. if (idx == 0) {
  436. s3c2410_udc_set_ep0_de_out(base_addr);
  437. ep->dev->ep0state = EP0_IDLE;
  438. } else {
  439. udc_write(idx, S3C2410_UDC_INDEX_REG);
  440. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  441. udc_write(idx, S3C2410_UDC_INDEX_REG);
  442. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  443. S3C2410_UDC_OUT_CSR1_REG);
  444. }
  445. s3c2410_udc_done(ep, req, 0);
  446. } else {
  447. if (idx == 0) {
  448. s3c2410_udc_clear_ep0_opr(base_addr);
  449. } else {
  450. udc_write(idx, S3C2410_UDC_INDEX_REG);
  451. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  452. udc_write(idx, S3C2410_UDC_INDEX_REG);
  453. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  454. S3C2410_UDC_OUT_CSR1_REG);
  455. }
  456. }
  457. return is_last;
  458. }
  459. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  460. {
  461. unsigned char *outbuf = (unsigned char *)crq;
  462. int bytes_read = 0;
  463. udc_write(0, S3C2410_UDC_INDEX_REG);
  464. bytes_read = s3c2410_udc_fifo_count_out();
  465. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  466. if (bytes_read > sizeof(struct usb_ctrlrequest))
  467. bytes_read = sizeof(struct usb_ctrlrequest);
  468. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  469. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  470. bytes_read, crq->bRequest, crq->bRequestType,
  471. crq->wValue, crq->wIndex, crq->wLength);
  472. return bytes_read;
  473. }
  474. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  475. struct usb_ctrlrequest *crq)
  476. {
  477. u16 status = 0;
  478. u8 ep_num = crq->wIndex & 0x7F;
  479. u8 is_in = crq->wIndex & USB_DIR_IN;
  480. switch (crq->bRequestType & USB_RECIP_MASK) {
  481. case USB_RECIP_INTERFACE:
  482. break;
  483. case USB_RECIP_DEVICE:
  484. status = dev->devstatus;
  485. break;
  486. case USB_RECIP_ENDPOINT:
  487. if (ep_num > 4 || crq->wLength > 2)
  488. return 1;
  489. if (ep_num == 0) {
  490. udc_write(0, S3C2410_UDC_INDEX_REG);
  491. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  492. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  493. } else {
  494. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  495. if (is_in) {
  496. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  497. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  498. } else {
  499. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  500. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  501. }
  502. }
  503. status = status ? 1 : 0;
  504. break;
  505. default:
  506. return 1;
  507. }
  508. /* Seems to be needed to get it working. ouch :( */
  509. udelay(5);
  510. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  511. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  512. s3c2410_udc_set_ep0_de_in(base_addr);
  513. return 0;
  514. }
  515. /*------------------------- usb state machine -------------------------------*/
  516. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  517. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  518. struct s3c2410_ep *ep,
  519. struct usb_ctrlrequest *crq,
  520. u32 ep0csr)
  521. {
  522. int len, ret, tmp;
  523. /* start control request? */
  524. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  525. return;
  526. s3c2410_udc_nuke(dev, ep, -EPROTO);
  527. len = s3c2410_udc_read_fifo_crq(crq);
  528. if (len != sizeof(*crq)) {
  529. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  530. " wanted %d bytes got %d. Stalling out...\n",
  531. sizeof(*crq), len);
  532. s3c2410_udc_set_ep0_ss(base_addr);
  533. return;
  534. }
  535. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  536. crq->bRequest, crq->bRequestType, crq->wLength);
  537. /* cope with automagic for some standard requests. */
  538. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  539. == USB_TYPE_STANDARD;
  540. dev->req_config = 0;
  541. dev->req_pending = 1;
  542. switch (crq->bRequest) {
  543. case USB_REQ_SET_CONFIGURATION:
  544. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
  545. if (crq->bRequestType == USB_RECIP_DEVICE) {
  546. dev->req_config = 1;
  547. s3c2410_udc_set_ep0_de_out(base_addr);
  548. }
  549. break;
  550. case USB_REQ_SET_INTERFACE:
  551. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
  552. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  553. dev->req_config = 1;
  554. s3c2410_udc_set_ep0_de_out(base_addr);
  555. }
  556. break;
  557. case USB_REQ_SET_ADDRESS:
  558. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
  559. if (crq->bRequestType == USB_RECIP_DEVICE) {
  560. tmp = crq->wValue & 0x7F;
  561. dev->address = tmp;
  562. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  563. S3C2410_UDC_FUNC_ADDR_REG);
  564. s3c2410_udc_set_ep0_de_out(base_addr);
  565. return;
  566. }
  567. break;
  568. case USB_REQ_GET_STATUS:
  569. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
  570. s3c2410_udc_clear_ep0_opr(base_addr);
  571. if (dev->req_std) {
  572. if (!s3c2410_udc_get_status(dev, crq))
  573. return;
  574. }
  575. break;
  576. case USB_REQ_CLEAR_FEATURE:
  577. s3c2410_udc_clear_ep0_opr(base_addr);
  578. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  579. break;
  580. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  581. break;
  582. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  583. s3c2410_udc_set_ep0_de_out(base_addr);
  584. return;
  585. case USB_REQ_SET_FEATURE:
  586. s3c2410_udc_clear_ep0_opr(base_addr);
  587. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  588. break;
  589. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  590. break;
  591. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  592. s3c2410_udc_set_ep0_de_out(base_addr);
  593. return;
  594. default:
  595. s3c2410_udc_clear_ep0_opr(base_addr);
  596. break;
  597. }
  598. if (crq->bRequestType & USB_DIR_IN)
  599. dev->ep0state = EP0_IN_DATA_PHASE;
  600. else
  601. dev->ep0state = EP0_OUT_DATA_PHASE;
  602. if (!dev->driver)
  603. return;
  604. /* deliver the request to the gadget driver */
  605. ret = dev->driver->setup(&dev->gadget, crq);
  606. if (ret < 0) {
  607. if (dev->req_config) {
  608. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  609. crq->bRequest, ret);
  610. return;
  611. }
  612. if (ret == -EOPNOTSUPP)
  613. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  614. else
  615. dprintk(DEBUG_NORMAL,
  616. "dev->driver->setup failed. (%d)\n", ret);
  617. udelay(5);
  618. s3c2410_udc_set_ep0_ss(base_addr);
  619. s3c2410_udc_set_ep0_de_out(base_addr);
  620. dev->ep0state = EP0_IDLE;
  621. /* deferred i/o == no response yet */
  622. } else if (dev->req_pending) {
  623. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  624. dev->req_pending = 0;
  625. }
  626. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  627. }
  628. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  629. {
  630. u32 ep0csr;
  631. struct s3c2410_ep *ep = &dev->ep[0];
  632. struct s3c2410_request *req;
  633. struct usb_ctrlrequest crq;
  634. if (list_empty(&ep->queue))
  635. req = NULL;
  636. else
  637. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  638. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  639. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  640. udc_write(0, S3C2410_UDC_INDEX_REG);
  641. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  642. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  643. ep0csr, ep0states[dev->ep0state]);
  644. /* clear stall status */
  645. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  646. s3c2410_udc_nuke(dev, ep, -EPIPE);
  647. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  648. s3c2410_udc_clear_ep0_sst(base_addr);
  649. dev->ep0state = EP0_IDLE;
  650. return;
  651. }
  652. /* clear setup end */
  653. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  654. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  655. s3c2410_udc_nuke(dev, ep, 0);
  656. s3c2410_udc_clear_ep0_se(base_addr);
  657. dev->ep0state = EP0_IDLE;
  658. }
  659. switch (dev->ep0state) {
  660. case EP0_IDLE:
  661. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  662. break;
  663. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  664. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  665. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
  666. s3c2410_udc_write_fifo(ep, req);
  667. break;
  668. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  669. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  670. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
  671. s3c2410_udc_read_fifo(ep, req);
  672. break;
  673. case EP0_END_XFER:
  674. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  675. dev->ep0state = EP0_IDLE;
  676. break;
  677. case EP0_STALL:
  678. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  679. dev->ep0state = EP0_IDLE;
  680. break;
  681. }
  682. }
  683. /*
  684. * handle_ep - Manage I/O endpoints
  685. */
  686. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  687. {
  688. struct s3c2410_request *req;
  689. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  690. u32 ep_csr1;
  691. u32 idx;
  692. if (likely(!list_empty(&ep->queue)))
  693. req = list_entry(ep->queue.next,
  694. struct s3c2410_request, queue);
  695. else
  696. req = NULL;
  697. idx = ep->bEndpointAddress & 0x7F;
  698. if (is_in) {
  699. udc_write(idx, S3C2410_UDC_INDEX_REG);
  700. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  701. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  702. idx, ep_csr1, req ? 1 : 0);
  703. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  704. dprintk(DEBUG_VERBOSE, "st\n");
  705. udc_write(idx, S3C2410_UDC_INDEX_REG);
  706. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  707. S3C2410_UDC_IN_CSR1_REG);
  708. return;
  709. }
  710. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
  711. s3c2410_udc_write_fifo(ep, req);
  712. } else {
  713. udc_write(idx, S3C2410_UDC_INDEX_REG);
  714. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  715. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  716. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  717. udc_write(idx, S3C2410_UDC_INDEX_REG);
  718. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  719. S3C2410_UDC_OUT_CSR1_REG);
  720. return;
  721. }
  722. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
  723. s3c2410_udc_read_fifo(ep, req);
  724. }
  725. }
  726. #include <mach/regs-irq.h>
  727. /*
  728. * s3c2410_udc_irq - interrupt handler
  729. */
  730. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  731. {
  732. struct s3c2410_udc *dev = _dev;
  733. int usb_status;
  734. int usbd_status;
  735. int pwr_reg;
  736. int ep0csr;
  737. int i;
  738. u32 idx, idx2;
  739. unsigned long flags;
  740. spin_lock_irqsave(&dev->lock, flags);
  741. /* Driver connected ? */
  742. if (!dev->driver) {
  743. /* Clear interrupts */
  744. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  745. S3C2410_UDC_USB_INT_REG);
  746. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  747. S3C2410_UDC_EP_INT_REG);
  748. }
  749. /* Save index */
  750. idx = udc_read(S3C2410_UDC_INDEX_REG);
  751. /* Read status registers */
  752. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  753. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  754. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  755. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  756. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  757. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  758. usb_status, usbd_status, pwr_reg, ep0csr);
  759. /*
  760. * Now, handle interrupts. There's two types :
  761. * - Reset, Resume, Suspend coming -> usb_int_reg
  762. * - EP -> ep_int_reg
  763. */
  764. /* RESET */
  765. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  766. /* two kind of reset :
  767. * - reset start -> pwr reg = 8
  768. * - reset end -> pwr reg = 0
  769. **/
  770. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  771. ep0csr, pwr_reg);
  772. dev->gadget.speed = USB_SPEED_UNKNOWN;
  773. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  774. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  775. S3C2410_UDC_MAXP_REG);
  776. dev->address = 0;
  777. dev->ep0state = EP0_IDLE;
  778. dev->gadget.speed = USB_SPEED_FULL;
  779. /* clear interrupt */
  780. udc_write(S3C2410_UDC_USBINT_RESET,
  781. S3C2410_UDC_USB_INT_REG);
  782. udc_write(idx, S3C2410_UDC_INDEX_REG);
  783. spin_unlock_irqrestore(&dev->lock, flags);
  784. return IRQ_HANDLED;
  785. }
  786. /* RESUME */
  787. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  788. dprintk(DEBUG_NORMAL, "USB resume\n");
  789. /* clear interrupt */
  790. udc_write(S3C2410_UDC_USBINT_RESUME,
  791. S3C2410_UDC_USB_INT_REG);
  792. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  793. && dev->driver
  794. && dev->driver->resume)
  795. dev->driver->resume(&dev->gadget);
  796. }
  797. /* SUSPEND */
  798. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  799. dprintk(DEBUG_NORMAL, "USB suspend\n");
  800. /* clear interrupt */
  801. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  802. S3C2410_UDC_USB_INT_REG);
  803. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  804. && dev->driver
  805. && dev->driver->suspend)
  806. dev->driver->suspend(&dev->gadget);
  807. dev->ep0state = EP0_IDLE;
  808. }
  809. /* EP */
  810. /* control traffic */
  811. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  812. * generate an interrupt
  813. */
  814. if (usbd_status & S3C2410_UDC_INT_EP0) {
  815. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  816. /* Clear the interrupt bit by setting it to 1 */
  817. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  818. s3c2410_udc_handle_ep0(dev);
  819. }
  820. /* endpoint data transfers */
  821. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  822. u32 tmp = 1 << i;
  823. if (usbd_status & tmp) {
  824. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  825. /* Clear the interrupt bit by setting it to 1 */
  826. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  827. s3c2410_udc_handle_ep(&dev->ep[i]);
  828. }
  829. }
  830. /* what else causes this interrupt? a receive! who is it? */
  831. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  832. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  833. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  834. udc_write(i, S3C2410_UDC_INDEX_REG);
  835. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  836. s3c2410_udc_handle_ep(&dev->ep[i]);
  837. /* restore index */
  838. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  839. }
  840. }
  841. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  842. /* Restore old index */
  843. udc_write(idx, S3C2410_UDC_INDEX_REG);
  844. spin_unlock_irqrestore(&dev->lock, flags);
  845. return IRQ_HANDLED;
  846. }
  847. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  848. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  849. {
  850. return container_of(ep, struct s3c2410_ep, ep);
  851. }
  852. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  853. {
  854. return container_of(gadget, struct s3c2410_udc, gadget);
  855. }
  856. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  857. {
  858. return container_of(req, struct s3c2410_request, req);
  859. }
  860. /*
  861. * s3c2410_udc_ep_enable
  862. */
  863. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  864. const struct usb_endpoint_descriptor *desc)
  865. {
  866. struct s3c2410_udc *dev;
  867. struct s3c2410_ep *ep;
  868. u32 max, tmp;
  869. unsigned long flags;
  870. u32 csr1, csr2;
  871. u32 int_en_reg;
  872. ep = to_s3c2410_ep(_ep);
  873. if (!_ep || !desc
  874. || _ep->name == ep0name
  875. || desc->bDescriptorType != USB_DT_ENDPOINT)
  876. return -EINVAL;
  877. dev = ep->dev;
  878. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  879. return -ESHUTDOWN;
  880. max = usb_endpoint_maxp(desc) & 0x1fff;
  881. local_irq_save(flags);
  882. _ep->maxpacket = max & 0x7ff;
  883. ep->ep.desc = desc;
  884. ep->halted = 0;
  885. ep->bEndpointAddress = desc->bEndpointAddress;
  886. /* set max packet */
  887. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  888. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  889. /* set type, direction, address; reset fifo counters */
  890. if (desc->bEndpointAddress & USB_DIR_IN) {
  891. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  892. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  893. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  894. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  895. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  896. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  897. } else {
  898. /* don't flush in fifo or it will cause endpoint interrupt */
  899. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  900. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  901. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  902. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  903. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  904. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  905. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  906. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  907. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  908. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  909. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  910. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  911. }
  912. /* enable irqs */
  913. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  914. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  915. /* print some debug message */
  916. tmp = desc->bEndpointAddress;
  917. dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  918. _ep->name, ep->num, tmp,
  919. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  920. local_irq_restore(flags);
  921. s3c2410_udc_set_halt(_ep, 0);
  922. return 0;
  923. }
  924. /*
  925. * s3c2410_udc_ep_disable
  926. */
  927. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  928. {
  929. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  930. unsigned long flags;
  931. u32 int_en_reg;
  932. if (!_ep || !ep->ep.desc) {
  933. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  934. _ep ? ep->ep.name : NULL);
  935. return -EINVAL;
  936. }
  937. local_irq_save(flags);
  938. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  939. ep->ep.desc = NULL;
  940. ep->halted = 1;
  941. s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
  942. /* disable irqs */
  943. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  944. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  945. local_irq_restore(flags);
  946. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  947. return 0;
  948. }
  949. /*
  950. * s3c2410_udc_alloc_request
  951. */
  952. static struct usb_request *
  953. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  954. {
  955. struct s3c2410_request *req;
  956. dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
  957. if (!_ep)
  958. return NULL;
  959. req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
  960. if (!req)
  961. return NULL;
  962. INIT_LIST_HEAD(&req->queue);
  963. return &req->req;
  964. }
  965. /*
  966. * s3c2410_udc_free_request
  967. */
  968. static void
  969. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  970. {
  971. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  972. struct s3c2410_request *req = to_s3c2410_req(_req);
  973. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  974. if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
  975. return;
  976. WARN_ON(!list_empty(&req->queue));
  977. kfree(req);
  978. }
  979. /*
  980. * s3c2410_udc_queue
  981. */
  982. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  983. gfp_t gfp_flags)
  984. {
  985. struct s3c2410_request *req = to_s3c2410_req(_req);
  986. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  987. struct s3c2410_udc *dev;
  988. u32 ep_csr = 0;
  989. int fifo_count = 0;
  990. unsigned long flags;
  991. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  992. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  993. return -EINVAL;
  994. }
  995. dev = ep->dev;
  996. if (unlikely(!dev->driver
  997. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  998. return -ESHUTDOWN;
  999. }
  1000. local_irq_save(flags);
  1001. if (unlikely(!_req || !_req->complete
  1002. || !_req->buf || !list_empty(&req->queue))) {
  1003. if (!_req)
  1004. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1005. else {
  1006. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1007. __func__, !_req->complete, !_req->buf,
  1008. !list_empty(&req->queue));
  1009. }
  1010. local_irq_restore(flags);
  1011. return -EINVAL;
  1012. }
  1013. _req->status = -EINPROGRESS;
  1014. _req->actual = 0;
  1015. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1016. __func__, ep->bEndpointAddress, _req->length);
  1017. if (ep->bEndpointAddress) {
  1018. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1019. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1020. ? S3C2410_UDC_IN_CSR1_REG
  1021. : S3C2410_UDC_OUT_CSR1_REG);
  1022. fifo_count = s3c2410_udc_fifo_count_out();
  1023. } else {
  1024. udc_write(0, S3C2410_UDC_INDEX_REG);
  1025. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1026. fifo_count = s3c2410_udc_fifo_count_out();
  1027. }
  1028. /* kickstart this i/o queue? */
  1029. if (list_empty(&ep->queue) && !ep->halted) {
  1030. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1031. switch (dev->ep0state) {
  1032. case EP0_IN_DATA_PHASE:
  1033. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1034. && s3c2410_udc_write_fifo(ep,
  1035. req)) {
  1036. dev->ep0state = EP0_IDLE;
  1037. req = NULL;
  1038. }
  1039. break;
  1040. case EP0_OUT_DATA_PHASE:
  1041. if ((!_req->length)
  1042. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1043. && s3c2410_udc_read_fifo(ep,
  1044. req))) {
  1045. dev->ep0state = EP0_IDLE;
  1046. req = NULL;
  1047. }
  1048. break;
  1049. default:
  1050. local_irq_restore(flags);
  1051. return -EL2HLT;
  1052. }
  1053. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1054. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1055. && s3c2410_udc_write_fifo(ep, req)) {
  1056. req = NULL;
  1057. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1058. && fifo_count
  1059. && s3c2410_udc_read_fifo(ep, req)) {
  1060. req = NULL;
  1061. }
  1062. }
  1063. /* pio or dma irq handler advances the queue. */
  1064. if (likely(req))
  1065. list_add_tail(&req->queue, &ep->queue);
  1066. local_irq_restore(flags);
  1067. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1068. return 0;
  1069. }
  1070. /*
  1071. * s3c2410_udc_dequeue
  1072. */
  1073. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1074. {
  1075. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1076. struct s3c2410_udc *udc;
  1077. int retval = -EINVAL;
  1078. unsigned long flags;
  1079. struct s3c2410_request *req = NULL;
  1080. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1081. if (!the_controller->driver)
  1082. return -ESHUTDOWN;
  1083. if (!_ep || !_req)
  1084. return retval;
  1085. udc = to_s3c2410_udc(ep->gadget);
  1086. local_irq_save(flags);
  1087. list_for_each_entry(req, &ep->queue, queue) {
  1088. if (&req->req == _req) {
  1089. list_del_init(&req->queue);
  1090. _req->status = -ECONNRESET;
  1091. retval = 0;
  1092. break;
  1093. }
  1094. }
  1095. if (retval == 0) {
  1096. dprintk(DEBUG_VERBOSE,
  1097. "dequeued req %p from %s, len %d buf %p\n",
  1098. req, _ep->name, _req->length, _req->buf);
  1099. s3c2410_udc_done(ep, req, -ECONNRESET);
  1100. }
  1101. local_irq_restore(flags);
  1102. return retval;
  1103. }
  1104. /*
  1105. * s3c2410_udc_set_halt
  1106. */
  1107. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1108. {
  1109. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1110. u32 ep_csr = 0;
  1111. unsigned long flags;
  1112. u32 idx;
  1113. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  1114. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1115. return -EINVAL;
  1116. }
  1117. local_irq_save(flags);
  1118. idx = ep->bEndpointAddress & 0x7F;
  1119. if (idx == 0) {
  1120. s3c2410_udc_set_ep0_ss(base_addr);
  1121. s3c2410_udc_set_ep0_de_out(base_addr);
  1122. } else {
  1123. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1124. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1125. ? S3C2410_UDC_IN_CSR1_REG
  1126. : S3C2410_UDC_OUT_CSR1_REG);
  1127. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1128. if (value)
  1129. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1130. S3C2410_UDC_IN_CSR1_REG);
  1131. else {
  1132. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1133. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1134. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1135. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1136. }
  1137. } else {
  1138. if (value)
  1139. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1140. S3C2410_UDC_OUT_CSR1_REG);
  1141. else {
  1142. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1143. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1144. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1145. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1146. }
  1147. }
  1148. }
  1149. ep->halted = value ? 1 : 0;
  1150. local_irq_restore(flags);
  1151. return 0;
  1152. }
  1153. static const struct usb_ep_ops s3c2410_ep_ops = {
  1154. .enable = s3c2410_udc_ep_enable,
  1155. .disable = s3c2410_udc_ep_disable,
  1156. .alloc_request = s3c2410_udc_alloc_request,
  1157. .free_request = s3c2410_udc_free_request,
  1158. .queue = s3c2410_udc_queue,
  1159. .dequeue = s3c2410_udc_dequeue,
  1160. .set_halt = s3c2410_udc_set_halt,
  1161. };
  1162. /*------------------------- usb_gadget_ops ----------------------------------*/
  1163. /*
  1164. * s3c2410_udc_get_frame
  1165. */
  1166. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1167. {
  1168. int tmp;
  1169. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1170. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1171. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1172. return tmp;
  1173. }
  1174. /*
  1175. * s3c2410_udc_wakeup
  1176. */
  1177. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1178. {
  1179. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1180. return 0;
  1181. }
  1182. /*
  1183. * s3c2410_udc_set_selfpowered
  1184. */
  1185. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1186. {
  1187. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1188. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1189. if (value)
  1190. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1191. else
  1192. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1193. return 0;
  1194. }
  1195. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1196. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1197. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1198. {
  1199. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1200. if (udc_info && (udc_info->udc_command ||
  1201. gpio_is_valid(udc_info->pullup_pin))) {
  1202. if (is_on)
  1203. s3c2410_udc_enable(udc);
  1204. else {
  1205. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1206. if (udc->driver && udc->driver->disconnect)
  1207. udc->driver->disconnect(&udc->gadget);
  1208. }
  1209. s3c2410_udc_disable(udc);
  1210. }
  1211. } else {
  1212. return -EOPNOTSUPP;
  1213. }
  1214. return 0;
  1215. }
  1216. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1217. {
  1218. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1219. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1220. udc->vbus = (is_active != 0);
  1221. s3c2410_udc_set_pullup(udc, is_active);
  1222. return 0;
  1223. }
  1224. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1225. {
  1226. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1227. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1228. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1229. return 0;
  1230. }
  1231. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1232. {
  1233. struct s3c2410_udc *dev = _dev;
  1234. unsigned int value;
  1235. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1236. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1237. if (udc_info->vbus_pin_inverted)
  1238. value = !value;
  1239. if (value != dev->vbus)
  1240. s3c2410_udc_vbus_session(&dev->gadget, value);
  1241. return IRQ_HANDLED;
  1242. }
  1243. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1244. {
  1245. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1246. if (udc_info && udc_info->vbus_draw) {
  1247. udc_info->vbus_draw(ma);
  1248. return 0;
  1249. }
  1250. return -ENOTSUPP;
  1251. }
  1252. static int s3c2410_udc_start(struct usb_gadget *g,
  1253. struct usb_gadget_driver *driver);
  1254. static int s3c2410_udc_stop(struct usb_gadget *g,
  1255. struct usb_gadget_driver *driver);
  1256. static const struct usb_gadget_ops s3c2410_ops = {
  1257. .get_frame = s3c2410_udc_get_frame,
  1258. .wakeup = s3c2410_udc_wakeup,
  1259. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1260. .pullup = s3c2410_udc_pullup,
  1261. .vbus_session = s3c2410_udc_vbus_session,
  1262. .vbus_draw = s3c2410_vbus_draw,
  1263. .udc_start = s3c2410_udc_start,
  1264. .udc_stop = s3c2410_udc_stop,
  1265. };
  1266. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1267. {
  1268. if (!udc_info)
  1269. return;
  1270. if (udc_info->udc_command) {
  1271. udc_info->udc_command(cmd);
  1272. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1273. int value;
  1274. switch (cmd) {
  1275. case S3C2410_UDC_P_ENABLE:
  1276. value = 1;
  1277. break;
  1278. case S3C2410_UDC_P_DISABLE:
  1279. value = 0;
  1280. break;
  1281. default:
  1282. return;
  1283. }
  1284. value ^= udc_info->pullup_pin_inverted;
  1285. gpio_set_value(udc_info->pullup_pin, value);
  1286. }
  1287. }
  1288. /*------------------------- gadget driver handling---------------------------*/
  1289. /*
  1290. * s3c2410_udc_disable
  1291. */
  1292. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1293. {
  1294. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1295. /* Disable all interrupts */
  1296. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1297. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1298. /* Clear the interrupt registers */
  1299. udc_write(S3C2410_UDC_USBINT_RESET
  1300. | S3C2410_UDC_USBINT_RESUME
  1301. | S3C2410_UDC_USBINT_SUSPEND,
  1302. S3C2410_UDC_USB_INT_REG);
  1303. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1304. /* Good bye, cruel world */
  1305. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1306. /* Set speed to unknown */
  1307. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1308. }
  1309. /*
  1310. * s3c2410_udc_reinit
  1311. */
  1312. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1313. {
  1314. u32 i;
  1315. /* device/ep0 records init */
  1316. INIT_LIST_HEAD(&dev->gadget.ep_list);
  1317. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  1318. dev->ep0state = EP0_IDLE;
  1319. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1320. struct s3c2410_ep *ep = &dev->ep[i];
  1321. if (i != 0)
  1322. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1323. ep->dev = dev;
  1324. ep->ep.desc = NULL;
  1325. ep->halted = 0;
  1326. INIT_LIST_HEAD(&ep->queue);
  1327. }
  1328. }
  1329. /*
  1330. * s3c2410_udc_enable
  1331. */
  1332. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1333. {
  1334. int i;
  1335. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1336. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1337. dev->gadget.speed = USB_SPEED_FULL;
  1338. /* Set MAXP for all endpoints */
  1339. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1340. udc_write(i, S3C2410_UDC_INDEX_REG);
  1341. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1342. S3C2410_UDC_MAXP_REG);
  1343. }
  1344. /* Set default power state */
  1345. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1346. /* Enable reset and suspend interrupt interrupts */
  1347. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1348. S3C2410_UDC_USB_INT_EN_REG);
  1349. /* Enable ep0 interrupt */
  1350. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1351. /* time to say "hello, world" */
  1352. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1353. }
  1354. static int s3c2410_udc_start(struct usb_gadget *g,
  1355. struct usb_gadget_driver *driver)
  1356. {
  1357. struct s3c2410_udc *udc = to_s3c2410(g);
  1358. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1359. /* Hook the driver */
  1360. udc->driver = driver;
  1361. udc->gadget.dev.driver = &driver->driver;
  1362. /* Enable udc */
  1363. s3c2410_udc_enable(udc);
  1364. return 0;
  1365. }
  1366. static int s3c2410_udc_stop(struct usb_gadget *g,
  1367. struct usb_gadget_driver *driver)
  1368. {
  1369. struct s3c2410_udc *udc = to_s3c2410(g);
  1370. udc->driver = NULL;
  1371. /* Disable udc */
  1372. s3c2410_udc_disable(udc);
  1373. return 0;
  1374. }
  1375. /*---------------------------------------------------------------------------*/
  1376. static struct s3c2410_udc memory = {
  1377. .gadget = {
  1378. .ops = &s3c2410_ops,
  1379. .ep0 = &memory.ep[0].ep,
  1380. .name = gadget_name,
  1381. .dev = {
  1382. .init_name = "gadget",
  1383. },
  1384. },
  1385. /* control endpoint */
  1386. .ep[0] = {
  1387. .num = 0,
  1388. .ep = {
  1389. .name = ep0name,
  1390. .ops = &s3c2410_ep_ops,
  1391. .maxpacket = EP0_FIFO_SIZE,
  1392. },
  1393. .dev = &memory,
  1394. },
  1395. /* first group of endpoints */
  1396. .ep[1] = {
  1397. .num = 1,
  1398. .ep = {
  1399. .name = "ep1-bulk",
  1400. .ops = &s3c2410_ep_ops,
  1401. .maxpacket = EP_FIFO_SIZE,
  1402. },
  1403. .dev = &memory,
  1404. .fifo_size = EP_FIFO_SIZE,
  1405. .bEndpointAddress = 1,
  1406. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1407. },
  1408. .ep[2] = {
  1409. .num = 2,
  1410. .ep = {
  1411. .name = "ep2-bulk",
  1412. .ops = &s3c2410_ep_ops,
  1413. .maxpacket = EP_FIFO_SIZE,
  1414. },
  1415. .dev = &memory,
  1416. .fifo_size = EP_FIFO_SIZE,
  1417. .bEndpointAddress = 2,
  1418. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1419. },
  1420. .ep[3] = {
  1421. .num = 3,
  1422. .ep = {
  1423. .name = "ep3-bulk",
  1424. .ops = &s3c2410_ep_ops,
  1425. .maxpacket = EP_FIFO_SIZE,
  1426. },
  1427. .dev = &memory,
  1428. .fifo_size = EP_FIFO_SIZE,
  1429. .bEndpointAddress = 3,
  1430. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1431. },
  1432. .ep[4] = {
  1433. .num = 4,
  1434. .ep = {
  1435. .name = "ep4-bulk",
  1436. .ops = &s3c2410_ep_ops,
  1437. .maxpacket = EP_FIFO_SIZE,
  1438. },
  1439. .dev = &memory,
  1440. .fifo_size = EP_FIFO_SIZE,
  1441. .bEndpointAddress = 4,
  1442. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1443. }
  1444. };
  1445. /*
  1446. * probe - binds to the platform device
  1447. */
  1448. static int s3c2410_udc_probe(struct platform_device *pdev)
  1449. {
  1450. struct s3c2410_udc *udc = &memory;
  1451. struct device *dev = &pdev->dev;
  1452. int retval;
  1453. int irq;
  1454. dev_dbg(dev, "%s()\n", __func__);
  1455. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1456. if (IS_ERR(usb_bus_clock)) {
  1457. dev_err(dev, "failed to get usb bus clock source\n");
  1458. return PTR_ERR(usb_bus_clock);
  1459. }
  1460. clk_enable(usb_bus_clock);
  1461. udc_clock = clk_get(NULL, "usb-device");
  1462. if (IS_ERR(udc_clock)) {
  1463. dev_err(dev, "failed to get udc clock source\n");
  1464. return PTR_ERR(udc_clock);
  1465. }
  1466. clk_enable(udc_clock);
  1467. mdelay(10);
  1468. dev_dbg(dev, "got and enabled clocks\n");
  1469. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1470. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1471. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1472. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1473. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1474. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1475. }
  1476. spin_lock_init(&udc->lock);
  1477. udc_info = pdev->dev.platform_data;
  1478. rsrc_start = S3C2410_PA_USBDEV;
  1479. rsrc_len = S3C24XX_SZ_USBDEV;
  1480. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1481. return -EBUSY;
  1482. base_addr = ioremap(rsrc_start, rsrc_len);
  1483. if (!base_addr) {
  1484. retval = -ENOMEM;
  1485. goto err_mem;
  1486. }
  1487. device_initialize(&udc->gadget.dev);
  1488. udc->gadget.dev.parent = &pdev->dev;
  1489. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1490. /* Bind the driver */
  1491. retval = device_add(&udc->gadget.dev);
  1492. if (retval) {
  1493. dev_err(&udc->gadget.dev, "Error in device_add() : %d\n", retval);
  1494. goto err_device_add;
  1495. }
  1496. the_controller = udc;
  1497. platform_set_drvdata(pdev, udc);
  1498. s3c2410_udc_disable(udc);
  1499. s3c2410_udc_reinit(udc);
  1500. /* irq setup after old hardware state is cleaned up */
  1501. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1502. 0, gadget_name, udc);
  1503. if (retval != 0) {
  1504. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1505. retval = -EBUSY;
  1506. goto err_map;
  1507. }
  1508. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1509. if (udc_info && udc_info->vbus_pin > 0) {
  1510. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1511. if (retval < 0) {
  1512. dev_err(dev, "cannot claim vbus pin\n");
  1513. goto err_int;
  1514. }
  1515. irq = gpio_to_irq(udc_info->vbus_pin);
  1516. if (irq < 0) {
  1517. dev_err(dev, "no irq for gpio vbus pin\n");
  1518. goto err_gpio_claim;
  1519. }
  1520. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1521. IRQF_TRIGGER_RISING
  1522. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1523. gadget_name, udc);
  1524. if (retval != 0) {
  1525. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1526. irq, retval);
  1527. retval = -EBUSY;
  1528. goto err_gpio_claim;
  1529. }
  1530. dev_dbg(dev, "got irq %i\n", irq);
  1531. } else {
  1532. udc->vbus = 1;
  1533. }
  1534. if (udc_info && !udc_info->udc_command &&
  1535. gpio_is_valid(udc_info->pullup_pin)) {
  1536. retval = gpio_request_one(udc_info->pullup_pin,
  1537. udc_info->vbus_pin_inverted ?
  1538. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1539. "udc pullup");
  1540. if (retval)
  1541. goto err_vbus_irq;
  1542. }
  1543. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1544. if (retval)
  1545. goto err_add_udc;
  1546. if (s3c2410_udc_debugfs_root) {
  1547. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1548. s3c2410_udc_debugfs_root,
  1549. udc, &s3c2410_udc_debugfs_fops);
  1550. if (!udc->regs_info)
  1551. dev_warn(dev, "debugfs file creation failed\n");
  1552. }
  1553. dev_dbg(dev, "probe ok\n");
  1554. return 0;
  1555. err_add_udc:
  1556. if (udc_info && !udc_info->udc_command &&
  1557. gpio_is_valid(udc_info->pullup_pin))
  1558. gpio_free(udc_info->pullup_pin);
  1559. err_vbus_irq:
  1560. if (udc_info && udc_info->vbus_pin > 0)
  1561. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1562. err_gpio_claim:
  1563. if (udc_info && udc_info->vbus_pin > 0)
  1564. gpio_free(udc_info->vbus_pin);
  1565. err_int:
  1566. free_irq(IRQ_USBD, udc);
  1567. err_map:
  1568. device_unregister(&udc->gadget.dev);
  1569. err_device_add:
  1570. iounmap(base_addr);
  1571. err_mem:
  1572. release_mem_region(rsrc_start, rsrc_len);
  1573. return retval;
  1574. }
  1575. /*
  1576. * s3c2410_udc_remove
  1577. */
  1578. static int s3c2410_udc_remove(struct platform_device *pdev)
  1579. {
  1580. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1581. unsigned int irq;
  1582. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1583. if (udc->driver)
  1584. return -EBUSY;
  1585. usb_del_gadget_udc(&udc->gadget);
  1586. device_unregister(&udc->gadget.dev);
  1587. debugfs_remove(udc->regs_info);
  1588. if (udc_info && !udc_info->udc_command &&
  1589. gpio_is_valid(udc_info->pullup_pin))
  1590. gpio_free(udc_info->pullup_pin);
  1591. if (udc_info && udc_info->vbus_pin > 0) {
  1592. irq = gpio_to_irq(udc_info->vbus_pin);
  1593. free_irq(irq, udc);
  1594. }
  1595. free_irq(IRQ_USBD, udc);
  1596. iounmap(base_addr);
  1597. release_mem_region(rsrc_start, rsrc_len);
  1598. platform_set_drvdata(pdev, NULL);
  1599. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1600. clk_disable(udc_clock);
  1601. clk_put(udc_clock);
  1602. udc_clock = NULL;
  1603. }
  1604. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1605. clk_disable(usb_bus_clock);
  1606. clk_put(usb_bus_clock);
  1607. usb_bus_clock = NULL;
  1608. }
  1609. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1610. return 0;
  1611. }
  1612. #ifdef CONFIG_PM
  1613. static int
  1614. s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1615. {
  1616. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1617. return 0;
  1618. }
  1619. static int s3c2410_udc_resume(struct platform_device *pdev)
  1620. {
  1621. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1622. return 0;
  1623. }
  1624. #else
  1625. #define s3c2410_udc_suspend NULL
  1626. #define s3c2410_udc_resume NULL
  1627. #endif
  1628. static const struct platform_device_id s3c_udc_ids[] = {
  1629. { "s3c2410-usbgadget", },
  1630. { "s3c2440-usbgadget", },
  1631. { }
  1632. };
  1633. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1634. static struct platform_driver udc_driver_24x0 = {
  1635. .driver = {
  1636. .name = "s3c24x0-usbgadget",
  1637. .owner = THIS_MODULE,
  1638. },
  1639. .probe = s3c2410_udc_probe,
  1640. .remove = s3c2410_udc_remove,
  1641. .suspend = s3c2410_udc_suspend,
  1642. .resume = s3c2410_udc_resume,
  1643. .id_table = s3c_udc_ids,
  1644. };
  1645. static int __init udc_init(void)
  1646. {
  1647. int retval;
  1648. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1649. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1650. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1651. pr_err("%s: debugfs dir creation failed %ld\n",
  1652. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1653. s3c2410_udc_debugfs_root = NULL;
  1654. }
  1655. retval = platform_driver_register(&udc_driver_24x0);
  1656. if (retval)
  1657. goto err;
  1658. return 0;
  1659. err:
  1660. debugfs_remove(s3c2410_udc_debugfs_root);
  1661. return retval;
  1662. }
  1663. static void __exit udc_exit(void)
  1664. {
  1665. platform_driver_unregister(&udc_driver_24x0);
  1666. debugfs_remove(s3c2410_udc_debugfs_root);
  1667. }
  1668. module_init(udc_init);
  1669. module_exit(udc_exit);
  1670. MODULE_AUTHOR(DRIVER_AUTHOR);
  1671. MODULE_DESCRIPTION(DRIVER_DESC);
  1672. MODULE_VERSION(DRIVER_VERSION);
  1673. MODULE_LICENSE("GPL");