fsl_mxc_udc.c 3.1 KB

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  1. /*
  2. * Copyright (C) 2009
  3. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  4. *
  5. * Description:
  6. * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
  7. * driver to function correctly on these systems.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/fsl_devices.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. static struct clk *mxc_ahb_clk;
  21. static struct clk *mxc_per_clk;
  22. static struct clk *mxc_ipg_clk;
  23. /* workaround ENGcm09152 for i.MX35 */
  24. #define MX35_USBPHYCTRL_OFFSET 0x600
  25. #define USBPHYCTRL_OTGBASE_OFFSET 0x8
  26. #define USBPHYCTRL_EVDO (1 << 23)
  27. int fsl_udc_clk_init(struct platform_device *pdev)
  28. {
  29. struct fsl_usb2_platform_data *pdata;
  30. unsigned long freq;
  31. int ret;
  32. pdata = pdev->dev.platform_data;
  33. mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  34. if (IS_ERR(mxc_ipg_clk)) {
  35. dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
  36. return PTR_ERR(mxc_ipg_clk);
  37. }
  38. mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
  39. if (IS_ERR(mxc_ahb_clk)) {
  40. dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
  41. return PTR_ERR(mxc_ahb_clk);
  42. }
  43. mxc_per_clk = devm_clk_get(&pdev->dev, "per");
  44. if (IS_ERR(mxc_per_clk)) {
  45. dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
  46. return PTR_ERR(mxc_per_clk);
  47. }
  48. clk_prepare_enable(mxc_ipg_clk);
  49. clk_prepare_enable(mxc_ahb_clk);
  50. clk_prepare_enable(mxc_per_clk);
  51. /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
  52. if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
  53. freq = clk_get_rate(mxc_per_clk);
  54. if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
  55. (freq < 59999000 || freq > 60001000)) {
  56. dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
  57. ret = -EINVAL;
  58. goto eclkrate;
  59. }
  60. }
  61. return 0;
  62. eclkrate:
  63. clk_disable_unprepare(mxc_ipg_clk);
  64. clk_disable_unprepare(mxc_ahb_clk);
  65. clk_disable_unprepare(mxc_per_clk);
  66. mxc_per_clk = NULL;
  67. return ret;
  68. }
  69. int fsl_udc_clk_finalize(struct platform_device *pdev)
  70. {
  71. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  72. int ret = 0;
  73. /* workaround ENGcm09152 for i.MX35 */
  74. if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
  75. unsigned int v;
  76. struct resource *res = platform_get_resource
  77. (pdev, IORESOURCE_MEM, 0);
  78. void __iomem *phy_regs = ioremap(res->start +
  79. MX35_USBPHYCTRL_OFFSET, 512);
  80. if (!phy_regs) {
  81. dev_err(&pdev->dev, "ioremap for phy address fails\n");
  82. ret = -EINVAL;
  83. goto ioremap_err;
  84. }
  85. v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
  86. writel(v | USBPHYCTRL_EVDO,
  87. phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
  88. iounmap(phy_regs);
  89. }
  90. ioremap_err:
  91. /* ULPI transceivers don't need usbpll */
  92. if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
  93. clk_disable_unprepare(mxc_per_clk);
  94. mxc_per_clk = NULL;
  95. }
  96. return ret;
  97. }
  98. void fsl_udc_clk_release(void)
  99. {
  100. if (mxc_per_clk)
  101. clk_disable_unprepare(mxc_per_clk);
  102. clk_disable_unprepare(mxc_ahb_clk);
  103. clk_disable_unprepare(mxc_ipg_clk);
  104. }