atmel_usba_udc.c 50 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/list.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/atmel_usba_udc.h>
  23. #include <linux/delay.h>
  24. #include <linux/platform_data/atmel.h>
  25. #include <asm/gpio.h>
  26. #include "atmel_usba_udc.h"
  27. static struct usba_udc the_udc;
  28. static struct usba_ep *usba_ep;
  29. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  30. #include <linux/debugfs.h>
  31. #include <linux/uaccess.h>
  32. static int queue_dbg_open(struct inode *inode, struct file *file)
  33. {
  34. struct usba_ep *ep = inode->i_private;
  35. struct usba_request *req, *req_copy;
  36. struct list_head *queue_data;
  37. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  38. if (!queue_data)
  39. return -ENOMEM;
  40. INIT_LIST_HEAD(queue_data);
  41. spin_lock_irq(&ep->udc->lock);
  42. list_for_each_entry(req, &ep->queue, queue) {
  43. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  44. if (!req_copy)
  45. goto fail;
  46. list_add_tail(&req_copy->queue, queue_data);
  47. }
  48. spin_unlock_irq(&ep->udc->lock);
  49. file->private_data = queue_data;
  50. return 0;
  51. fail:
  52. spin_unlock_irq(&ep->udc->lock);
  53. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  54. list_del(&req->queue);
  55. kfree(req);
  56. }
  57. kfree(queue_data);
  58. return -ENOMEM;
  59. }
  60. /*
  61. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  62. *
  63. * b: buffer address
  64. * l: buffer length
  65. * I/i: interrupt/no interrupt
  66. * Z/z: zero/no zero
  67. * S/s: short ok/short not ok
  68. * s: status
  69. * n: nr_packets
  70. * F/f: submitted/not submitted to FIFO
  71. * D/d: using/not using DMA
  72. * L/l: last transaction/not last transaction
  73. */
  74. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  75. size_t nbytes, loff_t *ppos)
  76. {
  77. struct list_head *queue = file->private_data;
  78. struct usba_request *req, *tmp_req;
  79. size_t len, remaining, actual = 0;
  80. char tmpbuf[38];
  81. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  82. return -EFAULT;
  83. mutex_lock(&file_inode(file)->i_mutex);
  84. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  85. len = snprintf(tmpbuf, sizeof(tmpbuf),
  86. "%8p %08x %c%c%c %5d %c%c%c\n",
  87. req->req.buf, req->req.length,
  88. req->req.no_interrupt ? 'i' : 'I',
  89. req->req.zero ? 'Z' : 'z',
  90. req->req.short_not_ok ? 's' : 'S',
  91. req->req.status,
  92. req->submitted ? 'F' : 'f',
  93. req->using_dma ? 'D' : 'd',
  94. req->last_transaction ? 'L' : 'l');
  95. len = min(len, sizeof(tmpbuf));
  96. if (len > nbytes)
  97. break;
  98. list_del(&req->queue);
  99. kfree(req);
  100. remaining = __copy_to_user(buf, tmpbuf, len);
  101. actual += len - remaining;
  102. if (remaining)
  103. break;
  104. nbytes -= len;
  105. buf += len;
  106. }
  107. mutex_unlock(&file_inode(file)->i_mutex);
  108. return actual;
  109. }
  110. static int queue_dbg_release(struct inode *inode, struct file *file)
  111. {
  112. struct list_head *queue_data = file->private_data;
  113. struct usba_request *req, *tmp_req;
  114. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  115. list_del(&req->queue);
  116. kfree(req);
  117. }
  118. kfree(queue_data);
  119. return 0;
  120. }
  121. static int regs_dbg_open(struct inode *inode, struct file *file)
  122. {
  123. struct usba_udc *udc;
  124. unsigned int i;
  125. u32 *data;
  126. int ret = -ENOMEM;
  127. mutex_lock(&inode->i_mutex);
  128. udc = inode->i_private;
  129. data = kmalloc(inode->i_size, GFP_KERNEL);
  130. if (!data)
  131. goto out;
  132. spin_lock_irq(&udc->lock);
  133. for (i = 0; i < inode->i_size / 4; i++)
  134. data[i] = __raw_readl(udc->regs + i * 4);
  135. spin_unlock_irq(&udc->lock);
  136. file->private_data = data;
  137. ret = 0;
  138. out:
  139. mutex_unlock(&inode->i_mutex);
  140. return ret;
  141. }
  142. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  143. size_t nbytes, loff_t *ppos)
  144. {
  145. struct inode *inode = file_inode(file);
  146. int ret;
  147. mutex_lock(&inode->i_mutex);
  148. ret = simple_read_from_buffer(buf, nbytes, ppos,
  149. file->private_data,
  150. file_inode(file)->i_size);
  151. mutex_unlock(&inode->i_mutex);
  152. return ret;
  153. }
  154. static int regs_dbg_release(struct inode *inode, struct file *file)
  155. {
  156. kfree(file->private_data);
  157. return 0;
  158. }
  159. const struct file_operations queue_dbg_fops = {
  160. .owner = THIS_MODULE,
  161. .open = queue_dbg_open,
  162. .llseek = no_llseek,
  163. .read = queue_dbg_read,
  164. .release = queue_dbg_release,
  165. };
  166. const struct file_operations regs_dbg_fops = {
  167. .owner = THIS_MODULE,
  168. .open = regs_dbg_open,
  169. .llseek = generic_file_llseek,
  170. .read = regs_dbg_read,
  171. .release = regs_dbg_release,
  172. };
  173. static void usba_ep_init_debugfs(struct usba_udc *udc,
  174. struct usba_ep *ep)
  175. {
  176. struct dentry *ep_root;
  177. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  178. if (!ep_root)
  179. goto err_root;
  180. ep->debugfs_dir = ep_root;
  181. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  182. ep, &queue_dbg_fops);
  183. if (!ep->debugfs_queue)
  184. goto err_queue;
  185. if (ep->can_dma) {
  186. ep->debugfs_dma_status
  187. = debugfs_create_u32("dma_status", 0400, ep_root,
  188. &ep->last_dma_status);
  189. if (!ep->debugfs_dma_status)
  190. goto err_dma_status;
  191. }
  192. if (ep_is_control(ep)) {
  193. ep->debugfs_state
  194. = debugfs_create_u32("state", 0400, ep_root,
  195. &ep->state);
  196. if (!ep->debugfs_state)
  197. goto err_state;
  198. }
  199. return;
  200. err_state:
  201. if (ep->can_dma)
  202. debugfs_remove(ep->debugfs_dma_status);
  203. err_dma_status:
  204. debugfs_remove(ep->debugfs_queue);
  205. err_queue:
  206. debugfs_remove(ep_root);
  207. err_root:
  208. dev_err(&ep->udc->pdev->dev,
  209. "failed to create debugfs directory for %s\n", ep->ep.name);
  210. }
  211. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  212. {
  213. debugfs_remove(ep->debugfs_queue);
  214. debugfs_remove(ep->debugfs_dma_status);
  215. debugfs_remove(ep->debugfs_state);
  216. debugfs_remove(ep->debugfs_dir);
  217. ep->debugfs_dma_status = NULL;
  218. ep->debugfs_dir = NULL;
  219. }
  220. static void usba_init_debugfs(struct usba_udc *udc)
  221. {
  222. struct dentry *root, *regs;
  223. struct resource *regs_resource;
  224. root = debugfs_create_dir(udc->gadget.name, NULL);
  225. if (IS_ERR(root) || !root)
  226. goto err_root;
  227. udc->debugfs_root = root;
  228. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  229. if (!regs)
  230. goto err_regs;
  231. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  232. CTRL_IOMEM_ID);
  233. regs->d_inode->i_size = resource_size(regs_resource);
  234. udc->debugfs_regs = regs;
  235. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  236. return;
  237. err_regs:
  238. debugfs_remove(root);
  239. err_root:
  240. udc->debugfs_root = NULL;
  241. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  242. }
  243. static void usba_cleanup_debugfs(struct usba_udc *udc)
  244. {
  245. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  246. debugfs_remove(udc->debugfs_regs);
  247. debugfs_remove(udc->debugfs_root);
  248. udc->debugfs_regs = NULL;
  249. udc->debugfs_root = NULL;
  250. }
  251. #else
  252. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  253. struct usba_ep *ep)
  254. {
  255. }
  256. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  257. {
  258. }
  259. static inline void usba_init_debugfs(struct usba_udc *udc)
  260. {
  261. }
  262. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  263. {
  264. }
  265. #endif
  266. static int vbus_is_present(struct usba_udc *udc)
  267. {
  268. if (gpio_is_valid(udc->vbus_pin))
  269. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  270. /* No Vbus detection: Assume always present */
  271. return 1;
  272. }
  273. #if defined(CONFIG_ARCH_AT91SAM9RL)
  274. #include <mach/at91_pmc.h>
  275. static void toggle_bias(int is_on)
  276. {
  277. unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
  278. if (is_on)
  279. at91_pmc_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
  280. else
  281. at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
  282. }
  283. #else
  284. static void toggle_bias(int is_on)
  285. {
  286. }
  287. #endif /* CONFIG_ARCH_AT91SAM9RL */
  288. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  289. {
  290. unsigned int transaction_len;
  291. transaction_len = req->req.length - req->req.actual;
  292. req->last_transaction = 1;
  293. if (transaction_len > ep->ep.maxpacket) {
  294. transaction_len = ep->ep.maxpacket;
  295. req->last_transaction = 0;
  296. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  297. req->last_transaction = 0;
  298. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  299. ep->ep.name, req, transaction_len,
  300. req->last_transaction ? ", done" : "");
  301. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  302. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  303. req->req.actual += transaction_len;
  304. }
  305. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  306. {
  307. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  308. ep->ep.name, req, req->req.length);
  309. req->req.actual = 0;
  310. req->submitted = 1;
  311. if (req->using_dma) {
  312. if (req->req.length == 0) {
  313. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  314. return;
  315. }
  316. if (req->req.zero)
  317. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  318. else
  319. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  320. usba_dma_writel(ep, ADDRESS, req->req.dma);
  321. usba_dma_writel(ep, CONTROL, req->ctrl);
  322. } else {
  323. next_fifo_transaction(ep, req);
  324. if (req->last_transaction) {
  325. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  326. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  327. } else {
  328. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  329. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  330. }
  331. }
  332. }
  333. static void submit_next_request(struct usba_ep *ep)
  334. {
  335. struct usba_request *req;
  336. if (list_empty(&ep->queue)) {
  337. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  338. return;
  339. }
  340. req = list_entry(ep->queue.next, struct usba_request, queue);
  341. if (!req->submitted)
  342. submit_request(ep, req);
  343. }
  344. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  345. {
  346. ep->state = STATUS_STAGE_IN;
  347. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  348. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  349. }
  350. static void receive_data(struct usba_ep *ep)
  351. {
  352. struct usba_udc *udc = ep->udc;
  353. struct usba_request *req;
  354. unsigned long status;
  355. unsigned int bytecount, nr_busy;
  356. int is_complete = 0;
  357. status = usba_ep_readl(ep, STA);
  358. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  359. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  360. while (nr_busy > 0) {
  361. if (list_empty(&ep->queue)) {
  362. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  363. break;
  364. }
  365. req = list_entry(ep->queue.next,
  366. struct usba_request, queue);
  367. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  368. if (status & (1 << 31))
  369. is_complete = 1;
  370. if (req->req.actual + bytecount >= req->req.length) {
  371. is_complete = 1;
  372. bytecount = req->req.length - req->req.actual;
  373. }
  374. memcpy_fromio(req->req.buf + req->req.actual,
  375. ep->fifo, bytecount);
  376. req->req.actual += bytecount;
  377. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  378. if (is_complete) {
  379. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  380. req->req.status = 0;
  381. list_del_init(&req->queue);
  382. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  383. spin_unlock(&udc->lock);
  384. req->req.complete(&ep->ep, &req->req);
  385. spin_lock(&udc->lock);
  386. }
  387. status = usba_ep_readl(ep, STA);
  388. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  389. if (is_complete && ep_is_control(ep)) {
  390. send_status(udc, ep);
  391. break;
  392. }
  393. }
  394. }
  395. static void
  396. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  397. {
  398. struct usba_udc *udc = ep->udc;
  399. WARN_ON(!list_empty(&req->queue));
  400. if (req->req.status == -EINPROGRESS)
  401. req->req.status = status;
  402. if (req->mapped) {
  403. dma_unmap_single(
  404. &udc->pdev->dev, req->req.dma, req->req.length,
  405. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  406. req->req.dma = DMA_ADDR_INVALID;
  407. req->mapped = 0;
  408. }
  409. DBG(DBG_GADGET | DBG_REQ,
  410. "%s: req %p complete: status %d, actual %u\n",
  411. ep->ep.name, req, req->req.status, req->req.actual);
  412. spin_unlock(&udc->lock);
  413. req->req.complete(&ep->ep, &req->req);
  414. spin_lock(&udc->lock);
  415. }
  416. static void
  417. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  418. {
  419. struct usba_request *req, *tmp_req;
  420. list_for_each_entry_safe(req, tmp_req, list, queue) {
  421. list_del_init(&req->queue);
  422. request_complete(ep, req, status);
  423. }
  424. }
  425. static int
  426. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  427. {
  428. struct usba_ep *ep = to_usba_ep(_ep);
  429. struct usba_udc *udc = ep->udc;
  430. unsigned long flags, ept_cfg, maxpacket;
  431. unsigned int nr_trans;
  432. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  433. maxpacket = usb_endpoint_maxp(desc) & 0x7ff;
  434. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  435. || ep->index == 0
  436. || desc->bDescriptorType != USB_DT_ENDPOINT
  437. || maxpacket == 0
  438. || maxpacket > ep->fifo_size) {
  439. DBG(DBG_ERR, "ep_enable: Invalid argument");
  440. return -EINVAL;
  441. }
  442. ep->is_isoc = 0;
  443. ep->is_in = 0;
  444. if (maxpacket <= 8)
  445. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  446. else
  447. /* LSB is bit 1, not 0 */
  448. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  449. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  450. ep->ep.name, ept_cfg, maxpacket);
  451. if (usb_endpoint_dir_in(desc)) {
  452. ep->is_in = 1;
  453. ept_cfg |= USBA_EPT_DIR_IN;
  454. }
  455. switch (usb_endpoint_type(desc)) {
  456. case USB_ENDPOINT_XFER_CONTROL:
  457. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  458. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  459. break;
  460. case USB_ENDPOINT_XFER_ISOC:
  461. if (!ep->can_isoc) {
  462. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  463. ep->ep.name);
  464. return -EINVAL;
  465. }
  466. /*
  467. * Bits 11:12 specify number of _additional_
  468. * transactions per microframe.
  469. */
  470. nr_trans = ((usb_endpoint_maxp(desc) >> 11) & 3) + 1;
  471. if (nr_trans > 3)
  472. return -EINVAL;
  473. ep->is_isoc = 1;
  474. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  475. /*
  476. * Do triple-buffering on high-bandwidth iso endpoints.
  477. */
  478. if (nr_trans > 1 && ep->nr_banks == 3)
  479. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  480. else
  481. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  482. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  483. break;
  484. case USB_ENDPOINT_XFER_BULK:
  485. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  486. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  487. break;
  488. case USB_ENDPOINT_XFER_INT:
  489. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  490. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  491. break;
  492. }
  493. spin_lock_irqsave(&ep->udc->lock, flags);
  494. ep->ep.desc = desc;
  495. ep->ep.maxpacket = maxpacket;
  496. usba_ep_writel(ep, CFG, ept_cfg);
  497. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  498. if (ep->can_dma) {
  499. u32 ctrl;
  500. usba_writel(udc, INT_ENB,
  501. (usba_readl(udc, INT_ENB)
  502. | USBA_BF(EPT_INT, 1 << ep->index)
  503. | USBA_BF(DMA_INT, 1 << ep->index)));
  504. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  505. usba_ep_writel(ep, CTL_ENB, ctrl);
  506. } else {
  507. usba_writel(udc, INT_ENB,
  508. (usba_readl(udc, INT_ENB)
  509. | USBA_BF(EPT_INT, 1 << ep->index)));
  510. }
  511. spin_unlock_irqrestore(&udc->lock, flags);
  512. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  513. (unsigned long)usba_ep_readl(ep, CFG));
  514. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  515. (unsigned long)usba_readl(udc, INT_ENB));
  516. return 0;
  517. }
  518. static int usba_ep_disable(struct usb_ep *_ep)
  519. {
  520. struct usba_ep *ep = to_usba_ep(_ep);
  521. struct usba_udc *udc = ep->udc;
  522. LIST_HEAD(req_list);
  523. unsigned long flags;
  524. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  525. spin_lock_irqsave(&udc->lock, flags);
  526. if (!ep->ep.desc) {
  527. spin_unlock_irqrestore(&udc->lock, flags);
  528. /* REVISIT because this driver disables endpoints in
  529. * reset_all_endpoints() before calling disconnect(),
  530. * most gadget drivers would trigger this non-error ...
  531. */
  532. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  533. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  534. ep->ep.name);
  535. return -EINVAL;
  536. }
  537. ep->ep.desc = NULL;
  538. list_splice_init(&ep->queue, &req_list);
  539. if (ep->can_dma) {
  540. usba_dma_writel(ep, CONTROL, 0);
  541. usba_dma_writel(ep, ADDRESS, 0);
  542. usba_dma_readl(ep, STATUS);
  543. }
  544. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  545. usba_writel(udc, INT_ENB,
  546. usba_readl(udc, INT_ENB)
  547. & ~USBA_BF(EPT_INT, 1 << ep->index));
  548. request_complete_list(ep, &req_list, -ESHUTDOWN);
  549. spin_unlock_irqrestore(&udc->lock, flags);
  550. return 0;
  551. }
  552. static struct usb_request *
  553. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  554. {
  555. struct usba_request *req;
  556. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  557. req = kzalloc(sizeof(*req), gfp_flags);
  558. if (!req)
  559. return NULL;
  560. INIT_LIST_HEAD(&req->queue);
  561. req->req.dma = DMA_ADDR_INVALID;
  562. return &req->req;
  563. }
  564. static void
  565. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  566. {
  567. struct usba_request *req = to_usba_req(_req);
  568. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  569. kfree(req);
  570. }
  571. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  572. struct usba_request *req, gfp_t gfp_flags)
  573. {
  574. unsigned long flags;
  575. int ret;
  576. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  577. ep->ep.name, req->req.length, req->req.dma,
  578. req->req.zero ? 'Z' : 'z',
  579. req->req.short_not_ok ? 'S' : 's',
  580. req->req.no_interrupt ? 'I' : 'i');
  581. if (req->req.length > 0x10000) {
  582. /* Lengths from 0 to 65536 (inclusive) are supported */
  583. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  584. return -EINVAL;
  585. }
  586. req->using_dma = 1;
  587. if (req->req.dma == DMA_ADDR_INVALID) {
  588. req->req.dma = dma_map_single(
  589. &udc->pdev->dev, req->req.buf, req->req.length,
  590. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  591. req->mapped = 1;
  592. } else {
  593. dma_sync_single_for_device(
  594. &udc->pdev->dev, req->req.dma, req->req.length,
  595. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  596. req->mapped = 0;
  597. }
  598. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  599. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  600. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  601. if (ep->is_in)
  602. req->ctrl |= USBA_DMA_END_BUF_EN;
  603. /*
  604. * Add this request to the queue and submit for DMA if
  605. * possible. Check if we're still alive first -- we may have
  606. * received a reset since last time we checked.
  607. */
  608. ret = -ESHUTDOWN;
  609. spin_lock_irqsave(&udc->lock, flags);
  610. if (ep->ep.desc) {
  611. if (list_empty(&ep->queue))
  612. submit_request(ep, req);
  613. list_add_tail(&req->queue, &ep->queue);
  614. ret = 0;
  615. }
  616. spin_unlock_irqrestore(&udc->lock, flags);
  617. return ret;
  618. }
  619. static int
  620. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  621. {
  622. struct usba_request *req = to_usba_req(_req);
  623. struct usba_ep *ep = to_usba_ep(_ep);
  624. struct usba_udc *udc = ep->udc;
  625. unsigned long flags;
  626. int ret;
  627. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  628. ep->ep.name, req, _req->length);
  629. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
  630. !ep->ep.desc)
  631. return -ESHUTDOWN;
  632. req->submitted = 0;
  633. req->using_dma = 0;
  634. req->last_transaction = 0;
  635. _req->status = -EINPROGRESS;
  636. _req->actual = 0;
  637. if (ep->can_dma)
  638. return queue_dma(udc, ep, req, gfp_flags);
  639. /* May have received a reset since last time we checked */
  640. ret = -ESHUTDOWN;
  641. spin_lock_irqsave(&udc->lock, flags);
  642. if (ep->ep.desc) {
  643. list_add_tail(&req->queue, &ep->queue);
  644. if ((!ep_is_control(ep) && ep->is_in) ||
  645. (ep_is_control(ep)
  646. && (ep->state == DATA_STAGE_IN
  647. || ep->state == STATUS_STAGE_IN)))
  648. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  649. else
  650. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  651. ret = 0;
  652. }
  653. spin_unlock_irqrestore(&udc->lock, flags);
  654. return ret;
  655. }
  656. static void
  657. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  658. {
  659. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  660. }
  661. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  662. {
  663. unsigned int timeout;
  664. u32 status;
  665. /*
  666. * Stop the DMA controller. When writing both CH_EN
  667. * and LINK to 0, the other bits are not affected.
  668. */
  669. usba_dma_writel(ep, CONTROL, 0);
  670. /* Wait for the FIFO to empty */
  671. for (timeout = 40; timeout; --timeout) {
  672. status = usba_dma_readl(ep, STATUS);
  673. if (!(status & USBA_DMA_CH_EN))
  674. break;
  675. udelay(1);
  676. }
  677. if (pstatus)
  678. *pstatus = status;
  679. if (timeout == 0) {
  680. dev_err(&ep->udc->pdev->dev,
  681. "%s: timed out waiting for DMA FIFO to empty\n",
  682. ep->ep.name);
  683. return -ETIMEDOUT;
  684. }
  685. return 0;
  686. }
  687. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  688. {
  689. struct usba_ep *ep = to_usba_ep(_ep);
  690. struct usba_udc *udc = ep->udc;
  691. struct usba_request *req = to_usba_req(_req);
  692. unsigned long flags;
  693. u32 status;
  694. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  695. ep->ep.name, req);
  696. spin_lock_irqsave(&udc->lock, flags);
  697. if (req->using_dma) {
  698. /*
  699. * If this request is currently being transferred,
  700. * stop the DMA controller and reset the FIFO.
  701. */
  702. if (ep->queue.next == &req->queue) {
  703. status = usba_dma_readl(ep, STATUS);
  704. if (status & USBA_DMA_CH_EN)
  705. stop_dma(ep, &status);
  706. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  707. ep->last_dma_status = status;
  708. #endif
  709. usba_writel(udc, EPT_RST, 1 << ep->index);
  710. usba_update_req(ep, req, status);
  711. }
  712. }
  713. /*
  714. * Errors should stop the queue from advancing until the
  715. * completion function returns.
  716. */
  717. list_del_init(&req->queue);
  718. request_complete(ep, req, -ECONNRESET);
  719. /* Process the next request if any */
  720. submit_next_request(ep);
  721. spin_unlock_irqrestore(&udc->lock, flags);
  722. return 0;
  723. }
  724. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  725. {
  726. struct usba_ep *ep = to_usba_ep(_ep);
  727. struct usba_udc *udc = ep->udc;
  728. unsigned long flags;
  729. int ret = 0;
  730. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  731. value ? "set" : "clear");
  732. if (!ep->ep.desc) {
  733. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  734. ep->ep.name);
  735. return -ENODEV;
  736. }
  737. if (ep->is_isoc) {
  738. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  739. ep->ep.name);
  740. return -ENOTTY;
  741. }
  742. spin_lock_irqsave(&udc->lock, flags);
  743. /*
  744. * We can't halt IN endpoints while there are still data to be
  745. * transferred
  746. */
  747. if (!list_empty(&ep->queue)
  748. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  749. & USBA_BF(BUSY_BANKS, -1L))))) {
  750. ret = -EAGAIN;
  751. } else {
  752. if (value)
  753. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  754. else
  755. usba_ep_writel(ep, CLR_STA,
  756. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  757. usba_ep_readl(ep, STA);
  758. }
  759. spin_unlock_irqrestore(&udc->lock, flags);
  760. return ret;
  761. }
  762. static int usba_ep_fifo_status(struct usb_ep *_ep)
  763. {
  764. struct usba_ep *ep = to_usba_ep(_ep);
  765. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  766. }
  767. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  768. {
  769. struct usba_ep *ep = to_usba_ep(_ep);
  770. struct usba_udc *udc = ep->udc;
  771. usba_writel(udc, EPT_RST, 1 << ep->index);
  772. }
  773. static const struct usb_ep_ops usba_ep_ops = {
  774. .enable = usba_ep_enable,
  775. .disable = usba_ep_disable,
  776. .alloc_request = usba_ep_alloc_request,
  777. .free_request = usba_ep_free_request,
  778. .queue = usba_ep_queue,
  779. .dequeue = usba_ep_dequeue,
  780. .set_halt = usba_ep_set_halt,
  781. .fifo_status = usba_ep_fifo_status,
  782. .fifo_flush = usba_ep_fifo_flush,
  783. };
  784. static int usba_udc_get_frame(struct usb_gadget *gadget)
  785. {
  786. struct usba_udc *udc = to_usba_udc(gadget);
  787. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  788. }
  789. static int usba_udc_wakeup(struct usb_gadget *gadget)
  790. {
  791. struct usba_udc *udc = to_usba_udc(gadget);
  792. unsigned long flags;
  793. u32 ctrl;
  794. int ret = -EINVAL;
  795. spin_lock_irqsave(&udc->lock, flags);
  796. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  797. ctrl = usba_readl(udc, CTRL);
  798. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  799. ret = 0;
  800. }
  801. spin_unlock_irqrestore(&udc->lock, flags);
  802. return ret;
  803. }
  804. static int
  805. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  806. {
  807. struct usba_udc *udc = to_usba_udc(gadget);
  808. unsigned long flags;
  809. spin_lock_irqsave(&udc->lock, flags);
  810. if (is_selfpowered)
  811. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  812. else
  813. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  814. spin_unlock_irqrestore(&udc->lock, flags);
  815. return 0;
  816. }
  817. static int atmel_usba_start(struct usb_gadget *gadget,
  818. struct usb_gadget_driver *driver);
  819. static int atmel_usba_stop(struct usb_gadget *gadget,
  820. struct usb_gadget_driver *driver);
  821. static const struct usb_gadget_ops usba_udc_ops = {
  822. .get_frame = usba_udc_get_frame,
  823. .wakeup = usba_udc_wakeup,
  824. .set_selfpowered = usba_udc_set_selfpowered,
  825. .udc_start = atmel_usba_start,
  826. .udc_stop = atmel_usba_stop,
  827. };
  828. static struct usb_endpoint_descriptor usba_ep0_desc = {
  829. .bLength = USB_DT_ENDPOINT_SIZE,
  830. .bDescriptorType = USB_DT_ENDPOINT,
  831. .bEndpointAddress = 0,
  832. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  833. .wMaxPacketSize = cpu_to_le16(64),
  834. /* FIXME: I have no idea what to put here */
  835. .bInterval = 1,
  836. };
  837. static void nop_release(struct device *dev)
  838. {
  839. }
  840. static struct usba_udc the_udc = {
  841. .gadget = {
  842. .ops = &usba_udc_ops,
  843. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  844. .max_speed = USB_SPEED_HIGH,
  845. .name = "atmel_usba_udc",
  846. .dev = {
  847. .init_name = "gadget",
  848. .release = nop_release,
  849. },
  850. },
  851. };
  852. /*
  853. * Called with interrupts disabled and udc->lock held.
  854. */
  855. static void reset_all_endpoints(struct usba_udc *udc)
  856. {
  857. struct usba_ep *ep;
  858. struct usba_request *req, *tmp_req;
  859. usba_writel(udc, EPT_RST, ~0UL);
  860. ep = to_usba_ep(udc->gadget.ep0);
  861. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  862. list_del_init(&req->queue);
  863. request_complete(ep, req, -ECONNRESET);
  864. }
  865. /* NOTE: normally, the next call to the gadget driver is in
  866. * charge of disabling endpoints... usually disconnect().
  867. * The exception would be entering a high speed test mode.
  868. *
  869. * FIXME remove this code ... and retest thoroughly.
  870. */
  871. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  872. if (ep->ep.desc) {
  873. spin_unlock(&udc->lock);
  874. usba_ep_disable(&ep->ep);
  875. spin_lock(&udc->lock);
  876. }
  877. }
  878. }
  879. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  880. {
  881. struct usba_ep *ep;
  882. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  883. return to_usba_ep(udc->gadget.ep0);
  884. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  885. u8 bEndpointAddress;
  886. if (!ep->ep.desc)
  887. continue;
  888. bEndpointAddress = ep->ep.desc->bEndpointAddress;
  889. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  890. continue;
  891. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  892. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  893. return ep;
  894. }
  895. return NULL;
  896. }
  897. /* Called with interrupts disabled and udc->lock held */
  898. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  899. {
  900. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  901. ep->state = WAIT_FOR_SETUP;
  902. }
  903. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  904. {
  905. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  906. return 1;
  907. return 0;
  908. }
  909. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  910. {
  911. u32 regval;
  912. DBG(DBG_BUS, "setting address %u...\n", addr);
  913. regval = usba_readl(udc, CTRL);
  914. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  915. usba_writel(udc, CTRL, regval);
  916. }
  917. static int do_test_mode(struct usba_udc *udc)
  918. {
  919. static const char test_packet_buffer[] = {
  920. /* JKJKJKJK * 9 */
  921. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  922. /* JJKKJJKK * 8 */
  923. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  924. /* JJKKJJKK * 8 */
  925. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  926. /* JJJJJJJKKKKKKK * 8 */
  927. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  928. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  929. /* JJJJJJJK * 8 */
  930. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  931. /* {JKKKKKKK * 10}, JK */
  932. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  933. };
  934. struct usba_ep *ep;
  935. struct device *dev = &udc->pdev->dev;
  936. int test_mode;
  937. test_mode = udc->test_mode;
  938. /* Start from a clean slate */
  939. reset_all_endpoints(udc);
  940. switch (test_mode) {
  941. case 0x0100:
  942. /* Test_J */
  943. usba_writel(udc, TST, USBA_TST_J_MODE);
  944. dev_info(dev, "Entering Test_J mode...\n");
  945. break;
  946. case 0x0200:
  947. /* Test_K */
  948. usba_writel(udc, TST, USBA_TST_K_MODE);
  949. dev_info(dev, "Entering Test_K mode...\n");
  950. break;
  951. case 0x0300:
  952. /*
  953. * Test_SE0_NAK: Force high-speed mode and set up ep0
  954. * for Bulk IN transfers
  955. */
  956. ep = &usba_ep[0];
  957. usba_writel(udc, TST,
  958. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  959. usba_ep_writel(ep, CFG,
  960. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  961. | USBA_EPT_DIR_IN
  962. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  963. | USBA_BF(BK_NUMBER, 1));
  964. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  965. set_protocol_stall(udc, ep);
  966. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  967. } else {
  968. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  969. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  970. }
  971. break;
  972. case 0x0400:
  973. /* Test_Packet */
  974. ep = &usba_ep[0];
  975. usba_ep_writel(ep, CFG,
  976. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  977. | USBA_EPT_DIR_IN
  978. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  979. | USBA_BF(BK_NUMBER, 1));
  980. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  981. set_protocol_stall(udc, ep);
  982. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  983. } else {
  984. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  985. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  986. memcpy_toio(ep->fifo, test_packet_buffer,
  987. sizeof(test_packet_buffer));
  988. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  989. dev_info(dev, "Entering Test_Packet mode...\n");
  990. }
  991. break;
  992. default:
  993. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  994. return -EINVAL;
  995. }
  996. return 0;
  997. }
  998. /* Avoid overly long expressions */
  999. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  1000. {
  1001. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  1002. return true;
  1003. return false;
  1004. }
  1005. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1006. {
  1007. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  1008. return true;
  1009. return false;
  1010. }
  1011. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1012. {
  1013. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  1014. return true;
  1015. return false;
  1016. }
  1017. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1018. struct usb_ctrlrequest *crq)
  1019. {
  1020. int retval = 0;
  1021. switch (crq->bRequest) {
  1022. case USB_REQ_GET_STATUS: {
  1023. u16 status;
  1024. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1025. status = cpu_to_le16(udc->devstatus);
  1026. } else if (crq->bRequestType
  1027. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1028. status = cpu_to_le16(0);
  1029. } else if (crq->bRequestType
  1030. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1031. struct usba_ep *target;
  1032. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1033. if (!target)
  1034. goto stall;
  1035. status = 0;
  1036. if (is_stalled(udc, target))
  1037. status |= cpu_to_le16(1);
  1038. } else
  1039. goto delegate;
  1040. /* Write directly to the FIFO. No queueing is done. */
  1041. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1042. goto stall;
  1043. ep->state = DATA_STAGE_IN;
  1044. __raw_writew(status, ep->fifo);
  1045. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1046. break;
  1047. }
  1048. case USB_REQ_CLEAR_FEATURE: {
  1049. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1050. if (feature_is_dev_remote_wakeup(crq))
  1051. udc->devstatus
  1052. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1053. else
  1054. /* Can't CLEAR_FEATURE TEST_MODE */
  1055. goto stall;
  1056. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1057. struct usba_ep *target;
  1058. if (crq->wLength != cpu_to_le16(0)
  1059. || !feature_is_ep_halt(crq))
  1060. goto stall;
  1061. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1062. if (!target)
  1063. goto stall;
  1064. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1065. if (target->index != 0)
  1066. usba_ep_writel(target, CLR_STA,
  1067. USBA_TOGGLE_CLR);
  1068. } else {
  1069. goto delegate;
  1070. }
  1071. send_status(udc, ep);
  1072. break;
  1073. }
  1074. case USB_REQ_SET_FEATURE: {
  1075. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1076. if (feature_is_dev_test_mode(crq)) {
  1077. send_status(udc, ep);
  1078. ep->state = STATUS_STAGE_TEST;
  1079. udc->test_mode = le16_to_cpu(crq->wIndex);
  1080. return 0;
  1081. } else if (feature_is_dev_remote_wakeup(crq)) {
  1082. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1083. } else {
  1084. goto stall;
  1085. }
  1086. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1087. struct usba_ep *target;
  1088. if (crq->wLength != cpu_to_le16(0)
  1089. || !feature_is_ep_halt(crq))
  1090. goto stall;
  1091. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1092. if (!target)
  1093. goto stall;
  1094. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1095. } else
  1096. goto delegate;
  1097. send_status(udc, ep);
  1098. break;
  1099. }
  1100. case USB_REQ_SET_ADDRESS:
  1101. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1102. goto delegate;
  1103. set_address(udc, le16_to_cpu(crq->wValue));
  1104. send_status(udc, ep);
  1105. ep->state = STATUS_STAGE_ADDR;
  1106. break;
  1107. default:
  1108. delegate:
  1109. spin_unlock(&udc->lock);
  1110. retval = udc->driver->setup(&udc->gadget, crq);
  1111. spin_lock(&udc->lock);
  1112. }
  1113. return retval;
  1114. stall:
  1115. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1116. "halting endpoint...\n",
  1117. ep->ep.name, crq->bRequestType, crq->bRequest,
  1118. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1119. le16_to_cpu(crq->wLength));
  1120. set_protocol_stall(udc, ep);
  1121. return -1;
  1122. }
  1123. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1124. {
  1125. struct usba_request *req;
  1126. u32 epstatus;
  1127. u32 epctrl;
  1128. restart:
  1129. epstatus = usba_ep_readl(ep, STA);
  1130. epctrl = usba_ep_readl(ep, CTL);
  1131. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1132. ep->ep.name, ep->state, epstatus, epctrl);
  1133. req = NULL;
  1134. if (!list_empty(&ep->queue))
  1135. req = list_entry(ep->queue.next,
  1136. struct usba_request, queue);
  1137. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1138. if (req->submitted)
  1139. next_fifo_transaction(ep, req);
  1140. else
  1141. submit_request(ep, req);
  1142. if (req->last_transaction) {
  1143. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1144. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1145. }
  1146. goto restart;
  1147. }
  1148. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1149. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1150. switch (ep->state) {
  1151. case DATA_STAGE_IN:
  1152. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1153. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1154. ep->state = STATUS_STAGE_OUT;
  1155. break;
  1156. case STATUS_STAGE_ADDR:
  1157. /* Activate our new address */
  1158. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1159. | USBA_FADDR_EN));
  1160. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1161. ep->state = WAIT_FOR_SETUP;
  1162. break;
  1163. case STATUS_STAGE_IN:
  1164. if (req) {
  1165. list_del_init(&req->queue);
  1166. request_complete(ep, req, 0);
  1167. submit_next_request(ep);
  1168. }
  1169. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1170. ep->state = WAIT_FOR_SETUP;
  1171. break;
  1172. case STATUS_STAGE_TEST:
  1173. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1174. ep->state = WAIT_FOR_SETUP;
  1175. if (do_test_mode(udc))
  1176. set_protocol_stall(udc, ep);
  1177. break;
  1178. default:
  1179. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1180. "halting endpoint...\n",
  1181. ep->ep.name, ep->state);
  1182. set_protocol_stall(udc, ep);
  1183. break;
  1184. }
  1185. goto restart;
  1186. }
  1187. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1188. switch (ep->state) {
  1189. case STATUS_STAGE_OUT:
  1190. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1191. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1192. if (req) {
  1193. list_del_init(&req->queue);
  1194. request_complete(ep, req, 0);
  1195. }
  1196. ep->state = WAIT_FOR_SETUP;
  1197. break;
  1198. case DATA_STAGE_OUT:
  1199. receive_data(ep);
  1200. break;
  1201. default:
  1202. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1203. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1204. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1205. "halting endpoint...\n",
  1206. ep->ep.name, ep->state);
  1207. set_protocol_stall(udc, ep);
  1208. break;
  1209. }
  1210. goto restart;
  1211. }
  1212. if (epstatus & USBA_RX_SETUP) {
  1213. union {
  1214. struct usb_ctrlrequest crq;
  1215. unsigned long data[2];
  1216. } crq;
  1217. unsigned int pkt_len;
  1218. int ret;
  1219. if (ep->state != WAIT_FOR_SETUP) {
  1220. /*
  1221. * Didn't expect a SETUP packet at this
  1222. * point. Clean up any pending requests (which
  1223. * may be successful).
  1224. */
  1225. int status = -EPROTO;
  1226. /*
  1227. * RXRDY and TXCOMP are dropped when SETUP
  1228. * packets arrive. Just pretend we received
  1229. * the status packet.
  1230. */
  1231. if (ep->state == STATUS_STAGE_OUT
  1232. || ep->state == STATUS_STAGE_IN) {
  1233. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1234. status = 0;
  1235. }
  1236. if (req) {
  1237. list_del_init(&req->queue);
  1238. request_complete(ep, req, status);
  1239. }
  1240. }
  1241. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1242. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1243. if (pkt_len != sizeof(crq)) {
  1244. pr_warning("udc: Invalid packet length %u "
  1245. "(expected %zu)\n", pkt_len, sizeof(crq));
  1246. set_protocol_stall(udc, ep);
  1247. return;
  1248. }
  1249. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1250. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1251. /* Free up one bank in the FIFO so that we can
  1252. * generate or receive a reply right away. */
  1253. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1254. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1255. ep->state, crq.crq.bRequestType,
  1256. crq.crq.bRequest); */
  1257. if (crq.crq.bRequestType & USB_DIR_IN) {
  1258. /*
  1259. * The USB 2.0 spec states that "if wLength is
  1260. * zero, there is no data transfer phase."
  1261. * However, testusb #14 seems to actually
  1262. * expect a data phase even if wLength = 0...
  1263. */
  1264. ep->state = DATA_STAGE_IN;
  1265. } else {
  1266. if (crq.crq.wLength != cpu_to_le16(0))
  1267. ep->state = DATA_STAGE_OUT;
  1268. else
  1269. ep->state = STATUS_STAGE_IN;
  1270. }
  1271. ret = -1;
  1272. if (ep->index == 0)
  1273. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1274. else {
  1275. spin_unlock(&udc->lock);
  1276. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1277. spin_lock(&udc->lock);
  1278. }
  1279. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1280. crq.crq.bRequestType, crq.crq.bRequest,
  1281. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1282. if (ret < 0) {
  1283. /* Let the host know that we failed */
  1284. set_protocol_stall(udc, ep);
  1285. }
  1286. }
  1287. }
  1288. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1289. {
  1290. struct usba_request *req;
  1291. u32 epstatus;
  1292. u32 epctrl;
  1293. epstatus = usba_ep_readl(ep, STA);
  1294. epctrl = usba_ep_readl(ep, CTL);
  1295. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1296. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1297. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1298. if (list_empty(&ep->queue)) {
  1299. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1300. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1301. return;
  1302. }
  1303. req = list_entry(ep->queue.next, struct usba_request, queue);
  1304. if (req->using_dma) {
  1305. /* Send a zero-length packet */
  1306. usba_ep_writel(ep, SET_STA,
  1307. USBA_TX_PK_RDY);
  1308. usba_ep_writel(ep, CTL_DIS,
  1309. USBA_TX_PK_RDY);
  1310. list_del_init(&req->queue);
  1311. submit_next_request(ep);
  1312. request_complete(ep, req, 0);
  1313. } else {
  1314. if (req->submitted)
  1315. next_fifo_transaction(ep, req);
  1316. else
  1317. submit_request(ep, req);
  1318. if (req->last_transaction) {
  1319. list_del_init(&req->queue);
  1320. submit_next_request(ep);
  1321. request_complete(ep, req, 0);
  1322. }
  1323. }
  1324. epstatus = usba_ep_readl(ep, STA);
  1325. epctrl = usba_ep_readl(ep, CTL);
  1326. }
  1327. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1328. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1329. receive_data(ep);
  1330. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1331. }
  1332. }
  1333. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1334. {
  1335. struct usba_request *req;
  1336. u32 status, control, pending;
  1337. status = usba_dma_readl(ep, STATUS);
  1338. control = usba_dma_readl(ep, CONTROL);
  1339. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1340. ep->last_dma_status = status;
  1341. #endif
  1342. pending = status & control;
  1343. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1344. if (status & USBA_DMA_CH_EN) {
  1345. dev_err(&udc->pdev->dev,
  1346. "DMA_CH_EN is set after transfer is finished!\n");
  1347. dev_err(&udc->pdev->dev,
  1348. "status=%#08x, pending=%#08x, control=%#08x\n",
  1349. status, pending, control);
  1350. /*
  1351. * try to pretend nothing happened. We might have to
  1352. * do something here...
  1353. */
  1354. }
  1355. if (list_empty(&ep->queue))
  1356. /* Might happen if a reset comes along at the right moment */
  1357. return;
  1358. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1359. req = list_entry(ep->queue.next, struct usba_request, queue);
  1360. usba_update_req(ep, req, status);
  1361. list_del_init(&req->queue);
  1362. submit_next_request(ep);
  1363. request_complete(ep, req, 0);
  1364. }
  1365. }
  1366. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1367. {
  1368. struct usba_udc *udc = devid;
  1369. u32 status;
  1370. u32 dma_status;
  1371. u32 ep_status;
  1372. spin_lock(&udc->lock);
  1373. status = usba_readl(udc, INT_STA);
  1374. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1375. if (status & USBA_DET_SUSPEND) {
  1376. toggle_bias(0);
  1377. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1378. DBG(DBG_BUS, "Suspend detected\n");
  1379. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1380. && udc->driver && udc->driver->suspend) {
  1381. spin_unlock(&udc->lock);
  1382. udc->driver->suspend(&udc->gadget);
  1383. spin_lock(&udc->lock);
  1384. }
  1385. }
  1386. if (status & USBA_WAKE_UP) {
  1387. toggle_bias(1);
  1388. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1389. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1390. }
  1391. if (status & USBA_END_OF_RESUME) {
  1392. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1393. DBG(DBG_BUS, "Resume detected\n");
  1394. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1395. && udc->driver && udc->driver->resume) {
  1396. spin_unlock(&udc->lock);
  1397. udc->driver->resume(&udc->gadget);
  1398. spin_lock(&udc->lock);
  1399. }
  1400. }
  1401. dma_status = USBA_BFEXT(DMA_INT, status);
  1402. if (dma_status) {
  1403. int i;
  1404. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1405. if (dma_status & (1 << i))
  1406. usba_dma_irq(udc, &usba_ep[i]);
  1407. }
  1408. ep_status = USBA_BFEXT(EPT_INT, status);
  1409. if (ep_status) {
  1410. int i;
  1411. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1412. if (ep_status & (1 << i)) {
  1413. if (ep_is_control(&usba_ep[i]))
  1414. usba_control_irq(udc, &usba_ep[i]);
  1415. else
  1416. usba_ep_irq(udc, &usba_ep[i]);
  1417. }
  1418. }
  1419. if (status & USBA_END_OF_RESET) {
  1420. struct usba_ep *ep0;
  1421. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1422. reset_all_endpoints(udc);
  1423. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1424. && udc->driver->disconnect) {
  1425. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1426. spin_unlock(&udc->lock);
  1427. udc->driver->disconnect(&udc->gadget);
  1428. spin_lock(&udc->lock);
  1429. }
  1430. if (status & USBA_HIGH_SPEED)
  1431. udc->gadget.speed = USB_SPEED_HIGH;
  1432. else
  1433. udc->gadget.speed = USB_SPEED_FULL;
  1434. DBG(DBG_BUS, "%s bus reset detected\n",
  1435. usb_speed_string(udc->gadget.speed));
  1436. ep0 = &usba_ep[0];
  1437. ep0->ep.desc = &usba_ep0_desc;
  1438. ep0->state = WAIT_FOR_SETUP;
  1439. usba_ep_writel(ep0, CFG,
  1440. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1441. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1442. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1443. usba_ep_writel(ep0, CTL_ENB,
  1444. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1445. usba_writel(udc, INT_ENB,
  1446. (usba_readl(udc, INT_ENB)
  1447. | USBA_BF(EPT_INT, 1)
  1448. | USBA_DET_SUSPEND
  1449. | USBA_END_OF_RESUME));
  1450. /*
  1451. * Unclear why we hit this irregularly, e.g. in usbtest,
  1452. * but it's clearly harmless...
  1453. */
  1454. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1455. dev_dbg(&udc->pdev->dev,
  1456. "ODD: EP0 configuration is invalid!\n");
  1457. }
  1458. spin_unlock(&udc->lock);
  1459. return IRQ_HANDLED;
  1460. }
  1461. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1462. {
  1463. struct usba_udc *udc = devid;
  1464. int vbus;
  1465. /* debounce */
  1466. udelay(10);
  1467. spin_lock(&udc->lock);
  1468. /* May happen if Vbus pin toggles during probe() */
  1469. if (!udc->driver)
  1470. goto out;
  1471. vbus = vbus_is_present(udc);
  1472. if (vbus != udc->vbus_prev) {
  1473. if (vbus) {
  1474. toggle_bias(1);
  1475. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1476. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1477. } else {
  1478. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1479. reset_all_endpoints(udc);
  1480. toggle_bias(0);
  1481. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1482. if (udc->driver->disconnect) {
  1483. spin_unlock(&udc->lock);
  1484. udc->driver->disconnect(&udc->gadget);
  1485. spin_lock(&udc->lock);
  1486. }
  1487. }
  1488. udc->vbus_prev = vbus;
  1489. }
  1490. out:
  1491. spin_unlock(&udc->lock);
  1492. return IRQ_HANDLED;
  1493. }
  1494. static int atmel_usba_start(struct usb_gadget *gadget,
  1495. struct usb_gadget_driver *driver)
  1496. {
  1497. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1498. unsigned long flags;
  1499. spin_lock_irqsave(&udc->lock, flags);
  1500. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1501. udc->driver = driver;
  1502. udc->gadget.dev.driver = &driver->driver;
  1503. spin_unlock_irqrestore(&udc->lock, flags);
  1504. clk_enable(udc->pclk);
  1505. clk_enable(udc->hclk);
  1506. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1507. udc->vbus_prev = 0;
  1508. if (gpio_is_valid(udc->vbus_pin))
  1509. enable_irq(gpio_to_irq(udc->vbus_pin));
  1510. /* If Vbus is present, enable the controller and wait for reset */
  1511. spin_lock_irqsave(&udc->lock, flags);
  1512. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1513. toggle_bias(1);
  1514. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1515. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1516. }
  1517. spin_unlock_irqrestore(&udc->lock, flags);
  1518. return 0;
  1519. }
  1520. static int atmel_usba_stop(struct usb_gadget *gadget,
  1521. struct usb_gadget_driver *driver)
  1522. {
  1523. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1524. unsigned long flags;
  1525. if (gpio_is_valid(udc->vbus_pin))
  1526. disable_irq(gpio_to_irq(udc->vbus_pin));
  1527. spin_lock_irqsave(&udc->lock, flags);
  1528. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1529. reset_all_endpoints(udc);
  1530. spin_unlock_irqrestore(&udc->lock, flags);
  1531. /* This will also disable the DP pullup */
  1532. toggle_bias(0);
  1533. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1534. udc->gadget.dev.driver = NULL;
  1535. udc->driver = NULL;
  1536. clk_disable(udc->hclk);
  1537. clk_disable(udc->pclk);
  1538. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1539. return 0;
  1540. }
  1541. static int __init usba_udc_probe(struct platform_device *pdev)
  1542. {
  1543. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1544. struct resource *regs, *fifo;
  1545. struct clk *pclk, *hclk;
  1546. struct usba_udc *udc = &the_udc;
  1547. int irq, ret, i;
  1548. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1549. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1550. if (!regs || !fifo || !pdata)
  1551. return -ENXIO;
  1552. irq = platform_get_irq(pdev, 0);
  1553. if (irq < 0)
  1554. return irq;
  1555. pclk = clk_get(&pdev->dev, "pclk");
  1556. if (IS_ERR(pclk))
  1557. return PTR_ERR(pclk);
  1558. hclk = clk_get(&pdev->dev, "hclk");
  1559. if (IS_ERR(hclk)) {
  1560. ret = PTR_ERR(hclk);
  1561. goto err_get_hclk;
  1562. }
  1563. spin_lock_init(&udc->lock);
  1564. udc->pdev = pdev;
  1565. udc->pclk = pclk;
  1566. udc->hclk = hclk;
  1567. udc->vbus_pin = -ENODEV;
  1568. ret = -ENOMEM;
  1569. udc->regs = ioremap(regs->start, resource_size(regs));
  1570. if (!udc->regs) {
  1571. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1572. goto err_map_regs;
  1573. }
  1574. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1575. (unsigned long)regs->start, udc->regs);
  1576. udc->fifo = ioremap(fifo->start, resource_size(fifo));
  1577. if (!udc->fifo) {
  1578. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1579. goto err_map_fifo;
  1580. }
  1581. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1582. (unsigned long)fifo->start, udc->fifo);
  1583. device_initialize(&udc->gadget.dev);
  1584. udc->gadget.dev.parent = &pdev->dev;
  1585. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1586. platform_set_drvdata(pdev, udc);
  1587. /* Make sure we start from a clean slate */
  1588. clk_enable(pclk);
  1589. toggle_bias(0);
  1590. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1591. clk_disable(pclk);
  1592. usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1593. GFP_KERNEL);
  1594. if (!usba_ep)
  1595. goto err_alloc_ep;
  1596. the_udc.gadget.ep0 = &usba_ep[0].ep;
  1597. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1598. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1599. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1600. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1601. usba_ep[0].ep.ops = &usba_ep_ops;
  1602. usba_ep[0].ep.name = pdata->ep[0].name;
  1603. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1604. usba_ep[0].udc = &the_udc;
  1605. INIT_LIST_HEAD(&usba_ep[0].queue);
  1606. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1607. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1608. usba_ep[0].index = pdata->ep[0].index;
  1609. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1610. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1611. for (i = 1; i < pdata->num_ep; i++) {
  1612. struct usba_ep *ep = &usba_ep[i];
  1613. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1614. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1615. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1616. ep->ep.ops = &usba_ep_ops;
  1617. ep->ep.name = pdata->ep[i].name;
  1618. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1619. ep->udc = &the_udc;
  1620. INIT_LIST_HEAD(&ep->queue);
  1621. ep->fifo_size = pdata->ep[i].fifo_size;
  1622. ep->nr_banks = pdata->ep[i].nr_banks;
  1623. ep->index = pdata->ep[i].index;
  1624. ep->can_dma = pdata->ep[i].can_dma;
  1625. ep->can_isoc = pdata->ep[i].can_isoc;
  1626. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1627. }
  1628. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1629. if (ret) {
  1630. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1631. irq, ret);
  1632. goto err_request_irq;
  1633. }
  1634. udc->irq = irq;
  1635. ret = device_add(&udc->gadget.dev);
  1636. if (ret) {
  1637. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1638. goto err_device_add;
  1639. }
  1640. if (gpio_is_valid(pdata->vbus_pin)) {
  1641. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1642. udc->vbus_pin = pdata->vbus_pin;
  1643. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1644. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1645. usba_vbus_irq, 0,
  1646. "atmel_usba_udc", udc);
  1647. if (ret) {
  1648. gpio_free(udc->vbus_pin);
  1649. udc->vbus_pin = -ENODEV;
  1650. dev_warn(&udc->pdev->dev,
  1651. "failed to request vbus irq; "
  1652. "assuming always on\n");
  1653. } else {
  1654. disable_irq(gpio_to_irq(udc->vbus_pin));
  1655. }
  1656. } else {
  1657. /* gpio_request fail so use -EINVAL for gpio_is_valid */
  1658. udc->vbus_pin = -EINVAL;
  1659. }
  1660. }
  1661. ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1662. if (ret)
  1663. goto err_add_udc;
  1664. usba_init_debugfs(udc);
  1665. for (i = 1; i < pdata->num_ep; i++)
  1666. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1667. return 0;
  1668. err_add_udc:
  1669. if (gpio_is_valid(pdata->vbus_pin)) {
  1670. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1671. gpio_free(udc->vbus_pin);
  1672. }
  1673. device_unregister(&udc->gadget.dev);
  1674. err_device_add:
  1675. free_irq(irq, udc);
  1676. err_request_irq:
  1677. kfree(usba_ep);
  1678. err_alloc_ep:
  1679. iounmap(udc->fifo);
  1680. err_map_fifo:
  1681. iounmap(udc->regs);
  1682. err_map_regs:
  1683. clk_put(hclk);
  1684. err_get_hclk:
  1685. clk_put(pclk);
  1686. platform_set_drvdata(pdev, NULL);
  1687. return ret;
  1688. }
  1689. static int __exit usba_udc_remove(struct platform_device *pdev)
  1690. {
  1691. struct usba_udc *udc;
  1692. int i;
  1693. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1694. udc = platform_get_drvdata(pdev);
  1695. usb_del_gadget_udc(&udc->gadget);
  1696. for (i = 1; i < pdata->num_ep; i++)
  1697. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1698. usba_cleanup_debugfs(udc);
  1699. if (gpio_is_valid(udc->vbus_pin)) {
  1700. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1701. gpio_free(udc->vbus_pin);
  1702. }
  1703. free_irq(udc->irq, udc);
  1704. kfree(usba_ep);
  1705. iounmap(udc->fifo);
  1706. iounmap(udc->regs);
  1707. clk_put(udc->hclk);
  1708. clk_put(udc->pclk);
  1709. device_unregister(&udc->gadget.dev);
  1710. return 0;
  1711. }
  1712. static struct platform_driver udc_driver = {
  1713. .remove = __exit_p(usba_udc_remove),
  1714. .driver = {
  1715. .name = "atmel_usba_udc",
  1716. .owner = THIS_MODULE,
  1717. },
  1718. };
  1719. module_platform_driver_probe(udc_driver, usba_udc_probe);
  1720. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1721. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1722. MODULE_LICENSE("GPL");
  1723. MODULE_ALIAS("platform:atmel_usba_udc");