vt8500_serial.c 17 KB

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  1. /*
  2. * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  3. *
  4. * Based on msm_serial.c, which is:
  5. * Copyright (C) 2007 Google, Inc.
  6. * Author: Robert Love <rlove@google.com>
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18. # define SUPPORT_SYSRQ
  19. #endif
  20. #include <linux/hrtimer.h>
  21. #include <linux/delay.h>
  22. #include <linux/module.h>
  23. #include <linux/io.h>
  24. #include <linux/ioport.h>
  25. #include <linux/irq.h>
  26. #include <linux/init.h>
  27. #include <linux/console.h>
  28. #include <linux/tty.h>
  29. #include <linux/tty_flip.h>
  30. #include <linux/serial_core.h>
  31. #include <linux/serial.h>
  32. #include <linux/slab.h>
  33. #include <linux/clk.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/of.h>
  36. /*
  37. * UART Register offsets
  38. */
  39. #define VT8500_URTDR 0x0000 /* Transmit data */
  40. #define VT8500_URRDR 0x0004 /* Receive data */
  41. #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
  42. #define VT8500_URLCR 0x000C /* Line control */
  43. #define VT8500_URICR 0x0010 /* IrDA control */
  44. #define VT8500_URIER 0x0014 /* Interrupt enable */
  45. #define VT8500_URISR 0x0018 /* Interrupt status */
  46. #define VT8500_URUSR 0x001c /* UART status */
  47. #define VT8500_URFCR 0x0020 /* FIFO control */
  48. #define VT8500_URFIDX 0x0024 /* FIFO index */
  49. #define VT8500_URBKR 0x0028 /* Break signal count */
  50. #define VT8500_URTOD 0x002c /* Time out divisor */
  51. #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
  52. #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
  53. /*
  54. * Interrupt enable and status bits
  55. */
  56. #define TXDE (1 << 0) /* Tx Data empty */
  57. #define RXDF (1 << 1) /* Rx Data full */
  58. #define TXFAE (1 << 2) /* Tx FIFO almost empty */
  59. #define TXFE (1 << 3) /* Tx FIFO empty */
  60. #define RXFAF (1 << 4) /* Rx FIFO almost full */
  61. #define RXFF (1 << 5) /* Rx FIFO full */
  62. #define TXUDR (1 << 6) /* Tx underrun */
  63. #define RXOVER (1 << 7) /* Rx overrun */
  64. #define PER (1 << 8) /* Parity error */
  65. #define FER (1 << 9) /* Frame error */
  66. #define TCTS (1 << 10) /* Toggle of CTS */
  67. #define RXTOUT (1 << 11) /* Rx timeout */
  68. #define BKDONE (1 << 12) /* Break signal done */
  69. #define ERR (1 << 13) /* AHB error response */
  70. #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
  71. #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
  72. #define VT8500_MAX_PORTS 6
  73. struct vt8500_port {
  74. struct uart_port uart;
  75. char name[16];
  76. struct clk *clk;
  77. unsigned int ier;
  78. };
  79. /*
  80. * we use this variable to keep track of which ports
  81. * have been allocated as we can't use pdev->id in
  82. * devicetree
  83. */
  84. static unsigned long vt8500_ports_in_use;
  85. static inline void vt8500_write(struct uart_port *port, unsigned int val,
  86. unsigned int off)
  87. {
  88. writel(val, port->membase + off);
  89. }
  90. static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
  91. {
  92. return readl(port->membase + off);
  93. }
  94. static void vt8500_stop_tx(struct uart_port *port)
  95. {
  96. struct vt8500_port *vt8500_port = container_of(port,
  97. struct vt8500_port,
  98. uart);
  99. vt8500_port->ier &= ~TX_FIFO_INTS;
  100. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  101. }
  102. static void vt8500_stop_rx(struct uart_port *port)
  103. {
  104. struct vt8500_port *vt8500_port = container_of(port,
  105. struct vt8500_port,
  106. uart);
  107. vt8500_port->ier &= ~RX_FIFO_INTS;
  108. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  109. }
  110. static void vt8500_enable_ms(struct uart_port *port)
  111. {
  112. struct vt8500_port *vt8500_port = container_of(port,
  113. struct vt8500_port,
  114. uart);
  115. vt8500_port->ier |= TCTS;
  116. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  117. }
  118. static void handle_rx(struct uart_port *port)
  119. {
  120. struct tty_port *tport = &port->state->port;
  121. /*
  122. * Handle overrun
  123. */
  124. if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
  125. port->icount.overrun++;
  126. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  127. }
  128. /* and now the main RX loop */
  129. while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
  130. unsigned int c;
  131. char flag = TTY_NORMAL;
  132. c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
  133. /* Mask conditions we're ignorning. */
  134. c &= ~port->read_status_mask;
  135. if (c & FER) {
  136. port->icount.frame++;
  137. flag = TTY_FRAME;
  138. } else if (c & PER) {
  139. port->icount.parity++;
  140. flag = TTY_PARITY;
  141. }
  142. port->icount.rx++;
  143. if (!uart_handle_sysrq_char(port, c))
  144. tty_insert_flip_char(tport, c, flag);
  145. }
  146. tty_flip_buffer_push(tport);
  147. }
  148. static void handle_tx(struct uart_port *port)
  149. {
  150. struct circ_buf *xmit = &port->state->xmit;
  151. if (port->x_char) {
  152. writeb(port->x_char, port->membase + VT8500_TXFIFO);
  153. port->icount.tx++;
  154. port->x_char = 0;
  155. }
  156. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  157. vt8500_stop_tx(port);
  158. return;
  159. }
  160. while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
  161. if (uart_circ_empty(xmit))
  162. break;
  163. writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
  164. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  165. port->icount.tx++;
  166. }
  167. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  168. uart_write_wakeup(port);
  169. if (uart_circ_empty(xmit))
  170. vt8500_stop_tx(port);
  171. }
  172. static void vt8500_start_tx(struct uart_port *port)
  173. {
  174. struct vt8500_port *vt8500_port = container_of(port,
  175. struct vt8500_port,
  176. uart);
  177. vt8500_port->ier &= ~TX_FIFO_INTS;
  178. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  179. handle_tx(port);
  180. vt8500_port->ier |= TX_FIFO_INTS;
  181. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  182. }
  183. static void handle_delta_cts(struct uart_port *port)
  184. {
  185. port->icount.cts++;
  186. wake_up_interruptible(&port->state->port.delta_msr_wait);
  187. }
  188. static irqreturn_t vt8500_irq(int irq, void *dev_id)
  189. {
  190. struct uart_port *port = dev_id;
  191. unsigned long isr;
  192. spin_lock(&port->lock);
  193. isr = vt8500_read(port, VT8500_URISR);
  194. /* Acknowledge active status bits */
  195. vt8500_write(port, isr, VT8500_URISR);
  196. if (isr & RX_FIFO_INTS)
  197. handle_rx(port);
  198. if (isr & TX_FIFO_INTS)
  199. handle_tx(port);
  200. if (isr & TCTS)
  201. handle_delta_cts(port);
  202. spin_unlock(&port->lock);
  203. return IRQ_HANDLED;
  204. }
  205. static unsigned int vt8500_tx_empty(struct uart_port *port)
  206. {
  207. return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
  208. TIOCSER_TEMT : 0;
  209. }
  210. static unsigned int vt8500_get_mctrl(struct uart_port *port)
  211. {
  212. unsigned int usr;
  213. usr = vt8500_read(port, VT8500_URUSR);
  214. if (usr & (1 << 4))
  215. return TIOCM_CTS;
  216. else
  217. return 0;
  218. }
  219. static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
  220. {
  221. }
  222. static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
  223. {
  224. if (break_ctl)
  225. vt8500_write(port, vt8500_read(port, VT8500_URLCR) | (1 << 9),
  226. VT8500_URLCR);
  227. }
  228. static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
  229. {
  230. unsigned long div;
  231. unsigned int loops = 1000;
  232. div = vt8500_read(port, VT8500_URDIV) & ~(0x3ff);
  233. if (unlikely((baud < 900) || (baud > 921600)))
  234. div |= 7;
  235. else
  236. div |= (921600 / baud) - 1;
  237. while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
  238. cpu_relax();
  239. vt8500_write(port, div, VT8500_URDIV);
  240. return baud;
  241. }
  242. static int vt8500_startup(struct uart_port *port)
  243. {
  244. struct vt8500_port *vt8500_port =
  245. container_of(port, struct vt8500_port, uart);
  246. int ret;
  247. snprintf(vt8500_port->name, sizeof(vt8500_port->name),
  248. "vt8500_serial%d", port->line);
  249. ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
  250. vt8500_port->name, port);
  251. if (unlikely(ret))
  252. return ret;
  253. vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
  254. return 0;
  255. }
  256. static void vt8500_shutdown(struct uart_port *port)
  257. {
  258. struct vt8500_port *vt8500_port =
  259. container_of(port, struct vt8500_port, uart);
  260. vt8500_port->ier = 0;
  261. /* disable interrupts and FIFOs */
  262. vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
  263. vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
  264. free_irq(port->irq, port);
  265. }
  266. static void vt8500_set_termios(struct uart_port *port,
  267. struct ktermios *termios,
  268. struct ktermios *old)
  269. {
  270. struct vt8500_port *vt8500_port =
  271. container_of(port, struct vt8500_port, uart);
  272. unsigned long flags;
  273. unsigned int baud, lcr;
  274. unsigned int loops = 1000;
  275. spin_lock_irqsave(&port->lock, flags);
  276. /* calculate and set baud rate */
  277. baud = uart_get_baud_rate(port, termios, old, 900, 921600);
  278. baud = vt8500_set_baud_rate(port, baud);
  279. if (tty_termios_baud_rate(termios))
  280. tty_termios_encode_baud_rate(termios, baud, baud);
  281. /* calculate parity */
  282. lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
  283. lcr &= ~((1 << 5) | (1 << 4));
  284. if (termios->c_cflag & PARENB) {
  285. lcr |= (1 << 4);
  286. termios->c_cflag &= ~CMSPAR;
  287. if (termios->c_cflag & PARODD)
  288. lcr |= (1 << 5);
  289. }
  290. /* calculate bits per char */
  291. lcr &= ~(1 << 2);
  292. switch (termios->c_cflag & CSIZE) {
  293. case CS7:
  294. break;
  295. case CS8:
  296. default:
  297. lcr |= (1 << 2);
  298. termios->c_cflag &= ~CSIZE;
  299. termios->c_cflag |= CS8;
  300. break;
  301. }
  302. /* calculate stop bits */
  303. lcr &= ~(1 << 3);
  304. if (termios->c_cflag & CSTOPB)
  305. lcr |= (1 << 3);
  306. /* set parity, bits per char, and stop bit */
  307. vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
  308. /* Configure status bits to ignore based on termio flags. */
  309. port->read_status_mask = 0;
  310. if (termios->c_iflag & IGNPAR)
  311. port->read_status_mask = FER | PER;
  312. uart_update_timeout(port, termios->c_cflag, baud);
  313. /* Reset FIFOs */
  314. vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
  315. while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
  316. && --loops)
  317. cpu_relax();
  318. /* Every possible FIFO-related interrupt */
  319. vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
  320. /*
  321. * CTS flow control
  322. */
  323. if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
  324. vt8500_port->ier |= TCTS;
  325. vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
  326. vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
  327. spin_unlock_irqrestore(&port->lock, flags);
  328. }
  329. static const char *vt8500_type(struct uart_port *port)
  330. {
  331. struct vt8500_port *vt8500_port =
  332. container_of(port, struct vt8500_port, uart);
  333. return vt8500_port->name;
  334. }
  335. static void vt8500_release_port(struct uart_port *port)
  336. {
  337. }
  338. static int vt8500_request_port(struct uart_port *port)
  339. {
  340. return 0;
  341. }
  342. static void vt8500_config_port(struct uart_port *port, int flags)
  343. {
  344. port->type = PORT_VT8500;
  345. }
  346. static int vt8500_verify_port(struct uart_port *port,
  347. struct serial_struct *ser)
  348. {
  349. if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
  350. return -EINVAL;
  351. if (unlikely(port->irq != ser->irq))
  352. return -EINVAL;
  353. return 0;
  354. }
  355. static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
  356. static struct uart_driver vt8500_uart_driver;
  357. #ifdef CONFIG_SERIAL_VT8500_CONSOLE
  358. static inline void wait_for_xmitr(struct uart_port *port)
  359. {
  360. unsigned int status, tmout = 10000;
  361. /* Wait up to 10ms for the character(s) to be sent. */
  362. do {
  363. status = vt8500_read(port, VT8500_URFIDX);
  364. if (--tmout == 0)
  365. break;
  366. udelay(1);
  367. } while (status & 0x10);
  368. }
  369. static void vt8500_console_putchar(struct uart_port *port, int c)
  370. {
  371. wait_for_xmitr(port);
  372. writeb(c, port->membase + VT8500_TXFIFO);
  373. }
  374. static void vt8500_console_write(struct console *co, const char *s,
  375. unsigned int count)
  376. {
  377. struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
  378. unsigned long ier;
  379. BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
  380. ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
  381. vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
  382. uart_console_write(&vt8500_port->uart, s, count,
  383. vt8500_console_putchar);
  384. /*
  385. * Finally, wait for transmitter to become empty
  386. * and switch back to FIFO
  387. */
  388. wait_for_xmitr(&vt8500_port->uart);
  389. vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
  390. }
  391. static int __init vt8500_console_setup(struct console *co, char *options)
  392. {
  393. struct vt8500_port *vt8500_port;
  394. int baud = 9600;
  395. int bits = 8;
  396. int parity = 'n';
  397. int flow = 'n';
  398. if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
  399. return -ENXIO;
  400. vt8500_port = vt8500_uart_ports[co->index];
  401. if (!vt8500_port)
  402. return -ENODEV;
  403. if (options)
  404. uart_parse_options(options, &baud, &parity, &bits, &flow);
  405. return uart_set_options(&vt8500_port->uart,
  406. co, baud, parity, bits, flow);
  407. }
  408. static struct console vt8500_console = {
  409. .name = "ttyWMT",
  410. .write = vt8500_console_write,
  411. .device = uart_console_device,
  412. .setup = vt8500_console_setup,
  413. .flags = CON_PRINTBUFFER,
  414. .index = -1,
  415. .data = &vt8500_uart_driver,
  416. };
  417. #define VT8500_CONSOLE (&vt8500_console)
  418. #else
  419. #define VT8500_CONSOLE NULL
  420. #endif
  421. static struct uart_ops vt8500_uart_pops = {
  422. .tx_empty = vt8500_tx_empty,
  423. .set_mctrl = vt8500_set_mctrl,
  424. .get_mctrl = vt8500_get_mctrl,
  425. .stop_tx = vt8500_stop_tx,
  426. .start_tx = vt8500_start_tx,
  427. .stop_rx = vt8500_stop_rx,
  428. .enable_ms = vt8500_enable_ms,
  429. .break_ctl = vt8500_break_ctl,
  430. .startup = vt8500_startup,
  431. .shutdown = vt8500_shutdown,
  432. .set_termios = vt8500_set_termios,
  433. .type = vt8500_type,
  434. .release_port = vt8500_release_port,
  435. .request_port = vt8500_request_port,
  436. .config_port = vt8500_config_port,
  437. .verify_port = vt8500_verify_port,
  438. };
  439. static struct uart_driver vt8500_uart_driver = {
  440. .owner = THIS_MODULE,
  441. .driver_name = "vt8500_serial",
  442. .dev_name = "ttyWMT",
  443. .nr = 6,
  444. .cons = VT8500_CONSOLE,
  445. };
  446. static int vt8500_serial_probe(struct platform_device *pdev)
  447. {
  448. struct vt8500_port *vt8500_port;
  449. struct resource *mmres, *irqres;
  450. struct device_node *np = pdev->dev.of_node;
  451. int ret;
  452. int port;
  453. mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  454. irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  455. if (!mmres || !irqres)
  456. return -ENODEV;
  457. if (np)
  458. port = of_alias_get_id(np, "serial");
  459. if (port >= VT8500_MAX_PORTS)
  460. port = -1;
  461. else
  462. port = -1;
  463. if (port < 0) {
  464. /* calculate the port id */
  465. port = find_first_zero_bit(&vt8500_ports_in_use,
  466. sizeof(vt8500_ports_in_use));
  467. }
  468. if (port >= VT8500_MAX_PORTS)
  469. return -ENODEV;
  470. /* reserve the port id */
  471. if (test_and_set_bit(port, &vt8500_ports_in_use)) {
  472. /* port already in use - shouldn't really happen */
  473. return -EBUSY;
  474. }
  475. vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
  476. GFP_KERNEL);
  477. if (!vt8500_port)
  478. return -ENOMEM;
  479. vt8500_port->uart.membase = devm_request_and_ioremap(&pdev->dev, mmres);
  480. if (!vt8500_port->uart.membase)
  481. return -EADDRNOTAVAIL;
  482. vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
  483. if (IS_ERR(vt8500_port->clk)) {
  484. dev_err(&pdev->dev, "failed to get clock\n");
  485. return -EINVAL;
  486. }
  487. ret = clk_prepare_enable(vt8500_port->clk);
  488. if (ret) {
  489. dev_err(&pdev->dev, "failed to enable clock\n");
  490. return ret;
  491. }
  492. vt8500_port->uart.type = PORT_VT8500;
  493. vt8500_port->uart.iotype = UPIO_MEM;
  494. vt8500_port->uart.mapbase = mmres->start;
  495. vt8500_port->uart.irq = irqres->start;
  496. vt8500_port->uart.fifosize = 16;
  497. vt8500_port->uart.ops = &vt8500_uart_pops;
  498. vt8500_port->uart.line = port;
  499. vt8500_port->uart.dev = &pdev->dev;
  500. vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
  501. vt8500_port->uart.uartclk = clk_get_rate(vt8500_port->clk);
  502. snprintf(vt8500_port->name, sizeof(vt8500_port->name),
  503. "VT8500 UART%d", pdev->id);
  504. vt8500_uart_ports[port] = vt8500_port;
  505. uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
  506. platform_set_drvdata(pdev, vt8500_port);
  507. return 0;
  508. }
  509. static int vt8500_serial_remove(struct platform_device *pdev)
  510. {
  511. struct vt8500_port *vt8500_port = platform_get_drvdata(pdev);
  512. platform_set_drvdata(pdev, NULL);
  513. clk_disable_unprepare(vt8500_port->clk);
  514. uart_remove_one_port(&vt8500_uart_driver, &vt8500_port->uart);
  515. return 0;
  516. }
  517. static const struct of_device_id wmt_dt_ids[] = {
  518. { .compatible = "via,vt8500-uart", },
  519. {}
  520. };
  521. static struct platform_driver vt8500_platform_driver = {
  522. .probe = vt8500_serial_probe,
  523. .remove = vt8500_serial_remove,
  524. .driver = {
  525. .name = "vt8500_serial",
  526. .owner = THIS_MODULE,
  527. .of_match_table = of_match_ptr(wmt_dt_ids),
  528. },
  529. };
  530. static int __init vt8500_serial_init(void)
  531. {
  532. int ret;
  533. ret = uart_register_driver(&vt8500_uart_driver);
  534. if (unlikely(ret))
  535. return ret;
  536. ret = platform_driver_register(&vt8500_platform_driver);
  537. if (unlikely(ret))
  538. uart_unregister_driver(&vt8500_uart_driver);
  539. return ret;
  540. }
  541. static void __exit vt8500_serial_exit(void)
  542. {
  543. #ifdef CONFIG_SERIAL_VT8500_CONSOLE
  544. unregister_console(&vt8500_console);
  545. #endif
  546. platform_driver_unregister(&vt8500_platform_driver);
  547. uart_unregister_driver(&vt8500_uart_driver);
  548. }
  549. module_init(vt8500_serial_init);
  550. module_exit(vt8500_serial_exit);
  551. MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
  552. MODULE_DESCRIPTION("Driver for vt8500 serial device");
  553. MODULE_LICENSE("GPL v2");