sirfsoc_uart.c 22 KB

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  1. /*
  2. * Driver for CSR SiRFprimaII onboard UARTs.
  3. *
  4. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/ioport.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/sysrq.h>
  13. #include <linux/console.h>
  14. #include <linux/tty.h>
  15. #include <linux/tty_flip.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/serial.h>
  18. #include <linux/clk.h>
  19. #include <linux/of.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. #include <asm/irq.h>
  23. #include <asm/mach/irq.h>
  24. #include <linux/pinctrl/consumer.h>
  25. #include "sirfsoc_uart.h"
  26. static unsigned int
  27. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
  28. static unsigned int
  29. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
  30. static struct uart_driver sirfsoc_uart_drv;
  31. static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
  32. {4000000, 2359296},
  33. {3500000, 1310721},
  34. {3000000, 1572865},
  35. {2500000, 1245186},
  36. {2000000, 1572866},
  37. {1500000, 1245188},
  38. {1152000, 1638404},
  39. {1000000, 1572869},
  40. {921600, 1114120},
  41. {576000, 1245196},
  42. {500000, 1245198},
  43. {460800, 1572876},
  44. {230400, 1310750},
  45. {115200, 1310781},
  46. {57600, 1310843},
  47. {38400, 1114328},
  48. {19200, 1114545},
  49. {9600, 1114979},
  50. };
  51. static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
  52. [0] = {
  53. .port = {
  54. .iotype = UPIO_MEM,
  55. .flags = UPF_BOOT_AUTOCONF,
  56. .line = 0,
  57. },
  58. },
  59. [1] = {
  60. .port = {
  61. .iotype = UPIO_MEM,
  62. .flags = UPF_BOOT_AUTOCONF,
  63. .line = 1,
  64. },
  65. },
  66. [2] = {
  67. .port = {
  68. .iotype = UPIO_MEM,
  69. .flags = UPF_BOOT_AUTOCONF,
  70. .line = 2,
  71. },
  72. },
  73. [3] = {
  74. .port = {
  75. .iotype = UPIO_MEM,
  76. .flags = UPF_BOOT_AUTOCONF,
  77. .line = 3,
  78. },
  79. },
  80. [4] = {
  81. .port = {
  82. .iotype = UPIO_MEM,
  83. .flags = UPF_BOOT_AUTOCONF,
  84. .line = 4,
  85. },
  86. },
  87. };
  88. static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
  89. {
  90. return container_of(port, struct sirfsoc_uart_port, port);
  91. }
  92. static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
  93. {
  94. unsigned long reg;
  95. reg = rd_regl(port, SIRFUART_TX_FIFO_STATUS);
  96. if (reg & SIRFUART_FIFOEMPTY_MASK(port))
  97. return TIOCSER_TEMT;
  98. else
  99. return 0;
  100. }
  101. static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
  102. {
  103. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  104. if (!(sirfport->ms_enabled)) {
  105. goto cts_asserted;
  106. } else if (sirfport->hw_flow_ctrl) {
  107. if (!(rd_regl(port, SIRFUART_AFC_CTRL) &
  108. SIRFUART_CTS_IN_STATUS))
  109. goto cts_asserted;
  110. else
  111. goto cts_deasserted;
  112. }
  113. cts_deasserted:
  114. return TIOCM_CAR | TIOCM_DSR;
  115. cts_asserted:
  116. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  117. }
  118. static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  119. {
  120. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  121. unsigned int assert = mctrl & TIOCM_RTS;
  122. unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
  123. unsigned int current_val;
  124. if (sirfport->hw_flow_ctrl) {
  125. current_val = rd_regl(port, SIRFUART_AFC_CTRL) & ~0xFF;
  126. val |= current_val;
  127. wr_regl(port, SIRFUART_AFC_CTRL, val);
  128. }
  129. }
  130. static void sirfsoc_uart_stop_tx(struct uart_port *port)
  131. {
  132. unsigned int regv;
  133. regv = rd_regl(port, SIRFUART_INT_EN);
  134. wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN);
  135. }
  136. void sirfsoc_uart_start_tx(struct uart_port *port)
  137. {
  138. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  139. unsigned long regv;
  140. sirfsoc_uart_pio_tx_chars(sirfport, 1);
  141. wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START);
  142. regv = rd_regl(port, SIRFUART_INT_EN);
  143. wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN);
  144. }
  145. static void sirfsoc_uart_stop_rx(struct uart_port *port)
  146. {
  147. unsigned long regv;
  148. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  149. regv = rd_regl(port, SIRFUART_INT_EN);
  150. wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN);
  151. }
  152. static void sirfsoc_uart_disable_ms(struct uart_port *port)
  153. {
  154. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  155. unsigned long reg;
  156. sirfport->ms_enabled = 0;
  157. if (!sirfport->hw_flow_ctrl)
  158. return;
  159. reg = rd_regl(port, SIRFUART_AFC_CTRL);
  160. wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF);
  161. reg = rd_regl(port, SIRFUART_INT_EN);
  162. wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN);
  163. }
  164. static void sirfsoc_uart_enable_ms(struct uart_port *port)
  165. {
  166. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  167. unsigned long reg;
  168. unsigned long flg;
  169. if (!sirfport->hw_flow_ctrl)
  170. return;
  171. flg = SIRFUART_AFC_RX_EN | SIRFUART_AFC_TX_EN;
  172. reg = rd_regl(port, SIRFUART_AFC_CTRL);
  173. wr_regl(port, SIRFUART_AFC_CTRL, reg | flg);
  174. reg = rd_regl(port, SIRFUART_INT_EN);
  175. wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN);
  176. uart_handle_cts_change(port,
  177. !(rd_regl(port, SIRFUART_AFC_CTRL) & SIRFUART_CTS_IN_STATUS));
  178. sirfport->ms_enabled = 1;
  179. }
  180. static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
  181. {
  182. unsigned long ulcon = rd_regl(port, SIRFUART_LINE_CTRL);
  183. if (break_state)
  184. ulcon |= SIRFUART_SET_BREAK;
  185. else
  186. ulcon &= ~SIRFUART_SET_BREAK;
  187. wr_regl(port, SIRFUART_LINE_CTRL, ulcon);
  188. }
  189. static unsigned int
  190. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
  191. {
  192. unsigned int ch, rx_count = 0;
  193. while (!(rd_regl(port, SIRFUART_RX_FIFO_STATUS) &
  194. SIRFUART_FIFOEMPTY_MASK(port))) {
  195. ch = rd_regl(port, SIRFUART_RX_FIFO_DATA) | SIRFUART_DUMMY_READ;
  196. if (unlikely(uart_handle_sysrq_char(port, ch)))
  197. continue;
  198. uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
  199. rx_count++;
  200. if (rx_count >= max_rx_count)
  201. break;
  202. }
  203. port->icount.rx += rx_count;
  204. tty_flip_buffer_push(&port->state->port);
  205. return rx_count;
  206. }
  207. static unsigned int
  208. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
  209. {
  210. struct uart_port *port = &sirfport->port;
  211. struct circ_buf *xmit = &port->state->xmit;
  212. unsigned int num_tx = 0;
  213. while (!uart_circ_empty(xmit) &&
  214. !(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
  215. SIRFUART_FIFOFULL_MASK(port)) &&
  216. count--) {
  217. wr_regl(port, SIRFUART_TX_FIFO_DATA, xmit->buf[xmit->tail]);
  218. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  219. port->icount.tx++;
  220. num_tx++;
  221. }
  222. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  223. uart_write_wakeup(port);
  224. return num_tx;
  225. }
  226. static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
  227. {
  228. unsigned long intr_status;
  229. unsigned long cts_status;
  230. unsigned long flag = TTY_NORMAL;
  231. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
  232. struct uart_port *port = &sirfport->port;
  233. struct uart_state *state = port->state;
  234. struct circ_buf *xmit = &port->state->xmit;
  235. spin_lock(&port->lock);
  236. intr_status = rd_regl(port, SIRFUART_INT_STATUS);
  237. wr_regl(port, SIRFUART_INT_STATUS, intr_status);
  238. intr_status &= rd_regl(port, SIRFUART_INT_EN);
  239. if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
  240. if (intr_status & SIRFUART_RXD_BREAK) {
  241. if (uart_handle_break(port))
  242. goto recv_char;
  243. uart_insert_char(port, intr_status,
  244. SIRFUART_RX_OFLOW, 0, TTY_BREAK);
  245. spin_unlock(&port->lock);
  246. return IRQ_HANDLED;
  247. }
  248. if (intr_status & SIRFUART_RX_OFLOW)
  249. port->icount.overrun++;
  250. if (intr_status & SIRFUART_FRM_ERR) {
  251. port->icount.frame++;
  252. flag = TTY_FRAME;
  253. }
  254. if (intr_status & SIRFUART_PARITY_ERR)
  255. flag = TTY_PARITY;
  256. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
  257. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  258. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
  259. intr_status &= port->read_status_mask;
  260. uart_insert_char(port, intr_status,
  261. SIRFUART_RX_OFLOW_INT, 0, flag);
  262. }
  263. recv_char:
  264. if (intr_status & SIRFUART_CTS_INT_EN) {
  265. cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
  266. SIRFUART_CTS_IN_STATUS);
  267. if (cts_status != 0) {
  268. uart_handle_cts_change(port, 1);
  269. } else {
  270. uart_handle_cts_change(port, 0);
  271. wake_up_interruptible(&state->port.delta_msr_wait);
  272. }
  273. }
  274. if (intr_status & SIRFUART_RX_IO_INT_EN)
  275. sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
  276. if (intr_status & SIRFUART_TX_INT_EN) {
  277. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  278. spin_unlock(&port->lock);
  279. return IRQ_HANDLED;
  280. } else {
  281. sirfsoc_uart_pio_tx_chars(sirfport,
  282. SIRFSOC_UART_IO_TX_REASONABLE_CNT);
  283. if ((uart_circ_empty(xmit)) &&
  284. (rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
  285. SIRFUART_FIFOEMPTY_MASK(port)))
  286. sirfsoc_uart_stop_tx(port);
  287. }
  288. }
  289. spin_unlock(&port->lock);
  290. return IRQ_HANDLED;
  291. }
  292. static void sirfsoc_uart_start_rx(struct uart_port *port)
  293. {
  294. unsigned long regv;
  295. regv = rd_regl(port, SIRFUART_INT_EN);
  296. wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_RX_IO_INT_EN);
  297. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
  298. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  299. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
  300. }
  301. static unsigned int
  302. sirfsoc_calc_sample_div(unsigned long baud_rate,
  303. unsigned long ioclk_rate, unsigned long *setted_baud)
  304. {
  305. unsigned long min_delta = ~0UL;
  306. unsigned short sample_div;
  307. unsigned int regv = 0;
  308. unsigned long ioclk_div;
  309. unsigned long baud_tmp;
  310. int temp_delta;
  311. for (sample_div = SIRF_MIN_SAMPLE_DIV;
  312. sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
  313. ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
  314. if (ioclk_div > SIRF_IOCLK_DIV_MAX)
  315. continue;
  316. baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
  317. temp_delta = baud_tmp - baud_rate;
  318. temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
  319. if (temp_delta < min_delta) {
  320. regv = regv & (~SIRF_IOCLK_DIV_MASK);
  321. regv = regv | ioclk_div;
  322. regv = regv & (~SIRF_SAMPLE_DIV_MASK);
  323. regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
  324. min_delta = temp_delta;
  325. *setted_baud = baud_tmp;
  326. }
  327. }
  328. return regv;
  329. }
  330. static void sirfsoc_uart_set_termios(struct uart_port *port,
  331. struct ktermios *termios,
  332. struct ktermios *old)
  333. {
  334. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  335. unsigned long config_reg = 0;
  336. unsigned long baud_rate;
  337. unsigned long setted_baud;
  338. unsigned long flags;
  339. unsigned long ic;
  340. unsigned int clk_div_reg = 0;
  341. unsigned long temp_reg_val;
  342. unsigned long rx_time_out;
  343. int threshold_div;
  344. int temp;
  345. switch (termios->c_cflag & CSIZE) {
  346. default:
  347. case CS8:
  348. config_reg |= SIRFUART_DATA_BIT_LEN_8;
  349. break;
  350. case CS7:
  351. config_reg |= SIRFUART_DATA_BIT_LEN_7;
  352. break;
  353. case CS6:
  354. config_reg |= SIRFUART_DATA_BIT_LEN_6;
  355. break;
  356. case CS5:
  357. config_reg |= SIRFUART_DATA_BIT_LEN_5;
  358. break;
  359. }
  360. if (termios->c_cflag & CSTOPB)
  361. config_reg |= SIRFUART_STOP_BIT_LEN_2;
  362. baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
  363. spin_lock_irqsave(&port->lock, flags);
  364. port->read_status_mask = SIRFUART_RX_OFLOW_INT;
  365. port->ignore_status_mask = 0;
  366. /* read flags */
  367. if (termios->c_iflag & INPCK)
  368. port->read_status_mask |=
  369. SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
  370. if (termios->c_iflag & (BRKINT | PARMRK))
  371. port->read_status_mask |= SIRFUART_RXD_BREAK_INT;
  372. /* ignore flags */
  373. if (termios->c_iflag & IGNPAR)
  374. port->ignore_status_mask |=
  375. SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
  376. if ((termios->c_cflag & CREAD) == 0)
  377. port->ignore_status_mask |= SIRFUART_DUMMY_READ;
  378. /* enable parity if PARENB is set*/
  379. if (termios->c_cflag & PARENB) {
  380. if (termios->c_cflag & CMSPAR) {
  381. if (termios->c_cflag & PARODD)
  382. config_reg |= SIRFUART_STICK_BIT_MARK;
  383. else
  384. config_reg |= SIRFUART_STICK_BIT_SPACE;
  385. } else if (termios->c_cflag & PARODD) {
  386. config_reg |= SIRFUART_STICK_BIT_ODD;
  387. } else {
  388. config_reg |= SIRFUART_STICK_BIT_EVEN;
  389. }
  390. }
  391. /* Hardware Flow Control Settings */
  392. if (UART_ENABLE_MS(port, termios->c_cflag)) {
  393. if (!sirfport->ms_enabled)
  394. sirfsoc_uart_enable_ms(port);
  395. } else {
  396. if (sirfport->ms_enabled)
  397. sirfsoc_uart_disable_ms(port);
  398. }
  399. if (port->uartclk == 150000000) {
  400. /* common rate: fast calculation */
  401. for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
  402. if (baud_rate == baudrate_to_regv[ic].baud_rate)
  403. clk_div_reg = baudrate_to_regv[ic].reg_val;
  404. }
  405. setted_baud = baud_rate;
  406. /* arbitary rate setting */
  407. if (unlikely(clk_div_reg == 0))
  408. clk_div_reg = sirfsoc_calc_sample_div(baud_rate, port->uartclk,
  409. &setted_baud);
  410. wr_regl(port, SIRFUART_DIVISOR, clk_div_reg);
  411. if (tty_termios_baud_rate(termios))
  412. tty_termios_encode_baud_rate(termios, setted_baud, setted_baud);
  413. /* set receive timeout */
  414. rx_time_out = SIRFSOC_UART_RX_TIMEOUT(baud_rate, 20000);
  415. rx_time_out = (rx_time_out > 0xFFFF) ? 0xFFFF : rx_time_out;
  416. config_reg |= SIRFUART_RECV_TIMEOUT(rx_time_out);
  417. temp_reg_val = rd_regl(port, SIRFUART_TX_FIFO_OP);
  418. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  419. wr_regl(port, SIRFUART_TX_FIFO_OP,
  420. temp_reg_val & ~SIRFUART_TX_FIFO_START);
  421. wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, SIRFUART_TX_MODE_IO);
  422. wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, SIRFUART_RX_MODE_IO);
  423. wr_regl(port, SIRFUART_LINE_CTRL, config_reg);
  424. /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
  425. if (baud_rate < 1000000)
  426. threshold_div = 1;
  427. else
  428. threshold_div = 2;
  429. temp = port->line == 1 ? 16 : 64;
  430. wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp / threshold_div);
  431. wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp / threshold_div);
  432. temp_reg_val |= SIRFUART_TX_FIFO_START;
  433. wr_regl(port, SIRFUART_TX_FIFO_OP, temp_reg_val);
  434. uart_update_timeout(port, termios->c_cflag, baud_rate);
  435. sirfsoc_uart_start_rx(port);
  436. wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_TX_EN | SIRFUART_RX_EN);
  437. spin_unlock_irqrestore(&port->lock, flags);
  438. }
  439. static void startup_uart_controller(struct uart_port *port)
  440. {
  441. unsigned long temp_regv;
  442. int temp;
  443. temp_regv = rd_regl(port, SIRFUART_TX_DMA_IO_CTRL);
  444. wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, temp_regv | SIRFUART_TX_MODE_IO);
  445. temp_regv = rd_regl(port, SIRFUART_RX_DMA_IO_CTRL);
  446. wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, temp_regv | SIRFUART_RX_MODE_IO);
  447. wr_regl(port, SIRFUART_TX_DMA_IO_LEN, 0);
  448. wr_regl(port, SIRFUART_RX_DMA_IO_LEN, 0);
  449. wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_RX_EN | SIRFUART_TX_EN);
  450. wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_RESET);
  451. wr_regl(port, SIRFUART_TX_FIFO_OP, 0);
  452. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
  453. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  454. temp = port->line == 1 ? 16 : 64;
  455. wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp);
  456. wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp);
  457. }
  458. static int sirfsoc_uart_startup(struct uart_port *port)
  459. {
  460. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  461. unsigned int index = port->line;
  462. int ret;
  463. set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
  464. ret = request_irq(port->irq,
  465. sirfsoc_uart_isr,
  466. 0,
  467. SIRFUART_PORT_NAME,
  468. sirfport);
  469. if (ret != 0) {
  470. dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
  471. index, port->irq);
  472. goto irq_err;
  473. }
  474. startup_uart_controller(port);
  475. enable_irq(port->irq);
  476. irq_err:
  477. return ret;
  478. }
  479. static void sirfsoc_uart_shutdown(struct uart_port *port)
  480. {
  481. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  482. wr_regl(port, SIRFUART_INT_EN, 0);
  483. free_irq(port->irq, sirfport);
  484. if (sirfport->ms_enabled) {
  485. sirfsoc_uart_disable_ms(port);
  486. sirfport->ms_enabled = 0;
  487. }
  488. }
  489. static const char *sirfsoc_uart_type(struct uart_port *port)
  490. {
  491. return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
  492. }
  493. static int sirfsoc_uart_request_port(struct uart_port *port)
  494. {
  495. void *ret;
  496. ret = request_mem_region(port->mapbase,
  497. SIRFUART_MAP_SIZE, SIRFUART_PORT_NAME);
  498. return ret ? 0 : -EBUSY;
  499. }
  500. static void sirfsoc_uart_release_port(struct uart_port *port)
  501. {
  502. release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
  503. }
  504. static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
  505. {
  506. if (flags & UART_CONFIG_TYPE) {
  507. port->type = SIRFSOC_PORT_TYPE;
  508. sirfsoc_uart_request_port(port);
  509. }
  510. }
  511. static struct uart_ops sirfsoc_uart_ops = {
  512. .tx_empty = sirfsoc_uart_tx_empty,
  513. .get_mctrl = sirfsoc_uart_get_mctrl,
  514. .set_mctrl = sirfsoc_uart_set_mctrl,
  515. .stop_tx = sirfsoc_uart_stop_tx,
  516. .start_tx = sirfsoc_uart_start_tx,
  517. .stop_rx = sirfsoc_uart_stop_rx,
  518. .enable_ms = sirfsoc_uart_enable_ms,
  519. .break_ctl = sirfsoc_uart_break_ctl,
  520. .startup = sirfsoc_uart_startup,
  521. .shutdown = sirfsoc_uart_shutdown,
  522. .set_termios = sirfsoc_uart_set_termios,
  523. .type = sirfsoc_uart_type,
  524. .release_port = sirfsoc_uart_release_port,
  525. .request_port = sirfsoc_uart_request_port,
  526. .config_port = sirfsoc_uart_config_port,
  527. };
  528. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  529. static int __init sirfsoc_uart_console_setup(struct console *co, char *options)
  530. {
  531. unsigned int baud = 115200;
  532. unsigned int bits = 8;
  533. unsigned int parity = 'n';
  534. unsigned int flow = 'n';
  535. struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
  536. if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
  537. return -EINVAL;
  538. if (!port->mapbase)
  539. return -ENODEV;
  540. if (options)
  541. uart_parse_options(options, &baud, &parity, &bits, &flow);
  542. port->cons = co;
  543. return uart_set_options(port, co, baud, parity, bits, flow);
  544. }
  545. static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
  546. {
  547. while (rd_regl(port,
  548. SIRFUART_TX_FIFO_STATUS) & SIRFUART_FIFOFULL_MASK(port))
  549. cpu_relax();
  550. wr_regb(port, SIRFUART_TX_FIFO_DATA, ch);
  551. }
  552. static void sirfsoc_uart_console_write(struct console *co, const char *s,
  553. unsigned int count)
  554. {
  555. struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
  556. uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
  557. }
  558. static struct console sirfsoc_uart_console = {
  559. .name = SIRFSOC_UART_NAME,
  560. .device = uart_console_device,
  561. .flags = CON_PRINTBUFFER,
  562. .index = -1,
  563. .write = sirfsoc_uart_console_write,
  564. .setup = sirfsoc_uart_console_setup,
  565. .data = &sirfsoc_uart_drv,
  566. };
  567. static int __init sirfsoc_uart_console_init(void)
  568. {
  569. register_console(&sirfsoc_uart_console);
  570. return 0;
  571. }
  572. console_initcall(sirfsoc_uart_console_init);
  573. #endif
  574. static struct uart_driver sirfsoc_uart_drv = {
  575. .owner = THIS_MODULE,
  576. .driver_name = SIRFUART_PORT_NAME,
  577. .nr = SIRFSOC_UART_NR,
  578. .dev_name = SIRFSOC_UART_NAME,
  579. .major = SIRFSOC_UART_MAJOR,
  580. .minor = SIRFSOC_UART_MINOR,
  581. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  582. .cons = &sirfsoc_uart_console,
  583. #else
  584. .cons = NULL,
  585. #endif
  586. };
  587. int sirfsoc_uart_probe(struct platform_device *pdev)
  588. {
  589. struct sirfsoc_uart_port *sirfport;
  590. struct uart_port *port;
  591. struct resource *res;
  592. int ret;
  593. if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
  594. dev_err(&pdev->dev,
  595. "Unable to find cell-index in uart node.\n");
  596. ret = -EFAULT;
  597. goto err;
  598. }
  599. sirfport = &sirfsoc_uart_ports[pdev->id];
  600. port = &sirfport->port;
  601. port->dev = &pdev->dev;
  602. port->private_data = sirfport;
  603. if (of_find_property(pdev->dev.of_node, "hw_flow_ctrl", NULL))
  604. sirfport->hw_flow_ctrl = 1;
  605. if (of_property_read_u32(pdev->dev.of_node,
  606. "fifosize",
  607. &port->fifosize)) {
  608. dev_err(&pdev->dev,
  609. "Unable to find fifosize in uart node.\n");
  610. ret = -EFAULT;
  611. goto err;
  612. }
  613. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  614. if (res == NULL) {
  615. dev_err(&pdev->dev, "Insufficient resources.\n");
  616. ret = -EFAULT;
  617. goto err;
  618. }
  619. port->mapbase = res->start;
  620. port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  621. if (!port->membase) {
  622. dev_err(&pdev->dev, "Cannot remap resource.\n");
  623. ret = -ENOMEM;
  624. goto err;
  625. }
  626. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  627. if (res == NULL) {
  628. dev_err(&pdev->dev, "Insufficient resources.\n");
  629. ret = -EFAULT;
  630. goto err;
  631. }
  632. port->irq = res->start;
  633. if (sirfport->hw_flow_ctrl) {
  634. sirfport->p = pinctrl_get_select_default(&pdev->dev);
  635. ret = IS_ERR(sirfport->p);
  636. if (ret)
  637. goto err;
  638. }
  639. sirfport->clk = clk_get(&pdev->dev, NULL);
  640. if (IS_ERR(sirfport->clk)) {
  641. ret = PTR_ERR(sirfport->clk);
  642. goto clk_err;
  643. }
  644. clk_prepare_enable(sirfport->clk);
  645. port->uartclk = clk_get_rate(sirfport->clk);
  646. port->ops = &sirfsoc_uart_ops;
  647. spin_lock_init(&port->lock);
  648. platform_set_drvdata(pdev, sirfport);
  649. ret = uart_add_one_port(&sirfsoc_uart_drv, port);
  650. if (ret != 0) {
  651. dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
  652. goto port_err;
  653. }
  654. return 0;
  655. port_err:
  656. clk_disable_unprepare(sirfport->clk);
  657. clk_put(sirfport->clk);
  658. clk_err:
  659. platform_set_drvdata(pdev, NULL);
  660. if (sirfport->hw_flow_ctrl)
  661. pinctrl_put(sirfport->p);
  662. err:
  663. return ret;
  664. }
  665. static int sirfsoc_uart_remove(struct platform_device *pdev)
  666. {
  667. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  668. struct uart_port *port = &sirfport->port;
  669. platform_set_drvdata(pdev, NULL);
  670. if (sirfport->hw_flow_ctrl)
  671. pinctrl_put(sirfport->p);
  672. clk_disable_unprepare(sirfport->clk);
  673. clk_put(sirfport->clk);
  674. uart_remove_one_port(&sirfsoc_uart_drv, port);
  675. return 0;
  676. }
  677. static int
  678. sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
  679. {
  680. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  681. struct uart_port *port = &sirfport->port;
  682. uart_suspend_port(&sirfsoc_uart_drv, port);
  683. return 0;
  684. }
  685. static int sirfsoc_uart_resume(struct platform_device *pdev)
  686. {
  687. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  688. struct uart_port *port = &sirfport->port;
  689. uart_resume_port(&sirfsoc_uart_drv, port);
  690. return 0;
  691. }
  692. static struct of_device_id sirfsoc_uart_ids[] = {
  693. { .compatible = "sirf,prima2-uart", },
  694. { .compatible = "sirf,marco-uart", },
  695. {}
  696. };
  697. MODULE_DEVICE_TABLE(of, sirfsoc_serial_of_match);
  698. static struct platform_driver sirfsoc_uart_driver = {
  699. .probe = sirfsoc_uart_probe,
  700. .remove = sirfsoc_uart_remove,
  701. .suspend = sirfsoc_uart_suspend,
  702. .resume = sirfsoc_uart_resume,
  703. .driver = {
  704. .name = SIRFUART_PORT_NAME,
  705. .owner = THIS_MODULE,
  706. .of_match_table = sirfsoc_uart_ids,
  707. },
  708. };
  709. static int __init sirfsoc_uart_init(void)
  710. {
  711. int ret = 0;
  712. ret = uart_register_driver(&sirfsoc_uart_drv);
  713. if (ret)
  714. goto out;
  715. ret = platform_driver_register(&sirfsoc_uart_driver);
  716. if (ret)
  717. uart_unregister_driver(&sirfsoc_uart_drv);
  718. out:
  719. return ret;
  720. }
  721. module_init(sirfsoc_uart_init);
  722. static void __exit sirfsoc_uart_exit(void)
  723. {
  724. platform_driver_unregister(&sirfsoc_uart_driver);
  725. uart_unregister_driver(&sirfsoc_uart_drv);
  726. }
  727. module_exit(sirfsoc_uart_exit);
  728. MODULE_LICENSE("GPL v2");
  729. MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
  730. MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");