scan.c 10 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Bus scanning
  4. *
  5. * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
  6. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  7. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  8. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (C) 2006 Broadcom Corporation.
  11. *
  12. * Licensed under the GNU/GPL. See COPYING for details.
  13. */
  14. #include <linux/ssb/ssb.h>
  15. #include <linux/ssb/ssb_regs.h>
  16. #include <linux/pci.h>
  17. #include <linux/io.h>
  18. #include <pcmcia/cistpl.h>
  19. #include <pcmcia/ds.h>
  20. #include "ssb_private.h"
  21. const char *ssb_core_name(u16 coreid)
  22. {
  23. switch (coreid) {
  24. case SSB_DEV_CHIPCOMMON:
  25. return "ChipCommon";
  26. case SSB_DEV_ILINE20:
  27. return "ILine 20";
  28. case SSB_DEV_SDRAM:
  29. return "SDRAM";
  30. case SSB_DEV_PCI:
  31. return "PCI";
  32. case SSB_DEV_MIPS:
  33. return "MIPS";
  34. case SSB_DEV_ETHERNET:
  35. return "Fast Ethernet";
  36. case SSB_DEV_V90:
  37. return "V90";
  38. case SSB_DEV_USB11_HOSTDEV:
  39. return "USB 1.1 Hostdev";
  40. case SSB_DEV_ADSL:
  41. return "ADSL";
  42. case SSB_DEV_ILINE100:
  43. return "ILine 100";
  44. case SSB_DEV_IPSEC:
  45. return "IPSEC";
  46. case SSB_DEV_PCMCIA:
  47. return "PCMCIA";
  48. case SSB_DEV_INTERNAL_MEM:
  49. return "Internal Memory";
  50. case SSB_DEV_MEMC_SDRAM:
  51. return "MEMC SDRAM";
  52. case SSB_DEV_EXTIF:
  53. return "EXTIF";
  54. case SSB_DEV_80211:
  55. return "IEEE 802.11";
  56. case SSB_DEV_MIPS_3302:
  57. return "MIPS 3302";
  58. case SSB_DEV_USB11_HOST:
  59. return "USB 1.1 Host";
  60. case SSB_DEV_USB11_DEV:
  61. return "USB 1.1 Device";
  62. case SSB_DEV_USB20_HOST:
  63. return "USB 2.0 Host";
  64. case SSB_DEV_USB20_DEV:
  65. return "USB 2.0 Device";
  66. case SSB_DEV_SDIO_HOST:
  67. return "SDIO Host";
  68. case SSB_DEV_ROBOSWITCH:
  69. return "Roboswitch";
  70. case SSB_DEV_PARA_ATA:
  71. return "PATA";
  72. case SSB_DEV_SATA_XORDMA:
  73. return "SATA XOR-DMA";
  74. case SSB_DEV_ETHERNET_GBIT:
  75. return "GBit Ethernet";
  76. case SSB_DEV_PCIE:
  77. return "PCI-E";
  78. case SSB_DEV_MIMO_PHY:
  79. return "MIMO PHY";
  80. case SSB_DEV_SRAM_CTRLR:
  81. return "SRAM Controller";
  82. case SSB_DEV_MINI_MACPHY:
  83. return "Mini MACPHY";
  84. case SSB_DEV_ARM_1176:
  85. return "ARM 1176";
  86. case SSB_DEV_ARM_7TDMI:
  87. return "ARM 7TDMI";
  88. case SSB_DEV_ARM_CM3:
  89. return "ARM Cortex M3";
  90. }
  91. return "UNKNOWN";
  92. }
  93. static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
  94. {
  95. u16 chipid_fallback = 0;
  96. switch (pci_dev->device) {
  97. case 0x4301:
  98. chipid_fallback = 0x4301;
  99. break;
  100. case 0x4305 ... 0x4307:
  101. chipid_fallback = 0x4307;
  102. break;
  103. case 0x4403:
  104. chipid_fallback = 0x4402;
  105. break;
  106. case 0x4610 ... 0x4615:
  107. chipid_fallback = 0x4610;
  108. break;
  109. case 0x4710 ... 0x4715:
  110. chipid_fallback = 0x4710;
  111. break;
  112. case 0x4320 ... 0x4325:
  113. chipid_fallback = 0x4309;
  114. break;
  115. case PCI_DEVICE_ID_BCM4401:
  116. case PCI_DEVICE_ID_BCM4401B0:
  117. case PCI_DEVICE_ID_BCM4401B1:
  118. chipid_fallback = 0x4401;
  119. break;
  120. default:
  121. ssb_printk(KERN_ERR PFX
  122. "PCI-ID not in fallback list\n");
  123. }
  124. return chipid_fallback;
  125. }
  126. static u8 chipid_to_nrcores(u16 chipid)
  127. {
  128. switch (chipid) {
  129. case 0x5365:
  130. return 7;
  131. case 0x4306:
  132. return 6;
  133. case 0x4310:
  134. return 8;
  135. case 0x4307:
  136. case 0x4301:
  137. return 5;
  138. case 0x4401:
  139. case 0x4402:
  140. return 3;
  141. case 0x4710:
  142. case 0x4610:
  143. case 0x4704:
  144. return 9;
  145. default:
  146. ssb_printk(KERN_ERR PFX
  147. "CHIPID not in nrcores fallback list\n");
  148. }
  149. return 1;
  150. }
  151. static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
  152. u16 offset)
  153. {
  154. u32 lo, hi;
  155. switch (bus->bustype) {
  156. case SSB_BUSTYPE_SSB:
  157. offset += current_coreidx * SSB_CORE_SIZE;
  158. break;
  159. case SSB_BUSTYPE_PCI:
  160. break;
  161. case SSB_BUSTYPE_PCMCIA:
  162. if (offset >= 0x800) {
  163. ssb_pcmcia_switch_segment(bus, 1);
  164. offset -= 0x800;
  165. } else
  166. ssb_pcmcia_switch_segment(bus, 0);
  167. lo = readw(bus->mmio + offset);
  168. hi = readw(bus->mmio + offset + 2);
  169. return lo | (hi << 16);
  170. case SSB_BUSTYPE_SDIO:
  171. offset += current_coreidx * SSB_CORE_SIZE;
  172. return ssb_sdio_scan_read32(bus, offset);
  173. }
  174. return readl(bus->mmio + offset);
  175. }
  176. static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
  177. {
  178. switch (bus->bustype) {
  179. case SSB_BUSTYPE_SSB:
  180. break;
  181. case SSB_BUSTYPE_PCI:
  182. return ssb_pci_switch_coreidx(bus, coreidx);
  183. case SSB_BUSTYPE_PCMCIA:
  184. return ssb_pcmcia_switch_coreidx(bus, coreidx);
  185. case SSB_BUSTYPE_SDIO:
  186. return ssb_sdio_scan_switch_coreidx(bus, coreidx);
  187. }
  188. return 0;
  189. }
  190. void ssb_iounmap(struct ssb_bus *bus)
  191. {
  192. switch (bus->bustype) {
  193. case SSB_BUSTYPE_SSB:
  194. case SSB_BUSTYPE_PCMCIA:
  195. iounmap(bus->mmio);
  196. break;
  197. case SSB_BUSTYPE_PCI:
  198. #ifdef CONFIG_SSB_PCIHOST
  199. pci_iounmap(bus->host_pci, bus->mmio);
  200. #else
  201. SSB_BUG_ON(1); /* Can't reach this code. */
  202. #endif
  203. break;
  204. case SSB_BUSTYPE_SDIO:
  205. break;
  206. }
  207. bus->mmio = NULL;
  208. bus->mapped_device = NULL;
  209. }
  210. static void __iomem *ssb_ioremap(struct ssb_bus *bus,
  211. unsigned long baseaddr)
  212. {
  213. void __iomem *mmio = NULL;
  214. switch (bus->bustype) {
  215. case SSB_BUSTYPE_SSB:
  216. /* Only map the first core for now. */
  217. /* fallthrough... */
  218. case SSB_BUSTYPE_PCMCIA:
  219. mmio = ioremap(baseaddr, SSB_CORE_SIZE);
  220. break;
  221. case SSB_BUSTYPE_PCI:
  222. #ifdef CONFIG_SSB_PCIHOST
  223. mmio = pci_iomap(bus->host_pci, 0, ~0UL);
  224. #else
  225. SSB_BUG_ON(1); /* Can't reach this code. */
  226. #endif
  227. break;
  228. case SSB_BUSTYPE_SDIO:
  229. /* Nothing to ioremap in the SDIO case, just fake it */
  230. mmio = (void __iomem *)baseaddr;
  231. break;
  232. }
  233. return mmio;
  234. }
  235. static int we_support_multiple_80211_cores(struct ssb_bus *bus)
  236. {
  237. /* More than one 802.11 core is only supported by special chips.
  238. * There are chips with two 802.11 cores, but with dangling
  239. * pins on the second core. Be careful and reject them here.
  240. */
  241. #ifdef CONFIG_SSB_PCIHOST
  242. if (bus->bustype == SSB_BUSTYPE_PCI) {
  243. if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
  244. ((bus->host_pci->device == 0x4313) ||
  245. (bus->host_pci->device == 0x431A) ||
  246. (bus->host_pci->device == 0x4321) ||
  247. (bus->host_pci->device == 0x4324)))
  248. return 1;
  249. }
  250. #endif /* CONFIG_SSB_PCIHOST */
  251. return 0;
  252. }
  253. int ssb_bus_scan(struct ssb_bus *bus,
  254. unsigned long baseaddr)
  255. {
  256. int err = -ENOMEM;
  257. void __iomem *mmio;
  258. u32 idhi, cc, rev, tmp;
  259. int dev_i, i;
  260. struct ssb_device *dev;
  261. int nr_80211_cores = 0;
  262. mmio = ssb_ioremap(bus, baseaddr);
  263. if (!mmio)
  264. goto out;
  265. bus->mmio = mmio;
  266. err = scan_switchcore(bus, 0); /* Switch to first core */
  267. if (err)
  268. goto err_unmap;
  269. idhi = scan_read32(bus, 0, SSB_IDHIGH);
  270. cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  271. rev = (idhi & SSB_IDHIGH_RCLO);
  272. rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  273. bus->nr_devices = 0;
  274. if (cc == SSB_DEV_CHIPCOMMON) {
  275. tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
  276. bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
  277. bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
  278. SSB_CHIPCO_REVSHIFT;
  279. bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
  280. SSB_CHIPCO_PACKSHIFT;
  281. if (rev >= 4) {
  282. bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
  283. SSB_CHIPCO_NRCORESSHIFT;
  284. }
  285. tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
  286. bus->chipco.capabilities = tmp;
  287. } else {
  288. if (bus->bustype == SSB_BUSTYPE_PCI) {
  289. bus->chip_id = pcidev_to_chipid(bus->host_pci);
  290. bus->chip_rev = bus->host_pci->revision;
  291. bus->chip_package = 0;
  292. } else {
  293. bus->chip_id = 0x4710;
  294. bus->chip_rev = 0;
  295. bus->chip_package = 0;
  296. }
  297. }
  298. ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
  299. "package 0x%02X\n", bus->chip_id, bus->chip_rev,
  300. bus->chip_package);
  301. if (!bus->nr_devices)
  302. bus->nr_devices = chipid_to_nrcores(bus->chip_id);
  303. if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
  304. ssb_printk(KERN_ERR PFX
  305. "More than %d ssb cores found (%d)\n",
  306. SSB_MAX_NR_CORES, bus->nr_devices);
  307. goto err_unmap;
  308. }
  309. if (bus->bustype == SSB_BUSTYPE_SSB) {
  310. /* Now that we know the number of cores,
  311. * remap the whole IO space for all cores.
  312. */
  313. err = -ENOMEM;
  314. iounmap(mmio);
  315. mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
  316. if (!mmio)
  317. goto out;
  318. bus->mmio = mmio;
  319. }
  320. /* Fetch basic information about each core/device */
  321. for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
  322. err = scan_switchcore(bus, i);
  323. if (err)
  324. goto err_unmap;
  325. dev = &(bus->devices[dev_i]);
  326. idhi = scan_read32(bus, i, SSB_IDHIGH);
  327. dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  328. dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
  329. dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  330. dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
  331. dev->core_index = i;
  332. dev->bus = bus;
  333. dev->ops = bus->ops;
  334. printk(KERN_DEBUG PFX
  335. "Core %d found: %s "
  336. "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
  337. i, ssb_core_name(dev->id.coreid),
  338. dev->id.coreid, dev->id.revision, dev->id.vendor);
  339. switch (dev->id.coreid) {
  340. case SSB_DEV_80211:
  341. nr_80211_cores++;
  342. if (nr_80211_cores > 1) {
  343. if (!we_support_multiple_80211_cores(bus)) {
  344. ssb_dprintk(KERN_INFO PFX "Ignoring additional "
  345. "802.11 core\n");
  346. continue;
  347. }
  348. }
  349. break;
  350. case SSB_DEV_EXTIF:
  351. #ifdef CONFIG_SSB_DRIVER_EXTIF
  352. if (bus->extif.dev) {
  353. ssb_printk(KERN_WARNING PFX
  354. "WARNING: Multiple EXTIFs found\n");
  355. break;
  356. }
  357. bus->extif.dev = dev;
  358. #endif /* CONFIG_SSB_DRIVER_EXTIF */
  359. break;
  360. case SSB_DEV_CHIPCOMMON:
  361. if (bus->chipco.dev) {
  362. ssb_printk(KERN_WARNING PFX
  363. "WARNING: Multiple ChipCommon found\n");
  364. break;
  365. }
  366. bus->chipco.dev = dev;
  367. break;
  368. case SSB_DEV_MIPS:
  369. case SSB_DEV_MIPS_3302:
  370. #ifdef CONFIG_SSB_DRIVER_MIPS
  371. if (bus->mipscore.dev) {
  372. ssb_printk(KERN_WARNING PFX
  373. "WARNING: Multiple MIPS cores found\n");
  374. break;
  375. }
  376. bus->mipscore.dev = dev;
  377. #endif /* CONFIG_SSB_DRIVER_MIPS */
  378. break;
  379. case SSB_DEV_PCI:
  380. case SSB_DEV_PCIE:
  381. #ifdef CONFIG_SSB_DRIVER_PCICORE
  382. if (bus->bustype == SSB_BUSTYPE_PCI) {
  383. /* Ignore PCI cores on PCI-E cards.
  384. * Ignore PCI-E cores on PCI cards. */
  385. if (dev->id.coreid == SSB_DEV_PCI) {
  386. if (pci_is_pcie(bus->host_pci))
  387. continue;
  388. } else {
  389. if (!pci_is_pcie(bus->host_pci))
  390. continue;
  391. }
  392. }
  393. if (bus->pcicore.dev) {
  394. ssb_printk(KERN_WARNING PFX
  395. "WARNING: Multiple PCI(E) cores found\n");
  396. break;
  397. }
  398. bus->pcicore.dev = dev;
  399. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  400. break;
  401. case SSB_DEV_ETHERNET:
  402. if (bus->bustype == SSB_BUSTYPE_PCI) {
  403. if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
  404. (bus->host_pci->device & 0xFF00) == 0x4300) {
  405. /* This is a dangling ethernet core on a
  406. * wireless device. Ignore it. */
  407. continue;
  408. }
  409. }
  410. break;
  411. default:
  412. break;
  413. }
  414. dev_i++;
  415. }
  416. bus->nr_devices = dev_i;
  417. err = 0;
  418. out:
  419. return err;
  420. err_unmap:
  421. ssb_iounmap(bus);
  422. goto out;
  423. }