ql4_mbx.c 59 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2012 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. #include "ql4_version.h"
  12. void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  13. int in_count)
  14. {
  15. int i;
  16. /* Load all mailbox registers, except mailbox 0. */
  17. for (i = 1; i < in_count; i++)
  18. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  19. /* Wakeup firmware */
  20. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  21. readl(&ha->reg->mailbox[0]);
  22. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  23. readl(&ha->reg->ctrl_status);
  24. }
  25. void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  26. {
  27. int intr_status;
  28. intr_status = readl(&ha->reg->ctrl_status);
  29. if (intr_status & INTR_PENDING) {
  30. /*
  31. * Service the interrupt.
  32. * The ISR will save the mailbox status registers
  33. * to a temporary storage location in the adapter structure.
  34. */
  35. ha->mbox_status_count = out_count;
  36. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  37. }
  38. }
  39. /**
  40. * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
  41. * @ha: Pointer to host adapter structure.
  42. * @ret: 1=polling mode, 0=non-polling mode
  43. **/
  44. static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
  45. {
  46. int rval = 1;
  47. if (is_qla8032(ha)) {
  48. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  49. test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
  50. rval = 0;
  51. } else {
  52. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  53. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  54. test_bit(AF_ONLINE, &ha->flags) &&
  55. !test_bit(AF_HA_REMOVAL, &ha->flags))
  56. rval = 0;
  57. }
  58. return rval;
  59. }
  60. /**
  61. * qla4xxx_mailbox_command - issues mailbox commands
  62. * @ha: Pointer to host adapter structure.
  63. * @inCount: number of mailbox registers to load.
  64. * @outCount: number of mailbox registers to return.
  65. * @mbx_cmd: data pointer for mailbox in registers.
  66. * @mbx_sts: data pointer for mailbox out registers.
  67. *
  68. * This routine issue mailbox commands and waits for completion.
  69. * If outCount is 0, this routine completes successfully WITHOUT waiting
  70. * for the mailbox command to complete.
  71. **/
  72. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  73. uint8_t outCount, uint32_t *mbx_cmd,
  74. uint32_t *mbx_sts)
  75. {
  76. int status = QLA_ERROR;
  77. uint8_t i;
  78. u_long wait_count;
  79. unsigned long flags = 0;
  80. uint32_t dev_state;
  81. /* Make sure that pointers are valid */
  82. if (!mbx_cmd || !mbx_sts) {
  83. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  84. "pointer\n", ha->host_no, __func__));
  85. return status;
  86. }
  87. if (is_qla40XX(ha)) {
  88. if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
  89. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  90. "prematurely completing mbx cmd as "
  91. "adapter removal detected\n",
  92. ha->host_no, __func__));
  93. return status;
  94. }
  95. }
  96. if ((is_aer_supported(ha)) &&
  97. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  98. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  99. "timeout MBX Exiting.\n", ha->host_no, __func__));
  100. return status;
  101. }
  102. /* Mailbox code active */
  103. wait_count = MBOX_TOV * 100;
  104. while (wait_count--) {
  105. mutex_lock(&ha->mbox_sem);
  106. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  107. set_bit(AF_MBOX_COMMAND, &ha->flags);
  108. mutex_unlock(&ha->mbox_sem);
  109. break;
  110. }
  111. mutex_unlock(&ha->mbox_sem);
  112. if (!wait_count) {
  113. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  114. ha->host_no, __func__));
  115. return status;
  116. }
  117. msleep(10);
  118. }
  119. if (is_qla80XX(ha)) {
  120. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  121. DEBUG2(ql4_printk(KERN_WARNING, ha,
  122. "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
  123. ha->host_no, __func__));
  124. goto mbox_exit;
  125. }
  126. /* Do not send any mbx cmd if h/w is in failed state*/
  127. ha->isp_ops->idc_lock(ha);
  128. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  129. ha->isp_ops->idc_unlock(ha);
  130. if (dev_state == QLA8XXX_DEV_FAILED) {
  131. ql4_printk(KERN_WARNING, ha,
  132. "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
  133. ha->host_no, __func__);
  134. goto mbox_exit;
  135. }
  136. }
  137. spin_lock_irqsave(&ha->hardware_lock, flags);
  138. ha->mbox_status_count = outCount;
  139. for (i = 0; i < outCount; i++)
  140. ha->mbox_status[i] = 0;
  141. /* Queue the mailbox command to the firmware */
  142. ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
  143. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  144. /* Wait for completion */
  145. /*
  146. * If we don't want status, don't wait for the mailbox command to
  147. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  148. * you must poll the inbound Interrupt Mask for completion.
  149. */
  150. if (outCount == 0) {
  151. status = QLA_SUCCESS;
  152. goto mbox_exit;
  153. }
  154. /*
  155. * Wait for completion: Poll or completion queue
  156. */
  157. if (qla4xxx_is_intr_poll_mode(ha)) {
  158. /* Poll for command to complete */
  159. wait_count = jiffies + MBOX_TOV * HZ;
  160. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  161. if (time_after_eq(jiffies, wait_count))
  162. break;
  163. /*
  164. * Service the interrupt.
  165. * The ISR will save the mailbox status registers
  166. * to a temporary storage location in the adapter
  167. * structure.
  168. */
  169. spin_lock_irqsave(&ha->hardware_lock, flags);
  170. ha->isp_ops->process_mailbox_interrupt(ha, outCount);
  171. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  172. msleep(10);
  173. }
  174. } else {
  175. /* Do not poll for completion. Use completion queue */
  176. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  177. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  178. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  179. }
  180. /* Check for mailbox timeout. */
  181. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  182. if (is_qla80XX(ha) &&
  183. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  184. DEBUG2(ql4_printk(KERN_INFO, ha,
  185. "scsi%ld: %s: prematurely completing mbx cmd as "
  186. "firmware recovery detected\n",
  187. ha->host_no, __func__));
  188. goto mbox_exit;
  189. }
  190. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  191. " Scheduling Adapter Reset\n", ha->host_no,
  192. mbx_cmd[0]));
  193. ha->mailbox_timeout_count++;
  194. mbx_sts[0] = (-1);
  195. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  196. if (is_qla8022(ha)) {
  197. ql4_printk(KERN_INFO, ha,
  198. "disabling pause transmit on port 0 & 1.\n");
  199. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
  200. CRB_NIU_XG_PAUSE_CTL_P0 |
  201. CRB_NIU_XG_PAUSE_CTL_P1);
  202. } else if (is_qla8032(ha)) {
  203. ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
  204. __func__);
  205. qla4_83xx_disable_pause(ha);
  206. }
  207. goto mbox_exit;
  208. }
  209. /*
  210. * Copy the mailbox out registers to the caller's mailbox in/out
  211. * structure.
  212. */
  213. spin_lock_irqsave(&ha->hardware_lock, flags);
  214. for (i = 0; i < outCount; i++)
  215. mbx_sts[i] = ha->mbox_status[i];
  216. /* Set return status and error flags (if applicable). */
  217. switch (ha->mbox_status[0]) {
  218. case MBOX_STS_COMMAND_COMPLETE:
  219. status = QLA_SUCCESS;
  220. break;
  221. case MBOX_STS_INTERMEDIATE_COMPLETION:
  222. status = QLA_SUCCESS;
  223. break;
  224. case MBOX_STS_BUSY:
  225. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  226. ha->host_no, __func__, mbx_cmd[0]));
  227. ha->mailbox_timeout_count++;
  228. break;
  229. default:
  230. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  231. "sts = %08X ****\n", ha->host_no, __func__,
  232. mbx_cmd[0], mbx_sts[0]));
  233. break;
  234. }
  235. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  236. mbox_exit:
  237. mutex_lock(&ha->mbox_sem);
  238. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  239. mutex_unlock(&ha->mbox_sem);
  240. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  241. return status;
  242. }
  243. /**
  244. * qla4xxx_get_minidump_template - Get the firmware template
  245. * @ha: Pointer to host adapter structure.
  246. * @phys_addr: dma address for template
  247. *
  248. * Obtain the minidump template from firmware during initialization
  249. * as it may not be available when minidump is desired.
  250. **/
  251. int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
  252. dma_addr_t phys_addr)
  253. {
  254. uint32_t mbox_cmd[MBOX_REG_COUNT];
  255. uint32_t mbox_sts[MBOX_REG_COUNT];
  256. int status;
  257. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  258. memset(&mbox_sts, 0, sizeof(mbox_sts));
  259. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  260. mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
  261. mbox_cmd[2] = LSDW(phys_addr);
  262. mbox_cmd[3] = MSDW(phys_addr);
  263. mbox_cmd[4] = ha->fw_dump_tmplt_size;
  264. mbox_cmd[5] = 0;
  265. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  266. &mbox_sts[0]);
  267. if (status != QLA_SUCCESS) {
  268. DEBUG2(ql4_printk(KERN_INFO, ha,
  269. "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
  270. ha->host_no, __func__, mbox_cmd[0],
  271. mbox_sts[0], mbox_sts[1]));
  272. }
  273. return status;
  274. }
  275. /**
  276. * qla4xxx_req_template_size - Get minidump template size from firmware.
  277. * @ha: Pointer to host adapter structure.
  278. **/
  279. int qla4xxx_req_template_size(struct scsi_qla_host *ha)
  280. {
  281. uint32_t mbox_cmd[MBOX_REG_COUNT];
  282. uint32_t mbox_sts[MBOX_REG_COUNT];
  283. int status;
  284. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  285. memset(&mbox_sts, 0, sizeof(mbox_sts));
  286. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  287. mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
  288. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
  289. &mbox_sts[0]);
  290. if (status == QLA_SUCCESS) {
  291. ha->fw_dump_tmplt_size = mbox_sts[1];
  292. DEBUG2(ql4_printk(KERN_INFO, ha,
  293. "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
  294. __func__, mbox_sts[0], mbox_sts[1],
  295. mbox_sts[2], mbox_sts[3], mbox_sts[4],
  296. mbox_sts[5], mbox_sts[6], mbox_sts[7]));
  297. if (ha->fw_dump_tmplt_size == 0)
  298. status = QLA_ERROR;
  299. } else {
  300. ql4_printk(KERN_WARNING, ha,
  301. "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
  302. __func__, mbox_sts[0], mbox_sts[1]);
  303. status = QLA_ERROR;
  304. }
  305. return status;
  306. }
  307. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  308. {
  309. set_bit(AF_FW_RECOVERY, &ha->flags);
  310. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  311. ha->host_no, __func__);
  312. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  313. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  314. complete(&ha->mbx_intr_comp);
  315. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  316. "recovery, doing premature completion of "
  317. "mbx cmd\n", ha->host_no, __func__);
  318. } else {
  319. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  320. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  321. "recovery, doing premature completion of "
  322. "polling mbx cmd\n", ha->host_no, __func__);
  323. }
  324. }
  325. }
  326. static uint8_t
  327. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  328. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  329. {
  330. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  331. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  332. if (is_qla8022(ha))
  333. qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  334. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  335. mbox_cmd[1] = 0;
  336. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  337. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  338. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  339. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  340. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  341. QLA_SUCCESS) {
  342. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  343. "MBOX_CMD_INITIALIZE_FIRMWARE"
  344. " failed w/ status %04X\n",
  345. ha->host_no, __func__, mbox_sts[0]));
  346. return QLA_ERROR;
  347. }
  348. return QLA_SUCCESS;
  349. }
  350. uint8_t
  351. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  352. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  353. {
  354. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  355. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  356. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  357. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  358. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  359. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  360. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  361. QLA_SUCCESS) {
  362. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  363. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  364. " failed w/ status %04X\n",
  365. ha->host_no, __func__, mbox_sts[0]));
  366. return QLA_ERROR;
  367. }
  368. return QLA_SUCCESS;
  369. }
  370. static void
  371. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  372. struct addr_ctrl_blk *init_fw_cb)
  373. {
  374. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  375. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  376. ha->ip_config.ipv4_addr_state =
  377. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  378. ha->ip_config.eth_mtu_size =
  379. le16_to_cpu(init_fw_cb->eth_mtu_size);
  380. ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
  381. if (ha->acb_version == ACB_SUPPORTED) {
  382. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  383. ha->ip_config.ipv6_addl_options =
  384. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  385. }
  386. /* Save IPv4 Address Info */
  387. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  388. min(sizeof(ha->ip_config.ip_address),
  389. sizeof(init_fw_cb->ipv4_addr)));
  390. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  391. min(sizeof(ha->ip_config.subnet_mask),
  392. sizeof(init_fw_cb->ipv4_subnet)));
  393. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  394. min(sizeof(ha->ip_config.gateway),
  395. sizeof(init_fw_cb->ipv4_gw_addr)));
  396. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  397. if (is_ipv6_enabled(ha)) {
  398. /* Save IPv6 Address */
  399. ha->ip_config.ipv6_link_local_state =
  400. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  401. ha->ip_config.ipv6_addr0_state =
  402. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  403. ha->ip_config.ipv6_addr1_state =
  404. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  405. ha->ip_config.ipv6_default_router_state =
  406. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  407. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  408. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  409. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  410. init_fw_cb->ipv6_if_id,
  411. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  412. sizeof(init_fw_cb->ipv6_if_id)));
  413. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  414. min(sizeof(ha->ip_config.ipv6_addr0),
  415. sizeof(init_fw_cb->ipv6_addr0)));
  416. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  417. min(sizeof(ha->ip_config.ipv6_addr1),
  418. sizeof(init_fw_cb->ipv6_addr1)));
  419. memcpy(&ha->ip_config.ipv6_default_router_addr,
  420. init_fw_cb->ipv6_dflt_rtr_addr,
  421. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  422. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  423. ha->ip_config.ipv6_vlan_tag =
  424. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  425. ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
  426. }
  427. }
  428. uint8_t
  429. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  430. uint32_t *mbox_cmd,
  431. uint32_t *mbox_sts,
  432. struct addr_ctrl_blk *init_fw_cb,
  433. dma_addr_t init_fw_cb_dma)
  434. {
  435. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  436. != QLA_SUCCESS) {
  437. DEBUG2(printk(KERN_WARNING
  438. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  439. ha->host_no, __func__));
  440. return QLA_ERROR;
  441. }
  442. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  443. /* Save some info in adapter structure. */
  444. ha->acb_version = init_fw_cb->acb_version;
  445. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  446. ha->heartbeat_interval = init_fw_cb->hb_interval;
  447. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  448. min(sizeof(ha->name_string),
  449. sizeof(init_fw_cb->iscsi_name)));
  450. ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
  451. /*memcpy(ha->alias, init_fw_cb->Alias,
  452. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  453. qla4xxx_update_local_ip(ha, init_fw_cb);
  454. return QLA_SUCCESS;
  455. }
  456. /**
  457. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  458. * @ha: Pointer to host adapter structure.
  459. **/
  460. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  461. {
  462. struct addr_ctrl_blk *init_fw_cb;
  463. dma_addr_t init_fw_cb_dma;
  464. uint32_t mbox_cmd[MBOX_REG_COUNT];
  465. uint32_t mbox_sts[MBOX_REG_COUNT];
  466. int status = QLA_ERROR;
  467. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  468. sizeof(struct addr_ctrl_blk),
  469. &init_fw_cb_dma, GFP_KERNEL);
  470. if (init_fw_cb == NULL) {
  471. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  472. ha->host_no, __func__));
  473. goto exit_init_fw_cb_no_free;
  474. }
  475. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  476. /* Get Initialize Firmware Control Block. */
  477. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  478. memset(&mbox_sts, 0, sizeof(mbox_sts));
  479. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  480. QLA_SUCCESS) {
  481. dma_free_coherent(&ha->pdev->dev,
  482. sizeof(struct addr_ctrl_blk),
  483. init_fw_cb, init_fw_cb_dma);
  484. goto exit_init_fw_cb;
  485. }
  486. /* Initialize request and response queues. */
  487. qla4xxx_init_rings(ha);
  488. /* Fill in the request and response queue information. */
  489. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  490. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  491. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  492. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  493. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  494. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  495. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  496. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  497. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  498. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  499. /* Set up required options. */
  500. init_fw_cb->fw_options |=
  501. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  502. FWOPT_INITIATOR_MODE);
  503. if (is_qla80XX(ha))
  504. init_fw_cb->fw_options |=
  505. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  506. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  507. init_fw_cb->add_fw_options = 0;
  508. init_fw_cb->add_fw_options |=
  509. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  510. init_fw_cb->add_fw_options |=
  511. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  512. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  513. != QLA_SUCCESS) {
  514. DEBUG2(printk(KERN_WARNING
  515. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  516. ha->host_no, __func__));
  517. goto exit_init_fw_cb;
  518. }
  519. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  520. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  521. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  522. ha->host_no, __func__));
  523. goto exit_init_fw_cb;
  524. }
  525. status = QLA_SUCCESS;
  526. exit_init_fw_cb:
  527. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  528. init_fw_cb, init_fw_cb_dma);
  529. exit_init_fw_cb_no_free:
  530. return status;
  531. }
  532. /**
  533. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  534. * @ha: Pointer to host adapter structure.
  535. **/
  536. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  537. {
  538. struct addr_ctrl_blk *init_fw_cb;
  539. dma_addr_t init_fw_cb_dma;
  540. uint32_t mbox_cmd[MBOX_REG_COUNT];
  541. uint32_t mbox_sts[MBOX_REG_COUNT];
  542. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  543. sizeof(struct addr_ctrl_blk),
  544. &init_fw_cb_dma, GFP_KERNEL);
  545. if (init_fw_cb == NULL) {
  546. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  547. __func__);
  548. return QLA_ERROR;
  549. }
  550. /* Get Initialize Firmware Control Block. */
  551. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  552. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  553. QLA_SUCCESS) {
  554. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  555. ha->host_no, __func__));
  556. dma_free_coherent(&ha->pdev->dev,
  557. sizeof(struct addr_ctrl_blk),
  558. init_fw_cb, init_fw_cb_dma);
  559. return QLA_ERROR;
  560. }
  561. /* Save IP Address. */
  562. qla4xxx_update_local_ip(ha, init_fw_cb);
  563. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  564. init_fw_cb, init_fw_cb_dma);
  565. return QLA_SUCCESS;
  566. }
  567. /**
  568. * qla4xxx_get_firmware_state - gets firmware state of HBA
  569. * @ha: Pointer to host adapter structure.
  570. **/
  571. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  572. {
  573. uint32_t mbox_cmd[MBOX_REG_COUNT];
  574. uint32_t mbox_sts[MBOX_REG_COUNT];
  575. /* Get firmware version */
  576. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  577. memset(&mbox_sts, 0, sizeof(mbox_sts));
  578. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  579. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  580. QLA_SUCCESS) {
  581. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  582. "status %04X\n", ha->host_no, __func__,
  583. mbox_sts[0]));
  584. return QLA_ERROR;
  585. }
  586. ha->firmware_state = mbox_sts[1];
  587. ha->board_id = mbox_sts[2];
  588. ha->addl_fw_state = mbox_sts[3];
  589. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  590. ha->host_no, __func__, ha->firmware_state);)
  591. return QLA_SUCCESS;
  592. }
  593. /**
  594. * qla4xxx_get_firmware_status - retrieves firmware status
  595. * @ha: Pointer to host adapter structure.
  596. **/
  597. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  598. {
  599. uint32_t mbox_cmd[MBOX_REG_COUNT];
  600. uint32_t mbox_sts[MBOX_REG_COUNT];
  601. /* Get firmware version */
  602. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  603. memset(&mbox_sts, 0, sizeof(mbox_sts));
  604. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  605. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  606. QLA_SUCCESS) {
  607. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  608. "status %04X\n", ha->host_no, __func__,
  609. mbox_sts[0]));
  610. return QLA_ERROR;
  611. }
  612. /* High-water mark of IOCBs */
  613. ha->iocb_hiwat = mbox_sts[2];
  614. DEBUG2(ql4_printk(KERN_INFO, ha,
  615. "%s: firmware IOCBs available = %d\n", __func__,
  616. ha->iocb_hiwat));
  617. if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
  618. ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
  619. /* Ideally, we should not enter this code, as the # of firmware
  620. * IOCBs is hard-coded in the firmware. We set a default
  621. * iocb_hiwat here just in case */
  622. if (ha->iocb_hiwat == 0) {
  623. ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
  624. DEBUG2(ql4_printk(KERN_WARNING, ha,
  625. "%s: Setting IOCB's to = %d\n", __func__,
  626. ha->iocb_hiwat));
  627. }
  628. return QLA_SUCCESS;
  629. }
  630. /**
  631. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  632. * @ha: Pointer to host adapter structure.
  633. * @fw_ddb_index: Firmware's device database index
  634. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  635. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  636. * @next_ddb_index: Pointer to next valid device database index
  637. * @fw_ddb_device_state: Pointer to device state
  638. **/
  639. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  640. uint16_t fw_ddb_index,
  641. struct dev_db_entry *fw_ddb_entry,
  642. dma_addr_t fw_ddb_entry_dma,
  643. uint32_t *num_valid_ddb_entries,
  644. uint32_t *next_ddb_index,
  645. uint32_t *fw_ddb_device_state,
  646. uint32_t *conn_err_detail,
  647. uint16_t *tcp_source_port_num,
  648. uint16_t *connection_id)
  649. {
  650. int status = QLA_ERROR;
  651. uint16_t options;
  652. uint32_t mbox_cmd[MBOX_REG_COUNT];
  653. uint32_t mbox_sts[MBOX_REG_COUNT];
  654. /* Make sure the device index is valid */
  655. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  656. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  657. ha->host_no, __func__, fw_ddb_index));
  658. goto exit_get_fwddb;
  659. }
  660. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  661. memset(&mbox_sts, 0, sizeof(mbox_sts));
  662. if (fw_ddb_entry)
  663. memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
  664. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  665. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  666. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  667. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  668. mbox_cmd[4] = sizeof(struct dev_db_entry);
  669. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  670. QLA_ERROR) {
  671. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  672. " with status 0x%04X\n", ha->host_no, __func__,
  673. mbox_sts[0]));
  674. goto exit_get_fwddb;
  675. }
  676. if (fw_ddb_index != mbox_sts[1]) {
  677. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  678. ha->host_no, __func__, fw_ddb_index,
  679. mbox_sts[1]));
  680. goto exit_get_fwddb;
  681. }
  682. if (fw_ddb_entry) {
  683. options = le16_to_cpu(fw_ddb_entry->options);
  684. if (options & DDB_OPT_IPV6_DEVICE) {
  685. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  686. "Next %d State %04x ConnErr %08x %pI6 "
  687. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  688. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  689. mbox_sts[4], mbox_sts[5],
  690. fw_ddb_entry->ip_addr,
  691. le16_to_cpu(fw_ddb_entry->port),
  692. fw_ddb_entry->iscsi_name);
  693. } else {
  694. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  695. "Next %d State %04x ConnErr %08x %pI4 "
  696. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  697. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  698. mbox_sts[4], mbox_sts[5],
  699. fw_ddb_entry->ip_addr,
  700. le16_to_cpu(fw_ddb_entry->port),
  701. fw_ddb_entry->iscsi_name);
  702. }
  703. }
  704. if (num_valid_ddb_entries)
  705. *num_valid_ddb_entries = mbox_sts[2];
  706. if (next_ddb_index)
  707. *next_ddb_index = mbox_sts[3];
  708. if (fw_ddb_device_state)
  709. *fw_ddb_device_state = mbox_sts[4];
  710. /*
  711. * RA: This mailbox has been changed to pass connection error and
  712. * details. Its true for ISP4010 as per Version E - Not sure when it
  713. * was changed. Get the time2wait from the fw_dd_entry field :
  714. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  715. * struct.
  716. */
  717. if (conn_err_detail)
  718. *conn_err_detail = mbox_sts[5];
  719. if (tcp_source_port_num)
  720. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  721. if (connection_id)
  722. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  723. status = QLA_SUCCESS;
  724. exit_get_fwddb:
  725. return status;
  726. }
  727. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  728. {
  729. uint32_t mbox_cmd[MBOX_REG_COUNT];
  730. uint32_t mbox_sts[MBOX_REG_COUNT];
  731. int status;
  732. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  733. memset(&mbox_sts, 0, sizeof(mbox_sts));
  734. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  735. mbox_cmd[1] = fw_ddb_index;
  736. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  737. &mbox_sts[0]);
  738. DEBUG2(ql4_printk(KERN_INFO, ha,
  739. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  740. __func__, status, mbox_sts[0], mbox_sts[1]));
  741. return status;
  742. }
  743. /**
  744. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  745. * @ha: Pointer to host adapter structure.
  746. * @fw_ddb_index: Firmware's device database index
  747. * @fw_ddb_entry_dma: dma address of ddb entry
  748. * @mbx_sts: mailbox 0 to be returned or NULL
  749. *
  750. * This routine initializes or updates the adapter's device database
  751. * entry for the specified device.
  752. **/
  753. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  754. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  755. {
  756. uint32_t mbox_cmd[MBOX_REG_COUNT];
  757. uint32_t mbox_sts[MBOX_REG_COUNT];
  758. int status;
  759. /* Do not wait for completion. The firmware will send us an
  760. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  761. */
  762. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  763. memset(&mbox_sts, 0, sizeof(mbox_sts));
  764. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  765. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  766. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  767. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  768. mbox_cmd[4] = sizeof(struct dev_db_entry);
  769. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  770. &mbox_sts[0]);
  771. if (mbx_sts)
  772. *mbx_sts = mbox_sts[0];
  773. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  774. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  775. return status;
  776. }
  777. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  778. struct ddb_entry *ddb_entry, int options)
  779. {
  780. int status;
  781. uint32_t mbox_cmd[MBOX_REG_COUNT];
  782. uint32_t mbox_sts[MBOX_REG_COUNT];
  783. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  784. memset(&mbox_sts, 0, sizeof(mbox_sts));
  785. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  786. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  787. mbox_cmd[3] = options;
  788. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  789. &mbox_sts[0]);
  790. if (status != QLA_SUCCESS) {
  791. DEBUG2(ql4_printk(KERN_INFO, ha,
  792. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  793. "failed sts %04X %04X", __func__,
  794. mbox_sts[0], mbox_sts[1]));
  795. }
  796. return status;
  797. }
  798. /**
  799. * qla4xxx_get_crash_record - retrieves crash record.
  800. * @ha: Pointer to host adapter structure.
  801. *
  802. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  803. **/
  804. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  805. {
  806. uint32_t mbox_cmd[MBOX_REG_COUNT];
  807. uint32_t mbox_sts[MBOX_REG_COUNT];
  808. struct crash_record *crash_record = NULL;
  809. dma_addr_t crash_record_dma = 0;
  810. uint32_t crash_record_size = 0;
  811. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  812. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  813. /* Get size of crash record. */
  814. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  815. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  816. QLA_SUCCESS) {
  817. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  818. ha->host_no, __func__));
  819. goto exit_get_crash_record;
  820. }
  821. crash_record_size = mbox_sts[4];
  822. if (crash_record_size == 0) {
  823. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  824. ha->host_no, __func__));
  825. goto exit_get_crash_record;
  826. }
  827. /* Alloc Memory for Crash Record. */
  828. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  829. &crash_record_dma, GFP_KERNEL);
  830. if (crash_record == NULL)
  831. goto exit_get_crash_record;
  832. /* Get Crash Record. */
  833. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  834. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  835. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  836. mbox_cmd[2] = LSDW(crash_record_dma);
  837. mbox_cmd[3] = MSDW(crash_record_dma);
  838. mbox_cmd[4] = crash_record_size;
  839. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  840. QLA_SUCCESS)
  841. goto exit_get_crash_record;
  842. /* Dump Crash Record. */
  843. exit_get_crash_record:
  844. if (crash_record)
  845. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  846. crash_record, crash_record_dma);
  847. }
  848. /**
  849. * qla4xxx_get_conn_event_log - retrieves connection event log
  850. * @ha: Pointer to host adapter structure.
  851. **/
  852. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  853. {
  854. uint32_t mbox_cmd[MBOX_REG_COUNT];
  855. uint32_t mbox_sts[MBOX_REG_COUNT];
  856. struct conn_event_log_entry *event_log = NULL;
  857. dma_addr_t event_log_dma = 0;
  858. uint32_t event_log_size = 0;
  859. uint32_t num_valid_entries;
  860. uint32_t oldest_entry = 0;
  861. uint32_t max_event_log_entries;
  862. uint8_t i;
  863. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  864. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  865. /* Get size of crash record. */
  866. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  867. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  868. QLA_SUCCESS)
  869. goto exit_get_event_log;
  870. event_log_size = mbox_sts[4];
  871. if (event_log_size == 0)
  872. goto exit_get_event_log;
  873. /* Alloc Memory for Crash Record. */
  874. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  875. &event_log_dma, GFP_KERNEL);
  876. if (event_log == NULL)
  877. goto exit_get_event_log;
  878. /* Get Crash Record. */
  879. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  880. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  881. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  882. mbox_cmd[2] = LSDW(event_log_dma);
  883. mbox_cmd[3] = MSDW(event_log_dma);
  884. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  885. QLA_SUCCESS) {
  886. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  887. "log!\n", ha->host_no, __func__));
  888. goto exit_get_event_log;
  889. }
  890. /* Dump Event Log. */
  891. num_valid_entries = mbox_sts[1];
  892. max_event_log_entries = event_log_size /
  893. sizeof(struct conn_event_log_entry);
  894. if (num_valid_entries > max_event_log_entries)
  895. oldest_entry = num_valid_entries % max_event_log_entries;
  896. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  897. ha->host_no, num_valid_entries));
  898. if (ql4xextended_error_logging == 3) {
  899. if (oldest_entry == 0) {
  900. /* Circular Buffer has not wrapped around */
  901. for (i=0; i < num_valid_entries; i++) {
  902. qla4xxx_dump_buffer((uint8_t *)event_log+
  903. (i*sizeof(*event_log)),
  904. sizeof(*event_log));
  905. }
  906. }
  907. else {
  908. /* Circular Buffer has wrapped around -
  909. * display accordingly*/
  910. for (i=oldest_entry; i < max_event_log_entries; i++) {
  911. qla4xxx_dump_buffer((uint8_t *)event_log+
  912. (i*sizeof(*event_log)),
  913. sizeof(*event_log));
  914. }
  915. for (i=0; i < oldest_entry; i++) {
  916. qla4xxx_dump_buffer((uint8_t *)event_log+
  917. (i*sizeof(*event_log)),
  918. sizeof(*event_log));
  919. }
  920. }
  921. }
  922. exit_get_event_log:
  923. if (event_log)
  924. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  925. event_log_dma);
  926. }
  927. /**
  928. * qla4xxx_abort_task - issues Abort Task
  929. * @ha: Pointer to host adapter structure.
  930. * @srb: Pointer to srb entry
  931. *
  932. * This routine performs a LUN RESET on the specified target/lun.
  933. * The caller must ensure that the ddb_entry and lun_entry pointers
  934. * are valid before calling this routine.
  935. **/
  936. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  937. {
  938. uint32_t mbox_cmd[MBOX_REG_COUNT];
  939. uint32_t mbox_sts[MBOX_REG_COUNT];
  940. struct scsi_cmnd *cmd = srb->cmd;
  941. int status = QLA_SUCCESS;
  942. unsigned long flags = 0;
  943. uint32_t index;
  944. /*
  945. * Send abort task command to ISP, so that the ISP will return
  946. * request with ABORT status
  947. */
  948. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  949. memset(&mbox_sts, 0, sizeof(mbox_sts));
  950. spin_lock_irqsave(&ha->hardware_lock, flags);
  951. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  952. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  953. /* Firmware already posted completion on response queue */
  954. if (index == MAX_SRBS)
  955. return status;
  956. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  957. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  958. mbox_cmd[2] = index;
  959. /* Immediate Command Enable */
  960. mbox_cmd[5] = 0x01;
  961. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  962. &mbox_sts[0]);
  963. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  964. status = QLA_ERROR;
  965. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  966. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  967. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  968. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  969. }
  970. return status;
  971. }
  972. /**
  973. * qla4xxx_reset_lun - issues LUN Reset
  974. * @ha: Pointer to host adapter structure.
  975. * @ddb_entry: Pointer to device database entry
  976. * @lun: lun number
  977. *
  978. * This routine performs a LUN RESET on the specified target/lun.
  979. * The caller must ensure that the ddb_entry and lun_entry pointers
  980. * are valid before calling this routine.
  981. **/
  982. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  983. int lun)
  984. {
  985. uint32_t mbox_cmd[MBOX_REG_COUNT];
  986. uint32_t mbox_sts[MBOX_REG_COUNT];
  987. int status = QLA_SUCCESS;
  988. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  989. ddb_entry->fw_ddb_index, lun));
  990. /*
  991. * Send lun reset command to ISP, so that the ISP will return all
  992. * outstanding requests with RESET status
  993. */
  994. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  995. memset(&mbox_sts, 0, sizeof(mbox_sts));
  996. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  997. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  998. mbox_cmd[2] = lun << 8;
  999. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  1000. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  1001. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  1002. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1003. status = QLA_ERROR;
  1004. return status;
  1005. }
  1006. /**
  1007. * qla4xxx_reset_target - issues target Reset
  1008. * @ha: Pointer to host adapter structure.
  1009. * @db_entry: Pointer to device database entry
  1010. * @un_entry: Pointer to lun entry structure
  1011. *
  1012. * This routine performs a TARGET RESET on the specified target.
  1013. * The caller must ensure that the ddb_entry pointers
  1014. * are valid before calling this routine.
  1015. **/
  1016. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  1017. struct ddb_entry *ddb_entry)
  1018. {
  1019. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1020. uint32_t mbox_sts[MBOX_REG_COUNT];
  1021. int status = QLA_SUCCESS;
  1022. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  1023. ddb_entry->fw_ddb_index));
  1024. /*
  1025. * Send target reset command to ISP, so that the ISP will return all
  1026. * outstanding requests with RESET status
  1027. */
  1028. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1029. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1030. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  1031. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  1032. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  1033. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1034. &mbox_sts[0]);
  1035. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  1036. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1037. status = QLA_ERROR;
  1038. return status;
  1039. }
  1040. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  1041. uint32_t offset, uint32_t len)
  1042. {
  1043. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1044. uint32_t mbox_sts[MBOX_REG_COUNT];
  1045. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1046. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1047. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  1048. mbox_cmd[1] = LSDW(dma_addr);
  1049. mbox_cmd[2] = MSDW(dma_addr);
  1050. mbox_cmd[3] = offset;
  1051. mbox_cmd[4] = len;
  1052. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  1053. QLA_SUCCESS) {
  1054. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  1055. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  1056. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  1057. return QLA_ERROR;
  1058. }
  1059. return QLA_SUCCESS;
  1060. }
  1061. /**
  1062. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  1063. * @ha: Pointer to host adapter structure.
  1064. *
  1065. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  1066. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  1067. * those mailboxes, if unused.
  1068. **/
  1069. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  1070. {
  1071. struct about_fw_info *about_fw = NULL;
  1072. dma_addr_t about_fw_dma;
  1073. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1074. uint32_t mbox_sts[MBOX_REG_COUNT];
  1075. int status = QLA_ERROR;
  1076. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  1077. sizeof(struct about_fw_info),
  1078. &about_fw_dma, GFP_KERNEL);
  1079. if (!about_fw) {
  1080. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  1081. "for about_fw\n", __func__));
  1082. return status;
  1083. }
  1084. memset(about_fw, 0, sizeof(struct about_fw_info));
  1085. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1086. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1087. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  1088. mbox_cmd[2] = LSDW(about_fw_dma);
  1089. mbox_cmd[3] = MSDW(about_fw_dma);
  1090. mbox_cmd[4] = sizeof(struct about_fw_info);
  1091. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1092. &mbox_cmd[0], &mbox_sts[0]);
  1093. if (status != QLA_SUCCESS) {
  1094. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  1095. "failed w/ status %04X\n", __func__,
  1096. mbox_sts[0]));
  1097. goto exit_about_fw;
  1098. }
  1099. /* Save version information. */
  1100. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1101. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1102. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1103. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1104. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1105. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1106. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1107. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1108. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1109. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1110. status = QLA_SUCCESS;
  1111. exit_about_fw:
  1112. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1113. about_fw, about_fw_dma);
  1114. return status;
  1115. }
  1116. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1117. dma_addr_t dma_addr)
  1118. {
  1119. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1120. uint32_t mbox_sts[MBOX_REG_COUNT];
  1121. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1122. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1123. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1124. mbox_cmd[1] = options;
  1125. mbox_cmd[2] = LSDW(dma_addr);
  1126. mbox_cmd[3] = MSDW(dma_addr);
  1127. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1128. QLA_SUCCESS) {
  1129. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1130. ha->host_no, __func__, mbox_sts[0]));
  1131. return QLA_ERROR;
  1132. }
  1133. return QLA_SUCCESS;
  1134. }
  1135. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1136. uint32_t *mbx_sts)
  1137. {
  1138. int status;
  1139. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1140. uint32_t mbox_sts[MBOX_REG_COUNT];
  1141. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1142. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1143. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1144. mbox_cmd[1] = ddb_index;
  1145. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1146. &mbox_sts[0]);
  1147. if (status != QLA_SUCCESS) {
  1148. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1149. __func__, mbox_sts[0]));
  1150. }
  1151. *mbx_sts = mbox_sts[0];
  1152. return status;
  1153. }
  1154. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1155. {
  1156. int status;
  1157. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1158. uint32_t mbox_sts[MBOX_REG_COUNT];
  1159. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1160. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1161. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1162. mbox_cmd[1] = ddb_index;
  1163. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1164. &mbox_sts[0]);
  1165. if (status != QLA_SUCCESS) {
  1166. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1167. __func__, mbox_sts[0]));
  1168. }
  1169. return status;
  1170. }
  1171. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1172. uint32_t offset, uint32_t length, uint32_t options)
  1173. {
  1174. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1175. uint32_t mbox_sts[MBOX_REG_COUNT];
  1176. int status = QLA_SUCCESS;
  1177. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1178. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1179. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1180. mbox_cmd[1] = LSDW(dma_addr);
  1181. mbox_cmd[2] = MSDW(dma_addr);
  1182. mbox_cmd[3] = offset;
  1183. mbox_cmd[4] = length;
  1184. mbox_cmd[5] = options;
  1185. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1186. if (status != QLA_SUCCESS) {
  1187. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1188. "failed w/ status %04X, mbx1 %04X\n",
  1189. __func__, mbox_sts[0], mbox_sts[1]));
  1190. }
  1191. return status;
  1192. }
  1193. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1194. struct dev_db_entry *fw_ddb_entry,
  1195. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1196. {
  1197. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1198. uint32_t dev_db_end_offset;
  1199. int status = QLA_ERROR;
  1200. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1201. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1202. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1203. if (dev_db_start_offset > dev_db_end_offset) {
  1204. DEBUG2(ql4_printk(KERN_ERR, ha,
  1205. "%s:Invalid DDB index %d", __func__,
  1206. ddb_index));
  1207. goto exit_bootdb_failed;
  1208. }
  1209. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1210. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1211. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1212. "failed\n", ha->host_no, __func__);
  1213. goto exit_bootdb_failed;
  1214. }
  1215. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1216. status = QLA_SUCCESS;
  1217. exit_bootdb_failed:
  1218. return status;
  1219. }
  1220. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1221. uint16_t idx)
  1222. {
  1223. int ret = 0;
  1224. int rval = QLA_ERROR;
  1225. uint32_t offset = 0, chap_size;
  1226. struct ql4_chap_table *chap_table;
  1227. dma_addr_t chap_dma;
  1228. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1229. if (chap_table == NULL)
  1230. return -ENOMEM;
  1231. chap_size = sizeof(struct ql4_chap_table);
  1232. memset(chap_table, 0, chap_size);
  1233. if (is_qla40XX(ha))
  1234. offset = FLASH_CHAP_OFFSET | (idx * chap_size);
  1235. else {
  1236. offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
  1237. /* flt_chap_size is CHAP table size for both ports
  1238. * so divide it by 2 to calculate the offset for second port
  1239. */
  1240. if (ha->port_num == 1)
  1241. offset += (ha->hw.flt_chap_size / 2);
  1242. offset += (idx * chap_size);
  1243. }
  1244. rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
  1245. if (rval != QLA_SUCCESS) {
  1246. ret = -EINVAL;
  1247. goto exit_get_chap;
  1248. }
  1249. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1250. __le16_to_cpu(chap_table->cookie)));
  1251. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1252. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1253. goto exit_get_chap;
  1254. }
  1255. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1256. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1257. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1258. exit_get_chap:
  1259. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1260. return ret;
  1261. }
  1262. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1263. char *password, uint16_t idx, int bidi)
  1264. {
  1265. int ret = 0;
  1266. int rval = QLA_ERROR;
  1267. uint32_t offset = 0;
  1268. struct ql4_chap_table *chap_table;
  1269. dma_addr_t chap_dma;
  1270. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1271. if (chap_table == NULL) {
  1272. ret = -ENOMEM;
  1273. goto exit_set_chap;
  1274. }
  1275. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1276. if (bidi)
  1277. chap_table->flags |= BIT_6; /* peer */
  1278. else
  1279. chap_table->flags |= BIT_7; /* local */
  1280. chap_table->secret_len = strlen(password);
  1281. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1282. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1283. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1284. offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
  1285. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1286. sizeof(struct ql4_chap_table),
  1287. FLASH_OPT_RMW_COMMIT);
  1288. if (rval == QLA_SUCCESS && ha->chap_list) {
  1289. /* Update ha chap_list cache */
  1290. memcpy((struct ql4_chap_table *)ha->chap_list + idx,
  1291. chap_table, sizeof(struct ql4_chap_table));
  1292. }
  1293. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1294. if (rval != QLA_SUCCESS)
  1295. ret = -EINVAL;
  1296. exit_set_chap:
  1297. return ret;
  1298. }
  1299. /**
  1300. * qla4xxx_get_chap_index - Get chap index given username and secret
  1301. * @ha: pointer to adapter structure
  1302. * @username: CHAP username to be searched
  1303. * @password: CHAP password to be searched
  1304. * @bidi: Is this a BIDI CHAP
  1305. * @chap_index: CHAP index to be returned
  1306. *
  1307. * Match the username and password in the chap_list, return the index if a
  1308. * match is found. If a match is not found then add the entry in FLASH and
  1309. * return the index at which entry is written in the FLASH.
  1310. **/
  1311. int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
  1312. char *password, int bidi, uint16_t *chap_index)
  1313. {
  1314. int i, rval;
  1315. int free_index = -1;
  1316. int found_index = 0;
  1317. int max_chap_entries = 0;
  1318. struct ql4_chap_table *chap_table;
  1319. if (is_qla8022(ha))
  1320. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1321. sizeof(struct ql4_chap_table);
  1322. else
  1323. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1324. if (!ha->chap_list) {
  1325. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1326. return QLA_ERROR;
  1327. }
  1328. if (!username || !password) {
  1329. ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
  1330. return QLA_ERROR;
  1331. }
  1332. mutex_lock(&ha->chap_sem);
  1333. for (i = 0; i < max_chap_entries; i++) {
  1334. chap_table = (struct ql4_chap_table *)ha->chap_list + i;
  1335. if (chap_table->cookie !=
  1336. __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1337. if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
  1338. free_index = i;
  1339. continue;
  1340. }
  1341. if (bidi) {
  1342. if (chap_table->flags & BIT_7)
  1343. continue;
  1344. } else {
  1345. if (chap_table->flags & BIT_6)
  1346. continue;
  1347. }
  1348. if (!strncmp(chap_table->secret, password,
  1349. MAX_CHAP_SECRET_LEN) &&
  1350. !strncmp(chap_table->name, username,
  1351. MAX_CHAP_NAME_LEN)) {
  1352. *chap_index = i;
  1353. found_index = 1;
  1354. break;
  1355. }
  1356. }
  1357. /* If chap entry is not present and a free index is available then
  1358. * write the entry in flash
  1359. */
  1360. if (!found_index && free_index != -1) {
  1361. rval = qla4xxx_set_chap(ha, username, password,
  1362. free_index, bidi);
  1363. if (!rval) {
  1364. *chap_index = free_index;
  1365. found_index = 1;
  1366. }
  1367. }
  1368. mutex_unlock(&ha->chap_sem);
  1369. if (found_index)
  1370. return QLA_SUCCESS;
  1371. return QLA_ERROR;
  1372. }
  1373. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1374. uint16_t fw_ddb_index,
  1375. uint16_t connection_id,
  1376. uint16_t option)
  1377. {
  1378. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1379. uint32_t mbox_sts[MBOX_REG_COUNT];
  1380. int status = QLA_SUCCESS;
  1381. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1382. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1383. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1384. mbox_cmd[1] = fw_ddb_index;
  1385. mbox_cmd[2] = connection_id;
  1386. mbox_cmd[3] = option;
  1387. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1388. if (status != QLA_SUCCESS) {
  1389. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1390. "option %04x failed w/ status %04X %04X\n",
  1391. __func__, option, mbox_sts[0], mbox_sts[1]));
  1392. }
  1393. return status;
  1394. }
  1395. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1396. {
  1397. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1398. uint32_t mbox_sts[MBOX_REG_COUNT];
  1399. int status = QLA_SUCCESS;
  1400. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1401. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1402. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1403. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1404. if (status != QLA_SUCCESS) {
  1405. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1406. "failed w/ status %04X %04X %04X", __func__,
  1407. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1408. }
  1409. return status;
  1410. }
  1411. int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
  1412. uint32_t acb_type, uint32_t len)
  1413. {
  1414. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1415. uint32_t mbox_sts[MBOX_REG_COUNT];
  1416. int status = QLA_SUCCESS;
  1417. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1418. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1419. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1420. mbox_cmd[1] = acb_type;
  1421. mbox_cmd[2] = LSDW(acb_dma);
  1422. mbox_cmd[3] = MSDW(acb_dma);
  1423. mbox_cmd[4] = len;
  1424. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1425. if (status != QLA_SUCCESS) {
  1426. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1427. "failed w/ status %04X\n", __func__,
  1428. mbox_sts[0]));
  1429. }
  1430. return status;
  1431. }
  1432. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1433. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1434. {
  1435. int status = QLA_SUCCESS;
  1436. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1437. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1438. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1439. mbox_cmd[1] = 0; /* Primary ACB */
  1440. mbox_cmd[2] = LSDW(acb_dma);
  1441. mbox_cmd[3] = MSDW(acb_dma);
  1442. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1443. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1444. if (status != QLA_SUCCESS) {
  1445. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1446. "failed w/ status %04X\n", __func__,
  1447. mbox_sts[0]));
  1448. }
  1449. return status;
  1450. }
  1451. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1452. struct ddb_entry *ddb_entry,
  1453. struct iscsi_cls_conn *cls_conn,
  1454. uint32_t *mbx_sts)
  1455. {
  1456. struct dev_db_entry *fw_ddb_entry;
  1457. struct iscsi_conn *conn;
  1458. struct iscsi_session *sess;
  1459. struct qla_conn *qla_conn;
  1460. struct sockaddr *dst_addr;
  1461. dma_addr_t fw_ddb_entry_dma;
  1462. int status = QLA_SUCCESS;
  1463. int rval = 0;
  1464. struct sockaddr_in *addr;
  1465. struct sockaddr_in6 *addr6;
  1466. char *ip;
  1467. uint16_t iscsi_opts = 0;
  1468. uint32_t options = 0;
  1469. uint16_t idx, *ptid;
  1470. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1471. &fw_ddb_entry_dma, GFP_KERNEL);
  1472. if (!fw_ddb_entry) {
  1473. DEBUG2(ql4_printk(KERN_ERR, ha,
  1474. "%s: Unable to allocate dma buffer.\n",
  1475. __func__));
  1476. rval = -ENOMEM;
  1477. goto exit_set_param_no_free;
  1478. }
  1479. conn = cls_conn->dd_data;
  1480. qla_conn = conn->dd_data;
  1481. sess = conn->session;
  1482. dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
  1483. if (dst_addr->sa_family == AF_INET6)
  1484. options |= IPV6_DEFAULT_DDB_ENTRY;
  1485. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1486. if (status == QLA_ERROR) {
  1487. rval = -EINVAL;
  1488. goto exit_set_param;
  1489. }
  1490. ptid = (uint16_t *)&fw_ddb_entry->isid[1];
  1491. *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
  1492. DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
  1493. fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
  1494. fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
  1495. fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
  1496. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1497. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1498. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1499. if (sess->targetname != NULL) {
  1500. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1501. min(strlen(sess->targetname),
  1502. sizeof(fw_ddb_entry->iscsi_name)));
  1503. }
  1504. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1505. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1506. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1507. if (dst_addr->sa_family == AF_INET) {
  1508. addr = (struct sockaddr_in *)dst_addr;
  1509. ip = (char *)&addr->sin_addr;
  1510. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1511. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1512. DEBUG2(ql4_printk(KERN_INFO, ha,
  1513. "%s: Destination Address [%pI4]: index [%d]\n",
  1514. __func__, fw_ddb_entry->ip_addr,
  1515. ddb_entry->fw_ddb_index));
  1516. } else if (dst_addr->sa_family == AF_INET6) {
  1517. addr6 = (struct sockaddr_in6 *)dst_addr;
  1518. ip = (char *)&addr6->sin6_addr;
  1519. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1520. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1521. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1522. DEBUG2(ql4_printk(KERN_INFO, ha,
  1523. "%s: Destination Address [%pI6]: index [%d]\n",
  1524. __func__, fw_ddb_entry->ip_addr,
  1525. ddb_entry->fw_ddb_index));
  1526. } else {
  1527. ql4_printk(KERN_ERR, ha,
  1528. "%s: Failed to get IP Address\n",
  1529. __func__);
  1530. rval = -EINVAL;
  1531. goto exit_set_param;
  1532. }
  1533. /* CHAP */
  1534. if (sess->username != NULL && sess->password != NULL) {
  1535. if (strlen(sess->username) && strlen(sess->password)) {
  1536. iscsi_opts |= BIT_7;
  1537. rval = qla4xxx_get_chap_index(ha, sess->username,
  1538. sess->password,
  1539. LOCAL_CHAP, &idx);
  1540. if (rval)
  1541. goto exit_set_param;
  1542. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1543. }
  1544. }
  1545. if (sess->username_in != NULL && sess->password_in != NULL) {
  1546. /* Check if BIDI CHAP */
  1547. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1548. iscsi_opts |= BIT_4;
  1549. rval = qla4xxx_get_chap_index(ha, sess->username_in,
  1550. sess->password_in,
  1551. BIDI_CHAP, &idx);
  1552. if (rval)
  1553. goto exit_set_param;
  1554. }
  1555. }
  1556. if (sess->initial_r2t_en)
  1557. iscsi_opts |= BIT_10;
  1558. if (sess->imm_data_en)
  1559. iscsi_opts |= BIT_11;
  1560. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1561. if (conn->max_recv_dlength)
  1562. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1563. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1564. if (sess->max_r2t)
  1565. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1566. if (sess->first_burst)
  1567. fw_ddb_entry->iscsi_first_burst_len =
  1568. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1569. if (sess->max_burst)
  1570. fw_ddb_entry->iscsi_max_burst_len =
  1571. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1572. if (sess->time2wait)
  1573. fw_ddb_entry->iscsi_def_time2wait =
  1574. cpu_to_le16(sess->time2wait);
  1575. if (sess->time2retain)
  1576. fw_ddb_entry->iscsi_def_time2retain =
  1577. cpu_to_le16(sess->time2retain);
  1578. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1579. fw_ddb_entry_dma, mbx_sts);
  1580. if (status != QLA_SUCCESS)
  1581. rval = -EINVAL;
  1582. exit_set_param:
  1583. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1584. fw_ddb_entry, fw_ddb_entry_dma);
  1585. exit_set_param_no_free:
  1586. return rval;
  1587. }
  1588. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1589. uint16_t stats_size, dma_addr_t stats_dma)
  1590. {
  1591. int status = QLA_SUCCESS;
  1592. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1593. uint32_t mbox_sts[MBOX_REG_COUNT];
  1594. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1595. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1596. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1597. mbox_cmd[1] = fw_ddb_index;
  1598. mbox_cmd[2] = LSDW(stats_dma);
  1599. mbox_cmd[3] = MSDW(stats_dma);
  1600. mbox_cmd[4] = stats_size;
  1601. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1602. if (status != QLA_SUCCESS) {
  1603. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1604. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1605. "failed w/ status %04X\n", __func__,
  1606. mbox_sts[0]));
  1607. }
  1608. return status;
  1609. }
  1610. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1611. uint32_t ip_idx, uint32_t *sts)
  1612. {
  1613. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1614. uint32_t mbox_sts[MBOX_REG_COUNT];
  1615. int status = QLA_SUCCESS;
  1616. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1617. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1618. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1619. mbox_cmd[1] = acb_idx;
  1620. mbox_cmd[2] = ip_idx;
  1621. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1622. if (status != QLA_SUCCESS) {
  1623. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1624. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1625. "status %04X\n", __func__, mbox_sts[0]));
  1626. }
  1627. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1628. return status;
  1629. }
  1630. int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1631. uint32_t offset, uint32_t size)
  1632. {
  1633. int status = QLA_SUCCESS;
  1634. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1635. uint32_t mbox_sts[MBOX_REG_COUNT];
  1636. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1637. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1638. mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
  1639. mbox_cmd[1] = LSDW(nvram_dma);
  1640. mbox_cmd[2] = MSDW(nvram_dma);
  1641. mbox_cmd[3] = offset;
  1642. mbox_cmd[4] = size;
  1643. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1644. &mbox_sts[0]);
  1645. if (status != QLA_SUCCESS) {
  1646. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1647. "status %04X\n", ha->host_no, __func__,
  1648. mbox_sts[0]));
  1649. }
  1650. return status;
  1651. }
  1652. int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1653. uint32_t offset, uint32_t size)
  1654. {
  1655. int status = QLA_SUCCESS;
  1656. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1657. uint32_t mbox_sts[MBOX_REG_COUNT];
  1658. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1659. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1660. mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
  1661. mbox_cmd[1] = LSDW(nvram_dma);
  1662. mbox_cmd[2] = MSDW(nvram_dma);
  1663. mbox_cmd[3] = offset;
  1664. mbox_cmd[4] = size;
  1665. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1666. &mbox_sts[0]);
  1667. if (status != QLA_SUCCESS) {
  1668. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1669. "status %04X\n", ha->host_no, __func__,
  1670. mbox_sts[0]));
  1671. }
  1672. return status;
  1673. }
  1674. int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
  1675. uint32_t region, uint32_t field0,
  1676. uint32_t field1)
  1677. {
  1678. int status = QLA_SUCCESS;
  1679. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1680. uint32_t mbox_sts[MBOX_REG_COUNT];
  1681. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1682. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1683. mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
  1684. mbox_cmd[3] = region;
  1685. mbox_cmd[4] = field0;
  1686. mbox_cmd[5] = field1;
  1687. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
  1688. &mbox_sts[0]);
  1689. if (status != QLA_SUCCESS) {
  1690. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1691. "status %04X\n", ha->host_no, __func__,
  1692. mbox_sts[0]));
  1693. }
  1694. return status;
  1695. }
  1696. /**
  1697. * qla4_8xxx_set_param - set driver version in firmware.
  1698. * @ha: Pointer to host adapter structure.
  1699. * @param: Parameter to set i.e driver version
  1700. **/
  1701. int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
  1702. {
  1703. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1704. uint32_t mbox_sts[MBOX_REG_COUNT];
  1705. uint32_t status;
  1706. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1707. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1708. mbox_cmd[0] = MBOX_CMD_SET_PARAM;
  1709. if (param == SET_DRVR_VERSION) {
  1710. mbox_cmd[1] = SET_DRVR_VERSION;
  1711. strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
  1712. MAX_DRVR_VER_LEN);
  1713. } else {
  1714. ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
  1715. __func__, param);
  1716. status = QLA_ERROR;
  1717. goto exit_set_param;
  1718. }
  1719. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
  1720. mbox_sts);
  1721. if (status == QLA_ERROR)
  1722. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1723. __func__, mbox_sts[0]);
  1724. exit_set_param:
  1725. return status;
  1726. }
  1727. /**
  1728. * qla4_83xx_post_idc_ack - post IDC ACK
  1729. * @ha: Pointer to host adapter structure.
  1730. *
  1731. * Posts IDC ACK for IDC Request Notification AEN.
  1732. **/
  1733. int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
  1734. {
  1735. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1736. uint32_t mbox_sts[MBOX_REG_COUNT];
  1737. int status;
  1738. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1739. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1740. mbox_cmd[0] = MBOX_CMD_IDC_ACK;
  1741. mbox_cmd[1] = ha->idc_info.request_desc;
  1742. mbox_cmd[2] = ha->idc_info.info1;
  1743. mbox_cmd[3] = ha->idc_info.info2;
  1744. mbox_cmd[4] = ha->idc_info.info3;
  1745. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1746. mbox_cmd, mbox_sts);
  1747. if (status == QLA_ERROR)
  1748. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
  1749. mbox_sts[0]);
  1750. else
  1751. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n",
  1752. __func__));
  1753. return status;
  1754. }