mpi2_ioc.h 82 KB

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  1. /*
  2. * Copyright (c) 2000-2012 LSI Corporation.
  3. *
  4. *
  5. * Name: mpi2_ioc.h
  6. * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
  7. * Creation Date: October 11, 2006
  8. *
  9. * mpi2_ioc.h Version: 02.00.21
  10. *
  11. * Version History
  12. * ---------------
  13. *
  14. * Date Version Description
  15. * -------- -------- ------------------------------------------------------
  16. * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
  17. * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
  18. * MaxTargets.
  19. * Added TotalImageSize field to FWDownload Request.
  20. * Added reserved words to FWUpload Request.
  21. * 06-26-07 02.00.02 Added IR Configuration Change List Event.
  22. * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
  23. * request and replaced it with
  24. * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  25. * Replaced the MinReplyQueueDepth field of the IOCFacts
  26. * reply with MaxReplyDescriptorPostQueueDepth.
  27. * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  28. * depth for the Reply Descriptor Post Queue.
  29. * Added SASAddress field to Initiator Device Table
  30. * Overflow Event data.
  31. * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  32. * for SAS Initiator Device Status Change Event data.
  33. * Modified Reason Code defines for SAS Topology Change
  34. * List Event data, including adding a bit for PHY Vacant
  35. * status, and adding a mask for the Reason Code.
  36. * Added define for
  37. * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  38. * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  39. * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
  40. * the IOCFacts Reply.
  41. * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  42. * Moved MPI2_VERSION_UNION to mpi2.h.
  43. * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  44. * instead of enables, and added SASBroadcastPrimitiveMasks
  45. * field.
  46. * Added Log Entry Added Event and related structure.
  47. * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  48. * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  49. * Added MaxVolumes and MaxPersistentEntries fields to
  50. * IOCFacts reply.
  51. * Added ProtocalFlags and IOCCapabilities fields to
  52. * MPI2_FW_IMAGE_HEADER.
  53. * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  54. * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  55. * a U16 (from a U32).
  56. * Removed extra 's' from EventMasks name.
  57. * 06-27-08 02.00.08 Fixed an offset in a comment.
  58. * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  59. * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  60. * renamed MinReplyFrameSize to ReplyFrameSize.
  61. * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  62. * Added two new RAIDOperation values for Integrated RAID
  63. * Operations Status Event data.
  64. * Added four new IR Configuration Change List Event data
  65. * ReasonCode values.
  66. * Added two new ReasonCode defines for SAS Device Status
  67. * Change Event data.
  68. * Added three new DiscoveryStatus bits for the SAS
  69. * Discovery event data.
  70. * Added Multiplexing Status Change bit to the PhyStatus
  71. * field of the SAS Topology Change List event data.
  72. * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  73. * BootFlags are now product-specific.
  74. * Added defines for the indivdual signature bytes
  75. * for MPI2_INIT_IMAGE_FOOTER.
  76. * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  77. * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  78. * define.
  79. * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  80. * define.
  81. * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  82. * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  83. * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  84. * Added two new reason codes for SAS Device Status Change
  85. * Event.
  86. * Added new event: SAS PHY Counter.
  87. * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
  88. * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  89. * Added new product id family for 2208.
  90. * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  91. * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  92. * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  93. * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  94. * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  95. * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  96. * Added Host Based Discovery Phy Event data.
  97. * Added defines for ProductID Product field
  98. * (MPI2_FW_HEADER_PID_).
  99. * Modified values for SAS ProductID Family
  100. * (MPI2_FW_HEADER_PID_FAMILY_).
  101. * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
  102. * Added PowerManagementControl Request structures and
  103. * defines.
  104. * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
  105. * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
  106. * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
  107. * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
  108. * SASNotifyPrimitiveMasks field to
  109. * MPI2_EVENT_NOTIFICATION_REQUEST.
  110. * Added Temperature Threshold Event.
  111. * Added Host Message Event.
  112. * Added Send Host Message request and reply.
  113. * 05-25-11 02.00.18 For Extended Image Header, added
  114. * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
  115. * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
  116. * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
  117. * 08-24-11 02.00.19 Added PhysicalPort field to
  118. * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
  119. * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
  120. * 03-29-12 02.00.21 Added a product specific range to event values.
  121. * --------------------------------------------------------------------------
  122. */
  123. #ifndef MPI2_IOC_H
  124. #define MPI2_IOC_H
  125. /*****************************************************************************
  126. *
  127. * IOC Messages
  128. *
  129. *****************************************************************************/
  130. /****************************************************************************
  131. * IOCInit message
  132. ****************************************************************************/
  133. /* IOCInit Request message */
  134. typedef struct _MPI2_IOC_INIT_REQUEST
  135. {
  136. U8 WhoInit; /* 0x00 */
  137. U8 Reserved1; /* 0x01 */
  138. U8 ChainOffset; /* 0x02 */
  139. U8 Function; /* 0x03 */
  140. U16 Reserved2; /* 0x04 */
  141. U8 Reserved3; /* 0x06 */
  142. U8 MsgFlags; /* 0x07 */
  143. U8 VP_ID; /* 0x08 */
  144. U8 VF_ID; /* 0x09 */
  145. U16 Reserved4; /* 0x0A */
  146. U16 MsgVersion; /* 0x0C */
  147. U16 HeaderVersion; /* 0x0E */
  148. U32 Reserved5; /* 0x10 */
  149. U16 Reserved6; /* 0x14 */
  150. U8 Reserved7; /* 0x16 */
  151. U8 HostMSIxVectors; /* 0x17 */
  152. U16 Reserved8; /* 0x18 */
  153. U16 SystemRequestFrameSize; /* 0x1A */
  154. U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
  155. U16 ReplyFreeQueueDepth; /* 0x1E */
  156. U32 SenseBufferAddressHigh; /* 0x20 */
  157. U32 SystemReplyAddressHigh; /* 0x24 */
  158. U64 SystemRequestFrameBaseAddress; /* 0x28 */
  159. U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
  160. U64 ReplyFreeQueueAddress; /* 0x38 */
  161. U64 TimeStamp; /* 0x40 */
  162. } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
  163. Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
  164. /* WhoInit values */
  165. #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
  166. #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
  167. #define MPI2_WHOINIT_ROM_BIOS (0x02)
  168. #define MPI2_WHOINIT_PCI_PEER (0x03)
  169. #define MPI2_WHOINIT_HOST_DRIVER (0x04)
  170. #define MPI2_WHOINIT_MANUFACTURER (0x05)
  171. /* MsgVersion */
  172. #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
  173. #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
  174. #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
  175. #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
  176. /* HeaderVersion */
  177. #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
  178. #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
  179. #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
  180. #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
  181. /* minimum depth for the Reply Descriptor Post Queue */
  182. #define MPI2_RDPQ_DEPTH_MIN (16)
  183. /* IOCInit Reply message */
  184. typedef struct _MPI2_IOC_INIT_REPLY
  185. {
  186. U8 WhoInit; /* 0x00 */
  187. U8 Reserved1; /* 0x01 */
  188. U8 MsgLength; /* 0x02 */
  189. U8 Function; /* 0x03 */
  190. U16 Reserved2; /* 0x04 */
  191. U8 Reserved3; /* 0x06 */
  192. U8 MsgFlags; /* 0x07 */
  193. U8 VP_ID; /* 0x08 */
  194. U8 VF_ID; /* 0x09 */
  195. U16 Reserved4; /* 0x0A */
  196. U16 Reserved5; /* 0x0C */
  197. U16 IOCStatus; /* 0x0E */
  198. U32 IOCLogInfo; /* 0x10 */
  199. } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
  200. Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
  201. /****************************************************************************
  202. * IOCFacts message
  203. ****************************************************************************/
  204. /* IOCFacts Request message */
  205. typedef struct _MPI2_IOC_FACTS_REQUEST
  206. {
  207. U16 Reserved1; /* 0x00 */
  208. U8 ChainOffset; /* 0x02 */
  209. U8 Function; /* 0x03 */
  210. U16 Reserved2; /* 0x04 */
  211. U8 Reserved3; /* 0x06 */
  212. U8 MsgFlags; /* 0x07 */
  213. U8 VP_ID; /* 0x08 */
  214. U8 VF_ID; /* 0x09 */
  215. U16 Reserved4; /* 0x0A */
  216. } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
  217. Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
  218. /* IOCFacts Reply message */
  219. typedef struct _MPI2_IOC_FACTS_REPLY
  220. {
  221. U16 MsgVersion; /* 0x00 */
  222. U8 MsgLength; /* 0x02 */
  223. U8 Function; /* 0x03 */
  224. U16 HeaderVersion; /* 0x04 */
  225. U8 IOCNumber; /* 0x06 */
  226. U8 MsgFlags; /* 0x07 */
  227. U8 VP_ID; /* 0x08 */
  228. U8 VF_ID; /* 0x09 */
  229. U16 Reserved1; /* 0x0A */
  230. U16 IOCExceptions; /* 0x0C */
  231. U16 IOCStatus; /* 0x0E */
  232. U32 IOCLogInfo; /* 0x10 */
  233. U8 MaxChainDepth; /* 0x14 */
  234. U8 WhoInit; /* 0x15 */
  235. U8 NumberOfPorts; /* 0x16 */
  236. U8 MaxMSIxVectors; /* 0x17 */
  237. U16 RequestCredit; /* 0x18 */
  238. U16 ProductID; /* 0x1A */
  239. U32 IOCCapabilities; /* 0x1C */
  240. MPI2_VERSION_UNION FWVersion; /* 0x20 */
  241. U16 IOCRequestFrameSize; /* 0x24 */
  242. U16 Reserved3; /* 0x26 */
  243. U16 MaxInitiators; /* 0x28 */
  244. U16 MaxTargets; /* 0x2A */
  245. U16 MaxSasExpanders; /* 0x2C */
  246. U16 MaxEnclosures; /* 0x2E */
  247. U16 ProtocolFlags; /* 0x30 */
  248. U16 HighPriorityCredit; /* 0x32 */
  249. U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
  250. U8 ReplyFrameSize; /* 0x36 */
  251. U8 MaxVolumes; /* 0x37 */
  252. U16 MaxDevHandle; /* 0x38 */
  253. U16 MaxPersistentEntries; /* 0x3A */
  254. U16 MinDevHandle; /* 0x3C */
  255. U16 Reserved4; /* 0x3E */
  256. } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
  257. Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
  258. /* MsgVersion */
  259. #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
  260. #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
  261. #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
  262. #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
  263. /* HeaderVersion */
  264. #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
  265. #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
  266. #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
  267. #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
  268. /* IOCExceptions */
  269. #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
  270. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
  271. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
  272. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
  273. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
  274. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
  275. #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
  276. #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
  277. #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
  278. #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
  279. #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
  280. /* defines for WhoInit field are after the IOCInit Request */
  281. /* ProductID field uses MPI2_FW_HEADER_PID_ */
  282. /* IOCCapabilities */
  283. #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
  284. #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
  285. #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
  286. #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
  287. #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
  288. #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
  289. #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
  290. #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
  291. #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
  292. #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
  293. #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
  294. #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
  295. #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
  296. /* ProtocolFlags */
  297. #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
  298. #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
  299. /****************************************************************************
  300. * PortFacts message
  301. ****************************************************************************/
  302. /* PortFacts Request message */
  303. typedef struct _MPI2_PORT_FACTS_REQUEST
  304. {
  305. U16 Reserved1; /* 0x00 */
  306. U8 ChainOffset; /* 0x02 */
  307. U8 Function; /* 0x03 */
  308. U16 Reserved2; /* 0x04 */
  309. U8 PortNumber; /* 0x06 */
  310. U8 MsgFlags; /* 0x07 */
  311. U8 VP_ID; /* 0x08 */
  312. U8 VF_ID; /* 0x09 */
  313. U16 Reserved3; /* 0x0A */
  314. } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
  315. Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
  316. /* PortFacts Reply message */
  317. typedef struct _MPI2_PORT_FACTS_REPLY
  318. {
  319. U16 Reserved1; /* 0x00 */
  320. U8 MsgLength; /* 0x02 */
  321. U8 Function; /* 0x03 */
  322. U16 Reserved2; /* 0x04 */
  323. U8 PortNumber; /* 0x06 */
  324. U8 MsgFlags; /* 0x07 */
  325. U8 VP_ID; /* 0x08 */
  326. U8 VF_ID; /* 0x09 */
  327. U16 Reserved3; /* 0x0A */
  328. U16 Reserved4; /* 0x0C */
  329. U16 IOCStatus; /* 0x0E */
  330. U32 IOCLogInfo; /* 0x10 */
  331. U8 Reserved5; /* 0x14 */
  332. U8 PortType; /* 0x15 */
  333. U16 Reserved6; /* 0x16 */
  334. U16 MaxPostedCmdBuffers; /* 0x18 */
  335. U16 Reserved7; /* 0x1A */
  336. } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
  337. Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
  338. /* PortType values */
  339. #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
  340. #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
  341. #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
  342. #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
  343. #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
  344. /****************************************************************************
  345. * PortEnable message
  346. ****************************************************************************/
  347. /* PortEnable Request message */
  348. typedef struct _MPI2_PORT_ENABLE_REQUEST
  349. {
  350. U16 Reserved1; /* 0x00 */
  351. U8 ChainOffset; /* 0x02 */
  352. U8 Function; /* 0x03 */
  353. U8 Reserved2; /* 0x04 */
  354. U8 PortFlags; /* 0x05 */
  355. U8 Reserved3; /* 0x06 */
  356. U8 MsgFlags; /* 0x07 */
  357. U8 VP_ID; /* 0x08 */
  358. U8 VF_ID; /* 0x09 */
  359. U16 Reserved4; /* 0x0A */
  360. } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
  361. Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
  362. /* PortEnable Reply message */
  363. typedef struct _MPI2_PORT_ENABLE_REPLY
  364. {
  365. U16 Reserved1; /* 0x00 */
  366. U8 MsgLength; /* 0x02 */
  367. U8 Function; /* 0x03 */
  368. U8 Reserved2; /* 0x04 */
  369. U8 PortFlags; /* 0x05 */
  370. U8 Reserved3; /* 0x06 */
  371. U8 MsgFlags; /* 0x07 */
  372. U8 VP_ID; /* 0x08 */
  373. U8 VF_ID; /* 0x09 */
  374. U16 Reserved4; /* 0x0A */
  375. U16 Reserved5; /* 0x0C */
  376. U16 IOCStatus; /* 0x0E */
  377. U32 IOCLogInfo; /* 0x10 */
  378. } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
  379. Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
  380. /****************************************************************************
  381. * EventNotification message
  382. ****************************************************************************/
  383. /* EventNotification Request message */
  384. #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
  385. typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
  386. {
  387. U16 Reserved1; /* 0x00 */
  388. U8 ChainOffset; /* 0x02 */
  389. U8 Function; /* 0x03 */
  390. U16 Reserved2; /* 0x04 */
  391. U8 Reserved3; /* 0x06 */
  392. U8 MsgFlags; /* 0x07 */
  393. U8 VP_ID; /* 0x08 */
  394. U8 VF_ID; /* 0x09 */
  395. U16 Reserved4; /* 0x0A */
  396. U32 Reserved5; /* 0x0C */
  397. U32 Reserved6; /* 0x10 */
  398. U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
  399. U16 SASBroadcastPrimitiveMasks; /* 0x24 */
  400. U16 SASNotifyPrimitiveMasks; /* 0x26 */
  401. U32 Reserved8; /* 0x28 */
  402. } MPI2_EVENT_NOTIFICATION_REQUEST,
  403. MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
  404. Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
  405. /* EventNotification Reply message */
  406. typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
  407. {
  408. U16 EventDataLength; /* 0x00 */
  409. U8 MsgLength; /* 0x02 */
  410. U8 Function; /* 0x03 */
  411. U16 Reserved1; /* 0x04 */
  412. U8 AckRequired; /* 0x06 */
  413. U8 MsgFlags; /* 0x07 */
  414. U8 VP_ID; /* 0x08 */
  415. U8 VF_ID; /* 0x09 */
  416. U16 Reserved2; /* 0x0A */
  417. U16 Reserved3; /* 0x0C */
  418. U16 IOCStatus; /* 0x0E */
  419. U32 IOCLogInfo; /* 0x10 */
  420. U16 Event; /* 0x14 */
  421. U16 Reserved4; /* 0x16 */
  422. U32 EventContext; /* 0x18 */
  423. U32 EventData[1]; /* 0x1C */
  424. } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
  425. Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
  426. /* AckRequired */
  427. #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
  428. #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
  429. /* Event */
  430. #define MPI2_EVENT_LOG_DATA (0x0001)
  431. #define MPI2_EVENT_STATE_CHANGE (0x0002)
  432. #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
  433. #define MPI2_EVENT_EVENT_CHANGE (0x000A)
  434. #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
  435. #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
  436. #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
  437. #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
  438. #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
  439. #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
  440. #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
  441. #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
  442. #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
  443. #define MPI2_EVENT_IR_VOLUME (0x001E)
  444. #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
  445. #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
  446. #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
  447. #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
  448. #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
  449. #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
  450. #define MPI2_EVENT_SAS_QUIESCE (0x0025)
  451. #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
  452. #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
  453. #define MPI2_EVENT_HOST_MESSAGE (0x0028)
  454. #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
  455. #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
  456. /* Log Entry Added Event data */
  457. /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
  458. #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
  459. typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
  460. {
  461. U64 TimeStamp; /* 0x00 */
  462. U32 Reserved1; /* 0x08 */
  463. U16 LogSequence; /* 0x0C */
  464. U16 LogEntryQualifier; /* 0x0E */
  465. U8 VP_ID; /* 0x10 */
  466. U8 VF_ID; /* 0x11 */
  467. U16 Reserved2; /* 0x12 */
  468. U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
  469. } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
  470. MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
  471. Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
  472. /* GPIO Interrupt Event data */
  473. typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
  474. U8 GPIONum; /* 0x00 */
  475. U8 Reserved1; /* 0x01 */
  476. U16 Reserved2; /* 0x02 */
  477. } MPI2_EVENT_DATA_GPIO_INTERRUPT,
  478. MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
  479. Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
  480. /* Temperature Threshold Event data */
  481. typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
  482. U16 Status; /* 0x00 */
  483. U8 SensorNum; /* 0x02 */
  484. U8 Reserved1; /* 0x03 */
  485. U16 CurrentTemperature; /* 0x04 */
  486. U16 Reserved2; /* 0x06 */
  487. U32 Reserved3; /* 0x08 */
  488. U32 Reserved4; /* 0x0C */
  489. } MPI2_EVENT_DATA_TEMPERATURE,
  490. MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
  491. Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
  492. /* Temperature Threshold Event data Status bits */
  493. #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
  494. #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
  495. #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
  496. #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
  497. /* Host Message Event data */
  498. typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
  499. U8 SourceVF_ID; /* 0x00 */
  500. U8 Reserved1; /* 0x01 */
  501. U16 Reserved2; /* 0x02 */
  502. U32 Reserved3; /* 0x04 */
  503. U32 HostData[1]; /* 0x08 */
  504. } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
  505. Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
  506. /* Hard Reset Received Event data */
  507. typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
  508. {
  509. U8 Reserved1; /* 0x00 */
  510. U8 Port; /* 0x01 */
  511. U16 Reserved2; /* 0x02 */
  512. } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
  513. MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
  514. Mpi2EventDataHardResetReceived_t,
  515. MPI2_POINTER pMpi2EventDataHardResetReceived_t;
  516. /* Task Set Full Event data */
  517. /* this event is obsolete */
  518. typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
  519. {
  520. U16 DevHandle; /* 0x00 */
  521. U16 CurrentDepth; /* 0x02 */
  522. } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
  523. Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
  524. /* SAS Device Status Change Event data */
  525. typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
  526. {
  527. U16 TaskTag; /* 0x00 */
  528. U8 ReasonCode; /* 0x02 */
  529. U8 PhysicalPort; /* 0x03 */
  530. U8 ASC; /* 0x04 */
  531. U8 ASCQ; /* 0x05 */
  532. U16 DevHandle; /* 0x06 */
  533. U32 Reserved2; /* 0x08 */
  534. U64 SASAddress; /* 0x0C */
  535. U8 LUN[8]; /* 0x14 */
  536. } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
  537. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
  538. Mpi2EventDataSasDeviceStatusChange_t,
  539. MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
  540. /* SAS Device Status Change Event data ReasonCode values */
  541. #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
  542. #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
  543. #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
  544. #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
  545. #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
  546. #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
  547. #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
  548. #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
  549. #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
  550. #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
  551. #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
  552. #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
  553. #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
  554. /* Integrated RAID Operation Status Event data */
  555. typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
  556. {
  557. U16 VolDevHandle; /* 0x00 */
  558. U16 Reserved1; /* 0x02 */
  559. U8 RAIDOperation; /* 0x04 */
  560. U8 PercentComplete; /* 0x05 */
  561. U16 Reserved2; /* 0x06 */
  562. U32 Resereved3; /* 0x08 */
  563. } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
  564. MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
  565. Mpi2EventDataIrOperationStatus_t,
  566. MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
  567. /* Integrated RAID Operation Status Event data RAIDOperation values */
  568. #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
  569. #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
  570. #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
  571. #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
  572. #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
  573. /* Integrated RAID Volume Event data */
  574. typedef struct _MPI2_EVENT_DATA_IR_VOLUME
  575. {
  576. U16 VolDevHandle; /* 0x00 */
  577. U8 ReasonCode; /* 0x02 */
  578. U8 Reserved1; /* 0x03 */
  579. U32 NewValue; /* 0x04 */
  580. U32 PreviousValue; /* 0x08 */
  581. } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
  582. Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
  583. /* Integrated RAID Volume Event data ReasonCode values */
  584. #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
  585. #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
  586. #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
  587. /* Integrated RAID Physical Disk Event data */
  588. typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
  589. {
  590. U16 Reserved1; /* 0x00 */
  591. U8 ReasonCode; /* 0x02 */
  592. U8 PhysDiskNum; /* 0x03 */
  593. U16 PhysDiskDevHandle; /* 0x04 */
  594. U16 Reserved2; /* 0x06 */
  595. U16 Slot; /* 0x08 */
  596. U16 EnclosureHandle; /* 0x0A */
  597. U32 NewValue; /* 0x0C */
  598. U32 PreviousValue; /* 0x10 */
  599. } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
  600. MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
  601. Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
  602. /* Integrated RAID Physical Disk Event data ReasonCode values */
  603. #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
  604. #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
  605. #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
  606. /* Integrated RAID Configuration Change List Event data */
  607. /*
  608. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  609. * one and check NumElements at runtime.
  610. */
  611. #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
  612. #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
  613. #endif
  614. typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
  615. {
  616. U16 ElementFlags; /* 0x00 */
  617. U16 VolDevHandle; /* 0x02 */
  618. U8 ReasonCode; /* 0x04 */
  619. U8 PhysDiskNum; /* 0x05 */
  620. U16 PhysDiskDevHandle; /* 0x06 */
  621. } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
  622. Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
  623. /* IR Configuration Change List Event data ElementFlags values */
  624. #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
  625. #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
  626. #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
  627. #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
  628. /* IR Configuration Change List Event data ReasonCode values */
  629. #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
  630. #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
  631. #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
  632. #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
  633. #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
  634. #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
  635. #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
  636. #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
  637. #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
  638. typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
  639. {
  640. U8 NumElements; /* 0x00 */
  641. U8 Reserved1; /* 0x01 */
  642. U8 Reserved2; /* 0x02 */
  643. U8 ConfigNum; /* 0x03 */
  644. U32 Flags; /* 0x04 */
  645. MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
  646. } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
  647. MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
  648. Mpi2EventDataIrConfigChangeList_t,
  649. MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
  650. /* IR Configuration Change List Event data Flags values */
  651. #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
  652. /* SAS Discovery Event data */
  653. typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
  654. {
  655. U8 Flags; /* 0x00 */
  656. U8 ReasonCode; /* 0x01 */
  657. U8 PhysicalPort; /* 0x02 */
  658. U8 Reserved1; /* 0x03 */
  659. U32 DiscoveryStatus; /* 0x04 */
  660. } MPI2_EVENT_DATA_SAS_DISCOVERY,
  661. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
  662. Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
  663. /* SAS Discovery Event data Flags values */
  664. #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
  665. #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
  666. /* SAS Discovery Event data ReasonCode values */
  667. #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
  668. #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
  669. /* SAS Discovery Event data DiscoveryStatus values */
  670. #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
  671. #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
  672. #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
  673. #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
  674. #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
  675. #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
  676. #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
  677. #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
  678. #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
  679. #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
  680. #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
  681. #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
  682. #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
  683. #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
  684. #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
  685. #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
  686. #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
  687. #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
  688. #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
  689. #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
  690. /* SAS Broadcast Primitive Event data */
  691. typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
  692. {
  693. U8 PhyNum; /* 0x00 */
  694. U8 Port; /* 0x01 */
  695. U8 PortWidth; /* 0x02 */
  696. U8 Primitive; /* 0x03 */
  697. } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
  698. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
  699. Mpi2EventDataSasBroadcastPrimitive_t,
  700. MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
  701. /* defines for the Primitive field */
  702. #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
  703. #define MPI2_EVENT_PRIMITIVE_SES (0x02)
  704. #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
  705. #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
  706. #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
  707. #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
  708. #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
  709. #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
  710. /* SAS Notify Primitive Event data */
  711. typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
  712. U8 PhyNum; /* 0x00 */
  713. U8 Port; /* 0x01 */
  714. U8 Reserved1; /* 0x02 */
  715. U8 Primitive; /* 0x03 */
  716. } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
  717. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
  718. Mpi2EventDataSasNotifyPrimitive_t,
  719. MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
  720. /* defines for the Primitive field */
  721. #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
  722. #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
  723. #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
  724. #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
  725. /* SAS Initiator Device Status Change Event data */
  726. typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
  727. {
  728. U8 ReasonCode; /* 0x00 */
  729. U8 PhysicalPort; /* 0x01 */
  730. U16 DevHandle; /* 0x02 */
  731. U64 SASAddress; /* 0x04 */
  732. } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
  733. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
  734. Mpi2EventDataSasInitDevStatusChange_t,
  735. MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
  736. /* SAS Initiator Device Status Change event ReasonCode values */
  737. #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
  738. #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
  739. /* SAS Initiator Device Table Overflow Event data */
  740. typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
  741. {
  742. U16 MaxInit; /* 0x00 */
  743. U16 CurrentInit; /* 0x02 */
  744. U64 SASAddress; /* 0x04 */
  745. } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
  746. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
  747. Mpi2EventDataSasInitTableOverflow_t,
  748. MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
  749. /* SAS Topology Change List Event data */
  750. /*
  751. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  752. * one and check NumEntries at runtime.
  753. */
  754. #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
  755. #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
  756. #endif
  757. typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
  758. {
  759. U16 AttachedDevHandle; /* 0x00 */
  760. U8 LinkRate; /* 0x02 */
  761. U8 PhyStatus; /* 0x03 */
  762. } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
  763. Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
  764. typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
  765. {
  766. U16 EnclosureHandle; /* 0x00 */
  767. U16 ExpanderDevHandle; /* 0x02 */
  768. U8 NumPhys; /* 0x04 */
  769. U8 Reserved1; /* 0x05 */
  770. U16 Reserved2; /* 0x06 */
  771. U8 NumEntries; /* 0x08 */
  772. U8 StartPhyNum; /* 0x09 */
  773. U8 ExpStatus; /* 0x0A */
  774. U8 PhysicalPort; /* 0x0B */
  775. MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
  776. } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
  777. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
  778. Mpi2EventDataSasTopologyChangeList_t,
  779. MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
  780. /* values for the ExpStatus field */
  781. #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
  782. #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
  783. #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
  784. #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
  785. #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
  786. /* defines for the LinkRate field */
  787. #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
  788. #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
  789. #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
  790. #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
  791. #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
  792. #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
  793. #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
  794. #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
  795. #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
  796. #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
  797. #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
  798. #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
  799. #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
  800. #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
  801. /* values for the PhyStatus field */
  802. #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
  803. #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
  804. /* values for the PhyStatus ReasonCode sub-field */
  805. #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
  806. #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
  807. #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
  808. #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
  809. #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
  810. #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
  811. /* SAS Enclosure Device Status Change Event data */
  812. typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
  813. {
  814. U16 EnclosureHandle; /* 0x00 */
  815. U8 ReasonCode; /* 0x02 */
  816. U8 PhysicalPort; /* 0x03 */
  817. U64 EnclosureLogicalID; /* 0x04 */
  818. U16 NumSlots; /* 0x0C */
  819. U16 StartSlot; /* 0x0E */
  820. U32 PhyBits; /* 0x10 */
  821. } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
  822. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
  823. Mpi2EventDataSasEnclDevStatusChange_t,
  824. MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
  825. /* SAS Enclosure Device Status Change event ReasonCode values */
  826. #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
  827. #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
  828. /* SAS PHY Counter Event data */
  829. typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
  830. U64 TimeStamp; /* 0x00 */
  831. U32 Reserved1; /* 0x08 */
  832. U8 PhyEventCode; /* 0x0C */
  833. U8 PhyNum; /* 0x0D */
  834. U16 Reserved2; /* 0x0E */
  835. U32 PhyEventInfo; /* 0x10 */
  836. U8 CounterType; /* 0x14 */
  837. U8 ThresholdWindow; /* 0x15 */
  838. U8 TimeUnits; /* 0x16 */
  839. U8 Reserved3; /* 0x17 */
  840. U32 EventThreshold; /* 0x18 */
  841. U16 ThresholdFlags; /* 0x1C */
  842. U16 Reserved4; /* 0x1E */
  843. } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
  844. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
  845. Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
  846. /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
  847. * PhyEventCode field
  848. * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
  849. * CounterType field
  850. * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
  851. * TimeUnits field
  852. * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
  853. * ThresholdFlags field
  854. * */
  855. /* SAS Quiesce Event data */
  856. typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
  857. U8 ReasonCode; /* 0x00 */
  858. U8 Reserved1; /* 0x01 */
  859. U16 Reserved2; /* 0x02 */
  860. U32 Reserved3; /* 0x04 */
  861. } MPI2_EVENT_DATA_SAS_QUIESCE,
  862. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
  863. Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
  864. /* SAS Quiesce Event data ReasonCode values */
  865. #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
  866. #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
  867. /* Host Based Discovery Phy Event data */
  868. typedef struct _MPI2_EVENT_HBD_PHY_SAS {
  869. U8 Flags; /* 0x00 */
  870. U8 NegotiatedLinkRate; /* 0x01 */
  871. U8 PhyNum; /* 0x02 */
  872. U8 PhysicalPort; /* 0x03 */
  873. U32 Reserved1; /* 0x04 */
  874. U8 InitialFrame[28]; /* 0x08 */
  875. } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
  876. Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
  877. /* values for the Flags field */
  878. #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
  879. #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
  880. /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
  881. * the NegotiatedLinkRate field */
  882. typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
  883. MPI2_EVENT_HBD_PHY_SAS Sas;
  884. } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
  885. Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
  886. typedef struct _MPI2_EVENT_DATA_HBD_PHY {
  887. U8 DescriptorType; /* 0x00 */
  888. U8 Reserved1; /* 0x01 */
  889. U16 Reserved2; /* 0x02 */
  890. U32 Reserved3; /* 0x04 */
  891. MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
  892. } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
  893. Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
  894. /* values for the DescriptorType field */
  895. #define MPI2_EVENT_HBD_DT_SAS (0x01)
  896. /****************************************************************************
  897. * EventAck message
  898. ****************************************************************************/
  899. /* EventAck Request message */
  900. typedef struct _MPI2_EVENT_ACK_REQUEST
  901. {
  902. U16 Reserved1; /* 0x00 */
  903. U8 ChainOffset; /* 0x02 */
  904. U8 Function; /* 0x03 */
  905. U16 Reserved2; /* 0x04 */
  906. U8 Reserved3; /* 0x06 */
  907. U8 MsgFlags; /* 0x07 */
  908. U8 VP_ID; /* 0x08 */
  909. U8 VF_ID; /* 0x09 */
  910. U16 Reserved4; /* 0x0A */
  911. U16 Event; /* 0x0C */
  912. U16 Reserved5; /* 0x0E */
  913. U32 EventContext; /* 0x10 */
  914. } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
  915. Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
  916. /* EventAck Reply message */
  917. typedef struct _MPI2_EVENT_ACK_REPLY
  918. {
  919. U16 Reserved1; /* 0x00 */
  920. U8 MsgLength; /* 0x02 */
  921. U8 Function; /* 0x03 */
  922. U16 Reserved2; /* 0x04 */
  923. U8 Reserved3; /* 0x06 */
  924. U8 MsgFlags; /* 0x07 */
  925. U8 VP_ID; /* 0x08 */
  926. U8 VF_ID; /* 0x09 */
  927. U16 Reserved4; /* 0x0A */
  928. U16 Reserved5; /* 0x0C */
  929. U16 IOCStatus; /* 0x0E */
  930. U32 IOCLogInfo; /* 0x10 */
  931. } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
  932. Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
  933. /****************************************************************************
  934. * SendHostMessage message
  935. ****************************************************************************/
  936. /* SendHostMessage Request message */
  937. typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
  938. U16 HostDataLength; /* 0x00 */
  939. U8 ChainOffset; /* 0x02 */
  940. U8 Function; /* 0x03 */
  941. U16 Reserved1; /* 0x04 */
  942. U8 Reserved2; /* 0x06 */
  943. U8 MsgFlags; /* 0x07 */
  944. U8 VP_ID; /* 0x08 */
  945. U8 VF_ID; /* 0x09 */
  946. U16 Reserved3; /* 0x0A */
  947. U8 Reserved4; /* 0x0C */
  948. U8 DestVF_ID; /* 0x0D */
  949. U16 Reserved5; /* 0x0E */
  950. U32 Reserved6; /* 0x10 */
  951. U32 Reserved7; /* 0x14 */
  952. U32 Reserved8; /* 0x18 */
  953. U32 Reserved9; /* 0x1C */
  954. U32 Reserved10; /* 0x20 */
  955. U32 HostData[1]; /* 0x24 */
  956. } MPI2_SEND_HOST_MESSAGE_REQUEST,
  957. MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
  958. Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
  959. /* SendHostMessage Reply message */
  960. typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
  961. U16 HostDataLength; /* 0x00 */
  962. U8 MsgLength; /* 0x02 */
  963. U8 Function; /* 0x03 */
  964. U16 Reserved1; /* 0x04 */
  965. U8 Reserved2; /* 0x06 */
  966. U8 MsgFlags; /* 0x07 */
  967. U8 VP_ID; /* 0x08 */
  968. U8 VF_ID; /* 0x09 */
  969. U16 Reserved3; /* 0x0A */
  970. U16 Reserved4; /* 0x0C */
  971. U16 IOCStatus; /* 0x0E */
  972. U32 IOCLogInfo; /* 0x10 */
  973. } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
  974. Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
  975. /****************************************************************************
  976. * FWDownload message
  977. ****************************************************************************/
  978. /* FWDownload Request message */
  979. typedef struct _MPI2_FW_DOWNLOAD_REQUEST
  980. {
  981. U8 ImageType; /* 0x00 */
  982. U8 Reserved1; /* 0x01 */
  983. U8 ChainOffset; /* 0x02 */
  984. U8 Function; /* 0x03 */
  985. U16 Reserved2; /* 0x04 */
  986. U8 Reserved3; /* 0x06 */
  987. U8 MsgFlags; /* 0x07 */
  988. U8 VP_ID; /* 0x08 */
  989. U8 VF_ID; /* 0x09 */
  990. U16 Reserved4; /* 0x0A */
  991. U32 TotalImageSize; /* 0x0C */
  992. U32 Reserved5; /* 0x10 */
  993. MPI2_MPI_SGE_UNION SGL; /* 0x14 */
  994. } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
  995. Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
  996. #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
  997. #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
  998. #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
  999. #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
  1000. #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
  1001. #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
  1002. #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
  1003. #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
  1004. #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
  1005. #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
  1006. /* FWDownload TransactionContext Element */
  1007. typedef struct _MPI2_FW_DOWNLOAD_TCSGE
  1008. {
  1009. U8 Reserved1; /* 0x00 */
  1010. U8 ContextSize; /* 0x01 */
  1011. U8 DetailsLength; /* 0x02 */
  1012. U8 Flags; /* 0x03 */
  1013. U32 Reserved2; /* 0x04 */
  1014. U32 ImageOffset; /* 0x08 */
  1015. U32 ImageSize; /* 0x0C */
  1016. } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
  1017. Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
  1018. /* FWDownload Reply message */
  1019. typedef struct _MPI2_FW_DOWNLOAD_REPLY
  1020. {
  1021. U8 ImageType; /* 0x00 */
  1022. U8 Reserved1; /* 0x01 */
  1023. U8 MsgLength; /* 0x02 */
  1024. U8 Function; /* 0x03 */
  1025. U16 Reserved2; /* 0x04 */
  1026. U8 Reserved3; /* 0x06 */
  1027. U8 MsgFlags; /* 0x07 */
  1028. U8 VP_ID; /* 0x08 */
  1029. U8 VF_ID; /* 0x09 */
  1030. U16 Reserved4; /* 0x0A */
  1031. U16 Reserved5; /* 0x0C */
  1032. U16 IOCStatus; /* 0x0E */
  1033. U32 IOCLogInfo; /* 0x10 */
  1034. } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
  1035. Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
  1036. /****************************************************************************
  1037. * FWUpload message
  1038. ****************************************************************************/
  1039. /* FWUpload Request message */
  1040. typedef struct _MPI2_FW_UPLOAD_REQUEST
  1041. {
  1042. U8 ImageType; /* 0x00 */
  1043. U8 Reserved1; /* 0x01 */
  1044. U8 ChainOffset; /* 0x02 */
  1045. U8 Function; /* 0x03 */
  1046. U16 Reserved2; /* 0x04 */
  1047. U8 Reserved3; /* 0x06 */
  1048. U8 MsgFlags; /* 0x07 */
  1049. U8 VP_ID; /* 0x08 */
  1050. U8 VF_ID; /* 0x09 */
  1051. U16 Reserved4; /* 0x0A */
  1052. U32 Reserved5; /* 0x0C */
  1053. U32 Reserved6; /* 0x10 */
  1054. MPI2_MPI_SGE_UNION SGL; /* 0x14 */
  1055. } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
  1056. Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
  1057. #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
  1058. #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
  1059. #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
  1060. #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
  1061. #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
  1062. #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
  1063. #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
  1064. #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
  1065. #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
  1066. #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
  1067. typedef struct _MPI2_FW_UPLOAD_TCSGE
  1068. {
  1069. U8 Reserved1; /* 0x00 */
  1070. U8 ContextSize; /* 0x01 */
  1071. U8 DetailsLength; /* 0x02 */
  1072. U8 Flags; /* 0x03 */
  1073. U32 Reserved2; /* 0x04 */
  1074. U32 ImageOffset; /* 0x08 */
  1075. U32 ImageSize; /* 0x0C */
  1076. } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
  1077. Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
  1078. /* FWUpload Reply message */
  1079. typedef struct _MPI2_FW_UPLOAD_REPLY
  1080. {
  1081. U8 ImageType; /* 0x00 */
  1082. U8 Reserved1; /* 0x01 */
  1083. U8 MsgLength; /* 0x02 */
  1084. U8 Function; /* 0x03 */
  1085. U16 Reserved2; /* 0x04 */
  1086. U8 Reserved3; /* 0x06 */
  1087. U8 MsgFlags; /* 0x07 */
  1088. U8 VP_ID; /* 0x08 */
  1089. U8 VF_ID; /* 0x09 */
  1090. U16 Reserved4; /* 0x0A */
  1091. U16 Reserved5; /* 0x0C */
  1092. U16 IOCStatus; /* 0x0E */
  1093. U32 IOCLogInfo; /* 0x10 */
  1094. U32 ActualImageSize; /* 0x14 */
  1095. } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
  1096. Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
  1097. /* FW Image Header */
  1098. typedef struct _MPI2_FW_IMAGE_HEADER
  1099. {
  1100. U32 Signature; /* 0x00 */
  1101. U32 Signature0; /* 0x04 */
  1102. U32 Signature1; /* 0x08 */
  1103. U32 Signature2; /* 0x0C */
  1104. MPI2_VERSION_UNION MPIVersion; /* 0x10 */
  1105. MPI2_VERSION_UNION FWVersion; /* 0x14 */
  1106. MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
  1107. MPI2_VERSION_UNION PackageVersion; /* 0x1C */
  1108. U16 VendorID; /* 0x20 */
  1109. U16 ProductID; /* 0x22 */
  1110. U16 ProtocolFlags; /* 0x24 */
  1111. U16 Reserved26; /* 0x26 */
  1112. U32 IOCCapabilities; /* 0x28 */
  1113. U32 ImageSize; /* 0x2C */
  1114. U32 NextImageHeaderOffset; /* 0x30 */
  1115. U32 Checksum; /* 0x34 */
  1116. U32 Reserved38; /* 0x38 */
  1117. U32 Reserved3C; /* 0x3C */
  1118. U32 Reserved40; /* 0x40 */
  1119. U32 Reserved44; /* 0x44 */
  1120. U32 Reserved48; /* 0x48 */
  1121. U32 Reserved4C; /* 0x4C */
  1122. U32 Reserved50; /* 0x50 */
  1123. U32 Reserved54; /* 0x54 */
  1124. U32 Reserved58; /* 0x58 */
  1125. U32 Reserved5C; /* 0x5C */
  1126. U32 Reserved60; /* 0x60 */
  1127. U32 FirmwareVersionNameWhat; /* 0x64 */
  1128. U8 FirmwareVersionName[32]; /* 0x68 */
  1129. U32 VendorNameWhat; /* 0x88 */
  1130. U8 VendorName[32]; /* 0x8C */
  1131. U32 PackageNameWhat; /* 0x88 */
  1132. U8 PackageName[32]; /* 0x8C */
  1133. U32 ReservedD0; /* 0xD0 */
  1134. U32 ReservedD4; /* 0xD4 */
  1135. U32 ReservedD8; /* 0xD8 */
  1136. U32 ReservedDC; /* 0xDC */
  1137. U32 ReservedE0; /* 0xE0 */
  1138. U32 ReservedE4; /* 0xE4 */
  1139. U32 ReservedE8; /* 0xE8 */
  1140. U32 ReservedEC; /* 0xEC */
  1141. U32 ReservedF0; /* 0xF0 */
  1142. U32 ReservedF4; /* 0xF4 */
  1143. U32 ReservedF8; /* 0xF8 */
  1144. U32 ReservedFC; /* 0xFC */
  1145. } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
  1146. Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
  1147. /* Signature field */
  1148. #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
  1149. #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
  1150. #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
  1151. /* Signature0 field */
  1152. #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
  1153. #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
  1154. /* Signature1 field */
  1155. #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
  1156. #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
  1157. /* Signature2 field */
  1158. #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
  1159. #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
  1160. /* defines for using the ProductID field */
  1161. #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
  1162. #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
  1163. #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
  1164. #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
  1165. #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
  1166. #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
  1167. #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
  1168. /* SAS */
  1169. #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
  1170. #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
  1171. /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
  1172. /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
  1173. #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
  1174. #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
  1175. #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
  1176. #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
  1177. #define MPI2_FW_HEADER_SIZE (0x100)
  1178. /* Extended Image Header */
  1179. typedef struct _MPI2_EXT_IMAGE_HEADER
  1180. {
  1181. U8 ImageType; /* 0x00 */
  1182. U8 Reserved1; /* 0x01 */
  1183. U16 Reserved2; /* 0x02 */
  1184. U32 Checksum; /* 0x04 */
  1185. U32 ImageSize; /* 0x08 */
  1186. U32 NextImageHeaderOffset; /* 0x0C */
  1187. U32 PackageVersion; /* 0x10 */
  1188. U32 Reserved3; /* 0x14 */
  1189. U32 Reserved4; /* 0x18 */
  1190. U32 Reserved5; /* 0x1C */
  1191. U8 IdentifyString[32]; /* 0x20 */
  1192. } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
  1193. Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
  1194. /* useful offsets */
  1195. #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
  1196. #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
  1197. #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
  1198. #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
  1199. /* defines for the ImageType field */
  1200. #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
  1201. #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
  1202. #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
  1203. #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
  1204. #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
  1205. #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
  1206. #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
  1207. #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
  1208. #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
  1209. #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
  1210. #define MPI2_EXT_IMAGE_TYPE_MAX \
  1211. (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */
  1212. /* FLASH Layout Extended Image Data */
  1213. /*
  1214. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1215. * one and check RegionsPerLayout at runtime.
  1216. */
  1217. #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
  1218. #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
  1219. #endif
  1220. /*
  1221. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1222. * one and check NumberOfLayouts at runtime.
  1223. */
  1224. #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
  1225. #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
  1226. #endif
  1227. typedef struct _MPI2_FLASH_REGION
  1228. {
  1229. U8 RegionType; /* 0x00 */
  1230. U8 Reserved1; /* 0x01 */
  1231. U16 Reserved2; /* 0x02 */
  1232. U32 RegionOffset; /* 0x04 */
  1233. U32 RegionSize; /* 0x08 */
  1234. U32 Reserved3; /* 0x0C */
  1235. } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
  1236. Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
  1237. typedef struct _MPI2_FLASH_LAYOUT
  1238. {
  1239. U32 FlashSize; /* 0x00 */
  1240. U32 Reserved1; /* 0x04 */
  1241. U32 Reserved2; /* 0x08 */
  1242. U32 Reserved3; /* 0x0C */
  1243. MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
  1244. } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
  1245. Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
  1246. typedef struct _MPI2_FLASH_LAYOUT_DATA
  1247. {
  1248. U8 ImageRevision; /* 0x00 */
  1249. U8 Reserved1; /* 0x01 */
  1250. U8 SizeOfRegion; /* 0x02 */
  1251. U8 Reserved2; /* 0x03 */
  1252. U16 NumberOfLayouts; /* 0x04 */
  1253. U16 RegionsPerLayout; /* 0x06 */
  1254. U16 MinimumSectorAlignment; /* 0x08 */
  1255. U16 Reserved3; /* 0x0A */
  1256. U32 Reserved4; /* 0x0C */
  1257. MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
  1258. } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
  1259. Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
  1260. /* defines for the RegionType field */
  1261. #define MPI2_FLASH_REGION_UNUSED (0x00)
  1262. #define MPI2_FLASH_REGION_FIRMWARE (0x01)
  1263. #define MPI2_FLASH_REGION_BIOS (0x02)
  1264. #define MPI2_FLASH_REGION_NVDATA (0x03)
  1265. #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
  1266. #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
  1267. #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
  1268. #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
  1269. #define MPI2_FLASH_REGION_MEGARAID (0x09)
  1270. #define MPI2_FLASH_REGION_INIT (0x0A)
  1271. /* ImageRevision */
  1272. #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
  1273. /* Supported Devices Extended Image Data */
  1274. /*
  1275. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1276. * one and check NumberOfDevices at runtime.
  1277. */
  1278. #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
  1279. #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
  1280. #endif
  1281. typedef struct _MPI2_SUPPORTED_DEVICE
  1282. {
  1283. U16 DeviceID; /* 0x00 */
  1284. U16 VendorID; /* 0x02 */
  1285. U16 DeviceIDMask; /* 0x04 */
  1286. U16 Reserved1; /* 0x06 */
  1287. U8 LowPCIRev; /* 0x08 */
  1288. U8 HighPCIRev; /* 0x09 */
  1289. U16 Reserved2; /* 0x0A */
  1290. U32 Reserved3; /* 0x0C */
  1291. } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
  1292. Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
  1293. typedef struct _MPI2_SUPPORTED_DEVICES_DATA
  1294. {
  1295. U8 ImageRevision; /* 0x00 */
  1296. U8 Reserved1; /* 0x01 */
  1297. U8 NumberOfDevices; /* 0x02 */
  1298. U8 Reserved2; /* 0x03 */
  1299. U32 Reserved3; /* 0x04 */
  1300. MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
  1301. } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
  1302. Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
  1303. /* ImageRevision */
  1304. #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
  1305. /* Init Extended Image Data */
  1306. typedef struct _MPI2_INIT_IMAGE_FOOTER
  1307. {
  1308. U32 BootFlags; /* 0x00 */
  1309. U32 ImageSize; /* 0x04 */
  1310. U32 Signature0; /* 0x08 */
  1311. U32 Signature1; /* 0x0C */
  1312. U32 Signature2; /* 0x10 */
  1313. U32 ResetVector; /* 0x14 */
  1314. } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
  1315. Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
  1316. /* defines for the BootFlags field */
  1317. #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
  1318. /* defines for the ImageSize field */
  1319. #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
  1320. /* defines for the Signature0 field */
  1321. #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
  1322. #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
  1323. /* defines for the Signature1 field */
  1324. #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
  1325. #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
  1326. /* defines for the Signature2 field */
  1327. #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
  1328. #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
  1329. /* Signature fields as individual bytes */
  1330. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
  1331. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
  1332. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
  1333. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
  1334. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
  1335. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
  1336. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
  1337. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
  1338. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
  1339. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
  1340. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
  1341. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
  1342. /* defines for the ResetVector field */
  1343. #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
  1344. /****************************************************************************
  1345. * PowerManagementControl message
  1346. ****************************************************************************/
  1347. /* PowerManagementControl Request message */
  1348. typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
  1349. U8 Feature; /* 0x00 */
  1350. U8 Reserved1; /* 0x01 */
  1351. U8 ChainOffset; /* 0x02 */
  1352. U8 Function; /* 0x03 */
  1353. U16 Reserved2; /* 0x04 */
  1354. U8 Reserved3; /* 0x06 */
  1355. U8 MsgFlags; /* 0x07 */
  1356. U8 VP_ID; /* 0x08 */
  1357. U8 VF_ID; /* 0x09 */
  1358. U16 Reserved4; /* 0x0A */
  1359. U8 Parameter1; /* 0x0C */
  1360. U8 Parameter2; /* 0x0D */
  1361. U8 Parameter3; /* 0x0E */
  1362. U8 Parameter4; /* 0x0F */
  1363. U32 Reserved5; /* 0x10 */
  1364. U32 Reserved6; /* 0x14 */
  1365. } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
  1366. Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
  1367. /* defines for the Feature field */
  1368. #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
  1369. #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
  1370. #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */
  1371. #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
  1372. #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
  1373. #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
  1374. /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
  1375. /* Parameter1 contains a PHY number */
  1376. /* Parameter2 indicates power condition action using these defines */
  1377. #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
  1378. #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
  1379. #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
  1380. /* Parameter3 and Parameter4 are reserved */
  1381. /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
  1382. * Feature */
  1383. /* Parameter1 contains SAS port width modulation group number */
  1384. /* Parameter2 indicates IOC action using these defines */
  1385. #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
  1386. #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
  1387. #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
  1388. /* Parameter3 indicates desired modulation level using these defines */
  1389. #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
  1390. #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
  1391. #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
  1392. #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
  1393. /* Parameter4 is reserved */
  1394. /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
  1395. /* Parameter1 indicates desired PCIe link speed using these defines */
  1396. #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */
  1397. #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */
  1398. #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */
  1399. /* Parameter2 indicates desired PCIe link width using these defines */
  1400. #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */
  1401. #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */
  1402. #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */
  1403. #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */
  1404. /* Parameter3 and Parameter4 are reserved */
  1405. /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
  1406. /* Parameter1 indicates desired IOC hardware clock speed using these defines */
  1407. #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
  1408. #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
  1409. #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
  1410. #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
  1411. /* Parameter2, Parameter3, and Parameter4 are reserved */
  1412. /* PowerManagementControl Reply message */
  1413. typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
  1414. U8 Feature; /* 0x00 */
  1415. U8 Reserved1; /* 0x01 */
  1416. U8 MsgLength; /* 0x02 */
  1417. U8 Function; /* 0x03 */
  1418. U16 Reserved2; /* 0x04 */
  1419. U8 Reserved3; /* 0x06 */
  1420. U8 MsgFlags; /* 0x07 */
  1421. U8 VP_ID; /* 0x08 */
  1422. U8 VF_ID; /* 0x09 */
  1423. U16 Reserved4; /* 0x0A */
  1424. U16 Reserved5; /* 0x0C */
  1425. U16 IOCStatus; /* 0x0E */
  1426. U32 IOCLogInfo; /* 0x10 */
  1427. } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
  1428. Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
  1429. #endif