gdth.c 174 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #include <linux/mutex.h>
  117. #include <linux/slab.h>
  118. #ifdef GDTH_RTC
  119. #include <linux/mc146818rtc.h>
  120. #endif
  121. #include <linux/reboot.h>
  122. #include <asm/dma.h>
  123. #include <asm/io.h>
  124. #include <asm/uaccess.h>
  125. #include <linux/spinlock.h>
  126. #include <linux/blkdev.h>
  127. #include <linux/scatterlist.h>
  128. #include "scsi.h"
  129. #include <scsi/scsi_host.h>
  130. #include "gdth.h"
  131. static DEFINE_MUTEX(gdth_mutex);
  132. static void gdth_delay(int milliseconds);
  133. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
  134. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  135. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  136. int gdth_from_wait, int* pIndex);
  137. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  138. Scsi_Cmnd *scp);
  139. static int gdth_async_event(gdth_ha_str *ha);
  140. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  141. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority);
  142. static void gdth_next(gdth_ha_str *ha);
  143. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b);
  144. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  145. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  146. u16 idx, gdth_evt_data *evt);
  147. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  148. static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
  149. gdth_evt_str *estr);
  150. static void gdth_clear_events(void);
  151. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  152. char *buffer, u16 count);
  153. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  154. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive);
  155. static void gdth_enable_int(gdth_ha_str *ha);
  156. static int gdth_test_busy(gdth_ha_str *ha);
  157. static int gdth_get_cmd_index(gdth_ha_str *ha);
  158. static void gdth_release_event(gdth_ha_str *ha);
  159. static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
  160. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  161. u32 p1, u64 p2,u64 p3);
  162. static int gdth_search_drives(gdth_ha_str *ha);
  163. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
  164. static const char *gdth_ctr_name(gdth_ha_str *ha);
  165. static int gdth_open(struct inode *inode, struct file *filep);
  166. static int gdth_close(struct inode *inode, struct file *filep);
  167. static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
  168. unsigned long arg);
  169. static void gdth_flush(gdth_ha_str *ha);
  170. static int gdth_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  171. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  172. struct gdth_cmndinfo *cmndinfo);
  173. static void gdth_scsi_done(struct scsi_cmnd *scp);
  174. #ifdef DEBUG_GDTH
  175. static u8 DebugState = DEBUG_GDTH;
  176. #ifdef __SERIAL__
  177. #define MAX_SERBUF 160
  178. static void ser_init(void);
  179. static void ser_puts(char *str);
  180. static void ser_putc(char c);
  181. static int ser_printk(const char *fmt, ...);
  182. static char strbuf[MAX_SERBUF+1];
  183. #ifdef __COM2__
  184. #define COM_BASE 0x2f8
  185. #else
  186. #define COM_BASE 0x3f8
  187. #endif
  188. static void ser_init()
  189. {
  190. unsigned port=COM_BASE;
  191. outb(0x80,port+3);
  192. outb(0,port+1);
  193. /* 19200 Baud, if 9600: outb(12,port) */
  194. outb(6, port);
  195. outb(3,port+3);
  196. outb(0,port+1);
  197. /*
  198. ser_putc('I');
  199. ser_putc(' ');
  200. */
  201. }
  202. static void ser_puts(char *str)
  203. {
  204. char *ptr;
  205. ser_init();
  206. for (ptr=str;*ptr;++ptr)
  207. ser_putc(*ptr);
  208. }
  209. static void ser_putc(char c)
  210. {
  211. unsigned port=COM_BASE;
  212. while ((inb(port+5) & 0x20)==0);
  213. outb(c,port);
  214. if (c==0x0a)
  215. {
  216. while ((inb(port+5) & 0x20)==0);
  217. outb(0x0d,port);
  218. }
  219. }
  220. static int ser_printk(const char *fmt, ...)
  221. {
  222. va_list args;
  223. int i;
  224. va_start(args,fmt);
  225. i = vsprintf(strbuf,fmt,args);
  226. ser_puts(strbuf);
  227. va_end(args);
  228. return i;
  229. }
  230. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  231. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  232. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  233. #else /* !__SERIAL__ */
  234. #define TRACE(a) {if (DebugState==1) {printk a;}}
  235. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  236. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  237. #endif
  238. #else /* !DEBUG */
  239. #define TRACE(a)
  240. #define TRACE2(a)
  241. #define TRACE3(a)
  242. #endif
  243. #ifdef GDTH_STATISTICS
  244. static u32 max_rq=0, max_index=0, max_sg=0;
  245. #ifdef INT_COAL
  246. static u32 max_int_coal=0;
  247. #endif
  248. static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  249. static struct timer_list gdth_timer;
  250. #endif
  251. #define PTR2USHORT(a) (u16)(unsigned long)(a)
  252. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  253. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  254. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  255. #ifdef CONFIG_ISA
  256. static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  257. #endif
  258. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  259. static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  260. #endif
  261. static u8 gdth_polling; /* polling if TRUE */
  262. static int gdth_ctr_count = 0; /* controller count */
  263. static LIST_HEAD(gdth_instances); /* controller list */
  264. static u8 gdth_write_through = FALSE; /* write through */
  265. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  266. static int elastidx;
  267. static int eoldidx;
  268. static int major;
  269. #define DIN 1 /* IN data direction */
  270. #define DOU 2 /* OUT data direction */
  271. #define DNO DIN /* no data transfer */
  272. #define DUN DIN /* unknown data direction */
  273. static u8 gdth_direction_tab[0x100] = {
  274. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  275. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  276. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  277. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  278. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  285. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  290. };
  291. /* LILO and modprobe/insmod parameters */
  292. /* IRQ list for GDT3000/3020 EISA controllers */
  293. static int irq[MAXHA] __initdata =
  294. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  295. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  296. /* disable driver flag */
  297. static int disable __initdata = 0;
  298. /* reserve flag */
  299. static int reserve_mode = 1;
  300. /* reserve list */
  301. static int reserve_list[MAX_RES_ARGS] =
  302. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  304. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  305. /* scan order for PCI controllers */
  306. static int reverse_scan = 0;
  307. /* virtual channel for the host drives */
  308. static int hdr_channel = 0;
  309. /* max. IDs per channel */
  310. static int max_ids = MAXID;
  311. /* rescan all IDs */
  312. static int rescan = 0;
  313. /* shared access */
  314. static int shared_access = 1;
  315. /* enable support for EISA and ISA controllers */
  316. static int probe_eisa_isa = 0;
  317. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  318. static int force_dma32 = 0;
  319. /* parameters for modprobe/insmod */
  320. module_param_array(irq, int, NULL, 0);
  321. module_param(disable, int, 0);
  322. module_param(reserve_mode, int, 0);
  323. module_param_array(reserve_list, int, NULL, 0);
  324. module_param(reverse_scan, int, 0);
  325. module_param(hdr_channel, int, 0);
  326. module_param(max_ids, int, 0);
  327. module_param(rescan, int, 0);
  328. module_param(shared_access, int, 0);
  329. module_param(probe_eisa_isa, int, 0);
  330. module_param(force_dma32, int, 0);
  331. MODULE_AUTHOR("Achim Leubner");
  332. MODULE_LICENSE("GPL");
  333. /* ioctl interface */
  334. static const struct file_operations gdth_fops = {
  335. .unlocked_ioctl = gdth_unlocked_ioctl,
  336. .open = gdth_open,
  337. .release = gdth_close,
  338. .llseek = noop_llseek,
  339. };
  340. #include "gdth_proc.h"
  341. #include "gdth_proc.c"
  342. static gdth_ha_str *gdth_find_ha(int hanum)
  343. {
  344. gdth_ha_str *ha;
  345. list_for_each_entry(ha, &gdth_instances, list)
  346. if (hanum == ha->hanum)
  347. return ha;
  348. return NULL;
  349. }
  350. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  351. {
  352. struct gdth_cmndinfo *priv = NULL;
  353. unsigned long flags;
  354. int i;
  355. spin_lock_irqsave(&ha->smp_lock, flags);
  356. for (i=0; i<GDTH_MAXCMDS; ++i) {
  357. if (ha->cmndinfo[i].index == 0) {
  358. priv = &ha->cmndinfo[i];
  359. memset(priv, 0, sizeof(*priv));
  360. priv->index = i+1;
  361. break;
  362. }
  363. }
  364. spin_unlock_irqrestore(&ha->smp_lock, flags);
  365. return priv;
  366. }
  367. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  368. {
  369. BUG_ON(!priv);
  370. priv->index = 0;
  371. }
  372. static void gdth_delay(int milliseconds)
  373. {
  374. if (milliseconds == 0) {
  375. udelay(1);
  376. } else {
  377. mdelay(milliseconds);
  378. }
  379. }
  380. static void gdth_scsi_done(struct scsi_cmnd *scp)
  381. {
  382. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  383. int internal_command = cmndinfo->internal_command;
  384. TRACE2(("gdth_scsi_done()\n"));
  385. gdth_put_cmndinfo(cmndinfo);
  386. scp->host_scribble = NULL;
  387. if (internal_command)
  388. complete((struct completion *)scp->request);
  389. else
  390. scp->scsi_done(scp);
  391. }
  392. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  393. int timeout, u32 *info)
  394. {
  395. gdth_ha_str *ha = shost_priv(sdev->host);
  396. Scsi_Cmnd *scp;
  397. struct gdth_cmndinfo cmndinfo;
  398. DECLARE_COMPLETION_ONSTACK(wait);
  399. int rval;
  400. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  401. if (!scp)
  402. return -ENOMEM;
  403. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  404. if (!scp->sense_buffer) {
  405. kfree(scp);
  406. return -ENOMEM;
  407. }
  408. scp->device = sdev;
  409. memset(&cmndinfo, 0, sizeof(cmndinfo));
  410. /* use request field to save the ptr. to completion struct. */
  411. scp->request = (struct request *)&wait;
  412. scp->cmd_len = 12;
  413. scp->cmnd = cmnd;
  414. cmndinfo.priority = IOCTL_PRI;
  415. cmndinfo.internal_cmd_str = gdtcmd;
  416. cmndinfo.internal_command = 1;
  417. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  418. __gdth_queuecommand(ha, scp, &cmndinfo);
  419. wait_for_completion(&wait);
  420. rval = cmndinfo.status;
  421. if (info)
  422. *info = cmndinfo.info;
  423. kfree(scp->sense_buffer);
  424. kfree(scp);
  425. return rval;
  426. }
  427. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  428. int timeout, u32 *info)
  429. {
  430. struct scsi_device *sdev = scsi_get_host_dev(shost);
  431. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  432. scsi_free_host_dev(sdev);
  433. return rval;
  434. }
  435. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
  436. {
  437. *cyls = size /HEADS/SECS;
  438. if (*cyls <= MAXCYLS) {
  439. *heads = HEADS;
  440. *secs = SECS;
  441. } else { /* too high for 64*32 */
  442. *cyls = size /MEDHEADS/MEDSECS;
  443. if (*cyls <= MAXCYLS) {
  444. *heads = MEDHEADS;
  445. *secs = MEDSECS;
  446. } else { /* too high for 127*63 */
  447. *cyls = size /BIGHEADS/BIGSECS;
  448. *heads = BIGHEADS;
  449. *secs = BIGSECS;
  450. }
  451. }
  452. }
  453. /* controller search and initialization functions */
  454. #ifdef CONFIG_EISA
  455. static int __init gdth_search_eisa(u16 eisa_adr)
  456. {
  457. u32 id;
  458. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  459. id = inl(eisa_adr+ID0REG);
  460. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  461. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  462. return 0; /* not EISA configured */
  463. return 1;
  464. }
  465. if (id == GDT3_ID) /* GDT3000 */
  466. return 1;
  467. return 0;
  468. }
  469. #endif /* CONFIG_EISA */
  470. #ifdef CONFIG_ISA
  471. static int __init gdth_search_isa(u32 bios_adr)
  472. {
  473. void __iomem *addr;
  474. u32 id;
  475. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  476. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
  477. id = readl(addr);
  478. iounmap(addr);
  479. if (id == GDT2_ID) /* GDT2000 */
  480. return 1;
  481. }
  482. return 0;
  483. }
  484. #endif /* CONFIG_ISA */
  485. #ifdef CONFIG_PCI
  486. static bool gdth_search_vortex(u16 device)
  487. {
  488. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  489. return true;
  490. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  491. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  492. return true;
  493. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  494. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  495. return true;
  496. return false;
  497. }
  498. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  499. static int gdth_pci_init_one(struct pci_dev *pdev,
  500. const struct pci_device_id *ent);
  501. static void gdth_pci_remove_one(struct pci_dev *pdev);
  502. static void gdth_remove_one(gdth_ha_str *ha);
  503. /* Vortex only makes RAID controllers.
  504. * We do not really want to specify all 550 ids here, so wildcard match.
  505. */
  506. static const struct pci_device_id gdthtable[] = {
  507. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  508. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  509. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  510. { } /* terminate list */
  511. };
  512. MODULE_DEVICE_TABLE(pci, gdthtable);
  513. static struct pci_driver gdth_pci_driver = {
  514. .name = "gdth",
  515. .id_table = gdthtable,
  516. .probe = gdth_pci_init_one,
  517. .remove = gdth_pci_remove_one,
  518. };
  519. static void gdth_pci_remove_one(struct pci_dev *pdev)
  520. {
  521. gdth_ha_str *ha = pci_get_drvdata(pdev);
  522. pci_set_drvdata(pdev, NULL);
  523. list_del(&ha->list);
  524. gdth_remove_one(ha);
  525. pci_disable_device(pdev);
  526. }
  527. static int gdth_pci_init_one(struct pci_dev *pdev,
  528. const struct pci_device_id *ent)
  529. {
  530. u16 vendor = pdev->vendor;
  531. u16 device = pdev->device;
  532. unsigned long base0, base1, base2;
  533. int rc;
  534. gdth_pci_str gdth_pcistr;
  535. gdth_ha_str *ha = NULL;
  536. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  537. gdth_ctr_count, vendor, device));
  538. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  539. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  540. return -ENODEV;
  541. rc = pci_enable_device(pdev);
  542. if (rc)
  543. return rc;
  544. if (gdth_ctr_count >= MAXHA)
  545. return -EBUSY;
  546. /* GDT PCI controller found, resources are already in pdev */
  547. gdth_pcistr.pdev = pdev;
  548. base0 = pci_resource_flags(pdev, 0);
  549. base1 = pci_resource_flags(pdev, 1);
  550. base2 = pci_resource_flags(pdev, 2);
  551. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  552. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  553. if (!(base0 & IORESOURCE_MEM))
  554. return -ENODEV;
  555. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  556. } else { /* GDT6110, GDT6120, .. */
  557. if (!(base0 & IORESOURCE_MEM) ||
  558. !(base2 & IORESOURCE_MEM) ||
  559. !(base1 & IORESOURCE_IO))
  560. return -ENODEV;
  561. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  562. gdth_pcistr.io = pci_resource_start(pdev, 1);
  563. }
  564. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  565. gdth_pcistr.pdev->bus->number,
  566. PCI_SLOT(gdth_pcistr.pdev->devfn),
  567. gdth_pcistr.irq,
  568. gdth_pcistr.dpmem));
  569. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  570. if (rc)
  571. return rc;
  572. return 0;
  573. }
  574. #endif /* CONFIG_PCI */
  575. #ifdef CONFIG_EISA
  576. static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
  577. {
  578. u32 retries,id;
  579. u8 prot_ver,eisacf,i,irq_found;
  580. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  581. /* disable board interrupts, deinitialize services */
  582. outb(0xff,eisa_adr+EDOORREG);
  583. outb(0x00,eisa_adr+EDENABREG);
  584. outb(0x00,eisa_adr+EINTENABREG);
  585. outb(0xff,eisa_adr+LDOORREG);
  586. retries = INIT_RETRIES;
  587. gdth_delay(20);
  588. while (inb(eisa_adr+EDOORREG) != 0xff) {
  589. if (--retries == 0) {
  590. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  591. return 0;
  592. }
  593. gdth_delay(1);
  594. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  595. }
  596. prot_ver = inb(eisa_adr+MAILBOXREG);
  597. outb(0xff,eisa_adr+EDOORREG);
  598. if (prot_ver != PROTOCOL_VERSION) {
  599. printk("GDT-EISA: Illegal protocol version\n");
  600. return 0;
  601. }
  602. ha->bmic = eisa_adr;
  603. ha->brd_phys = (u32)eisa_adr >> 12;
  604. outl(0,eisa_adr+MAILBOXREG);
  605. outl(0,eisa_adr+MAILBOXREG+4);
  606. outl(0,eisa_adr+MAILBOXREG+8);
  607. outl(0,eisa_adr+MAILBOXREG+12);
  608. /* detect IRQ */
  609. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  610. ha->oem_id = OEM_ID_ICP;
  611. ha->type = GDT_EISA;
  612. ha->stype = id;
  613. outl(1,eisa_adr+MAILBOXREG+8);
  614. outb(0xfe,eisa_adr+LDOORREG);
  615. retries = INIT_RETRIES;
  616. gdth_delay(20);
  617. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  618. if (--retries == 0) {
  619. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  620. return 0;
  621. }
  622. gdth_delay(1);
  623. }
  624. ha->irq = inb(eisa_adr+MAILBOXREG);
  625. outb(0xff,eisa_adr+EDOORREG);
  626. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  627. /* check the result */
  628. if (ha->irq == 0) {
  629. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  630. for (i = 0, irq_found = FALSE;
  631. i < MAXHA && irq[i] != 0xff; ++i) {
  632. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  633. irq_found = TRUE;
  634. break;
  635. }
  636. }
  637. if (irq_found) {
  638. ha->irq = irq[i];
  639. irq[i] = 0;
  640. printk("GDT-EISA: Can not detect controller IRQ,\n");
  641. printk("Use IRQ setting from command line (IRQ = %d)\n",
  642. ha->irq);
  643. } else {
  644. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  645. printk("the controller BIOS or use command line parameters\n");
  646. return 0;
  647. }
  648. }
  649. } else {
  650. eisacf = inb(eisa_adr+EISAREG) & 7;
  651. if (eisacf > 4) /* level triggered */
  652. eisacf -= 4;
  653. ha->irq = gdth_irq_tab[eisacf];
  654. ha->oem_id = OEM_ID_ICP;
  655. ha->type = GDT_EISA;
  656. ha->stype = id;
  657. }
  658. ha->dma64_support = 0;
  659. return 1;
  660. }
  661. #endif /* CONFIG_EISA */
  662. #ifdef CONFIG_ISA
  663. static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
  664. {
  665. register gdt2_dpram_str __iomem *dp2_ptr;
  666. int i;
  667. u8 irq_drq,prot_ver;
  668. u32 retries;
  669. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  670. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  671. if (ha->brd == NULL) {
  672. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  673. return 0;
  674. }
  675. dp2_ptr = ha->brd;
  676. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  677. /* reset interface area */
  678. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  679. if (readl(&dp2_ptr->u) != 0) {
  680. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  681. iounmap(ha->brd);
  682. return 0;
  683. }
  684. /* disable board interrupts, read DRQ and IRQ */
  685. writeb(0xff, &dp2_ptr->io.irqdel);
  686. writeb(0x00, &dp2_ptr->io.irqen);
  687. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  688. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  689. irq_drq = readb(&dp2_ptr->io.rq);
  690. for (i=0; i<3; ++i) {
  691. if ((irq_drq & 1)==0)
  692. break;
  693. irq_drq >>= 1;
  694. }
  695. ha->drq = gdth_drq_tab[i];
  696. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  697. for (i=1; i<5; ++i) {
  698. if ((irq_drq & 1)==0)
  699. break;
  700. irq_drq >>= 1;
  701. }
  702. ha->irq = gdth_irq_tab[i];
  703. /* deinitialize services */
  704. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  705. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  706. writeb(0, &dp2_ptr->io.event);
  707. retries = INIT_RETRIES;
  708. gdth_delay(20);
  709. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  710. if (--retries == 0) {
  711. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  712. iounmap(ha->brd);
  713. return 0;
  714. }
  715. gdth_delay(1);
  716. }
  717. prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
  718. writeb(0, &dp2_ptr->u.ic.Status);
  719. writeb(0xff, &dp2_ptr->io.irqdel);
  720. if (prot_ver != PROTOCOL_VERSION) {
  721. printk("GDT-ISA: Illegal protocol version\n");
  722. iounmap(ha->brd);
  723. return 0;
  724. }
  725. ha->oem_id = OEM_ID_ICP;
  726. ha->type = GDT_ISA;
  727. ha->ic_all_size = sizeof(dp2_ptr->u);
  728. ha->stype= GDT2_ID;
  729. ha->brd_phys = bios_adr >> 4;
  730. /* special request to controller BIOS */
  731. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  732. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  733. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  734. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  735. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  736. writeb(0, &dp2_ptr->io.event);
  737. retries = INIT_RETRIES;
  738. gdth_delay(20);
  739. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  740. if (--retries == 0) {
  741. printk("GDT-ISA: Initialization error\n");
  742. iounmap(ha->brd);
  743. return 0;
  744. }
  745. gdth_delay(1);
  746. }
  747. writeb(0, &dp2_ptr->u.ic.Status);
  748. writeb(0xff, &dp2_ptr->io.irqdel);
  749. ha->dma64_support = 0;
  750. return 1;
  751. }
  752. #endif /* CONFIG_ISA */
  753. #ifdef CONFIG_PCI
  754. static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  755. gdth_ha_str *ha)
  756. {
  757. register gdt6_dpram_str __iomem *dp6_ptr;
  758. register gdt6c_dpram_str __iomem *dp6c_ptr;
  759. register gdt6m_dpram_str __iomem *dp6m_ptr;
  760. u32 retries;
  761. u8 prot_ver;
  762. u16 command;
  763. int i, found = FALSE;
  764. TRACE(("gdth_init_pci()\n"));
  765. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  766. ha->oem_id = OEM_ID_INTEL;
  767. else
  768. ha->oem_id = OEM_ID_ICP;
  769. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  770. ha->stype = (u32)pdev->device;
  771. ha->irq = pdev->irq;
  772. ha->pdev = pdev;
  773. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  774. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  775. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  776. if (ha->brd == NULL) {
  777. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  778. return 0;
  779. }
  780. /* check and reset interface area */
  781. dp6_ptr = ha->brd;
  782. writel(DPMEM_MAGIC, &dp6_ptr->u);
  783. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  784. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  785. pcistr->dpmem);
  786. found = FALSE;
  787. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  788. iounmap(ha->brd);
  789. ha->brd = ioremap(i, sizeof(u16));
  790. if (ha->brd == NULL) {
  791. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  792. return 0;
  793. }
  794. if (readw(ha->brd) != 0xffff) {
  795. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  796. continue;
  797. }
  798. iounmap(ha->brd);
  799. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  800. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  801. if (ha->brd == NULL) {
  802. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  803. return 0;
  804. }
  805. dp6_ptr = ha->brd;
  806. writel(DPMEM_MAGIC, &dp6_ptr->u);
  807. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  808. printk("GDT-PCI: Use free address at 0x%x\n", i);
  809. found = TRUE;
  810. break;
  811. }
  812. }
  813. if (!found) {
  814. printk("GDT-PCI: No free address found!\n");
  815. iounmap(ha->brd);
  816. return 0;
  817. }
  818. }
  819. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  820. if (readl(&dp6_ptr->u) != 0) {
  821. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  822. iounmap(ha->brd);
  823. return 0;
  824. }
  825. /* disable board interrupts, deinit services */
  826. writeb(0xff, &dp6_ptr->io.irqdel);
  827. writeb(0x00, &dp6_ptr->io.irqen);
  828. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  829. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  830. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  831. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  832. writeb(0, &dp6_ptr->io.event);
  833. retries = INIT_RETRIES;
  834. gdth_delay(20);
  835. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  836. if (--retries == 0) {
  837. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  838. iounmap(ha->brd);
  839. return 0;
  840. }
  841. gdth_delay(1);
  842. }
  843. prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
  844. writeb(0, &dp6_ptr->u.ic.S_Status);
  845. writeb(0xff, &dp6_ptr->io.irqdel);
  846. if (prot_ver != PROTOCOL_VERSION) {
  847. printk("GDT-PCI: Illegal protocol version\n");
  848. iounmap(ha->brd);
  849. return 0;
  850. }
  851. ha->type = GDT_PCI;
  852. ha->ic_all_size = sizeof(dp6_ptr->u);
  853. /* special command to controller BIOS */
  854. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  856. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  857. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  858. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  859. writeb(0, &dp6_ptr->io.event);
  860. retries = INIT_RETRIES;
  861. gdth_delay(20);
  862. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  863. if (--retries == 0) {
  864. printk("GDT-PCI: Initialization error\n");
  865. iounmap(ha->brd);
  866. return 0;
  867. }
  868. gdth_delay(1);
  869. }
  870. writeb(0, &dp6_ptr->u.ic.S_Status);
  871. writeb(0xff, &dp6_ptr->io.irqdel);
  872. ha->dma64_support = 0;
  873. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  874. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  875. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  876. pcistr->dpmem,ha->irq));
  877. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  878. if (ha->brd == NULL) {
  879. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  880. iounmap(ha->brd);
  881. return 0;
  882. }
  883. /* check and reset interface area */
  884. dp6c_ptr = ha->brd;
  885. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  886. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  887. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  888. pcistr->dpmem);
  889. found = FALSE;
  890. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  891. iounmap(ha->brd);
  892. ha->brd = ioremap(i, sizeof(u16));
  893. if (ha->brd == NULL) {
  894. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  895. return 0;
  896. }
  897. if (readw(ha->brd) != 0xffff) {
  898. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  899. continue;
  900. }
  901. iounmap(ha->brd);
  902. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  903. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  904. if (ha->brd == NULL) {
  905. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  906. return 0;
  907. }
  908. dp6c_ptr = ha->brd;
  909. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  910. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  911. printk("GDT-PCI: Use free address at 0x%x\n", i);
  912. found = TRUE;
  913. break;
  914. }
  915. }
  916. if (!found) {
  917. printk("GDT-PCI: No free address found!\n");
  918. iounmap(ha->brd);
  919. return 0;
  920. }
  921. }
  922. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  923. if (readl(&dp6c_ptr->u) != 0) {
  924. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  925. iounmap(ha->brd);
  926. return 0;
  927. }
  928. /* disable board interrupts, deinit services */
  929. outb(0x00,PTR2USHORT(&ha->plx->control1));
  930. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  931. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  932. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  933. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  934. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  935. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  936. retries = INIT_RETRIES;
  937. gdth_delay(20);
  938. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  939. if (--retries == 0) {
  940. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  941. iounmap(ha->brd);
  942. return 0;
  943. }
  944. gdth_delay(1);
  945. }
  946. prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
  947. writeb(0, &dp6c_ptr->u.ic.Status);
  948. if (prot_ver != PROTOCOL_VERSION) {
  949. printk("GDT-PCI: Illegal protocol version\n");
  950. iounmap(ha->brd);
  951. return 0;
  952. }
  953. ha->type = GDT_PCINEW;
  954. ha->ic_all_size = sizeof(dp6c_ptr->u);
  955. /* special command to controller BIOS */
  956. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  958. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  959. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  960. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  961. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  962. retries = INIT_RETRIES;
  963. gdth_delay(20);
  964. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  965. if (--retries == 0) {
  966. printk("GDT-PCI: Initialization error\n");
  967. iounmap(ha->brd);
  968. return 0;
  969. }
  970. gdth_delay(1);
  971. }
  972. writeb(0, &dp6c_ptr->u.ic.S_Status);
  973. ha->dma64_support = 0;
  974. } else { /* MPR */
  975. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  976. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  977. if (ha->brd == NULL) {
  978. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  979. return 0;
  980. }
  981. /* manipulate config. space to enable DPMEM, start RP controller */
  982. pci_read_config_word(pdev, PCI_COMMAND, &command);
  983. command |= 6;
  984. pci_write_config_word(pdev, PCI_COMMAND, command);
  985. gdth_delay(1);
  986. dp6m_ptr = ha->brd;
  987. /* Ensure that it is safe to access the non HW portions of DPMEM.
  988. * Aditional check needed for Xscale based RAID controllers */
  989. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  990. gdth_delay(1);
  991. /* check and reset interface area */
  992. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  993. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  994. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  995. pcistr->dpmem);
  996. found = FALSE;
  997. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  998. iounmap(ha->brd);
  999. ha->brd = ioremap(i, sizeof(u16));
  1000. if (ha->brd == NULL) {
  1001. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1002. return 0;
  1003. }
  1004. if (readw(ha->brd) != 0xffff) {
  1005. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1006. continue;
  1007. }
  1008. iounmap(ha->brd);
  1009. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1010. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1011. if (ha->brd == NULL) {
  1012. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1013. return 0;
  1014. }
  1015. dp6m_ptr = ha->brd;
  1016. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1017. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1018. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1019. found = TRUE;
  1020. break;
  1021. }
  1022. }
  1023. if (!found) {
  1024. printk("GDT-PCI: No free address found!\n");
  1025. iounmap(ha->brd);
  1026. return 0;
  1027. }
  1028. }
  1029. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1030. /* disable board interrupts, deinit services */
  1031. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1032. &dp6m_ptr->i960r.edoor_en_reg);
  1033. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1034. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1035. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1036. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1037. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1038. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1039. retries = INIT_RETRIES;
  1040. gdth_delay(20);
  1041. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1042. if (--retries == 0) {
  1043. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1044. iounmap(ha->brd);
  1045. return 0;
  1046. }
  1047. gdth_delay(1);
  1048. }
  1049. prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1050. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1051. if (prot_ver != PROTOCOL_VERSION) {
  1052. printk("GDT-PCI: Illegal protocol version\n");
  1053. iounmap(ha->brd);
  1054. return 0;
  1055. }
  1056. ha->type = GDT_PCIMPR;
  1057. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1058. /* special command to controller BIOS */
  1059. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1060. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1061. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1062. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1063. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1064. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1065. retries = INIT_RETRIES;
  1066. gdth_delay(20);
  1067. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1068. if (--retries == 0) {
  1069. printk("GDT-PCI: Initialization error\n");
  1070. iounmap(ha->brd);
  1071. return 0;
  1072. }
  1073. gdth_delay(1);
  1074. }
  1075. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1076. /* read FW version to detect 64-bit DMA support */
  1077. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1078. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1079. retries = INIT_RETRIES;
  1080. gdth_delay(20);
  1081. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1082. if (--retries == 0) {
  1083. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1084. iounmap(ha->brd);
  1085. return 0;
  1086. }
  1087. gdth_delay(1);
  1088. }
  1089. prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1090. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1091. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1092. ha->dma64_support = 0;
  1093. else
  1094. ha->dma64_support = 1;
  1095. }
  1096. return 1;
  1097. }
  1098. #endif /* CONFIG_PCI */
  1099. /* controller protocol functions */
  1100. static void gdth_enable_int(gdth_ha_str *ha)
  1101. {
  1102. unsigned long flags;
  1103. gdt2_dpram_str __iomem *dp2_ptr;
  1104. gdt6_dpram_str __iomem *dp6_ptr;
  1105. gdt6m_dpram_str __iomem *dp6m_ptr;
  1106. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1107. spin_lock_irqsave(&ha->smp_lock, flags);
  1108. if (ha->type == GDT_EISA) {
  1109. outb(0xff, ha->bmic + EDOORREG);
  1110. outb(0xff, ha->bmic + EDENABREG);
  1111. outb(0x01, ha->bmic + EINTENABREG);
  1112. } else if (ha->type == GDT_ISA) {
  1113. dp2_ptr = ha->brd;
  1114. writeb(1, &dp2_ptr->io.irqdel);
  1115. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1116. writeb(1, &dp2_ptr->io.irqen);
  1117. } else if (ha->type == GDT_PCI) {
  1118. dp6_ptr = ha->brd;
  1119. writeb(1, &dp6_ptr->io.irqdel);
  1120. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1121. writeb(1, &dp6_ptr->io.irqen);
  1122. } else if (ha->type == GDT_PCINEW) {
  1123. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1124. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1125. } else if (ha->type == GDT_PCIMPR) {
  1126. dp6m_ptr = ha->brd;
  1127. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1128. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1129. &dp6m_ptr->i960r.edoor_en_reg);
  1130. }
  1131. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1132. }
  1133. /* return IStatus if interrupt was from this card else 0 */
  1134. static u8 gdth_get_status(gdth_ha_str *ha)
  1135. {
  1136. u8 IStatus = 0;
  1137. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1138. if (ha->type == GDT_EISA)
  1139. IStatus = inb((u16)ha->bmic + EDOORREG);
  1140. else if (ha->type == GDT_ISA)
  1141. IStatus =
  1142. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1143. else if (ha->type == GDT_PCI)
  1144. IStatus =
  1145. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1146. else if (ha->type == GDT_PCINEW)
  1147. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1148. else if (ha->type == GDT_PCIMPR)
  1149. IStatus =
  1150. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1151. return IStatus;
  1152. }
  1153. static int gdth_test_busy(gdth_ha_str *ha)
  1154. {
  1155. register int gdtsema0 = 0;
  1156. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1157. if (ha->type == GDT_EISA)
  1158. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1159. else if (ha->type == GDT_ISA)
  1160. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1161. else if (ha->type == GDT_PCI)
  1162. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1163. else if (ha->type == GDT_PCINEW)
  1164. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1165. else if (ha->type == GDT_PCIMPR)
  1166. gdtsema0 =
  1167. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1168. return (gdtsema0 & 1);
  1169. }
  1170. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1171. {
  1172. int i;
  1173. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1174. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1175. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1176. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1177. ha->cmd_tab[i].service = ha->pccb->Service;
  1178. ha->pccb->CommandIndex = (u32)i+2;
  1179. return (i+2);
  1180. }
  1181. }
  1182. return 0;
  1183. }
  1184. static void gdth_set_sema0(gdth_ha_str *ha)
  1185. {
  1186. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1187. if (ha->type == GDT_EISA) {
  1188. outb(1, ha->bmic + SEMA0REG);
  1189. } else if (ha->type == GDT_ISA) {
  1190. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1191. } else if (ha->type == GDT_PCI) {
  1192. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1193. } else if (ha->type == GDT_PCINEW) {
  1194. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1195. } else if (ha->type == GDT_PCIMPR) {
  1196. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1197. }
  1198. }
  1199. static void gdth_copy_command(gdth_ha_str *ha)
  1200. {
  1201. register gdth_cmd_str *cmd_ptr;
  1202. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1203. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1204. gdt6_dpram_str __iomem *dp6_ptr;
  1205. gdt2_dpram_str __iomem *dp2_ptr;
  1206. u16 cp_count,dp_offset,cmd_no;
  1207. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1208. cp_count = ha->cmd_len;
  1209. dp_offset= ha->cmd_offs_dpmem;
  1210. cmd_no = ha->cmd_cnt;
  1211. cmd_ptr = ha->pccb;
  1212. ++ha->cmd_cnt;
  1213. if (ha->type == GDT_EISA)
  1214. return; /* no DPMEM, no copy */
  1215. /* set cpcount dword aligned */
  1216. if (cp_count & 3)
  1217. cp_count += (4 - (cp_count & 3));
  1218. ha->cmd_offs_dpmem += cp_count;
  1219. /* set offset and service, copy command to DPMEM */
  1220. if (ha->type == GDT_ISA) {
  1221. dp2_ptr = ha->brd;
  1222. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1223. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1224. writew((u16)cmd_ptr->Service,
  1225. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1226. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1227. } else if (ha->type == GDT_PCI) {
  1228. dp6_ptr = ha->brd;
  1229. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1230. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1231. writew((u16)cmd_ptr->Service,
  1232. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1233. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1234. } else if (ha->type == GDT_PCINEW) {
  1235. dp6c_ptr = ha->brd;
  1236. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1237. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1238. writew((u16)cmd_ptr->Service,
  1239. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1240. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1241. } else if (ha->type == GDT_PCIMPR) {
  1242. dp6m_ptr = ha->brd;
  1243. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1244. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1245. writew((u16)cmd_ptr->Service,
  1246. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1247. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1248. }
  1249. }
  1250. static void gdth_release_event(gdth_ha_str *ha)
  1251. {
  1252. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1253. #ifdef GDTH_STATISTICS
  1254. {
  1255. u32 i,j;
  1256. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1257. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1258. ++i;
  1259. }
  1260. if (max_index < i) {
  1261. max_index = i;
  1262. TRACE3(("GDT: max_index = %d\n",(u16)i));
  1263. }
  1264. }
  1265. #endif
  1266. if (ha->pccb->OpCode == GDT_INIT)
  1267. ha->pccb->Service |= 0x80;
  1268. if (ha->type == GDT_EISA) {
  1269. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1270. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1271. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1272. } else if (ha->type == GDT_ISA) {
  1273. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1274. } else if (ha->type == GDT_PCI) {
  1275. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1276. } else if (ha->type == GDT_PCINEW) {
  1277. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1278. } else if (ha->type == GDT_PCIMPR) {
  1279. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1280. }
  1281. }
  1282. static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
  1283. {
  1284. int answer_found = FALSE;
  1285. int wait_index = 0;
  1286. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1287. if (index == 0)
  1288. return 1; /* no wait required */
  1289. do {
  1290. __gdth_interrupt(ha, true, &wait_index);
  1291. if (wait_index == index) {
  1292. answer_found = TRUE;
  1293. break;
  1294. }
  1295. gdth_delay(1);
  1296. } while (--time);
  1297. while (gdth_test_busy(ha))
  1298. gdth_delay(0);
  1299. return (answer_found);
  1300. }
  1301. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  1302. u32 p1, u64 p2, u64 p3)
  1303. {
  1304. register gdth_cmd_str *cmd_ptr;
  1305. int retries,index;
  1306. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1307. cmd_ptr = ha->pccb;
  1308. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1309. /* make command */
  1310. for (retries = INIT_RETRIES;;) {
  1311. cmd_ptr->Service = service;
  1312. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1313. if (!(index=gdth_get_cmd_index(ha))) {
  1314. TRACE(("GDT: No free command index found\n"));
  1315. return 0;
  1316. }
  1317. gdth_set_sema0(ha);
  1318. cmd_ptr->OpCode = opcode;
  1319. cmd_ptr->BoardNode = LOCALBOARD;
  1320. if (service == CACHESERVICE) {
  1321. if (opcode == GDT_IOCTL) {
  1322. cmd_ptr->u.ioctl.subfunc = p1;
  1323. cmd_ptr->u.ioctl.channel = (u32)p2;
  1324. cmd_ptr->u.ioctl.param_size = (u16)p3;
  1325. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1326. } else {
  1327. if (ha->cache_feat & GDT_64BIT) {
  1328. cmd_ptr->u.cache64.DeviceNo = (u16)p1;
  1329. cmd_ptr->u.cache64.BlockNo = p2;
  1330. } else {
  1331. cmd_ptr->u.cache.DeviceNo = (u16)p1;
  1332. cmd_ptr->u.cache.BlockNo = (u32)p2;
  1333. }
  1334. }
  1335. } else if (service == SCSIRAWSERVICE) {
  1336. if (ha->raw_feat & GDT_64BIT) {
  1337. cmd_ptr->u.raw64.direction = p1;
  1338. cmd_ptr->u.raw64.bus = (u8)p2;
  1339. cmd_ptr->u.raw64.target = (u8)p3;
  1340. cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
  1341. } else {
  1342. cmd_ptr->u.raw.direction = p1;
  1343. cmd_ptr->u.raw.bus = (u8)p2;
  1344. cmd_ptr->u.raw.target = (u8)p3;
  1345. cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
  1346. }
  1347. } else if (service == SCREENSERVICE) {
  1348. if (opcode == GDT_REALTIME) {
  1349. *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1350. *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
  1351. *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
  1352. }
  1353. }
  1354. ha->cmd_len = sizeof(gdth_cmd_str);
  1355. ha->cmd_offs_dpmem = 0;
  1356. ha->cmd_cnt = 0;
  1357. gdth_copy_command(ha);
  1358. gdth_release_event(ha);
  1359. gdth_delay(20);
  1360. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1361. printk("GDT: Initialization error (timeout service %d)\n",service);
  1362. return 0;
  1363. }
  1364. if (ha->status != S_BSY || --retries == 0)
  1365. break;
  1366. gdth_delay(1);
  1367. }
  1368. return (ha->status != S_OK ? 0:1);
  1369. }
  1370. /* search for devices */
  1371. static int gdth_search_drives(gdth_ha_str *ha)
  1372. {
  1373. u16 cdev_cnt, i;
  1374. int ok;
  1375. u32 bus_no, drv_cnt, drv_no, j;
  1376. gdth_getch_str *chn;
  1377. gdth_drlist_str *drl;
  1378. gdth_iochan_str *ioc;
  1379. gdth_raw_iochan_str *iocr;
  1380. gdth_arcdl_str *alst;
  1381. gdth_alist_str *alst2;
  1382. gdth_oem_str_ioctl *oemstr;
  1383. #ifdef INT_COAL
  1384. gdth_perf_modes *pmod;
  1385. #endif
  1386. #ifdef GDTH_RTC
  1387. u8 rtc[12];
  1388. unsigned long flags;
  1389. #endif
  1390. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1391. ok = 0;
  1392. /* initialize controller services, at first: screen service */
  1393. ha->screen_feat = 0;
  1394. if (!force_dma32) {
  1395. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1396. if (ok)
  1397. ha->screen_feat = GDT_64BIT;
  1398. }
  1399. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1400. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1401. if (!ok) {
  1402. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1403. ha->hanum, ha->status);
  1404. return 0;
  1405. }
  1406. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1407. #ifdef GDTH_RTC
  1408. /* read realtime clock info, send to controller */
  1409. /* 1. wait for the falling edge of update flag */
  1410. spin_lock_irqsave(&rtc_lock, flags);
  1411. for (j = 0; j < 1000000; ++j)
  1412. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1413. break;
  1414. for (j = 0; j < 1000000; ++j)
  1415. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1416. break;
  1417. /* 2. read info */
  1418. do {
  1419. for (j = 0; j < 12; ++j)
  1420. rtc[j] = CMOS_READ(j);
  1421. } while (rtc[0] != CMOS_READ(0));
  1422. spin_unlock_irqrestore(&rtc_lock, flags);
  1423. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
  1424. *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
  1425. /* 3. send to controller firmware */
  1426. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
  1427. *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
  1428. #endif
  1429. /* unfreeze all IOs */
  1430. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1431. /* initialize cache service */
  1432. ha->cache_feat = 0;
  1433. if (!force_dma32) {
  1434. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1435. 0, 0);
  1436. if (ok)
  1437. ha->cache_feat = GDT_64BIT;
  1438. }
  1439. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1440. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1441. if (!ok) {
  1442. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1443. ha->hanum, ha->status);
  1444. return 0;
  1445. }
  1446. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1447. cdev_cnt = (u16)ha->info;
  1448. ha->fw_vers = ha->service;
  1449. #ifdef INT_COAL
  1450. if (ha->type == GDT_PCIMPR) {
  1451. /* set perf. modes */
  1452. pmod = (gdth_perf_modes *)ha->pscratch;
  1453. pmod->version = 1;
  1454. pmod->st_mode = 1; /* enable one status buffer */
  1455. *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1456. pmod->st_buff_indx1 = COALINDEX;
  1457. pmod->st_buff_addr2 = 0;
  1458. pmod->st_buff_u_addr2 = 0;
  1459. pmod->st_buff_indx2 = 0;
  1460. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1461. pmod->cmd_mode = 0; // disable all cmd buffers
  1462. pmod->cmd_buff_addr1 = 0;
  1463. pmod->cmd_buff_u_addr1 = 0;
  1464. pmod->cmd_buff_indx1 = 0;
  1465. pmod->cmd_buff_addr2 = 0;
  1466. pmod->cmd_buff_u_addr2 = 0;
  1467. pmod->cmd_buff_indx2 = 0;
  1468. pmod->cmd_buff_size = 0;
  1469. pmod->reserved1 = 0;
  1470. pmod->reserved2 = 0;
  1471. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1472. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1473. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1474. }
  1475. }
  1476. #endif
  1477. /* detect number of buses - try new IOCTL */
  1478. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1479. iocr->hdr.version = 0xffffffff;
  1480. iocr->hdr.list_entries = MAXBUS;
  1481. iocr->hdr.first_chan = 0;
  1482. iocr->hdr.last_chan = MAXBUS-1;
  1483. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1484. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1485. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1486. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1487. ha->bus_cnt = iocr->hdr.chan_count;
  1488. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1489. if (iocr->list[bus_no].proc_id < MAXID)
  1490. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1491. else
  1492. ha->bus_id[bus_no] = 0xff;
  1493. }
  1494. } else {
  1495. /* old method */
  1496. chn = (gdth_getch_str *)ha->pscratch;
  1497. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1498. chn->channel_no = bus_no;
  1499. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1500. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1501. IO_CHANNEL | INVALID_CHANNEL,
  1502. sizeof(gdth_getch_str))) {
  1503. if (bus_no == 0) {
  1504. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1505. ha->hanum, ha->status);
  1506. return 0;
  1507. }
  1508. break;
  1509. }
  1510. if (chn->siop_id < MAXID)
  1511. ha->bus_id[bus_no] = chn->siop_id;
  1512. else
  1513. ha->bus_id[bus_no] = 0xff;
  1514. }
  1515. ha->bus_cnt = (u8)bus_no;
  1516. }
  1517. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1518. /* read cache configuration */
  1519. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1520. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1521. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1522. ha->hanum, ha->status);
  1523. return 0;
  1524. }
  1525. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1526. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1527. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1528. ha->cpar.write_back,ha->cpar.block_size));
  1529. /* read board info and features */
  1530. ha->more_proc = FALSE;
  1531. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1532. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1533. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1534. sizeof(gdth_binfo_str));
  1535. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1536. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1537. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1538. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1539. ha->more_proc = TRUE;
  1540. }
  1541. } else {
  1542. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1543. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1544. }
  1545. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1546. /* read more informations */
  1547. if (ha->more_proc) {
  1548. /* physical drives, channel addresses */
  1549. ioc = (gdth_iochan_str *)ha->pscratch;
  1550. ioc->hdr.version = 0xffffffff;
  1551. ioc->hdr.list_entries = MAXBUS;
  1552. ioc->hdr.first_chan = 0;
  1553. ioc->hdr.last_chan = MAXBUS-1;
  1554. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1555. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1556. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1557. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1558. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1559. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1560. }
  1561. } else {
  1562. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1563. ha->raw[bus_no].address = IO_CHANNEL;
  1564. ha->raw[bus_no].local_no = bus_no;
  1565. }
  1566. }
  1567. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1568. chn = (gdth_getch_str *)ha->pscratch;
  1569. chn->channel_no = ha->raw[bus_no].local_no;
  1570. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1571. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1572. ha->raw[bus_no].address | INVALID_CHANNEL,
  1573. sizeof(gdth_getch_str))) {
  1574. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1575. TRACE2(("Channel %d: %d phys. drives\n",
  1576. bus_no,chn->drive_cnt));
  1577. }
  1578. if (ha->raw[bus_no].pdev_cnt > 0) {
  1579. drl = (gdth_drlist_str *)ha->pscratch;
  1580. drl->sc_no = ha->raw[bus_no].local_no;
  1581. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1582. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1583. SCSI_DR_LIST | L_CTRL_PATTERN,
  1584. ha->raw[bus_no].address | INVALID_CHANNEL,
  1585. sizeof(gdth_drlist_str))) {
  1586. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1587. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1588. } else {
  1589. ha->raw[bus_no].pdev_cnt = 0;
  1590. }
  1591. }
  1592. }
  1593. /* logical drives */
  1594. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1595. INVALID_CHANNEL,sizeof(u32))) {
  1596. drv_cnt = *(u32 *)ha->pscratch;
  1597. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1598. INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
  1599. for (j = 0; j < drv_cnt; ++j) {
  1600. drv_no = ((u32 *)ha->pscratch)[j];
  1601. if (drv_no < MAX_LDRIVES) {
  1602. ha->hdr[drv_no].is_logdrv = TRUE;
  1603. TRACE2(("Drive %d is log. drive\n",drv_no));
  1604. }
  1605. }
  1606. }
  1607. alst = (gdth_arcdl_str *)ha->pscratch;
  1608. alst->entries_avail = MAX_LDRIVES;
  1609. alst->first_entry = 0;
  1610. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1611. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1612. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1613. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1614. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1615. for (j = 0; j < alst->entries_init; ++j) {
  1616. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1617. ha->hdr[j].is_master = alst->list[j].is_master;
  1618. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1619. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1620. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1621. }
  1622. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1623. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1624. 0, 35 * sizeof(gdth_alist_str))) {
  1625. for (j = 0; j < 35; ++j) {
  1626. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1627. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1628. ha->hdr[j].is_master = alst2->is_master;
  1629. ha->hdr[j].is_parity = alst2->is_parity;
  1630. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1631. ha->hdr[j].master_no = alst2->cd_handle;
  1632. }
  1633. }
  1634. }
  1635. }
  1636. /* initialize raw service */
  1637. ha->raw_feat = 0;
  1638. if (!force_dma32) {
  1639. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1640. if (ok)
  1641. ha->raw_feat = GDT_64BIT;
  1642. }
  1643. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1644. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1645. if (!ok) {
  1646. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1647. ha->hanum, ha->status);
  1648. return 0;
  1649. }
  1650. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1651. /* set/get features raw service (scatter/gather) */
  1652. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1653. 0, 0)) {
  1654. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1655. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1656. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1657. ha->info));
  1658. ha->raw_feat |= (u16)ha->info;
  1659. }
  1660. }
  1661. /* set/get features cache service (equal to raw service) */
  1662. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1663. SCATTER_GATHER,0)) {
  1664. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1665. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1666. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1667. ha->info));
  1668. ha->cache_feat |= (u16)ha->info;
  1669. }
  1670. }
  1671. /* reserve drives for raw service */
  1672. if (reserve_mode != 0) {
  1673. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1674. reserve_mode == 1 ? 1 : 3, 0, 0);
  1675. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1676. ha->status));
  1677. }
  1678. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1679. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1680. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1681. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1682. reserve_list[i], reserve_list[i+1],
  1683. reserve_list[i+2], reserve_list[i+3]));
  1684. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1685. reserve_list[i+1], reserve_list[i+2] |
  1686. (reserve_list[i+3] << 8))) {
  1687. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1688. ha->hanum, ha->status);
  1689. }
  1690. }
  1691. }
  1692. /* Determine OEM string using IOCTL */
  1693. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1694. oemstr->params.ctl_version = 0x01;
  1695. oemstr->params.buffer_size = sizeof(oemstr->text);
  1696. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1697. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1698. sizeof(gdth_oem_str_ioctl))) {
  1699. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1700. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1701. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1702. /* Save the Host Drive inquiry data */
  1703. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1704. sizeof(ha->oem_name));
  1705. } else {
  1706. /* Old method, based on PCI ID */
  1707. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1708. printk("GDT-HA %d: Name: %s\n",
  1709. ha->hanum, ha->binfo.type_string);
  1710. if (ha->oem_id == OEM_ID_INTEL)
  1711. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1712. else
  1713. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1714. }
  1715. /* scanning for host drives */
  1716. for (i = 0; i < cdev_cnt; ++i)
  1717. gdth_analyse_hdrive(ha, i);
  1718. TRACE(("gdth_search_drives() OK\n"));
  1719. return 1;
  1720. }
  1721. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
  1722. {
  1723. u32 drv_cyls;
  1724. int drv_hds, drv_secs;
  1725. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1726. if (hdrive >= MAX_HDRIVES)
  1727. return 0;
  1728. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1729. return 0;
  1730. ha->hdr[hdrive].present = TRUE;
  1731. ha->hdr[hdrive].size = ha->info;
  1732. /* evaluate mapping (sectors per head, heads per cylinder) */
  1733. ha->hdr[hdrive].size &= ~SECS32;
  1734. if (ha->info2 == 0) {
  1735. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1736. } else {
  1737. drv_hds = ha->info2 & 0xff;
  1738. drv_secs = (ha->info2 >> 8) & 0xff;
  1739. drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1740. }
  1741. ha->hdr[hdrive].heads = (u8)drv_hds;
  1742. ha->hdr[hdrive].secs = (u8)drv_secs;
  1743. /* round size */
  1744. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1745. if (ha->cache_feat & GDT_64BIT) {
  1746. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1747. && ha->info2 != 0) {
  1748. ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
  1749. }
  1750. }
  1751. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1752. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1753. /* get informations about device */
  1754. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1755. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1756. hdrive,ha->info));
  1757. ha->hdr[hdrive].devtype = (u16)ha->info;
  1758. }
  1759. /* cluster info */
  1760. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1761. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1762. hdrive,ha->info));
  1763. if (!shared_access)
  1764. ha->hdr[hdrive].cluster_type = (u8)ha->info;
  1765. }
  1766. /* R/W attributes */
  1767. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1768. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1769. hdrive,ha->info));
  1770. ha->hdr[hdrive].rw_attribs = (u8)ha->info;
  1771. }
  1772. return 1;
  1773. }
  1774. /* command queueing/sending functions */
  1775. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority)
  1776. {
  1777. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1778. register Scsi_Cmnd *pscp;
  1779. register Scsi_Cmnd *nscp;
  1780. unsigned long flags;
  1781. TRACE(("gdth_putq() priority %d\n",priority));
  1782. spin_lock_irqsave(&ha->smp_lock, flags);
  1783. if (!cmndinfo->internal_command)
  1784. cmndinfo->priority = priority;
  1785. if (ha->req_first==NULL) {
  1786. ha->req_first = scp; /* queue was empty */
  1787. scp->SCp.ptr = NULL;
  1788. } else { /* queue not empty */
  1789. pscp = ha->req_first;
  1790. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1791. /* priority: 0-highest,..,0xff-lowest */
  1792. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1793. pscp = nscp;
  1794. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1795. }
  1796. pscp->SCp.ptr = (char *)scp;
  1797. scp->SCp.ptr = (char *)nscp;
  1798. }
  1799. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1800. #ifdef GDTH_STATISTICS
  1801. flags = 0;
  1802. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1803. ++flags;
  1804. if (max_rq < flags) {
  1805. max_rq = flags;
  1806. TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
  1807. }
  1808. #endif
  1809. }
  1810. static void gdth_next(gdth_ha_str *ha)
  1811. {
  1812. register Scsi_Cmnd *pscp;
  1813. register Scsi_Cmnd *nscp;
  1814. u8 b, t, l, firsttime;
  1815. u8 this_cmd, next_cmd;
  1816. unsigned long flags = 0;
  1817. int cmd_index;
  1818. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1819. if (!gdth_polling)
  1820. spin_lock_irqsave(&ha->smp_lock, flags);
  1821. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1822. this_cmd = firsttime = TRUE;
  1823. next_cmd = gdth_polling ? FALSE:TRUE;
  1824. cmd_index = 0;
  1825. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1826. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1827. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1828. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1829. if (!nscp_cmndinfo->internal_command) {
  1830. b = nscp->device->channel;
  1831. t = nscp->device->id;
  1832. l = nscp->device->lun;
  1833. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1834. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1835. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1836. continue;
  1837. }
  1838. } else
  1839. b = t = l = 0;
  1840. if (firsttime) {
  1841. if (gdth_test_busy(ha)) { /* controller busy ? */
  1842. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1843. if (!gdth_polling) {
  1844. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1845. return;
  1846. }
  1847. while (gdth_test_busy(ha))
  1848. gdth_delay(1);
  1849. }
  1850. firsttime = FALSE;
  1851. }
  1852. if (!nscp_cmndinfo->internal_command) {
  1853. if (nscp_cmndinfo->phase == -1) {
  1854. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1855. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1856. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1857. b, t, l));
  1858. /* TEST_UNIT_READY -> set scan mode */
  1859. if ((ha->scan_mode & 0x0f) == 0) {
  1860. if (b == 0 && t == 0 && l == 0) {
  1861. ha->scan_mode |= 1;
  1862. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1863. }
  1864. } else if ((ha->scan_mode & 0x0f) == 1) {
  1865. if (b == 0 && ((t == 0 && l == 1) ||
  1866. (t == 1 && l == 0))) {
  1867. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1868. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1869. | SCSIRAWSERVICE;
  1870. ha->scan_mode = 0x12;
  1871. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1872. ha->scan_mode));
  1873. } else {
  1874. ha->scan_mode &= 0x10;
  1875. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1876. }
  1877. } else if (ha->scan_mode == 0x12) {
  1878. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1879. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1880. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1881. ha->scan_mode &= 0x10;
  1882. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1883. ha->scan_mode));
  1884. }
  1885. }
  1886. }
  1887. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1888. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1889. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1890. /* always GDT_CLUST_INFO! */
  1891. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1892. }
  1893. }
  1894. }
  1895. if (nscp_cmndinfo->OpCode != -1) {
  1896. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1897. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1898. this_cmd = FALSE;
  1899. next_cmd = FALSE;
  1900. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1901. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1902. this_cmd = FALSE;
  1903. next_cmd = FALSE;
  1904. } else {
  1905. memset((char*)nscp->sense_buffer,0,16);
  1906. nscp->sense_buffer[0] = 0x70;
  1907. nscp->sense_buffer[2] = NOT_READY;
  1908. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1909. if (!nscp_cmndinfo->wait_for_completion)
  1910. nscp_cmndinfo->wait_for_completion++;
  1911. else
  1912. gdth_scsi_done(nscp);
  1913. }
  1914. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1915. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1916. this_cmd = FALSE;
  1917. next_cmd = FALSE;
  1918. } else if (b != ha->virt_bus) {
  1919. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1920. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1921. this_cmd = FALSE;
  1922. else
  1923. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1924. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1925. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1926. nscp->cmnd[0], b, t, l));
  1927. nscp->result = DID_BAD_TARGET << 16;
  1928. if (!nscp_cmndinfo->wait_for_completion)
  1929. nscp_cmndinfo->wait_for_completion++;
  1930. else
  1931. gdth_scsi_done(nscp);
  1932. } else {
  1933. switch (nscp->cmnd[0]) {
  1934. case TEST_UNIT_READY:
  1935. case INQUIRY:
  1936. case REQUEST_SENSE:
  1937. case READ_CAPACITY:
  1938. case VERIFY:
  1939. case START_STOP:
  1940. case MODE_SENSE:
  1941. case SERVICE_ACTION_IN:
  1942. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1943. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1944. nscp->cmnd[4],nscp->cmnd[5]));
  1945. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1946. /* return UNIT_ATTENTION */
  1947. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1948. nscp->cmnd[0], t));
  1949. ha->hdr[t].media_changed = FALSE;
  1950. memset((char*)nscp->sense_buffer,0,16);
  1951. nscp->sense_buffer[0] = 0x70;
  1952. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1953. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1954. if (!nscp_cmndinfo->wait_for_completion)
  1955. nscp_cmndinfo->wait_for_completion++;
  1956. else
  1957. gdth_scsi_done(nscp);
  1958. } else if (gdth_internal_cache_cmd(ha, nscp))
  1959. gdth_scsi_done(nscp);
  1960. break;
  1961. case ALLOW_MEDIUM_REMOVAL:
  1962. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1963. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1964. nscp->cmnd[4],nscp->cmnd[5]));
  1965. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1966. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1967. nscp->result = DID_OK << 16;
  1968. nscp->sense_buffer[0] = 0;
  1969. if (!nscp_cmndinfo->wait_for_completion)
  1970. nscp_cmndinfo->wait_for_completion++;
  1971. else
  1972. gdth_scsi_done(nscp);
  1973. } else {
  1974. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1975. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1976. nscp->cmnd[4],nscp->cmnd[3]));
  1977. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1978. this_cmd = FALSE;
  1979. }
  1980. break;
  1981. case RESERVE:
  1982. case RELEASE:
  1983. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1984. "RESERVE" : "RELEASE"));
  1985. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1986. this_cmd = FALSE;
  1987. break;
  1988. case READ_6:
  1989. case WRITE_6:
  1990. case READ_10:
  1991. case WRITE_10:
  1992. case READ_16:
  1993. case WRITE_16:
  1994. if (ha->hdr[t].media_changed) {
  1995. /* return UNIT_ATTENTION */
  1996. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1997. nscp->cmnd[0], t));
  1998. ha->hdr[t].media_changed = FALSE;
  1999. memset((char*)nscp->sense_buffer,0,16);
  2000. nscp->sense_buffer[0] = 0x70;
  2001. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2002. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2003. if (!nscp_cmndinfo->wait_for_completion)
  2004. nscp_cmndinfo->wait_for_completion++;
  2005. else
  2006. gdth_scsi_done(nscp);
  2007. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2008. this_cmd = FALSE;
  2009. break;
  2010. default:
  2011. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2012. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2013. nscp->cmnd[4],nscp->cmnd[5]));
  2014. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2015. ha->hanum, nscp->cmnd[0]);
  2016. nscp->result = DID_ABORT << 16;
  2017. if (!nscp_cmndinfo->wait_for_completion)
  2018. nscp_cmndinfo->wait_for_completion++;
  2019. else
  2020. gdth_scsi_done(nscp);
  2021. break;
  2022. }
  2023. }
  2024. if (!this_cmd)
  2025. break;
  2026. if (nscp == ha->req_first)
  2027. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2028. else
  2029. pscp->SCp.ptr = nscp->SCp.ptr;
  2030. if (!next_cmd)
  2031. break;
  2032. }
  2033. if (ha->cmd_cnt > 0) {
  2034. gdth_release_event(ha);
  2035. }
  2036. if (!gdth_polling)
  2037. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2038. if (gdth_polling && ha->cmd_cnt > 0) {
  2039. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2040. printk("GDT-HA %d: Command %d timed out !\n",
  2041. ha->hanum, cmd_index);
  2042. }
  2043. }
  2044. /*
  2045. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2046. * buffers, kmap_atomic() as needed.
  2047. */
  2048. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2049. char *buffer, u16 count)
  2050. {
  2051. u16 cpcount,i, max_sg = scsi_sg_count(scp);
  2052. u16 cpsum,cpnow;
  2053. struct scatterlist *sl;
  2054. char *address;
  2055. cpcount = min_t(u16, count, scsi_bufflen(scp));
  2056. if (cpcount) {
  2057. cpsum=0;
  2058. scsi_for_each_sg(scp, sl, max_sg, i) {
  2059. unsigned long flags;
  2060. cpnow = (u16)sl->length;
  2061. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2062. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2063. if (cpsum+cpnow > cpcount)
  2064. cpnow = cpcount - cpsum;
  2065. cpsum += cpnow;
  2066. if (!sg_page(sl)) {
  2067. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2068. ha->hanum);
  2069. return;
  2070. }
  2071. local_irq_save(flags);
  2072. address = kmap_atomic(sg_page(sl)) + sl->offset;
  2073. memcpy(address, buffer, cpnow);
  2074. flush_dcache_page(sg_page(sl));
  2075. kunmap_atomic(address);
  2076. local_irq_restore(flags);
  2077. if (cpsum == cpcount)
  2078. break;
  2079. buffer += cpnow;
  2080. }
  2081. } else if (count) {
  2082. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2083. ha->hanum);
  2084. WARN_ON(1);
  2085. }
  2086. }
  2087. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2088. {
  2089. u8 t;
  2090. gdth_inq_data inq;
  2091. gdth_rdcap_data rdc;
  2092. gdth_sense_data sd;
  2093. gdth_modep_data mpd;
  2094. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2095. t = scp->device->id;
  2096. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2097. scp->cmnd[0],t));
  2098. scp->result = DID_OK << 16;
  2099. scp->sense_buffer[0] = 0;
  2100. switch (scp->cmnd[0]) {
  2101. case TEST_UNIT_READY:
  2102. case VERIFY:
  2103. case START_STOP:
  2104. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2105. break;
  2106. case INQUIRY:
  2107. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2108. t,ha->hdr[t].devtype));
  2109. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2110. /* you can here set all disks to removable, if you want to do
  2111. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2112. inq.modif_rmb = 0x00;
  2113. if ((ha->hdr[t].devtype & 1) ||
  2114. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2115. inq.modif_rmb = 0x80;
  2116. inq.version = 2;
  2117. inq.resp_aenc = 2;
  2118. inq.add_length= 32;
  2119. strcpy(inq.vendor,ha->oem_name);
  2120. sprintf(inq.product,"Host Drive #%02d",t);
  2121. strcpy(inq.revision," ");
  2122. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2123. break;
  2124. case REQUEST_SENSE:
  2125. TRACE2(("Request sense hdrive %d\n",t));
  2126. sd.errorcode = 0x70;
  2127. sd.segno = 0x00;
  2128. sd.key = NO_SENSE;
  2129. sd.info = 0;
  2130. sd.add_length= 0;
  2131. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2132. break;
  2133. case MODE_SENSE:
  2134. TRACE2(("Mode sense hdrive %d\n",t));
  2135. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2136. mpd.hd.data_length = sizeof(gdth_modep_data);
  2137. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2138. mpd.hd.bd_length = sizeof(mpd.bd);
  2139. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2140. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2141. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2142. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2143. break;
  2144. case READ_CAPACITY:
  2145. TRACE2(("Read capacity hdrive %d\n",t));
  2146. if (ha->hdr[t].size > (u64)0xffffffff)
  2147. rdc.last_block_no = 0xffffffff;
  2148. else
  2149. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2150. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2151. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2152. break;
  2153. case SERVICE_ACTION_IN:
  2154. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2155. (ha->cache_feat & GDT_64BIT)) {
  2156. gdth_rdcap16_data rdc16;
  2157. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2158. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2159. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2160. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2161. sizeof(gdth_rdcap16_data));
  2162. } else {
  2163. scp->result = DID_ABORT << 16;
  2164. }
  2165. break;
  2166. default:
  2167. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2168. break;
  2169. }
  2170. if (!cmndinfo->wait_for_completion)
  2171. cmndinfo->wait_for_completion++;
  2172. else
  2173. return 1;
  2174. return 0;
  2175. }
  2176. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive)
  2177. {
  2178. register gdth_cmd_str *cmdp;
  2179. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2180. u32 cnt, blockcnt;
  2181. u64 no, blockno;
  2182. int i, cmd_index, read_write, sgcnt, mode64;
  2183. cmdp = ha->pccb;
  2184. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2185. scp->cmnd[0],scp->cmd_len,hdrive));
  2186. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2187. return 0;
  2188. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2189. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2190. not required, should not occur due to error return on
  2191. READ_CAPACITY_16 */
  2192. cmdp->Service = CACHESERVICE;
  2193. cmdp->RequestBuffer = scp;
  2194. /* search free command index */
  2195. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2196. TRACE(("GDT: No free command index found\n"));
  2197. return 0;
  2198. }
  2199. /* if it's the first command, set command semaphore */
  2200. if (ha->cmd_cnt == 0)
  2201. gdth_set_sema0(ha);
  2202. /* fill command */
  2203. read_write = 0;
  2204. if (cmndinfo->OpCode != -1)
  2205. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2206. else if (scp->cmnd[0] == RESERVE)
  2207. cmdp->OpCode = GDT_RESERVE_DRV;
  2208. else if (scp->cmnd[0] == RELEASE)
  2209. cmdp->OpCode = GDT_RELEASE_DRV;
  2210. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2211. if (scp->cmnd[4] & 1) /* prevent ? */
  2212. cmdp->OpCode = GDT_MOUNT;
  2213. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2214. cmdp->OpCode = GDT_UNMOUNT;
  2215. else
  2216. cmdp->OpCode = GDT_FLUSH;
  2217. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2218. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2219. ) {
  2220. read_write = 1;
  2221. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2222. (ha->cache_feat & GDT_WR_THROUGH)))
  2223. cmdp->OpCode = GDT_WRITE_THR;
  2224. else
  2225. cmdp->OpCode = GDT_WRITE;
  2226. } else {
  2227. read_write = 2;
  2228. cmdp->OpCode = GDT_READ;
  2229. }
  2230. cmdp->BoardNode = LOCALBOARD;
  2231. if (mode64) {
  2232. cmdp->u.cache64.DeviceNo = hdrive;
  2233. cmdp->u.cache64.BlockNo = 1;
  2234. cmdp->u.cache64.sg_canz = 0;
  2235. } else {
  2236. cmdp->u.cache.DeviceNo = hdrive;
  2237. cmdp->u.cache.BlockNo = 1;
  2238. cmdp->u.cache.sg_canz = 0;
  2239. }
  2240. if (read_write) {
  2241. if (scp->cmd_len == 16) {
  2242. memcpy(&no, &scp->cmnd[2], sizeof(u64));
  2243. blockno = be64_to_cpu(no);
  2244. memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
  2245. blockcnt = be32_to_cpu(cnt);
  2246. } else if (scp->cmd_len == 10) {
  2247. memcpy(&no, &scp->cmnd[2], sizeof(u32));
  2248. blockno = be32_to_cpu(no);
  2249. memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
  2250. blockcnt = be16_to_cpu(cnt);
  2251. } else {
  2252. memcpy(&no, &scp->cmnd[0], sizeof(u32));
  2253. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2254. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2255. }
  2256. if (mode64) {
  2257. cmdp->u.cache64.BlockNo = blockno;
  2258. cmdp->u.cache64.BlockCnt = blockcnt;
  2259. } else {
  2260. cmdp->u.cache.BlockNo = (u32)blockno;
  2261. cmdp->u.cache.BlockCnt = blockcnt;
  2262. }
  2263. if (scsi_bufflen(scp)) {
  2264. cmndinfo->dma_dir = (read_write == 1 ?
  2265. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2266. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2267. cmndinfo->dma_dir);
  2268. if (mode64) {
  2269. struct scatterlist *sl;
  2270. cmdp->u.cache64.DestAddr= (u64)-1;
  2271. cmdp->u.cache64.sg_canz = sgcnt;
  2272. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2273. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2274. #ifdef GDTH_DMA_STATISTICS
  2275. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2276. ha->dma64_cnt++;
  2277. else
  2278. ha->dma32_cnt++;
  2279. #endif
  2280. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2281. }
  2282. } else {
  2283. struct scatterlist *sl;
  2284. cmdp->u.cache.DestAddr= 0xffffffff;
  2285. cmdp->u.cache.sg_canz = sgcnt;
  2286. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2287. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2288. #ifdef GDTH_DMA_STATISTICS
  2289. ha->dma32_cnt++;
  2290. #endif
  2291. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2292. }
  2293. }
  2294. #ifdef GDTH_STATISTICS
  2295. if (max_sg < (u32)sgcnt) {
  2296. max_sg = (u32)sgcnt;
  2297. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2298. }
  2299. #endif
  2300. }
  2301. }
  2302. /* evaluate command size, check space */
  2303. if (mode64) {
  2304. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2305. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2306. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2307. cmdp->u.cache64.sg_lst[0].sg_len));
  2308. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2309. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2310. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2311. (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2312. } else {
  2313. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2314. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2315. cmdp->u.cache.sg_lst[0].sg_ptr,
  2316. cmdp->u.cache.sg_lst[0].sg_len));
  2317. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2318. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2319. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2320. (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2321. }
  2322. if (ha->cmd_len & 3)
  2323. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2324. if (ha->cmd_cnt > 0) {
  2325. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2326. ha->ic_all_size) {
  2327. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2328. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2329. return 0;
  2330. }
  2331. }
  2332. /* copy command */
  2333. gdth_copy_command(ha);
  2334. return cmd_index;
  2335. }
  2336. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b)
  2337. {
  2338. register gdth_cmd_str *cmdp;
  2339. u16 i;
  2340. dma_addr_t sense_paddr;
  2341. int cmd_index, sgcnt, mode64;
  2342. u8 t,l;
  2343. struct page *page;
  2344. unsigned long offset;
  2345. struct gdth_cmndinfo *cmndinfo;
  2346. t = scp->device->id;
  2347. l = scp->device->lun;
  2348. cmdp = ha->pccb;
  2349. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2350. scp->cmnd[0],b,t,l));
  2351. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2352. return 0;
  2353. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2354. cmdp->Service = SCSIRAWSERVICE;
  2355. cmdp->RequestBuffer = scp;
  2356. /* search free command index */
  2357. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2358. TRACE(("GDT: No free command index found\n"));
  2359. return 0;
  2360. }
  2361. /* if it's the first command, set command semaphore */
  2362. if (ha->cmd_cnt == 0)
  2363. gdth_set_sema0(ha);
  2364. cmndinfo = gdth_cmnd_priv(scp);
  2365. /* fill command */
  2366. if (cmndinfo->OpCode != -1) {
  2367. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2368. cmdp->BoardNode = LOCALBOARD;
  2369. if (mode64) {
  2370. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2371. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2372. cmdp->OpCode, cmdp->u.raw64.direction));
  2373. /* evaluate command size */
  2374. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2375. } else {
  2376. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2377. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2378. cmdp->OpCode, cmdp->u.raw.direction));
  2379. /* evaluate command size */
  2380. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2381. }
  2382. } else {
  2383. page = virt_to_page(scp->sense_buffer);
  2384. offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
  2385. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2386. 16,PCI_DMA_FROMDEVICE);
  2387. cmndinfo->sense_paddr = sense_paddr;
  2388. cmdp->OpCode = GDT_WRITE; /* always */
  2389. cmdp->BoardNode = LOCALBOARD;
  2390. if (mode64) {
  2391. cmdp->u.raw64.reserved = 0;
  2392. cmdp->u.raw64.mdisc_time = 0;
  2393. cmdp->u.raw64.mcon_time = 0;
  2394. cmdp->u.raw64.clen = scp->cmd_len;
  2395. cmdp->u.raw64.target = t;
  2396. cmdp->u.raw64.lun = l;
  2397. cmdp->u.raw64.bus = b;
  2398. cmdp->u.raw64.priority = 0;
  2399. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2400. cmdp->u.raw64.sense_len = 16;
  2401. cmdp->u.raw64.sense_data = sense_paddr;
  2402. cmdp->u.raw64.direction =
  2403. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2404. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2405. cmdp->u.raw64.sg_ranz = 0;
  2406. } else {
  2407. cmdp->u.raw.reserved = 0;
  2408. cmdp->u.raw.mdisc_time = 0;
  2409. cmdp->u.raw.mcon_time = 0;
  2410. cmdp->u.raw.clen = scp->cmd_len;
  2411. cmdp->u.raw.target = t;
  2412. cmdp->u.raw.lun = l;
  2413. cmdp->u.raw.bus = b;
  2414. cmdp->u.raw.priority = 0;
  2415. cmdp->u.raw.link_p = 0;
  2416. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2417. cmdp->u.raw.sense_len = 16;
  2418. cmdp->u.raw.sense_data = sense_paddr;
  2419. cmdp->u.raw.direction =
  2420. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2421. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2422. cmdp->u.raw.sg_ranz = 0;
  2423. }
  2424. if (scsi_bufflen(scp)) {
  2425. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2426. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2427. cmndinfo->dma_dir);
  2428. if (mode64) {
  2429. struct scatterlist *sl;
  2430. cmdp->u.raw64.sdata = (u64)-1;
  2431. cmdp->u.raw64.sg_ranz = sgcnt;
  2432. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2433. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2434. #ifdef GDTH_DMA_STATISTICS
  2435. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2436. ha->dma64_cnt++;
  2437. else
  2438. ha->dma32_cnt++;
  2439. #endif
  2440. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2441. }
  2442. } else {
  2443. struct scatterlist *sl;
  2444. cmdp->u.raw.sdata = 0xffffffff;
  2445. cmdp->u.raw.sg_ranz = sgcnt;
  2446. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2447. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2448. #ifdef GDTH_DMA_STATISTICS
  2449. ha->dma32_cnt++;
  2450. #endif
  2451. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2452. }
  2453. }
  2454. #ifdef GDTH_STATISTICS
  2455. if (max_sg < sgcnt) {
  2456. max_sg = sgcnt;
  2457. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2458. }
  2459. #endif
  2460. }
  2461. if (mode64) {
  2462. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2463. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2464. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2465. cmdp->u.raw64.sg_lst[0].sg_len));
  2466. /* evaluate command size */
  2467. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2468. (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2469. } else {
  2470. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2471. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2472. cmdp->u.raw.sg_lst[0].sg_ptr,
  2473. cmdp->u.raw.sg_lst[0].sg_len));
  2474. /* evaluate command size */
  2475. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2476. (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2477. }
  2478. }
  2479. /* check space */
  2480. if (ha->cmd_len & 3)
  2481. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2482. if (ha->cmd_cnt > 0) {
  2483. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2484. ha->ic_all_size) {
  2485. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2486. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2487. return 0;
  2488. }
  2489. }
  2490. /* copy command */
  2491. gdth_copy_command(ha);
  2492. return cmd_index;
  2493. }
  2494. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2495. {
  2496. register gdth_cmd_str *cmdp;
  2497. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2498. int cmd_index;
  2499. cmdp= ha->pccb;
  2500. TRACE2(("gdth_special_cmd(): "));
  2501. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2502. return 0;
  2503. *cmdp = *cmndinfo->internal_cmd_str;
  2504. cmdp->RequestBuffer = scp;
  2505. /* search free command index */
  2506. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2507. TRACE(("GDT: No free command index found\n"));
  2508. return 0;
  2509. }
  2510. /* if it's the first command, set command semaphore */
  2511. if (ha->cmd_cnt == 0)
  2512. gdth_set_sema0(ha);
  2513. /* evaluate command size, check space */
  2514. if (cmdp->OpCode == GDT_IOCTL) {
  2515. TRACE2(("IOCTL\n"));
  2516. ha->cmd_len =
  2517. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
  2518. } else if (cmdp->Service == CACHESERVICE) {
  2519. TRACE2(("cache command %d\n",cmdp->OpCode));
  2520. if (ha->cache_feat & GDT_64BIT)
  2521. ha->cmd_len =
  2522. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2523. else
  2524. ha->cmd_len =
  2525. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2526. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2527. TRACE2(("raw command %d\n",cmdp->OpCode));
  2528. if (ha->raw_feat & GDT_64BIT)
  2529. ha->cmd_len =
  2530. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2531. else
  2532. ha->cmd_len =
  2533. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2534. }
  2535. if (ha->cmd_len & 3)
  2536. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2537. if (ha->cmd_cnt > 0) {
  2538. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2539. ha->ic_all_size) {
  2540. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2541. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2542. return 0;
  2543. }
  2544. }
  2545. /* copy command */
  2546. gdth_copy_command(ha);
  2547. return cmd_index;
  2548. }
  2549. /* Controller event handling functions */
  2550. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  2551. u16 idx, gdth_evt_data *evt)
  2552. {
  2553. gdth_evt_str *e;
  2554. struct timeval tv;
  2555. /* no GDTH_LOCK_HA() ! */
  2556. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2557. if (source == 0) /* no source -> no event */
  2558. return NULL;
  2559. if (ebuffer[elastidx].event_source == source &&
  2560. ebuffer[elastidx].event_idx == idx &&
  2561. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2562. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2563. (char *)&evt->eu, evt->size)) ||
  2564. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2565. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2566. (char *)&evt->event_string)))) {
  2567. e = &ebuffer[elastidx];
  2568. do_gettimeofday(&tv);
  2569. e->last_stamp = tv.tv_sec;
  2570. ++e->same_count;
  2571. } else {
  2572. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2573. ++elastidx;
  2574. if (elastidx == MAX_EVENTS)
  2575. elastidx = 0;
  2576. if (elastidx == eoldidx) { /* reached mark ? */
  2577. ++eoldidx;
  2578. if (eoldidx == MAX_EVENTS)
  2579. eoldidx = 0;
  2580. }
  2581. }
  2582. e = &ebuffer[elastidx];
  2583. e->event_source = source;
  2584. e->event_idx = idx;
  2585. do_gettimeofday(&tv);
  2586. e->first_stamp = e->last_stamp = tv.tv_sec;
  2587. e->same_count = 1;
  2588. e->event_data = *evt;
  2589. e->application = 0;
  2590. }
  2591. return e;
  2592. }
  2593. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2594. {
  2595. gdth_evt_str *e;
  2596. int eindex;
  2597. unsigned long flags;
  2598. TRACE2(("gdth_read_event() handle %d\n", handle));
  2599. spin_lock_irqsave(&ha->smp_lock, flags);
  2600. if (handle == -1)
  2601. eindex = eoldidx;
  2602. else
  2603. eindex = handle;
  2604. estr->event_source = 0;
  2605. if (eindex < 0 || eindex >= MAX_EVENTS) {
  2606. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2607. return eindex;
  2608. }
  2609. e = &ebuffer[eindex];
  2610. if (e->event_source != 0) {
  2611. if (eindex != elastidx) {
  2612. if (++eindex == MAX_EVENTS)
  2613. eindex = 0;
  2614. } else {
  2615. eindex = -1;
  2616. }
  2617. memcpy(estr, e, sizeof(gdth_evt_str));
  2618. }
  2619. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2620. return eindex;
  2621. }
  2622. static void gdth_readapp_event(gdth_ha_str *ha,
  2623. u8 application, gdth_evt_str *estr)
  2624. {
  2625. gdth_evt_str *e;
  2626. int eindex;
  2627. unsigned long flags;
  2628. u8 found = FALSE;
  2629. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2630. spin_lock_irqsave(&ha->smp_lock, flags);
  2631. eindex = eoldidx;
  2632. for (;;) {
  2633. e = &ebuffer[eindex];
  2634. if (e->event_source == 0)
  2635. break;
  2636. if ((e->application & application) == 0) {
  2637. e->application |= application;
  2638. found = TRUE;
  2639. break;
  2640. }
  2641. if (eindex == elastidx)
  2642. break;
  2643. if (++eindex == MAX_EVENTS)
  2644. eindex = 0;
  2645. }
  2646. if (found)
  2647. memcpy(estr, e, sizeof(gdth_evt_str));
  2648. else
  2649. estr->event_source = 0;
  2650. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2651. }
  2652. static void gdth_clear_events(void)
  2653. {
  2654. TRACE(("gdth_clear_events()"));
  2655. eoldidx = elastidx = 0;
  2656. ebuffer[0].event_source = 0;
  2657. }
  2658. /* SCSI interface functions */
  2659. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2660. int gdth_from_wait, int* pIndex)
  2661. {
  2662. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2663. gdt6_dpram_str __iomem *dp6_ptr;
  2664. gdt2_dpram_str __iomem *dp2_ptr;
  2665. Scsi_Cmnd *scp;
  2666. int rval, i;
  2667. u8 IStatus;
  2668. u16 Service;
  2669. unsigned long flags = 0;
  2670. #ifdef INT_COAL
  2671. int coalesced = FALSE;
  2672. int next = FALSE;
  2673. gdth_coal_status *pcs = NULL;
  2674. int act_int_coal = 0;
  2675. #endif
  2676. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2677. /* if polling and not from gdth_wait() -> return */
  2678. if (gdth_polling) {
  2679. if (!gdth_from_wait) {
  2680. return IRQ_HANDLED;
  2681. }
  2682. }
  2683. if (!gdth_polling)
  2684. spin_lock_irqsave(&ha->smp_lock, flags);
  2685. /* search controller */
  2686. IStatus = gdth_get_status(ha);
  2687. if (IStatus == 0) {
  2688. /* spurious interrupt */
  2689. if (!gdth_polling)
  2690. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2691. return IRQ_HANDLED;
  2692. }
  2693. #ifdef GDTH_STATISTICS
  2694. ++act_ints;
  2695. #endif
  2696. #ifdef INT_COAL
  2697. /* See if the fw is returning coalesced status */
  2698. if (IStatus == COALINDEX) {
  2699. /* Coalesced status. Setup the initial status
  2700. buffer pointer and flags */
  2701. pcs = ha->coal_stat;
  2702. coalesced = TRUE;
  2703. next = TRUE;
  2704. }
  2705. do {
  2706. if (coalesced) {
  2707. /* For coalesced requests all status
  2708. information is found in the status buffer */
  2709. IStatus = (u8)(pcs->status & 0xff);
  2710. }
  2711. #endif
  2712. if (ha->type == GDT_EISA) {
  2713. if (IStatus & 0x80) { /* error flag */
  2714. IStatus &= ~0x80;
  2715. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2716. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2717. } else /* no error */
  2718. ha->status = S_OK;
  2719. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2720. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2721. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2722. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2723. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2724. } else if (ha->type == GDT_ISA) {
  2725. dp2_ptr = ha->brd;
  2726. if (IStatus & 0x80) { /* error flag */
  2727. IStatus &= ~0x80;
  2728. ha->status = readw(&dp2_ptr->u.ic.Status);
  2729. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2730. } else /* no error */
  2731. ha->status = S_OK;
  2732. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2733. ha->service = readw(&dp2_ptr->u.ic.Service);
  2734. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2735. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2736. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2737. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2738. } else if (ha->type == GDT_PCI) {
  2739. dp6_ptr = ha->brd;
  2740. if (IStatus & 0x80) { /* error flag */
  2741. IStatus &= ~0x80;
  2742. ha->status = readw(&dp6_ptr->u.ic.Status);
  2743. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2744. } else /* no error */
  2745. ha->status = S_OK;
  2746. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2747. ha->service = readw(&dp6_ptr->u.ic.Service);
  2748. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2749. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2750. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2751. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2752. } else if (ha->type == GDT_PCINEW) {
  2753. if (IStatus & 0x80) { /* error flag */
  2754. IStatus &= ~0x80;
  2755. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2756. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2757. } else
  2758. ha->status = S_OK;
  2759. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2760. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2761. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2762. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2763. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2764. } else if (ha->type == GDT_PCIMPR) {
  2765. dp6m_ptr = ha->brd;
  2766. if (IStatus & 0x80) { /* error flag */
  2767. IStatus &= ~0x80;
  2768. #ifdef INT_COAL
  2769. if (coalesced)
  2770. ha->status = pcs->ext_status & 0xffff;
  2771. else
  2772. #endif
  2773. ha->status = readw(&dp6m_ptr->i960r.status);
  2774. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2775. } else /* no error */
  2776. ha->status = S_OK;
  2777. #ifdef INT_COAL
  2778. /* get information */
  2779. if (coalesced) {
  2780. ha->info = pcs->info0;
  2781. ha->info2 = pcs->info1;
  2782. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2783. } else
  2784. #endif
  2785. {
  2786. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2787. ha->service = readw(&dp6m_ptr->i960r.service);
  2788. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2789. }
  2790. /* event string */
  2791. if (IStatus == ASYNCINDEX) {
  2792. if (ha->service != SCREENSERVICE &&
  2793. (ha->fw_vers & 0xff) >= 0x1a) {
  2794. ha->dvr.severity = readb
  2795. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2796. for (i = 0; i < 256; ++i) {
  2797. ha->dvr.event_string[i] = readb
  2798. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2799. if (ha->dvr.event_string[i] == 0)
  2800. break;
  2801. }
  2802. }
  2803. }
  2804. #ifdef INT_COAL
  2805. /* Make sure that non coalesced interrupts get cleared
  2806. before being handled by gdth_async_event/gdth_sync_event */
  2807. if (!coalesced)
  2808. #endif
  2809. {
  2810. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2811. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2812. }
  2813. } else {
  2814. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2815. if (!gdth_polling)
  2816. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2817. return IRQ_HANDLED;
  2818. }
  2819. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2820. IStatus,ha->status,ha->info));
  2821. if (gdth_from_wait) {
  2822. *pIndex = (int)IStatus;
  2823. }
  2824. if (IStatus == ASYNCINDEX) {
  2825. TRACE2(("gdth_interrupt() async. event\n"));
  2826. gdth_async_event(ha);
  2827. if (!gdth_polling)
  2828. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2829. gdth_next(ha);
  2830. return IRQ_HANDLED;
  2831. }
  2832. if (IStatus == SPEZINDEX) {
  2833. TRACE2(("Service unknown or not initialized !\n"));
  2834. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2835. ha->dvr.eu.driver.ionode = ha->hanum;
  2836. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2837. if (!gdth_polling)
  2838. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2839. return IRQ_HANDLED;
  2840. }
  2841. scp = ha->cmd_tab[IStatus-2].cmnd;
  2842. Service = ha->cmd_tab[IStatus-2].service;
  2843. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2844. if (scp == UNUSED_CMND) {
  2845. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2846. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2847. ha->dvr.eu.driver.ionode = ha->hanum;
  2848. ha->dvr.eu.driver.index = IStatus;
  2849. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2850. if (!gdth_polling)
  2851. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2852. return IRQ_HANDLED;
  2853. }
  2854. if (scp == INTERNAL_CMND) {
  2855. TRACE(("gdth_interrupt() answer to internal command\n"));
  2856. if (!gdth_polling)
  2857. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2858. return IRQ_HANDLED;
  2859. }
  2860. TRACE(("gdth_interrupt() sync. status\n"));
  2861. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2862. if (!gdth_polling)
  2863. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2864. if (rval == 2) {
  2865. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2866. } else if (rval == 1) {
  2867. gdth_scsi_done(scp);
  2868. }
  2869. #ifdef INT_COAL
  2870. if (coalesced) {
  2871. /* go to the next status in the status buffer */
  2872. ++pcs;
  2873. #ifdef GDTH_STATISTICS
  2874. ++act_int_coal;
  2875. if (act_int_coal > max_int_coal) {
  2876. max_int_coal = act_int_coal;
  2877. printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
  2878. }
  2879. #endif
  2880. /* see if there is another status */
  2881. if (pcs->status == 0)
  2882. /* Stop the coalesce loop */
  2883. next = FALSE;
  2884. }
  2885. } while (next);
  2886. /* coalescing only for new GDT_PCIMPR controllers available */
  2887. if (ha->type == GDT_PCIMPR && coalesced) {
  2888. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2889. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2890. }
  2891. #endif
  2892. gdth_next(ha);
  2893. return IRQ_HANDLED;
  2894. }
  2895. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2896. {
  2897. gdth_ha_str *ha = dev_id;
  2898. return __gdth_interrupt(ha, false, NULL);
  2899. }
  2900. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  2901. Scsi_Cmnd *scp)
  2902. {
  2903. gdth_msg_str *msg;
  2904. gdth_cmd_str *cmdp;
  2905. u8 b, t;
  2906. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2907. cmdp = ha->pccb;
  2908. TRACE(("gdth_sync_event() serv %d status %d\n",
  2909. service,ha->status));
  2910. if (service == SCREENSERVICE) {
  2911. msg = ha->pmsg;
  2912. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2913. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2914. if (msg->msg_len > MSGLEN+1)
  2915. msg->msg_len = MSGLEN+1;
  2916. if (msg->msg_len)
  2917. if (!(msg->msg_answer && msg->msg_ext)) {
  2918. msg->msg_text[msg->msg_len] = '\0';
  2919. printk("%s",msg->msg_text);
  2920. }
  2921. if (msg->msg_ext && !msg->msg_answer) {
  2922. while (gdth_test_busy(ha))
  2923. gdth_delay(0);
  2924. cmdp->Service = SCREENSERVICE;
  2925. cmdp->RequestBuffer = SCREEN_CMND;
  2926. gdth_get_cmd_index(ha);
  2927. gdth_set_sema0(ha);
  2928. cmdp->OpCode = GDT_READ;
  2929. cmdp->BoardNode = LOCALBOARD;
  2930. cmdp->u.screen.reserved = 0;
  2931. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2932. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2933. ha->cmd_offs_dpmem = 0;
  2934. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2935. + sizeof(u64);
  2936. ha->cmd_cnt = 0;
  2937. gdth_copy_command(ha);
  2938. gdth_release_event(ha);
  2939. return 0;
  2940. }
  2941. if (msg->msg_answer && msg->msg_alen) {
  2942. /* default answers (getchar() not possible) */
  2943. if (msg->msg_alen == 1) {
  2944. msg->msg_alen = 0;
  2945. msg->msg_len = 1;
  2946. msg->msg_text[0] = 0;
  2947. } else {
  2948. msg->msg_alen -= 2;
  2949. msg->msg_len = 2;
  2950. msg->msg_text[0] = 1;
  2951. msg->msg_text[1] = 0;
  2952. }
  2953. msg->msg_ext = 0;
  2954. msg->msg_answer = 0;
  2955. while (gdth_test_busy(ha))
  2956. gdth_delay(0);
  2957. cmdp->Service = SCREENSERVICE;
  2958. cmdp->RequestBuffer = SCREEN_CMND;
  2959. gdth_get_cmd_index(ha);
  2960. gdth_set_sema0(ha);
  2961. cmdp->OpCode = GDT_WRITE;
  2962. cmdp->BoardNode = LOCALBOARD;
  2963. cmdp->u.screen.reserved = 0;
  2964. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2965. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2966. ha->cmd_offs_dpmem = 0;
  2967. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2968. + sizeof(u64);
  2969. ha->cmd_cnt = 0;
  2970. gdth_copy_command(ha);
  2971. gdth_release_event(ha);
  2972. return 0;
  2973. }
  2974. printk("\n");
  2975. } else {
  2976. b = scp->device->channel;
  2977. t = scp->device->id;
  2978. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2979. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2980. }
  2981. /* cache or raw service */
  2982. if (ha->status == S_BSY) {
  2983. TRACE2(("Controller busy -> retry !\n"));
  2984. if (cmndinfo->OpCode == GDT_MOUNT)
  2985. cmndinfo->OpCode = GDT_CLUST_INFO;
  2986. /* retry */
  2987. return 2;
  2988. }
  2989. if (scsi_bufflen(scp))
  2990. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2991. cmndinfo->dma_dir);
  2992. if (cmndinfo->sense_paddr)
  2993. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  2994. PCI_DMA_FROMDEVICE);
  2995. if (ha->status == S_OK) {
  2996. cmndinfo->status = S_OK;
  2997. cmndinfo->info = ha->info;
  2998. if (cmndinfo->OpCode != -1) {
  2999. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3000. cmndinfo->OpCode));
  3001. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3002. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3003. ha->hdr[t].cluster_type = (u8)ha->info;
  3004. if (!(ha->hdr[t].cluster_type &
  3005. CLUSTER_MOUNTED)) {
  3006. /* NOT MOUNTED -> MOUNT */
  3007. cmndinfo->OpCode = GDT_MOUNT;
  3008. if (ha->hdr[t].cluster_type &
  3009. CLUSTER_RESERVED) {
  3010. /* cluster drive RESERVED (on the other node) */
  3011. cmndinfo->phase = -2; /* reservation conflict */
  3012. }
  3013. } else {
  3014. cmndinfo->OpCode = -1;
  3015. }
  3016. } else {
  3017. if (cmndinfo->OpCode == GDT_MOUNT) {
  3018. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3019. ha->hdr[t].media_changed = TRUE;
  3020. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3021. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3022. ha->hdr[t].media_changed = TRUE;
  3023. }
  3024. cmndinfo->OpCode = -1;
  3025. }
  3026. /* retry */
  3027. cmndinfo->priority = HIGH_PRI;
  3028. return 2;
  3029. } else {
  3030. /* RESERVE/RELEASE ? */
  3031. if (scp->cmnd[0] == RESERVE) {
  3032. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3033. } else if (scp->cmnd[0] == RELEASE) {
  3034. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3035. }
  3036. scp->result = DID_OK << 16;
  3037. scp->sense_buffer[0] = 0;
  3038. }
  3039. } else {
  3040. cmndinfo->status = ha->status;
  3041. cmndinfo->info = ha->info;
  3042. if (cmndinfo->OpCode != -1) {
  3043. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3044. cmndinfo->OpCode, ha->status));
  3045. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3046. cmndinfo->OpCode == GDT_SCAN_END) {
  3047. cmndinfo->OpCode = -1;
  3048. /* retry */
  3049. cmndinfo->priority = HIGH_PRI;
  3050. return 2;
  3051. }
  3052. memset((char*)scp->sense_buffer,0,16);
  3053. scp->sense_buffer[0] = 0x70;
  3054. scp->sense_buffer[2] = NOT_READY;
  3055. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3056. } else if (service == CACHESERVICE) {
  3057. if (ha->status == S_CACHE_UNKNOWN &&
  3058. (ha->hdr[t].cluster_type &
  3059. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3060. /* bus reset -> force GDT_CLUST_INFO */
  3061. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3062. }
  3063. memset((char*)scp->sense_buffer,0,16);
  3064. if (ha->status == (u16)S_CACHE_RESERV) {
  3065. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3066. } else {
  3067. scp->sense_buffer[0] = 0x70;
  3068. scp->sense_buffer[2] = NOT_READY;
  3069. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3070. }
  3071. if (!cmndinfo->internal_command) {
  3072. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3073. ha->dvr.eu.sync.ionode = ha->hanum;
  3074. ha->dvr.eu.sync.service = service;
  3075. ha->dvr.eu.sync.status = ha->status;
  3076. ha->dvr.eu.sync.info = ha->info;
  3077. ha->dvr.eu.sync.hostdrive = t;
  3078. if (ha->status >= 0x8000)
  3079. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3080. else
  3081. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3082. }
  3083. } else {
  3084. /* sense buffer filled from controller firmware (DMA) */
  3085. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3086. scp->result = DID_BAD_TARGET << 16;
  3087. } else {
  3088. scp->result = (DID_OK << 16) | ha->info;
  3089. }
  3090. }
  3091. }
  3092. if (!cmndinfo->wait_for_completion)
  3093. cmndinfo->wait_for_completion++;
  3094. else
  3095. return 1;
  3096. }
  3097. return 0;
  3098. }
  3099. static char *async_cache_tab[] = {
  3100. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3101. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3102. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3103. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3104. /* 2*/ "\005\000\002\006\004"
  3105. "GDT HA %u, Host Drive %lu not ready",
  3106. /* 3*/ "\005\000\002\006\004"
  3107. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3108. /* 4*/ "\005\000\002\006\004"
  3109. "GDT HA %u, mirror update on Host Drive %lu failed",
  3110. /* 5*/ "\005\000\002\006\004"
  3111. "GDT HA %u, Mirror Drive %lu failed",
  3112. /* 6*/ "\005\000\002\006\004"
  3113. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3114. /* 7*/ "\005\000\002\006\004"
  3115. "GDT HA %u, Host Drive %lu write protected",
  3116. /* 8*/ "\005\000\002\006\004"
  3117. "GDT HA %u, media changed in Host Drive %lu",
  3118. /* 9*/ "\005\000\002\006\004"
  3119. "GDT HA %u, Host Drive %lu is offline",
  3120. /*10*/ "\005\000\002\006\004"
  3121. "GDT HA %u, media change of Mirror Drive %lu",
  3122. /*11*/ "\005\000\002\006\004"
  3123. "GDT HA %u, Mirror Drive %lu is write protected",
  3124. /*12*/ "\005\000\002\006\004"
  3125. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3126. /*13*/ "\007\000\002\006\002\010\002"
  3127. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3128. /*14*/ "\005\000\002\006\002"
  3129. "GDT HA %u, Array Drive %u: FAIL state entered",
  3130. /*15*/ "\005\000\002\006\002"
  3131. "GDT HA %u, Array Drive %u: error",
  3132. /*16*/ "\007\000\002\006\002\010\002"
  3133. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3134. /*17*/ "\005\000\002\006\002"
  3135. "GDT HA %u, Array Drive %u: parity build failed",
  3136. /*18*/ "\005\000\002\006\002"
  3137. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3138. /*19*/ "\005\000\002\010\002"
  3139. "GDT HA %u, Test of Hot Fix %u failed",
  3140. /*20*/ "\005\000\002\006\002"
  3141. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3142. /*21*/ "\005\000\002\006\002"
  3143. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3144. /*22*/ "\007\000\002\006\002\010\002"
  3145. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3146. /*23*/ "\005\000\002\006\002"
  3147. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3148. /*24*/ "\005\000\002\010\002"
  3149. "GDT HA %u, mirror update on Cache Drive %u completed",
  3150. /*25*/ "\005\000\002\010\002"
  3151. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3152. /*26*/ "\005\000\002\006\002"
  3153. "GDT HA %u, Array Drive %u: drive rebuild started",
  3154. /*27*/ "\005\000\002\012\001"
  3155. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3156. /*28*/ "\005\000\002\012\001"
  3157. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3158. /*29*/ "\007\000\002\012\001\013\001"
  3159. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3160. /*30*/ "\007\000\002\012\001\013\001"
  3161. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3162. /*31*/ "\007\000\002\012\001\013\001"
  3163. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3164. /*32*/ "\007\000\002\012\001\013\001"
  3165. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3166. /*33*/ "\007\000\002\012\001\013\001"
  3167. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3168. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3169. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3170. /*35*/ "\007\000\002\012\001\013\001"
  3171. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3172. /*36*/ "\007\000\002\012\001\013\001"
  3173. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3174. /*37*/ "\007\000\002\012\001\006\004"
  3175. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3176. /*38*/ "\007\000\002\012\001\013\001"
  3177. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3178. /*39*/ "\007\000\002\012\001\013\001"
  3179. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3180. /*40*/ "\007\000\002\012\001\013\001"
  3181. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3182. /*41*/ "\007\000\002\012\001\013\001"
  3183. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3184. /*42*/ "\005\000\002\006\002"
  3185. "GDT HA %u, Array Drive %u: drive build started",
  3186. /*43*/ "\003\000\002"
  3187. "GDT HA %u, DRAM parity error detected",
  3188. /*44*/ "\005\000\002\006\002"
  3189. "GDT HA %u, Mirror Drive %u: update started",
  3190. /*45*/ "\007\000\002\006\002\010\002"
  3191. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3192. /*46*/ "\005\000\002\006\002"
  3193. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3194. /*47*/ "\005\000\002\006\002"
  3195. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3196. /*48*/ "\005\000\002\006\002"
  3197. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3198. /*49*/ "\005\000\002\006\002"
  3199. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3200. /*50*/ "\007\000\002\012\001\013\001"
  3201. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3202. /*51*/ "\005\000\002\006\002"
  3203. "GDT HA %u, Array Drive %u: expand started",
  3204. /*52*/ "\005\000\002\006\002"
  3205. "GDT HA %u, Array Drive %u: expand finished successfully",
  3206. /*53*/ "\005\000\002\006\002"
  3207. "GDT HA %u, Array Drive %u: expand failed",
  3208. /*54*/ "\003\000\002"
  3209. "GDT HA %u, CPU temperature critical",
  3210. /*55*/ "\003\000\002"
  3211. "GDT HA %u, CPU temperature OK",
  3212. /*56*/ "\005\000\002\006\004"
  3213. "GDT HA %u, Host drive %lu created",
  3214. /*57*/ "\005\000\002\006\002"
  3215. "GDT HA %u, Array Drive %u: expand restarted",
  3216. /*58*/ "\005\000\002\006\002"
  3217. "GDT HA %u, Array Drive %u: expand stopped",
  3218. /*59*/ "\005\000\002\010\002"
  3219. "GDT HA %u, Mirror Drive %u: drive build quited",
  3220. /*60*/ "\005\000\002\006\002"
  3221. "GDT HA %u, Array Drive %u: parity build quited",
  3222. /*61*/ "\005\000\002\006\002"
  3223. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3224. /*62*/ "\005\000\002\006\002"
  3225. "GDT HA %u, Array Drive %u: parity verify started",
  3226. /*63*/ "\005\000\002\006\002"
  3227. "GDT HA %u, Array Drive %u: parity verify done",
  3228. /*64*/ "\005\000\002\006\002"
  3229. "GDT HA %u, Array Drive %u: parity verify failed",
  3230. /*65*/ "\005\000\002\006\002"
  3231. "GDT HA %u, Array Drive %u: parity error detected",
  3232. /*66*/ "\005\000\002\006\002"
  3233. "GDT HA %u, Array Drive %u: parity verify quited",
  3234. /*67*/ "\005\000\002\006\002"
  3235. "GDT HA %u, Host Drive %u reserved",
  3236. /*68*/ "\005\000\002\006\002"
  3237. "GDT HA %u, Host Drive %u mounted and released",
  3238. /*69*/ "\005\000\002\006\002"
  3239. "GDT HA %u, Host Drive %u released",
  3240. /*70*/ "\003\000\002"
  3241. "GDT HA %u, DRAM error detected and corrected with ECC",
  3242. /*71*/ "\003\000\002"
  3243. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3244. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3245. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3246. /*73*/ "\005\000\002\006\002"
  3247. "GDT HA %u, Host drive %u resetted locally",
  3248. /*74*/ "\005\000\002\006\002"
  3249. "GDT HA %u, Host drive %u resetted remotely",
  3250. /*75*/ "\003\000\002"
  3251. "GDT HA %u, async. status 75 unknown",
  3252. };
  3253. static int gdth_async_event(gdth_ha_str *ha)
  3254. {
  3255. gdth_cmd_str *cmdp;
  3256. int cmd_index;
  3257. cmdp= ha->pccb;
  3258. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3259. ha->hanum, ha->service));
  3260. if (ha->service == SCREENSERVICE) {
  3261. if (ha->status == MSG_REQUEST) {
  3262. while (gdth_test_busy(ha))
  3263. gdth_delay(0);
  3264. cmdp->Service = SCREENSERVICE;
  3265. cmdp->RequestBuffer = SCREEN_CMND;
  3266. cmd_index = gdth_get_cmd_index(ha);
  3267. gdth_set_sema0(ha);
  3268. cmdp->OpCode = GDT_READ;
  3269. cmdp->BoardNode = LOCALBOARD;
  3270. cmdp->u.screen.reserved = 0;
  3271. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3272. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3273. ha->cmd_offs_dpmem = 0;
  3274. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3275. + sizeof(u64);
  3276. ha->cmd_cnt = 0;
  3277. gdth_copy_command(ha);
  3278. if (ha->type == GDT_EISA)
  3279. printk("[EISA slot %d] ",(u16)ha->brd_phys);
  3280. else if (ha->type == GDT_ISA)
  3281. printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
  3282. else
  3283. printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
  3284. (u16)((ha->brd_phys>>3)&0x1f));
  3285. gdth_release_event(ha);
  3286. }
  3287. } else {
  3288. if (ha->type == GDT_PCIMPR &&
  3289. (ha->fw_vers & 0xff) >= 0x1a) {
  3290. ha->dvr.size = 0;
  3291. ha->dvr.eu.async.ionode = ha->hanum;
  3292. ha->dvr.eu.async.status = ha->status;
  3293. /* severity and event_string already set! */
  3294. } else {
  3295. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3296. ha->dvr.eu.async.ionode = ha->hanum;
  3297. ha->dvr.eu.async.service = ha->service;
  3298. ha->dvr.eu.async.status = ha->status;
  3299. ha->dvr.eu.async.info = ha->info;
  3300. *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3301. }
  3302. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3303. gdth_log_event( &ha->dvr, NULL );
  3304. /* new host drive from expand? */
  3305. if (ha->service == CACHESERVICE && ha->status == 56) {
  3306. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3307. (u16)ha->info));
  3308. /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
  3309. }
  3310. }
  3311. return 1;
  3312. }
  3313. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3314. {
  3315. gdth_stackframe stack;
  3316. char *f = NULL;
  3317. int i,j;
  3318. TRACE2(("gdth_log_event()\n"));
  3319. if (dvr->size == 0) {
  3320. if (buffer == NULL) {
  3321. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3322. } else {
  3323. sprintf(buffer,"Adapter %d: %s\n",
  3324. dvr->eu.async.ionode,dvr->event_string);
  3325. }
  3326. } else if (dvr->eu.async.service == CACHESERVICE &&
  3327. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3328. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3329. dvr->eu.async.status));
  3330. f = async_cache_tab[dvr->eu.async.status];
  3331. /* i: parameter to push, j: stack element to fill */
  3332. for (j=0,i=1; i < f[0]; i+=2) {
  3333. switch (f[i+1]) {
  3334. case 4:
  3335. stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
  3336. break;
  3337. case 2:
  3338. stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
  3339. break;
  3340. case 1:
  3341. stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
  3342. break;
  3343. default:
  3344. break;
  3345. }
  3346. }
  3347. if (buffer == NULL) {
  3348. printk(&f[(int)f[0]],stack);
  3349. printk("\n");
  3350. } else {
  3351. sprintf(buffer,&f[(int)f[0]],stack);
  3352. }
  3353. } else {
  3354. if (buffer == NULL) {
  3355. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3356. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3357. } else {
  3358. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3359. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3360. }
  3361. }
  3362. }
  3363. #ifdef GDTH_STATISTICS
  3364. static u8 gdth_timer_running;
  3365. static void gdth_timeout(unsigned long data)
  3366. {
  3367. u32 i;
  3368. Scsi_Cmnd *nscp;
  3369. gdth_ha_str *ha;
  3370. unsigned long flags;
  3371. if(unlikely(list_empty(&gdth_instances))) {
  3372. gdth_timer_running = 0;
  3373. return;
  3374. }
  3375. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3376. spin_lock_irqsave(&ha->smp_lock, flags);
  3377. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3378. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3379. ++act_stats;
  3380. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3381. ++act_rq;
  3382. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3383. act_ints, act_ios, act_stats, act_rq));
  3384. act_ints = act_ios = 0;
  3385. gdth_timer.expires = jiffies + 30 * HZ;
  3386. add_timer(&gdth_timer);
  3387. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3388. }
  3389. static void gdth_timer_init(void)
  3390. {
  3391. if (gdth_timer_running)
  3392. return;
  3393. gdth_timer_running = 1;
  3394. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3395. gdth_timer.expires = jiffies + HZ;
  3396. gdth_timer.data = 0L;
  3397. gdth_timer.function = gdth_timeout;
  3398. add_timer(&gdth_timer);
  3399. }
  3400. #else
  3401. static inline void gdth_timer_init(void)
  3402. {
  3403. }
  3404. #endif
  3405. static void __init internal_setup(char *str,int *ints)
  3406. {
  3407. int i, argc;
  3408. char *cur_str, *argv;
  3409. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3410. str ? str:"NULL", ints ? ints[0]:0));
  3411. /* read irq[] from ints[] */
  3412. if (ints) {
  3413. argc = ints[0];
  3414. if (argc > 0) {
  3415. if (argc > MAXHA)
  3416. argc = MAXHA;
  3417. for (i = 0; i < argc; ++i)
  3418. irq[i] = ints[i+1];
  3419. }
  3420. }
  3421. /* analyse string */
  3422. argv = str;
  3423. while (argv && (cur_str = strchr(argv, ':'))) {
  3424. int val = 0, c = *++cur_str;
  3425. if (c == 'n' || c == 'N')
  3426. val = 0;
  3427. else if (c == 'y' || c == 'Y')
  3428. val = 1;
  3429. else
  3430. val = (int)simple_strtoul(cur_str, NULL, 0);
  3431. if (!strncmp(argv, "disable:", 8))
  3432. disable = val;
  3433. else if (!strncmp(argv, "reserve_mode:", 13))
  3434. reserve_mode = val;
  3435. else if (!strncmp(argv, "reverse_scan:", 13))
  3436. reverse_scan = val;
  3437. else if (!strncmp(argv, "hdr_channel:", 12))
  3438. hdr_channel = val;
  3439. else if (!strncmp(argv, "max_ids:", 8))
  3440. max_ids = val;
  3441. else if (!strncmp(argv, "rescan:", 7))
  3442. rescan = val;
  3443. else if (!strncmp(argv, "shared_access:", 14))
  3444. shared_access = val;
  3445. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3446. probe_eisa_isa = val;
  3447. else if (!strncmp(argv, "reserve_list:", 13)) {
  3448. reserve_list[0] = val;
  3449. for (i = 1; i < MAX_RES_ARGS; i++) {
  3450. cur_str = strchr(cur_str, ',');
  3451. if (!cur_str)
  3452. break;
  3453. if (!isdigit((int)*++cur_str)) {
  3454. --cur_str;
  3455. break;
  3456. }
  3457. reserve_list[i] =
  3458. (int)simple_strtoul(cur_str, NULL, 0);
  3459. }
  3460. if (!cur_str)
  3461. break;
  3462. argv = ++cur_str;
  3463. continue;
  3464. }
  3465. if ((argv = strchr(argv, ',')))
  3466. ++argv;
  3467. }
  3468. }
  3469. int __init option_setup(char *str)
  3470. {
  3471. int ints[MAXHA];
  3472. char *cur = str;
  3473. int i = 1;
  3474. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3475. while (cur && isdigit(*cur) && i < MAXHA) {
  3476. ints[i++] = simple_strtoul(cur, NULL, 0);
  3477. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3478. }
  3479. ints[0] = i - 1;
  3480. internal_setup(cur, ints);
  3481. return 1;
  3482. }
  3483. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3484. {
  3485. TRACE2(("gdth_ctr_name()\n"));
  3486. if (ha->type == GDT_EISA) {
  3487. switch (ha->stype) {
  3488. case GDT3_ID:
  3489. return("GDT3000/3020");
  3490. case GDT3A_ID:
  3491. return("GDT3000A/3020A/3050A");
  3492. case GDT3B_ID:
  3493. return("GDT3000B/3010A");
  3494. }
  3495. } else if (ha->type == GDT_ISA) {
  3496. return("GDT2000/2020");
  3497. } else if (ha->type == GDT_PCI) {
  3498. switch (ha->pdev->device) {
  3499. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3500. return("GDT6000/6020/6050");
  3501. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3502. return("GDT6000B/6010");
  3503. }
  3504. }
  3505. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3506. return("");
  3507. }
  3508. static const char *gdth_info(struct Scsi_Host *shp)
  3509. {
  3510. gdth_ha_str *ha = shost_priv(shp);
  3511. TRACE2(("gdth_info()\n"));
  3512. return ((const char *)ha->binfo.type_string);
  3513. }
  3514. static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
  3515. {
  3516. gdth_ha_str *ha = shost_priv(scp->device->host);
  3517. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  3518. u8 b, t;
  3519. unsigned long flags;
  3520. enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
  3521. TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
  3522. b = scp->device->channel;
  3523. t = scp->device->id;
  3524. /*
  3525. * We don't really honor the command timeout, but we try to
  3526. * honor 6 times of the actual command timeout! So reset the
  3527. * timer if this is less than 6th timeout on this command!
  3528. */
  3529. if (++cmndinfo->timeout_count < 6)
  3530. retval = BLK_EH_RESET_TIMER;
  3531. /* Reset the timeout if it is locked IO */
  3532. spin_lock_irqsave(&ha->smp_lock, flags);
  3533. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
  3534. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  3535. TRACE2(("%s(): locked IO, reset timeout\n", __func__));
  3536. retval = BLK_EH_RESET_TIMER;
  3537. }
  3538. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3539. return retval;
  3540. }
  3541. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3542. {
  3543. gdth_ha_str *ha = shost_priv(scp->device->host);
  3544. int i;
  3545. unsigned long flags;
  3546. Scsi_Cmnd *cmnd;
  3547. u8 b;
  3548. TRACE2(("gdth_eh_bus_reset()\n"));
  3549. b = scp->device->channel;
  3550. /* clear command tab */
  3551. spin_lock_irqsave(&ha->smp_lock, flags);
  3552. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3553. cmnd = ha->cmd_tab[i].cmnd;
  3554. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3555. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3556. }
  3557. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3558. if (b == ha->virt_bus) {
  3559. /* host drives */
  3560. for (i = 0; i < MAX_HDRIVES; ++i) {
  3561. if (ha->hdr[i].present) {
  3562. spin_lock_irqsave(&ha->smp_lock, flags);
  3563. gdth_polling = TRUE;
  3564. while (gdth_test_busy(ha))
  3565. gdth_delay(0);
  3566. if (gdth_internal_cmd(ha, CACHESERVICE,
  3567. GDT_CLUST_RESET, i, 0, 0))
  3568. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3569. gdth_polling = FALSE;
  3570. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3571. }
  3572. }
  3573. } else {
  3574. /* raw devices */
  3575. spin_lock_irqsave(&ha->smp_lock, flags);
  3576. for (i = 0; i < MAXID; ++i)
  3577. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3578. gdth_polling = TRUE;
  3579. while (gdth_test_busy(ha))
  3580. gdth_delay(0);
  3581. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3582. BUS_L2P(ha,b), 0, 0);
  3583. gdth_polling = FALSE;
  3584. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3585. }
  3586. return SUCCESS;
  3587. }
  3588. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3589. {
  3590. u8 b, t;
  3591. gdth_ha_str *ha = shost_priv(sdev->host);
  3592. struct scsi_device *sd;
  3593. unsigned capacity;
  3594. sd = sdev;
  3595. capacity = cap;
  3596. b = sd->channel;
  3597. t = sd->id;
  3598. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3599. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3600. /* raw device or host drive without mapping information */
  3601. TRACE2(("Evaluate mapping\n"));
  3602. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3603. } else {
  3604. ip[0] = ha->hdr[t].heads;
  3605. ip[1] = ha->hdr[t].secs;
  3606. ip[2] = capacity / ip[0] / ip[1];
  3607. }
  3608. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3609. ip[0],ip[1],ip[2]));
  3610. return 0;
  3611. }
  3612. static int gdth_queuecommand_lck(struct scsi_cmnd *scp,
  3613. void (*done)(struct scsi_cmnd *))
  3614. {
  3615. gdth_ha_str *ha = shost_priv(scp->device->host);
  3616. struct gdth_cmndinfo *cmndinfo;
  3617. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3618. cmndinfo = gdth_get_cmndinfo(ha);
  3619. BUG_ON(!cmndinfo);
  3620. scp->scsi_done = done;
  3621. cmndinfo->timeout_count = 0;
  3622. cmndinfo->priority = DEFAULT_PRI;
  3623. return __gdth_queuecommand(ha, scp, cmndinfo);
  3624. }
  3625. static DEF_SCSI_QCMD(gdth_queuecommand)
  3626. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3627. struct gdth_cmndinfo *cmndinfo)
  3628. {
  3629. scp->host_scribble = (unsigned char *)cmndinfo;
  3630. cmndinfo->wait_for_completion = 1;
  3631. cmndinfo->phase = -1;
  3632. cmndinfo->OpCode = -1;
  3633. #ifdef GDTH_STATISTICS
  3634. ++act_ios;
  3635. #endif
  3636. gdth_putq(ha, scp, cmndinfo->priority);
  3637. gdth_next(ha);
  3638. return 0;
  3639. }
  3640. static int gdth_open(struct inode *inode, struct file *filep)
  3641. {
  3642. gdth_ha_str *ha;
  3643. mutex_lock(&gdth_mutex);
  3644. list_for_each_entry(ha, &gdth_instances, list) {
  3645. if (!ha->sdev)
  3646. ha->sdev = scsi_get_host_dev(ha->shost);
  3647. }
  3648. mutex_unlock(&gdth_mutex);
  3649. TRACE(("gdth_open()\n"));
  3650. return 0;
  3651. }
  3652. static int gdth_close(struct inode *inode, struct file *filep)
  3653. {
  3654. TRACE(("gdth_close()\n"));
  3655. return 0;
  3656. }
  3657. static int ioc_event(void __user *arg)
  3658. {
  3659. gdth_ioctl_event evt;
  3660. gdth_ha_str *ha;
  3661. unsigned long flags;
  3662. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3663. return -EFAULT;
  3664. ha = gdth_find_ha(evt.ionode);
  3665. if (!ha)
  3666. return -EFAULT;
  3667. if (evt.erase == 0xff) {
  3668. if (evt.event.event_source == ES_TEST)
  3669. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3670. else if (evt.event.event_source == ES_DRIVER)
  3671. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3672. else if (evt.event.event_source == ES_SYNC)
  3673. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3674. else
  3675. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3676. spin_lock_irqsave(&ha->smp_lock, flags);
  3677. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3678. &evt.event.event_data);
  3679. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3680. } else if (evt.erase == 0xfe) {
  3681. gdth_clear_events();
  3682. } else if (evt.erase == 0) {
  3683. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3684. } else {
  3685. gdth_readapp_event(ha, evt.erase, &evt.event);
  3686. }
  3687. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3688. return -EFAULT;
  3689. return 0;
  3690. }
  3691. static int ioc_lockdrv(void __user *arg)
  3692. {
  3693. gdth_ioctl_lockdrv ldrv;
  3694. u8 i, j;
  3695. unsigned long flags;
  3696. gdth_ha_str *ha;
  3697. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3698. return -EFAULT;
  3699. ha = gdth_find_ha(ldrv.ionode);
  3700. if (!ha)
  3701. return -EFAULT;
  3702. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3703. j = ldrv.drives[i];
  3704. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3705. continue;
  3706. if (ldrv.lock) {
  3707. spin_lock_irqsave(&ha->smp_lock, flags);
  3708. ha->hdr[j].lock = 1;
  3709. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3710. gdth_wait_completion(ha, ha->bus_cnt, j);
  3711. } else {
  3712. spin_lock_irqsave(&ha->smp_lock, flags);
  3713. ha->hdr[j].lock = 0;
  3714. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3715. gdth_next(ha);
  3716. }
  3717. }
  3718. return 0;
  3719. }
  3720. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3721. {
  3722. gdth_ioctl_reset res;
  3723. gdth_cmd_str cmd;
  3724. gdth_ha_str *ha;
  3725. int rval;
  3726. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3727. res.number >= MAX_HDRIVES)
  3728. return -EFAULT;
  3729. ha = gdth_find_ha(res.ionode);
  3730. if (!ha)
  3731. return -EFAULT;
  3732. if (!ha->hdr[res.number].present)
  3733. return 0;
  3734. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3735. cmd.Service = CACHESERVICE;
  3736. cmd.OpCode = GDT_CLUST_RESET;
  3737. if (ha->cache_feat & GDT_64BIT)
  3738. cmd.u.cache64.DeviceNo = res.number;
  3739. else
  3740. cmd.u.cache.DeviceNo = res.number;
  3741. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3742. if (rval < 0)
  3743. return rval;
  3744. res.status = rval;
  3745. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3746. return -EFAULT;
  3747. return 0;
  3748. }
  3749. static int ioc_general(void __user *arg, char *cmnd)
  3750. {
  3751. gdth_ioctl_general gen;
  3752. char *buf = NULL;
  3753. u64 paddr;
  3754. gdth_ha_str *ha;
  3755. int rval;
  3756. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3757. return -EFAULT;
  3758. ha = gdth_find_ha(gen.ionode);
  3759. if (!ha)
  3760. return -EFAULT;
  3761. if (gen.data_len > INT_MAX)
  3762. return -EINVAL;
  3763. if (gen.sense_len > INT_MAX)
  3764. return -EINVAL;
  3765. if (gen.data_len + gen.sense_len > INT_MAX)
  3766. return -EINVAL;
  3767. if (gen.data_len + gen.sense_len != 0) {
  3768. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3769. FALSE, &paddr)))
  3770. return -EFAULT;
  3771. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3772. gen.data_len + gen.sense_len)) {
  3773. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3774. return -EFAULT;
  3775. }
  3776. if (gen.command.OpCode == GDT_IOCTL) {
  3777. gen.command.u.ioctl.p_param = paddr;
  3778. } else if (gen.command.Service == CACHESERVICE) {
  3779. if (ha->cache_feat & GDT_64BIT) {
  3780. /* copy elements from 32-bit IOCTL structure */
  3781. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3782. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3783. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3784. /* addresses */
  3785. if (ha->cache_feat & SCATTER_GATHER) {
  3786. gen.command.u.cache64.DestAddr = (u64)-1;
  3787. gen.command.u.cache64.sg_canz = 1;
  3788. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3789. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3790. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3791. } else {
  3792. gen.command.u.cache64.DestAddr = paddr;
  3793. gen.command.u.cache64.sg_canz = 0;
  3794. }
  3795. } else {
  3796. if (ha->cache_feat & SCATTER_GATHER) {
  3797. gen.command.u.cache.DestAddr = 0xffffffff;
  3798. gen.command.u.cache.sg_canz = 1;
  3799. gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
  3800. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3801. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3802. } else {
  3803. gen.command.u.cache.DestAddr = paddr;
  3804. gen.command.u.cache.sg_canz = 0;
  3805. }
  3806. }
  3807. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3808. if (ha->raw_feat & GDT_64BIT) {
  3809. /* copy elements from 32-bit IOCTL structure */
  3810. char cmd[16];
  3811. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3812. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3813. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3814. gen.command.u.raw64.target = gen.command.u.raw.target;
  3815. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3816. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3817. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3818. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3819. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3820. /* addresses */
  3821. if (ha->raw_feat & SCATTER_GATHER) {
  3822. gen.command.u.raw64.sdata = (u64)-1;
  3823. gen.command.u.raw64.sg_ranz = 1;
  3824. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3825. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3826. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3827. } else {
  3828. gen.command.u.raw64.sdata = paddr;
  3829. gen.command.u.raw64.sg_ranz = 0;
  3830. }
  3831. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3832. } else {
  3833. if (ha->raw_feat & SCATTER_GATHER) {
  3834. gen.command.u.raw.sdata = 0xffffffff;
  3835. gen.command.u.raw.sg_ranz = 1;
  3836. gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
  3837. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3838. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3839. } else {
  3840. gen.command.u.raw.sdata = paddr;
  3841. gen.command.u.raw.sg_ranz = 0;
  3842. }
  3843. gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
  3844. }
  3845. } else {
  3846. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3847. return -EFAULT;
  3848. }
  3849. }
  3850. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3851. if (rval < 0) {
  3852. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3853. return rval;
  3854. }
  3855. gen.status = rval;
  3856. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3857. gen.data_len + gen.sense_len)) {
  3858. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3859. return -EFAULT;
  3860. }
  3861. if (copy_to_user(arg, &gen,
  3862. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3863. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3864. return -EFAULT;
  3865. }
  3866. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3867. return 0;
  3868. }
  3869. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3870. {
  3871. gdth_ioctl_rescan *rsc;
  3872. gdth_cmd_str *cmd;
  3873. gdth_ha_str *ha;
  3874. u8 i;
  3875. int rc = -ENOMEM;
  3876. u32 cluster_type = 0;
  3877. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3878. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3879. if (!rsc || !cmd)
  3880. goto free_fail;
  3881. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3882. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3883. rc = -EFAULT;
  3884. goto free_fail;
  3885. }
  3886. memset(cmd, 0, sizeof(gdth_cmd_str));
  3887. for (i = 0; i < MAX_HDRIVES; ++i) {
  3888. if (!ha->hdr[i].present) {
  3889. rsc->hdr_list[i].bus = 0xff;
  3890. continue;
  3891. }
  3892. rsc->hdr_list[i].bus = ha->virt_bus;
  3893. rsc->hdr_list[i].target = i;
  3894. rsc->hdr_list[i].lun = 0;
  3895. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3896. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3897. cmd->Service = CACHESERVICE;
  3898. cmd->OpCode = GDT_CLUST_INFO;
  3899. if (ha->cache_feat & GDT_64BIT)
  3900. cmd->u.cache64.DeviceNo = i;
  3901. else
  3902. cmd->u.cache.DeviceNo = i;
  3903. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3904. rsc->hdr_list[i].cluster_type = cluster_type;
  3905. }
  3906. }
  3907. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3908. rc = -EFAULT;
  3909. else
  3910. rc = 0;
  3911. free_fail:
  3912. kfree(rsc);
  3913. kfree(cmd);
  3914. return rc;
  3915. }
  3916. static int ioc_rescan(void __user *arg, char *cmnd)
  3917. {
  3918. gdth_ioctl_rescan *rsc;
  3919. gdth_cmd_str *cmd;
  3920. u16 i, status, hdr_cnt;
  3921. u32 info;
  3922. int cyls, hds, secs;
  3923. int rc = -ENOMEM;
  3924. unsigned long flags;
  3925. gdth_ha_str *ha;
  3926. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3927. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3928. if (!cmd || !rsc)
  3929. goto free_fail;
  3930. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3931. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3932. rc = -EFAULT;
  3933. goto free_fail;
  3934. }
  3935. memset(cmd, 0, sizeof(gdth_cmd_str));
  3936. if (rsc->flag == 0) {
  3937. /* old method: re-init. cache service */
  3938. cmd->Service = CACHESERVICE;
  3939. if (ha->cache_feat & GDT_64BIT) {
  3940. cmd->OpCode = GDT_X_INIT_HOST;
  3941. cmd->u.cache64.DeviceNo = LINUX_OS;
  3942. } else {
  3943. cmd->OpCode = GDT_INIT;
  3944. cmd->u.cache.DeviceNo = LINUX_OS;
  3945. }
  3946. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3947. i = 0;
  3948. hdr_cnt = (status == S_OK ? (u16)info : 0);
  3949. } else {
  3950. i = rsc->hdr_no;
  3951. hdr_cnt = i + 1;
  3952. }
  3953. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3954. cmd->Service = CACHESERVICE;
  3955. cmd->OpCode = GDT_INFO;
  3956. if (ha->cache_feat & GDT_64BIT)
  3957. cmd->u.cache64.DeviceNo = i;
  3958. else
  3959. cmd->u.cache.DeviceNo = i;
  3960. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3961. spin_lock_irqsave(&ha->smp_lock, flags);
  3962. rsc->hdr_list[i].bus = ha->virt_bus;
  3963. rsc->hdr_list[i].target = i;
  3964. rsc->hdr_list[i].lun = 0;
  3965. if (status != S_OK) {
  3966. ha->hdr[i].present = FALSE;
  3967. } else {
  3968. ha->hdr[i].present = TRUE;
  3969. ha->hdr[i].size = info;
  3970. /* evaluate mapping */
  3971. ha->hdr[i].size &= ~SECS32;
  3972. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3973. ha->hdr[i].heads = hds;
  3974. ha->hdr[i].secs = secs;
  3975. /* round size */
  3976. ha->hdr[i].size = cyls * hds * secs;
  3977. }
  3978. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3979. if (status != S_OK)
  3980. continue;
  3981. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3982. /* but we need ha->info2, not yet stored in scp->SCp */
  3983. /* devtype, cluster info, R/W attribs */
  3984. cmd->Service = CACHESERVICE;
  3985. cmd->OpCode = GDT_DEVTYPE;
  3986. if (ha->cache_feat & GDT_64BIT)
  3987. cmd->u.cache64.DeviceNo = i;
  3988. else
  3989. cmd->u.cache.DeviceNo = i;
  3990. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3991. spin_lock_irqsave(&ha->smp_lock, flags);
  3992. ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
  3993. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3994. cmd->Service = CACHESERVICE;
  3995. cmd->OpCode = GDT_CLUST_INFO;
  3996. if (ha->cache_feat & GDT_64BIT)
  3997. cmd->u.cache64.DeviceNo = i;
  3998. else
  3999. cmd->u.cache.DeviceNo = i;
  4000. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4001. spin_lock_irqsave(&ha->smp_lock, flags);
  4002. ha->hdr[i].cluster_type =
  4003. ((status == S_OK && !shared_access) ? (u16)info : 0);
  4004. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4005. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4006. cmd->Service = CACHESERVICE;
  4007. cmd->OpCode = GDT_RW_ATTRIBS;
  4008. if (ha->cache_feat & GDT_64BIT)
  4009. cmd->u.cache64.DeviceNo = i;
  4010. else
  4011. cmd->u.cache.DeviceNo = i;
  4012. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4013. spin_lock_irqsave(&ha->smp_lock, flags);
  4014. ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
  4015. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4016. }
  4017. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4018. rc = -EFAULT;
  4019. else
  4020. rc = 0;
  4021. free_fail:
  4022. kfree(rsc);
  4023. kfree(cmd);
  4024. return rc;
  4025. }
  4026. static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  4027. {
  4028. gdth_ha_str *ha;
  4029. Scsi_Cmnd *scp;
  4030. unsigned long flags;
  4031. char cmnd[MAX_COMMAND_SIZE];
  4032. void __user *argp = (void __user *)arg;
  4033. memset(cmnd, 0xff, 12);
  4034. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4035. switch (cmd) {
  4036. case GDTIOCTL_CTRCNT:
  4037. {
  4038. int cnt = gdth_ctr_count;
  4039. if (put_user(cnt, (int __user *)argp))
  4040. return -EFAULT;
  4041. break;
  4042. }
  4043. case GDTIOCTL_DRVERS:
  4044. {
  4045. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4046. if (put_user(ver, (int __user *)argp))
  4047. return -EFAULT;
  4048. break;
  4049. }
  4050. case GDTIOCTL_OSVERS:
  4051. {
  4052. gdth_ioctl_osvers osv;
  4053. osv.version = (u8)(LINUX_VERSION_CODE >> 16);
  4054. osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
  4055. osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
  4056. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4057. return -EFAULT;
  4058. break;
  4059. }
  4060. case GDTIOCTL_CTRTYPE:
  4061. {
  4062. gdth_ioctl_ctrtype ctrt;
  4063. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4064. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4065. return -EFAULT;
  4066. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4067. ctrt.type = (u8)((ha->stype>>20) - 0x10);
  4068. } else {
  4069. if (ha->type != GDT_PCIMPR) {
  4070. ctrt.type = (u8)((ha->stype<<4) + 6);
  4071. } else {
  4072. ctrt.type =
  4073. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4074. if (ha->stype >= 0x300)
  4075. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4076. else
  4077. ctrt.ext_type = 0x6000 | ha->stype;
  4078. }
  4079. ctrt.device_id = ha->pdev->device;
  4080. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4081. }
  4082. ctrt.info = ha->brd_phys;
  4083. ctrt.oem_id = ha->oem_id;
  4084. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4085. return -EFAULT;
  4086. break;
  4087. }
  4088. case GDTIOCTL_GENERAL:
  4089. return ioc_general(argp, cmnd);
  4090. case GDTIOCTL_EVENT:
  4091. return ioc_event(argp);
  4092. case GDTIOCTL_LOCKDRV:
  4093. return ioc_lockdrv(argp);
  4094. case GDTIOCTL_LOCKCHN:
  4095. {
  4096. gdth_ioctl_lockchn lchn;
  4097. u8 i, j;
  4098. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4099. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4100. return -EFAULT;
  4101. i = lchn.channel;
  4102. if (i < ha->bus_cnt) {
  4103. if (lchn.lock) {
  4104. spin_lock_irqsave(&ha->smp_lock, flags);
  4105. ha->raw[i].lock = 1;
  4106. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4107. for (j = 0; j < ha->tid_cnt; ++j)
  4108. gdth_wait_completion(ha, i, j);
  4109. } else {
  4110. spin_lock_irqsave(&ha->smp_lock, flags);
  4111. ha->raw[i].lock = 0;
  4112. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4113. for (j = 0; j < ha->tid_cnt; ++j)
  4114. gdth_next(ha);
  4115. }
  4116. }
  4117. break;
  4118. }
  4119. case GDTIOCTL_RESCAN:
  4120. return ioc_rescan(argp, cmnd);
  4121. case GDTIOCTL_HDRLIST:
  4122. return ioc_hdrlist(argp, cmnd);
  4123. case GDTIOCTL_RESET_BUS:
  4124. {
  4125. gdth_ioctl_reset res;
  4126. int rval;
  4127. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4128. (NULL == (ha = gdth_find_ha(res.ionode))))
  4129. return -EFAULT;
  4130. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4131. if (!scp)
  4132. return -ENOMEM;
  4133. scp->device = ha->sdev;
  4134. scp->cmd_len = 12;
  4135. scp->device->channel = res.number;
  4136. rval = gdth_eh_bus_reset(scp);
  4137. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4138. kfree(scp);
  4139. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4140. return -EFAULT;
  4141. break;
  4142. }
  4143. case GDTIOCTL_RESET_DRV:
  4144. return ioc_resetdrv(argp, cmnd);
  4145. default:
  4146. break;
  4147. }
  4148. return 0;
  4149. }
  4150. static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
  4151. unsigned long arg)
  4152. {
  4153. int ret;
  4154. mutex_lock(&gdth_mutex);
  4155. ret = gdth_ioctl(file, cmd, arg);
  4156. mutex_unlock(&gdth_mutex);
  4157. return ret;
  4158. }
  4159. /* flush routine */
  4160. static void gdth_flush(gdth_ha_str *ha)
  4161. {
  4162. int i;
  4163. gdth_cmd_str gdtcmd;
  4164. char cmnd[MAX_COMMAND_SIZE];
  4165. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4166. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4167. for (i = 0; i < MAX_HDRIVES; ++i) {
  4168. if (ha->hdr[i].present) {
  4169. gdtcmd.BoardNode = LOCALBOARD;
  4170. gdtcmd.Service = CACHESERVICE;
  4171. gdtcmd.OpCode = GDT_FLUSH;
  4172. if (ha->cache_feat & GDT_64BIT) {
  4173. gdtcmd.u.cache64.DeviceNo = i;
  4174. gdtcmd.u.cache64.BlockNo = 1;
  4175. gdtcmd.u.cache64.sg_canz = 0;
  4176. } else {
  4177. gdtcmd.u.cache.DeviceNo = i;
  4178. gdtcmd.u.cache.BlockNo = 1;
  4179. gdtcmd.u.cache.sg_canz = 0;
  4180. }
  4181. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4182. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4183. }
  4184. }
  4185. }
  4186. /* configure lun */
  4187. static int gdth_slave_configure(struct scsi_device *sdev)
  4188. {
  4189. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4190. sdev->skip_ms_page_3f = 1;
  4191. sdev->skip_ms_page_8 = 1;
  4192. return 0;
  4193. }
  4194. static struct scsi_host_template gdth_template = {
  4195. .name = "GDT SCSI Disk Array Controller",
  4196. .info = gdth_info,
  4197. .queuecommand = gdth_queuecommand,
  4198. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4199. .slave_configure = gdth_slave_configure,
  4200. .bios_param = gdth_bios_param,
  4201. .proc_info = gdth_proc_info,
  4202. .eh_timed_out = gdth_timed_out,
  4203. .proc_name = "gdth",
  4204. .can_queue = GDTH_MAXCMDS,
  4205. .this_id = -1,
  4206. .sg_tablesize = GDTH_MAXSG,
  4207. .cmd_per_lun = GDTH_MAXC_P_L,
  4208. .unchecked_isa_dma = 1,
  4209. .use_clustering = ENABLE_CLUSTERING,
  4210. };
  4211. #ifdef CONFIG_ISA
  4212. static int __init gdth_isa_probe_one(u32 isa_bios)
  4213. {
  4214. struct Scsi_Host *shp;
  4215. gdth_ha_str *ha;
  4216. dma_addr_t scratch_dma_handle = 0;
  4217. int error, i;
  4218. if (!gdth_search_isa(isa_bios))
  4219. return -ENXIO;
  4220. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4221. if (!shp)
  4222. return -ENOMEM;
  4223. ha = shost_priv(shp);
  4224. error = -ENODEV;
  4225. if (!gdth_init_isa(isa_bios,ha))
  4226. goto out_host_put;
  4227. /* controller found and initialized */
  4228. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4229. isa_bios, ha->irq, ha->drq);
  4230. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4231. if (error) {
  4232. printk("GDT-ISA: Unable to allocate IRQ\n");
  4233. goto out_host_put;
  4234. }
  4235. error = request_dma(ha->drq, "gdth");
  4236. if (error) {
  4237. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4238. goto out_free_irq;
  4239. }
  4240. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4241. enable_dma(ha->drq);
  4242. shp->unchecked_isa_dma = 1;
  4243. shp->irq = ha->irq;
  4244. shp->dma_channel = ha->drq;
  4245. ha->hanum = gdth_ctr_count++;
  4246. ha->shost = shp;
  4247. ha->pccb = &ha->cmdext;
  4248. ha->ccb_phys = 0L;
  4249. ha->pdev = NULL;
  4250. error = -ENOMEM;
  4251. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4252. &scratch_dma_handle);
  4253. if (!ha->pscratch)
  4254. goto out_dec_counters;
  4255. ha->scratch_phys = scratch_dma_handle;
  4256. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4257. &scratch_dma_handle);
  4258. if (!ha->pmsg)
  4259. goto out_free_pscratch;
  4260. ha->msg_phys = scratch_dma_handle;
  4261. #ifdef INT_COAL
  4262. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4263. sizeof(gdth_coal_status) * MAXOFFSETS,
  4264. &scratch_dma_handle);
  4265. if (!ha->coal_stat)
  4266. goto out_free_pmsg;
  4267. ha->coal_stat_phys = scratch_dma_handle;
  4268. #endif
  4269. ha->scratch_busy = FALSE;
  4270. ha->req_first = NULL;
  4271. ha->tid_cnt = MAX_HDRIVES;
  4272. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4273. ha->tid_cnt = max_ids;
  4274. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4275. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4276. ha->scan_mode = rescan ? 0x10 : 0;
  4277. error = -ENODEV;
  4278. if (!gdth_search_drives(ha)) {
  4279. printk("GDT-ISA: Error during device scan\n");
  4280. goto out_free_coal_stat;
  4281. }
  4282. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4283. hdr_channel = ha->bus_cnt;
  4284. ha->virt_bus = hdr_channel;
  4285. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4286. shp->max_cmd_len = 16;
  4287. shp->max_id = ha->tid_cnt;
  4288. shp->max_lun = MAXLUN;
  4289. shp->max_channel = ha->bus_cnt;
  4290. spin_lock_init(&ha->smp_lock);
  4291. gdth_enable_int(ha);
  4292. error = scsi_add_host(shp, NULL);
  4293. if (error)
  4294. goto out_free_coal_stat;
  4295. list_add_tail(&ha->list, &gdth_instances);
  4296. gdth_timer_init();
  4297. scsi_scan_host(shp);
  4298. return 0;
  4299. out_free_coal_stat:
  4300. #ifdef INT_COAL
  4301. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4302. ha->coal_stat, ha->coal_stat_phys);
  4303. out_free_pmsg:
  4304. #endif
  4305. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4306. ha->pmsg, ha->msg_phys);
  4307. out_free_pscratch:
  4308. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4309. ha->pscratch, ha->scratch_phys);
  4310. out_dec_counters:
  4311. gdth_ctr_count--;
  4312. out_free_irq:
  4313. free_irq(ha->irq, ha);
  4314. out_host_put:
  4315. scsi_host_put(shp);
  4316. return error;
  4317. }
  4318. #endif /* CONFIG_ISA */
  4319. #ifdef CONFIG_EISA
  4320. static int __init gdth_eisa_probe_one(u16 eisa_slot)
  4321. {
  4322. struct Scsi_Host *shp;
  4323. gdth_ha_str *ha;
  4324. dma_addr_t scratch_dma_handle = 0;
  4325. int error, i;
  4326. if (!gdth_search_eisa(eisa_slot))
  4327. return -ENXIO;
  4328. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4329. if (!shp)
  4330. return -ENOMEM;
  4331. ha = shost_priv(shp);
  4332. error = -ENODEV;
  4333. if (!gdth_init_eisa(eisa_slot,ha))
  4334. goto out_host_put;
  4335. /* controller found and initialized */
  4336. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4337. eisa_slot >> 12, ha->irq);
  4338. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4339. if (error) {
  4340. printk("GDT-EISA: Unable to allocate IRQ\n");
  4341. goto out_host_put;
  4342. }
  4343. shp->unchecked_isa_dma = 0;
  4344. shp->irq = ha->irq;
  4345. shp->dma_channel = 0xff;
  4346. ha->hanum = gdth_ctr_count++;
  4347. ha->shost = shp;
  4348. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4349. ha->pccb = &ha->cmdext;
  4350. ha->ccb_phys = 0L;
  4351. error = -ENOMEM;
  4352. ha->pdev = NULL;
  4353. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4354. &scratch_dma_handle);
  4355. if (!ha->pscratch)
  4356. goto out_free_irq;
  4357. ha->scratch_phys = scratch_dma_handle;
  4358. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4359. &scratch_dma_handle);
  4360. if (!ha->pmsg)
  4361. goto out_free_pscratch;
  4362. ha->msg_phys = scratch_dma_handle;
  4363. #ifdef INT_COAL
  4364. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4365. sizeof(gdth_coal_status) * MAXOFFSETS,
  4366. &scratch_dma_handle);
  4367. if (!ha->coal_stat)
  4368. goto out_free_pmsg;
  4369. ha->coal_stat_phys = scratch_dma_handle;
  4370. #endif
  4371. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4372. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4373. if (!ha->ccb_phys)
  4374. goto out_free_coal_stat;
  4375. ha->scratch_busy = FALSE;
  4376. ha->req_first = NULL;
  4377. ha->tid_cnt = MAX_HDRIVES;
  4378. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4379. ha->tid_cnt = max_ids;
  4380. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4381. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4382. ha->scan_mode = rescan ? 0x10 : 0;
  4383. if (!gdth_search_drives(ha)) {
  4384. printk("GDT-EISA: Error during device scan\n");
  4385. error = -ENODEV;
  4386. goto out_free_ccb_phys;
  4387. }
  4388. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4389. hdr_channel = ha->bus_cnt;
  4390. ha->virt_bus = hdr_channel;
  4391. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4392. shp->max_cmd_len = 16;
  4393. shp->max_id = ha->tid_cnt;
  4394. shp->max_lun = MAXLUN;
  4395. shp->max_channel = ha->bus_cnt;
  4396. spin_lock_init(&ha->smp_lock);
  4397. gdth_enable_int(ha);
  4398. error = scsi_add_host(shp, NULL);
  4399. if (error)
  4400. goto out_free_ccb_phys;
  4401. list_add_tail(&ha->list, &gdth_instances);
  4402. gdth_timer_init();
  4403. scsi_scan_host(shp);
  4404. return 0;
  4405. out_free_ccb_phys:
  4406. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4407. PCI_DMA_BIDIRECTIONAL);
  4408. out_free_coal_stat:
  4409. #ifdef INT_COAL
  4410. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4411. ha->coal_stat, ha->coal_stat_phys);
  4412. out_free_pmsg:
  4413. #endif
  4414. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4415. ha->pmsg, ha->msg_phys);
  4416. out_free_pscratch:
  4417. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4418. ha->pscratch, ha->scratch_phys);
  4419. out_free_irq:
  4420. free_irq(ha->irq, ha);
  4421. gdth_ctr_count--;
  4422. out_host_put:
  4423. scsi_host_put(shp);
  4424. return error;
  4425. }
  4426. #endif /* CONFIG_EISA */
  4427. #ifdef CONFIG_PCI
  4428. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out)
  4429. {
  4430. struct Scsi_Host *shp;
  4431. gdth_ha_str *ha;
  4432. dma_addr_t scratch_dma_handle = 0;
  4433. int error, i;
  4434. struct pci_dev *pdev = pcistr->pdev;
  4435. *ha_out = NULL;
  4436. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4437. if (!shp)
  4438. return -ENOMEM;
  4439. ha = shost_priv(shp);
  4440. error = -ENODEV;
  4441. if (!gdth_init_pci(pdev, pcistr, ha))
  4442. goto out_host_put;
  4443. /* controller found and initialized */
  4444. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4445. pdev->bus->number,
  4446. PCI_SLOT(pdev->devfn),
  4447. ha->irq);
  4448. error = request_irq(ha->irq, gdth_interrupt,
  4449. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4450. if (error) {
  4451. printk("GDT-PCI: Unable to allocate IRQ\n");
  4452. goto out_host_put;
  4453. }
  4454. shp->unchecked_isa_dma = 0;
  4455. shp->irq = ha->irq;
  4456. shp->dma_channel = 0xff;
  4457. ha->hanum = gdth_ctr_count++;
  4458. ha->shost = shp;
  4459. ha->pccb = &ha->cmdext;
  4460. ha->ccb_phys = 0L;
  4461. error = -ENOMEM;
  4462. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4463. &scratch_dma_handle);
  4464. if (!ha->pscratch)
  4465. goto out_free_irq;
  4466. ha->scratch_phys = scratch_dma_handle;
  4467. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4468. &scratch_dma_handle);
  4469. if (!ha->pmsg)
  4470. goto out_free_pscratch;
  4471. ha->msg_phys = scratch_dma_handle;
  4472. #ifdef INT_COAL
  4473. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4474. sizeof(gdth_coal_status) * MAXOFFSETS,
  4475. &scratch_dma_handle);
  4476. if (!ha->coal_stat)
  4477. goto out_free_pmsg;
  4478. ha->coal_stat_phys = scratch_dma_handle;
  4479. #endif
  4480. ha->scratch_busy = FALSE;
  4481. ha->req_first = NULL;
  4482. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4483. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4484. ha->tid_cnt = max_ids;
  4485. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4486. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4487. ha->scan_mode = rescan ? 0x10 : 0;
  4488. error = -ENODEV;
  4489. if (!gdth_search_drives(ha)) {
  4490. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4491. goto out_free_coal_stat;
  4492. }
  4493. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4494. hdr_channel = ha->bus_cnt;
  4495. ha->virt_bus = hdr_channel;
  4496. /* 64-bit DMA only supported from FW >= x.43 */
  4497. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4498. !ha->dma64_support) {
  4499. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4500. printk(KERN_WARNING "GDT-PCI %d: "
  4501. "Unable to set 32-bit DMA\n", ha->hanum);
  4502. goto out_free_coal_stat;
  4503. }
  4504. } else {
  4505. shp->max_cmd_len = 16;
  4506. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4507. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4508. } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4509. printk(KERN_WARNING "GDT-PCI %d: "
  4510. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4511. goto out_free_coal_stat;
  4512. }
  4513. }
  4514. shp->max_id = ha->tid_cnt;
  4515. shp->max_lun = MAXLUN;
  4516. shp->max_channel = ha->bus_cnt;
  4517. spin_lock_init(&ha->smp_lock);
  4518. gdth_enable_int(ha);
  4519. error = scsi_add_host(shp, &pdev->dev);
  4520. if (error)
  4521. goto out_free_coal_stat;
  4522. list_add_tail(&ha->list, &gdth_instances);
  4523. pci_set_drvdata(ha->pdev, ha);
  4524. gdth_timer_init();
  4525. scsi_scan_host(shp);
  4526. *ha_out = ha;
  4527. return 0;
  4528. out_free_coal_stat:
  4529. #ifdef INT_COAL
  4530. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4531. ha->coal_stat, ha->coal_stat_phys);
  4532. out_free_pmsg:
  4533. #endif
  4534. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4535. ha->pmsg, ha->msg_phys);
  4536. out_free_pscratch:
  4537. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4538. ha->pscratch, ha->scratch_phys);
  4539. out_free_irq:
  4540. free_irq(ha->irq, ha);
  4541. gdth_ctr_count--;
  4542. out_host_put:
  4543. scsi_host_put(shp);
  4544. return error;
  4545. }
  4546. #endif /* CONFIG_PCI */
  4547. static void gdth_remove_one(gdth_ha_str *ha)
  4548. {
  4549. struct Scsi_Host *shp = ha->shost;
  4550. TRACE2(("gdth_remove_one()\n"));
  4551. scsi_remove_host(shp);
  4552. gdth_flush(ha);
  4553. if (ha->sdev) {
  4554. scsi_free_host_dev(ha->sdev);
  4555. ha->sdev = NULL;
  4556. }
  4557. if (shp->irq)
  4558. free_irq(shp->irq,ha);
  4559. #ifdef CONFIG_ISA
  4560. if (shp->dma_channel != 0xff)
  4561. free_dma(shp->dma_channel);
  4562. #endif
  4563. #ifdef INT_COAL
  4564. if (ha->coal_stat)
  4565. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4566. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4567. #endif
  4568. if (ha->pscratch)
  4569. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4570. ha->pscratch, ha->scratch_phys);
  4571. if (ha->pmsg)
  4572. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4573. ha->pmsg, ha->msg_phys);
  4574. if (ha->ccb_phys)
  4575. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4576. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4577. scsi_host_put(shp);
  4578. }
  4579. static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
  4580. {
  4581. gdth_ha_str *ha;
  4582. TRACE2(("gdth_halt() event %d\n", (int)event));
  4583. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4584. return NOTIFY_DONE;
  4585. list_for_each_entry(ha, &gdth_instances, list)
  4586. gdth_flush(ha);
  4587. return NOTIFY_OK;
  4588. }
  4589. static struct notifier_block gdth_notifier = {
  4590. gdth_halt, NULL, 0
  4591. };
  4592. static int __init gdth_init(void)
  4593. {
  4594. if (disable) {
  4595. printk("GDT-HA: Controller driver disabled from"
  4596. " command line !\n");
  4597. return 0;
  4598. }
  4599. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4600. GDTH_VERSION_STR);
  4601. /* initializations */
  4602. gdth_polling = TRUE;
  4603. gdth_clear_events();
  4604. init_timer(&gdth_timer);
  4605. /* As default we do not probe for EISA or ISA controllers */
  4606. if (probe_eisa_isa) {
  4607. /* scanning for controllers, at first: ISA controller */
  4608. #ifdef CONFIG_ISA
  4609. u32 isa_bios;
  4610. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4611. isa_bios += 0x8000UL)
  4612. gdth_isa_probe_one(isa_bios);
  4613. #endif
  4614. #ifdef CONFIG_EISA
  4615. {
  4616. u16 eisa_slot;
  4617. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4618. eisa_slot += 0x1000)
  4619. gdth_eisa_probe_one(eisa_slot);
  4620. }
  4621. #endif
  4622. }
  4623. #ifdef CONFIG_PCI
  4624. /* scanning for PCI controllers */
  4625. if (pci_register_driver(&gdth_pci_driver)) {
  4626. gdth_ha_str *ha;
  4627. list_for_each_entry(ha, &gdth_instances, list)
  4628. gdth_remove_one(ha);
  4629. return -ENODEV;
  4630. }
  4631. #endif /* CONFIG_PCI */
  4632. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4633. major = register_chrdev(0,"gdth", &gdth_fops);
  4634. register_reboot_notifier(&gdth_notifier);
  4635. gdth_polling = FALSE;
  4636. return 0;
  4637. }
  4638. static void __exit gdth_exit(void)
  4639. {
  4640. gdth_ha_str *ha;
  4641. unregister_chrdev(major, "gdth");
  4642. unregister_reboot_notifier(&gdth_notifier);
  4643. #ifdef GDTH_STATISTICS
  4644. del_timer_sync(&gdth_timer);
  4645. #endif
  4646. #ifdef CONFIG_PCI
  4647. pci_unregister_driver(&gdth_pci_driver);
  4648. #endif
  4649. list_for_each_entry(ha, &gdth_instances, list)
  4650. gdth_remove_one(ha);
  4651. }
  4652. module_init(gdth_init);
  4653. module_exit(gdth_exit);
  4654. #ifndef MODULE
  4655. __setup("gdth=", option_setup);
  4656. #endif