be_main.c 142 KB

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  1. /**
  2. * Copyright (C) 2005 - 2012 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
  145. struct device_attribute *beiscsi_attrs[] = {
  146. &dev_attr_beiscsi_log_enable,
  147. &dev_attr_beiscsi_drvr_ver,
  148. &dev_attr_beiscsi_adapter_family,
  149. NULL,
  150. };
  151. static char const *cqe_desc[] = {
  152. "RESERVED_DESC",
  153. "SOL_CMD_COMPLETE",
  154. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  155. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  156. "CXN_KILLED_BURST_LEN_MISMATCH",
  157. "CXN_KILLED_AHS_RCVD",
  158. "CXN_KILLED_HDR_DIGEST_ERR",
  159. "CXN_KILLED_UNKNOWN_HDR",
  160. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  161. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  162. "CXN_KILLED_RST_RCVD",
  163. "CXN_KILLED_TIMED_OUT",
  164. "CXN_KILLED_RST_SENT",
  165. "CXN_KILLED_FIN_RCVD",
  166. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  167. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  168. "CXN_KILLED_OVER_RUN_RESIDUAL",
  169. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  170. "CMD_KILLED_INVALID_STATSN_RCVD",
  171. "CMD_KILLED_INVALID_R2T_RCVD",
  172. "CMD_CXN_KILLED_LUN_INVALID",
  173. "CMD_CXN_KILLED_ICD_INVALID",
  174. "CMD_CXN_KILLED_ITT_INVALID",
  175. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  176. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  177. "CXN_INVALIDATE_NOTIFY",
  178. "CXN_INVALIDATE_INDEX_NOTIFY",
  179. "CMD_INVALIDATED_NOTIFY",
  180. "UNSOL_HDR_NOTIFY",
  181. "UNSOL_DATA_NOTIFY",
  182. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  183. "DRIVERMSG_NOTIFY",
  184. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  185. "SOL_CMD_KILLED_DIF_ERR",
  186. "CXN_KILLED_SYN_RCVD",
  187. "CXN_KILLED_IMM_DATA_RCVD"
  188. };
  189. static int beiscsi_slave_configure(struct scsi_device *sdev)
  190. {
  191. blk_queue_max_segment_size(sdev->request_queue, 65536);
  192. return 0;
  193. }
  194. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  195. {
  196. struct iscsi_cls_session *cls_session;
  197. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  198. struct beiscsi_io_task *aborted_io_task;
  199. struct iscsi_conn *conn;
  200. struct beiscsi_conn *beiscsi_conn;
  201. struct beiscsi_hba *phba;
  202. struct iscsi_session *session;
  203. struct invalidate_command_table *inv_tbl;
  204. struct be_dma_mem nonemb_cmd;
  205. unsigned int cid, tag, num_invalidate;
  206. cls_session = starget_to_session(scsi_target(sc->device));
  207. session = cls_session->dd_data;
  208. spin_lock_bh(&session->lock);
  209. if (!aborted_task || !aborted_task->sc) {
  210. /* we raced */
  211. spin_unlock_bh(&session->lock);
  212. return SUCCESS;
  213. }
  214. aborted_io_task = aborted_task->dd_data;
  215. if (!aborted_io_task->scsi_cmnd) {
  216. /* raced or invalid command */
  217. spin_unlock_bh(&session->lock);
  218. return SUCCESS;
  219. }
  220. spin_unlock_bh(&session->lock);
  221. conn = aborted_task->conn;
  222. beiscsi_conn = conn->dd_data;
  223. phba = beiscsi_conn->phba;
  224. /* invalidate iocb */
  225. cid = beiscsi_conn->beiscsi_conn_cid;
  226. inv_tbl = phba->inv_tbl;
  227. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  228. inv_tbl->cid = cid;
  229. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  230. num_invalidate = 1;
  231. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  232. sizeof(struct invalidate_commands_params_in),
  233. &nonemb_cmd.dma);
  234. if (nonemb_cmd.va == NULL) {
  235. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  236. "BM_%d : Failed to allocate memory for"
  237. "mgmt_invalidate_icds\n");
  238. return FAILED;
  239. }
  240. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  241. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  242. cid, &nonemb_cmd);
  243. if (!tag) {
  244. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  245. "BM_%d : mgmt_invalidate_icds could not be"
  246. "submitted\n");
  247. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  248. nonemb_cmd.va, nonemb_cmd.dma);
  249. return FAILED;
  250. }
  251. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  252. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  253. nonemb_cmd.va, nonemb_cmd.dma);
  254. return iscsi_eh_abort(sc);
  255. }
  256. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  257. {
  258. struct iscsi_task *abrt_task;
  259. struct beiscsi_io_task *abrt_io_task;
  260. struct iscsi_conn *conn;
  261. struct beiscsi_conn *beiscsi_conn;
  262. struct beiscsi_hba *phba;
  263. struct iscsi_session *session;
  264. struct iscsi_cls_session *cls_session;
  265. struct invalidate_command_table *inv_tbl;
  266. struct be_dma_mem nonemb_cmd;
  267. unsigned int cid, tag, i, num_invalidate;
  268. /* invalidate iocbs */
  269. cls_session = starget_to_session(scsi_target(sc->device));
  270. session = cls_session->dd_data;
  271. spin_lock_bh(&session->lock);
  272. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  273. spin_unlock_bh(&session->lock);
  274. return FAILED;
  275. }
  276. conn = session->leadconn;
  277. beiscsi_conn = conn->dd_data;
  278. phba = beiscsi_conn->phba;
  279. cid = beiscsi_conn->beiscsi_conn_cid;
  280. inv_tbl = phba->inv_tbl;
  281. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  282. num_invalidate = 0;
  283. for (i = 0; i < conn->session->cmds_max; i++) {
  284. abrt_task = conn->session->cmds[i];
  285. abrt_io_task = abrt_task->dd_data;
  286. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  287. continue;
  288. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  289. continue;
  290. inv_tbl->cid = cid;
  291. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  292. num_invalidate++;
  293. inv_tbl++;
  294. }
  295. spin_unlock_bh(&session->lock);
  296. inv_tbl = phba->inv_tbl;
  297. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  298. sizeof(struct invalidate_commands_params_in),
  299. &nonemb_cmd.dma);
  300. if (nonemb_cmd.va == NULL) {
  301. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  302. "BM_%d : Failed to allocate memory for"
  303. "mgmt_invalidate_icds\n");
  304. return FAILED;
  305. }
  306. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  307. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  308. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  309. cid, &nonemb_cmd);
  310. if (!tag) {
  311. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  312. "BM_%d : mgmt_invalidate_icds could not be"
  313. " submitted\n");
  314. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  315. nonemb_cmd.va, nonemb_cmd.dma);
  316. return FAILED;
  317. }
  318. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  319. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  320. nonemb_cmd.va, nonemb_cmd.dma);
  321. return iscsi_eh_device_reset(sc);
  322. }
  323. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  324. {
  325. struct beiscsi_hba *phba = data;
  326. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  327. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  328. char *str = buf;
  329. int rc;
  330. switch (type) {
  331. case ISCSI_BOOT_TGT_NAME:
  332. rc = sprintf(buf, "%.*s\n",
  333. (int)strlen(boot_sess->target_name),
  334. (char *)&boot_sess->target_name);
  335. break;
  336. case ISCSI_BOOT_TGT_IP_ADDR:
  337. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  338. rc = sprintf(buf, "%pI4\n",
  339. (char *)&boot_conn->dest_ipaddr.addr);
  340. else
  341. rc = sprintf(str, "%pI6\n",
  342. (char *)&boot_conn->dest_ipaddr.addr);
  343. break;
  344. case ISCSI_BOOT_TGT_PORT:
  345. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  346. break;
  347. case ISCSI_BOOT_TGT_CHAP_NAME:
  348. rc = sprintf(str, "%.*s\n",
  349. boot_conn->negotiated_login_options.auth_data.chap.
  350. target_chap_name_length,
  351. (char *)&boot_conn->negotiated_login_options.
  352. auth_data.chap.target_chap_name);
  353. break;
  354. case ISCSI_BOOT_TGT_CHAP_SECRET:
  355. rc = sprintf(str, "%.*s\n",
  356. boot_conn->negotiated_login_options.auth_data.chap.
  357. target_secret_length,
  358. (char *)&boot_conn->negotiated_login_options.
  359. auth_data.chap.target_secret);
  360. break;
  361. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  362. rc = sprintf(str, "%.*s\n",
  363. boot_conn->negotiated_login_options.auth_data.chap.
  364. intr_chap_name_length,
  365. (char *)&boot_conn->negotiated_login_options.
  366. auth_data.chap.intr_chap_name);
  367. break;
  368. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  369. rc = sprintf(str, "%.*s\n",
  370. boot_conn->negotiated_login_options.auth_data.chap.
  371. intr_secret_length,
  372. (char *)&boot_conn->negotiated_login_options.
  373. auth_data.chap.intr_secret);
  374. break;
  375. case ISCSI_BOOT_TGT_FLAGS:
  376. rc = sprintf(str, "2\n");
  377. break;
  378. case ISCSI_BOOT_TGT_NIC_ASSOC:
  379. rc = sprintf(str, "0\n");
  380. break;
  381. default:
  382. rc = -ENOSYS;
  383. break;
  384. }
  385. return rc;
  386. }
  387. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  388. {
  389. struct beiscsi_hba *phba = data;
  390. char *str = buf;
  391. int rc;
  392. switch (type) {
  393. case ISCSI_BOOT_INI_INITIATOR_NAME:
  394. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  395. break;
  396. default:
  397. rc = -ENOSYS;
  398. break;
  399. }
  400. return rc;
  401. }
  402. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  403. {
  404. struct beiscsi_hba *phba = data;
  405. char *str = buf;
  406. int rc;
  407. switch (type) {
  408. case ISCSI_BOOT_ETH_FLAGS:
  409. rc = sprintf(str, "2\n");
  410. break;
  411. case ISCSI_BOOT_ETH_INDEX:
  412. rc = sprintf(str, "0\n");
  413. break;
  414. case ISCSI_BOOT_ETH_MAC:
  415. rc = beiscsi_get_macaddr(str, phba);
  416. break;
  417. default:
  418. rc = -ENOSYS;
  419. break;
  420. }
  421. return rc;
  422. }
  423. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  424. {
  425. umode_t rc;
  426. switch (type) {
  427. case ISCSI_BOOT_TGT_NAME:
  428. case ISCSI_BOOT_TGT_IP_ADDR:
  429. case ISCSI_BOOT_TGT_PORT:
  430. case ISCSI_BOOT_TGT_CHAP_NAME:
  431. case ISCSI_BOOT_TGT_CHAP_SECRET:
  432. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  433. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  434. case ISCSI_BOOT_TGT_NIC_ASSOC:
  435. case ISCSI_BOOT_TGT_FLAGS:
  436. rc = S_IRUGO;
  437. break;
  438. default:
  439. rc = 0;
  440. break;
  441. }
  442. return rc;
  443. }
  444. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  445. {
  446. umode_t rc;
  447. switch (type) {
  448. case ISCSI_BOOT_INI_INITIATOR_NAME:
  449. rc = S_IRUGO;
  450. break;
  451. default:
  452. rc = 0;
  453. break;
  454. }
  455. return rc;
  456. }
  457. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  458. {
  459. umode_t rc;
  460. switch (type) {
  461. case ISCSI_BOOT_ETH_FLAGS:
  462. case ISCSI_BOOT_ETH_MAC:
  463. case ISCSI_BOOT_ETH_INDEX:
  464. rc = S_IRUGO;
  465. break;
  466. default:
  467. rc = 0;
  468. break;
  469. }
  470. return rc;
  471. }
  472. /*------------------- PCI Driver operations and data ----------------- */
  473. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  474. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  475. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  476. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  477. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  478. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  479. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  480. { 0 }
  481. };
  482. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  483. static struct scsi_host_template beiscsi_sht = {
  484. .module = THIS_MODULE,
  485. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  486. .proc_name = DRV_NAME,
  487. .queuecommand = iscsi_queuecommand,
  488. .change_queue_depth = iscsi_change_queue_depth,
  489. .slave_configure = beiscsi_slave_configure,
  490. .target_alloc = iscsi_target_alloc,
  491. .eh_abort_handler = beiscsi_eh_abort,
  492. .eh_device_reset_handler = beiscsi_eh_device_reset,
  493. .eh_target_reset_handler = iscsi_eh_session_reset,
  494. .shost_attrs = beiscsi_attrs,
  495. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  496. .can_queue = BE2_IO_DEPTH,
  497. .this_id = -1,
  498. .max_sectors = BEISCSI_MAX_SECTORS,
  499. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  500. .use_clustering = ENABLE_CLUSTERING,
  501. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  502. };
  503. static struct scsi_transport_template *beiscsi_scsi_transport;
  504. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  505. {
  506. struct beiscsi_hba *phba;
  507. struct Scsi_Host *shost;
  508. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  509. if (!shost) {
  510. dev_err(&pcidev->dev,
  511. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  512. return NULL;
  513. }
  514. shost->dma_boundary = pcidev->dma_mask;
  515. shost->max_id = BE2_MAX_SESSIONS;
  516. shost->max_channel = 0;
  517. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  518. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  519. shost->transportt = beiscsi_scsi_transport;
  520. phba = iscsi_host_priv(shost);
  521. memset(phba, 0, sizeof(*phba));
  522. phba->shost = shost;
  523. phba->pcidev = pci_dev_get(pcidev);
  524. pci_set_drvdata(pcidev, phba);
  525. phba->interface_handle = 0xFFFFFFFF;
  526. if (iscsi_host_add(shost, &phba->pcidev->dev))
  527. goto free_devices;
  528. return phba;
  529. free_devices:
  530. pci_dev_put(phba->pcidev);
  531. iscsi_host_free(phba->shost);
  532. return NULL;
  533. }
  534. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  535. {
  536. if (phba->csr_va) {
  537. iounmap(phba->csr_va);
  538. phba->csr_va = NULL;
  539. }
  540. if (phba->db_va) {
  541. iounmap(phba->db_va);
  542. phba->db_va = NULL;
  543. }
  544. if (phba->pci_va) {
  545. iounmap(phba->pci_va);
  546. phba->pci_va = NULL;
  547. }
  548. }
  549. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  550. struct pci_dev *pcidev)
  551. {
  552. u8 __iomem *addr;
  553. int pcicfg_reg;
  554. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  555. pci_resource_len(pcidev, 2));
  556. if (addr == NULL)
  557. return -ENOMEM;
  558. phba->ctrl.csr = addr;
  559. phba->csr_va = addr;
  560. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  561. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  562. if (addr == NULL)
  563. goto pci_map_err;
  564. phba->ctrl.db = addr;
  565. phba->db_va = addr;
  566. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  567. if (phba->generation == BE_GEN2)
  568. pcicfg_reg = 1;
  569. else
  570. pcicfg_reg = 0;
  571. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  572. pci_resource_len(pcidev, pcicfg_reg));
  573. if (addr == NULL)
  574. goto pci_map_err;
  575. phba->ctrl.pcicfg = addr;
  576. phba->pci_va = addr;
  577. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  578. return 0;
  579. pci_map_err:
  580. beiscsi_unmap_pci_function(phba);
  581. return -ENOMEM;
  582. }
  583. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  584. {
  585. int ret;
  586. ret = pci_enable_device(pcidev);
  587. if (ret) {
  588. dev_err(&pcidev->dev,
  589. "beiscsi_enable_pci - enable device failed\n");
  590. return ret;
  591. }
  592. pci_set_master(pcidev);
  593. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  594. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  595. if (ret) {
  596. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  597. pci_disable_device(pcidev);
  598. return ret;
  599. }
  600. }
  601. return 0;
  602. }
  603. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  604. {
  605. struct be_ctrl_info *ctrl = &phba->ctrl;
  606. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  607. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  608. int status = 0;
  609. ctrl->pdev = pdev;
  610. status = beiscsi_map_pci_bars(phba, pdev);
  611. if (status)
  612. return status;
  613. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  614. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  615. mbox_mem_alloc->size,
  616. &mbox_mem_alloc->dma);
  617. if (!mbox_mem_alloc->va) {
  618. beiscsi_unmap_pci_function(phba);
  619. return -ENOMEM;
  620. }
  621. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  622. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  623. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  624. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  625. spin_lock_init(&ctrl->mbox_lock);
  626. spin_lock_init(&phba->ctrl.mcc_lock);
  627. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  628. return status;
  629. }
  630. static void beiscsi_get_params(struct beiscsi_hba *phba)
  631. {
  632. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  633. - (phba->fw_config.iscsi_cid_count
  634. + BE2_TMFS
  635. + BE2_NOPOUT_REQ));
  636. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  637. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  638. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  639. phba->params.num_sge_per_io = BE2_SGE;
  640. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  641. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  642. phba->params.eq_timer = 64;
  643. phba->params.num_eq_entries =
  644. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  645. + BE2_TMFS) / 512) + 1) * 512;
  646. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  647. ? 1024 : phba->params.num_eq_entries;
  648. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  649. "BM_%d : phba->params.num_eq_entries=%d\n",
  650. phba->params.num_eq_entries);
  651. phba->params.num_cq_entries =
  652. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  653. + BE2_TMFS) / 512) + 1) * 512;
  654. phba->params.wrbs_per_cxn = 256;
  655. }
  656. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  657. unsigned int id, unsigned int clr_interrupt,
  658. unsigned int num_processed,
  659. unsigned char rearm, unsigned char event)
  660. {
  661. u32 val = 0;
  662. val |= id & DB_EQ_RING_ID_MASK;
  663. if (rearm)
  664. val |= 1 << DB_EQ_REARM_SHIFT;
  665. if (clr_interrupt)
  666. val |= 1 << DB_EQ_CLR_SHIFT;
  667. if (event)
  668. val |= 1 << DB_EQ_EVNT_SHIFT;
  669. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  670. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  671. }
  672. /**
  673. * be_isr_mcc - The isr routine of the driver.
  674. * @irq: Not used
  675. * @dev_id: Pointer to host adapter structure
  676. */
  677. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  678. {
  679. struct beiscsi_hba *phba;
  680. struct be_eq_entry *eqe = NULL;
  681. struct be_queue_info *eq;
  682. struct be_queue_info *mcc;
  683. unsigned int num_eq_processed;
  684. struct be_eq_obj *pbe_eq;
  685. unsigned long flags;
  686. pbe_eq = dev_id;
  687. eq = &pbe_eq->q;
  688. phba = pbe_eq->phba;
  689. mcc = &phba->ctrl.mcc_obj.cq;
  690. eqe = queue_tail_node(eq);
  691. num_eq_processed = 0;
  692. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  693. & EQE_VALID_MASK) {
  694. if (((eqe->dw[offsetof(struct amap_eq_entry,
  695. resource_id) / 32] &
  696. EQE_RESID_MASK) >> 16) == mcc->id) {
  697. spin_lock_irqsave(&phba->isr_lock, flags);
  698. pbe_eq->todo_mcc_cq = true;
  699. spin_unlock_irqrestore(&phba->isr_lock, flags);
  700. }
  701. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  702. queue_tail_inc(eq);
  703. eqe = queue_tail_node(eq);
  704. num_eq_processed++;
  705. }
  706. if (pbe_eq->todo_mcc_cq)
  707. queue_work(phba->wq, &pbe_eq->work_cqs);
  708. if (num_eq_processed)
  709. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  710. return IRQ_HANDLED;
  711. }
  712. /**
  713. * be_isr_msix - The isr routine of the driver.
  714. * @irq: Not used
  715. * @dev_id: Pointer to host adapter structure
  716. */
  717. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  718. {
  719. struct beiscsi_hba *phba;
  720. struct be_eq_entry *eqe = NULL;
  721. struct be_queue_info *eq;
  722. struct be_queue_info *cq;
  723. unsigned int num_eq_processed;
  724. struct be_eq_obj *pbe_eq;
  725. unsigned long flags;
  726. pbe_eq = dev_id;
  727. eq = &pbe_eq->q;
  728. cq = pbe_eq->cq;
  729. eqe = queue_tail_node(eq);
  730. phba = pbe_eq->phba;
  731. num_eq_processed = 0;
  732. if (blk_iopoll_enabled) {
  733. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  734. & EQE_VALID_MASK) {
  735. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  736. blk_iopoll_sched(&pbe_eq->iopoll);
  737. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  738. queue_tail_inc(eq);
  739. eqe = queue_tail_node(eq);
  740. num_eq_processed++;
  741. }
  742. } else {
  743. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  744. & EQE_VALID_MASK) {
  745. spin_lock_irqsave(&phba->isr_lock, flags);
  746. pbe_eq->todo_cq = true;
  747. spin_unlock_irqrestore(&phba->isr_lock, flags);
  748. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  749. queue_tail_inc(eq);
  750. eqe = queue_tail_node(eq);
  751. num_eq_processed++;
  752. }
  753. if (pbe_eq->todo_cq)
  754. queue_work(phba->wq, &pbe_eq->work_cqs);
  755. }
  756. if (num_eq_processed)
  757. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  758. return IRQ_HANDLED;
  759. }
  760. /**
  761. * be_isr - The isr routine of the driver.
  762. * @irq: Not used
  763. * @dev_id: Pointer to host adapter structure
  764. */
  765. static irqreturn_t be_isr(int irq, void *dev_id)
  766. {
  767. struct beiscsi_hba *phba;
  768. struct hwi_controller *phwi_ctrlr;
  769. struct hwi_context_memory *phwi_context;
  770. struct be_eq_entry *eqe = NULL;
  771. struct be_queue_info *eq;
  772. struct be_queue_info *cq;
  773. struct be_queue_info *mcc;
  774. unsigned long flags, index;
  775. unsigned int num_mcceq_processed, num_ioeq_processed;
  776. struct be_ctrl_info *ctrl;
  777. struct be_eq_obj *pbe_eq;
  778. int isr;
  779. phba = dev_id;
  780. ctrl = &phba->ctrl;
  781. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  782. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  783. if (!isr)
  784. return IRQ_NONE;
  785. phwi_ctrlr = phba->phwi_ctrlr;
  786. phwi_context = phwi_ctrlr->phwi_ctxt;
  787. pbe_eq = &phwi_context->be_eq[0];
  788. eq = &phwi_context->be_eq[0].q;
  789. mcc = &phba->ctrl.mcc_obj.cq;
  790. index = 0;
  791. eqe = queue_tail_node(eq);
  792. num_ioeq_processed = 0;
  793. num_mcceq_processed = 0;
  794. if (blk_iopoll_enabled) {
  795. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  796. & EQE_VALID_MASK) {
  797. if (((eqe->dw[offsetof(struct amap_eq_entry,
  798. resource_id) / 32] &
  799. EQE_RESID_MASK) >> 16) == mcc->id) {
  800. spin_lock_irqsave(&phba->isr_lock, flags);
  801. pbe_eq->todo_mcc_cq = true;
  802. spin_unlock_irqrestore(&phba->isr_lock, flags);
  803. num_mcceq_processed++;
  804. } else {
  805. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  806. blk_iopoll_sched(&pbe_eq->iopoll);
  807. num_ioeq_processed++;
  808. }
  809. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  810. queue_tail_inc(eq);
  811. eqe = queue_tail_node(eq);
  812. }
  813. if (num_ioeq_processed || num_mcceq_processed) {
  814. if (pbe_eq->todo_mcc_cq)
  815. queue_work(phba->wq, &pbe_eq->work_cqs);
  816. if ((num_mcceq_processed) && (!num_ioeq_processed))
  817. hwi_ring_eq_db(phba, eq->id, 0,
  818. (num_ioeq_processed +
  819. num_mcceq_processed) , 1, 1);
  820. else
  821. hwi_ring_eq_db(phba, eq->id, 0,
  822. (num_ioeq_processed +
  823. num_mcceq_processed), 0, 1);
  824. return IRQ_HANDLED;
  825. } else
  826. return IRQ_NONE;
  827. } else {
  828. cq = &phwi_context->be_cq[0];
  829. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  830. & EQE_VALID_MASK) {
  831. if (((eqe->dw[offsetof(struct amap_eq_entry,
  832. resource_id) / 32] &
  833. EQE_RESID_MASK) >> 16) != cq->id) {
  834. spin_lock_irqsave(&phba->isr_lock, flags);
  835. pbe_eq->todo_mcc_cq = true;
  836. spin_unlock_irqrestore(&phba->isr_lock, flags);
  837. } else {
  838. spin_lock_irqsave(&phba->isr_lock, flags);
  839. pbe_eq->todo_cq = true;
  840. spin_unlock_irqrestore(&phba->isr_lock, flags);
  841. }
  842. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  843. queue_tail_inc(eq);
  844. eqe = queue_tail_node(eq);
  845. num_ioeq_processed++;
  846. }
  847. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  848. queue_work(phba->wq, &pbe_eq->work_cqs);
  849. if (num_ioeq_processed) {
  850. hwi_ring_eq_db(phba, eq->id, 0,
  851. num_ioeq_processed, 1, 1);
  852. return IRQ_HANDLED;
  853. } else
  854. return IRQ_NONE;
  855. }
  856. }
  857. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  858. {
  859. struct pci_dev *pcidev = phba->pcidev;
  860. struct hwi_controller *phwi_ctrlr;
  861. struct hwi_context_memory *phwi_context;
  862. int ret, msix_vec, i, j;
  863. phwi_ctrlr = phba->phwi_ctrlr;
  864. phwi_context = phwi_ctrlr->phwi_ctxt;
  865. if (phba->msix_enabled) {
  866. for (i = 0; i < phba->num_cpus; i++) {
  867. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  868. GFP_KERNEL);
  869. if (!phba->msi_name[i]) {
  870. ret = -ENOMEM;
  871. goto free_msix_irqs;
  872. }
  873. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  874. phba->shost->host_no, i);
  875. msix_vec = phba->msix_entries[i].vector;
  876. ret = request_irq(msix_vec, be_isr_msix, 0,
  877. phba->msi_name[i],
  878. &phwi_context->be_eq[i]);
  879. if (ret) {
  880. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  881. "BM_%d : beiscsi_init_irqs-Failed to"
  882. "register msix for i = %d\n",
  883. i);
  884. kfree(phba->msi_name[i]);
  885. goto free_msix_irqs;
  886. }
  887. }
  888. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  889. if (!phba->msi_name[i]) {
  890. ret = -ENOMEM;
  891. goto free_msix_irqs;
  892. }
  893. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  894. phba->shost->host_no);
  895. msix_vec = phba->msix_entries[i].vector;
  896. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  897. &phwi_context->be_eq[i]);
  898. if (ret) {
  899. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  900. "BM_%d : beiscsi_init_irqs-"
  901. "Failed to register beiscsi_msix_mcc\n");
  902. kfree(phba->msi_name[i]);
  903. goto free_msix_irqs;
  904. }
  905. } else {
  906. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  907. "beiscsi", phba);
  908. if (ret) {
  909. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  910. "BM_%d : beiscsi_init_irqs-"
  911. "Failed to register irq\\n");
  912. return ret;
  913. }
  914. }
  915. return 0;
  916. free_msix_irqs:
  917. for (j = i - 1; j >= 0; j--) {
  918. kfree(phba->msi_name[j]);
  919. msix_vec = phba->msix_entries[j].vector;
  920. free_irq(msix_vec, &phwi_context->be_eq[j]);
  921. }
  922. return ret;
  923. }
  924. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  925. unsigned int id, unsigned int num_processed,
  926. unsigned char rearm, unsigned char event)
  927. {
  928. u32 val = 0;
  929. val |= id & DB_CQ_RING_ID_MASK;
  930. if (rearm)
  931. val |= 1 << DB_CQ_REARM_SHIFT;
  932. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  933. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  934. }
  935. static unsigned int
  936. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  937. struct beiscsi_hba *phba,
  938. unsigned short cid,
  939. struct pdu_base *ppdu,
  940. unsigned long pdu_len,
  941. void *pbuffer, unsigned long buf_len)
  942. {
  943. struct iscsi_conn *conn = beiscsi_conn->conn;
  944. struct iscsi_session *session = conn->session;
  945. struct iscsi_task *task;
  946. struct beiscsi_io_task *io_task;
  947. struct iscsi_hdr *login_hdr;
  948. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  949. PDUBASE_OPCODE_MASK) {
  950. case ISCSI_OP_NOOP_IN:
  951. pbuffer = NULL;
  952. buf_len = 0;
  953. break;
  954. case ISCSI_OP_ASYNC_EVENT:
  955. break;
  956. case ISCSI_OP_REJECT:
  957. WARN_ON(!pbuffer);
  958. WARN_ON(!(buf_len == 48));
  959. beiscsi_log(phba, KERN_ERR,
  960. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  961. "BM_%d : In ISCSI_OP_REJECT\n");
  962. break;
  963. case ISCSI_OP_LOGIN_RSP:
  964. case ISCSI_OP_TEXT_RSP:
  965. task = conn->login_task;
  966. io_task = task->dd_data;
  967. login_hdr = (struct iscsi_hdr *)ppdu;
  968. login_hdr->itt = io_task->libiscsi_itt;
  969. break;
  970. default:
  971. beiscsi_log(phba, KERN_WARNING,
  972. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  973. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  974. (ppdu->
  975. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  976. & PDUBASE_OPCODE_MASK));
  977. return 1;
  978. }
  979. spin_lock_bh(&session->lock);
  980. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  981. spin_unlock_bh(&session->lock);
  982. return 0;
  983. }
  984. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  985. {
  986. struct sgl_handle *psgl_handle;
  987. if (phba->io_sgl_hndl_avbl) {
  988. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  989. "BM_%d : In alloc_io_sgl_handle,"
  990. " io_sgl_alloc_index=%d\n",
  991. phba->io_sgl_alloc_index);
  992. psgl_handle = phba->io_sgl_hndl_base[phba->
  993. io_sgl_alloc_index];
  994. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  995. phba->io_sgl_hndl_avbl--;
  996. if (phba->io_sgl_alloc_index == (phba->params.
  997. ios_per_ctrl - 1))
  998. phba->io_sgl_alloc_index = 0;
  999. else
  1000. phba->io_sgl_alloc_index++;
  1001. } else
  1002. psgl_handle = NULL;
  1003. return psgl_handle;
  1004. }
  1005. static void
  1006. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1007. {
  1008. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1009. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1010. phba->io_sgl_free_index);
  1011. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1012. /*
  1013. * this can happen if clean_task is called on a task that
  1014. * failed in xmit_task or alloc_pdu.
  1015. */
  1016. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1017. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1018. "value there=%p\n", phba->io_sgl_free_index,
  1019. phba->io_sgl_hndl_base
  1020. [phba->io_sgl_free_index]);
  1021. return;
  1022. }
  1023. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1024. phba->io_sgl_hndl_avbl++;
  1025. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1026. phba->io_sgl_free_index = 0;
  1027. else
  1028. phba->io_sgl_free_index++;
  1029. }
  1030. /**
  1031. * alloc_wrb_handle - To allocate a wrb handle
  1032. * @phba: The hba pointer
  1033. * @cid: The cid to use for allocation
  1034. *
  1035. * This happens under session_lock until submission to chip
  1036. */
  1037. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1038. {
  1039. struct hwi_wrb_context *pwrb_context;
  1040. struct hwi_controller *phwi_ctrlr;
  1041. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1042. phwi_ctrlr = phba->phwi_ctrlr;
  1043. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1044. if (pwrb_context->wrb_handles_available >= 2) {
  1045. pwrb_handle = pwrb_context->pwrb_handle_base[
  1046. pwrb_context->alloc_index];
  1047. pwrb_context->wrb_handles_available--;
  1048. if (pwrb_context->alloc_index ==
  1049. (phba->params.wrbs_per_cxn - 1))
  1050. pwrb_context->alloc_index = 0;
  1051. else
  1052. pwrb_context->alloc_index++;
  1053. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1054. pwrb_context->alloc_index];
  1055. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1056. } else
  1057. pwrb_handle = NULL;
  1058. return pwrb_handle;
  1059. }
  1060. /**
  1061. * free_wrb_handle - To free the wrb handle back to pool
  1062. * @phba: The hba pointer
  1063. * @pwrb_context: The context to free from
  1064. * @pwrb_handle: The wrb_handle to free
  1065. *
  1066. * This happens under session_lock until submission to chip
  1067. */
  1068. static void
  1069. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1070. struct wrb_handle *pwrb_handle)
  1071. {
  1072. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1073. pwrb_context->wrb_handles_available++;
  1074. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1075. pwrb_context->free_index = 0;
  1076. else
  1077. pwrb_context->free_index++;
  1078. beiscsi_log(phba, KERN_INFO,
  1079. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1080. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1081. "wrb_handles_available=%d\n",
  1082. pwrb_handle, pwrb_context->free_index,
  1083. pwrb_context->wrb_handles_available);
  1084. }
  1085. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1086. {
  1087. struct sgl_handle *psgl_handle;
  1088. if (phba->eh_sgl_hndl_avbl) {
  1089. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1090. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1091. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1092. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1093. phba->eh_sgl_alloc_index,
  1094. phba->eh_sgl_alloc_index);
  1095. phba->eh_sgl_hndl_avbl--;
  1096. if (phba->eh_sgl_alloc_index ==
  1097. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1098. 1))
  1099. phba->eh_sgl_alloc_index = 0;
  1100. else
  1101. phba->eh_sgl_alloc_index++;
  1102. } else
  1103. psgl_handle = NULL;
  1104. return psgl_handle;
  1105. }
  1106. void
  1107. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1108. {
  1109. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1110. "BM_%d : In free_mgmt_sgl_handle,"
  1111. "eh_sgl_free_index=%d\n",
  1112. phba->eh_sgl_free_index);
  1113. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1114. /*
  1115. * this can happen if clean_task is called on a task that
  1116. * failed in xmit_task or alloc_pdu.
  1117. */
  1118. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1119. "BM_%d : Double Free in eh SGL ,"
  1120. "eh_sgl_free_index=%d\n",
  1121. phba->eh_sgl_free_index);
  1122. return;
  1123. }
  1124. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1125. phba->eh_sgl_hndl_avbl++;
  1126. if (phba->eh_sgl_free_index ==
  1127. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1128. phba->eh_sgl_free_index = 0;
  1129. else
  1130. phba->eh_sgl_free_index++;
  1131. }
  1132. static void
  1133. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1134. struct iscsi_task *task,
  1135. struct common_sol_cqe *csol_cqe)
  1136. {
  1137. struct beiscsi_io_task *io_task = task->dd_data;
  1138. struct be_status_bhs *sts_bhs =
  1139. (struct be_status_bhs *)io_task->cmd_bhs;
  1140. struct iscsi_conn *conn = beiscsi_conn->conn;
  1141. unsigned char *sense;
  1142. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1143. u8 rsp, status, flags;
  1144. exp_cmdsn = csol_cqe->exp_cmdsn;
  1145. max_cmdsn = (csol_cqe->exp_cmdsn +
  1146. csol_cqe->cmd_wnd - 1);
  1147. rsp = csol_cqe->i_resp;
  1148. status = csol_cqe->i_sts;
  1149. flags = csol_cqe->i_flags;
  1150. resid = csol_cqe->res_cnt;
  1151. if (!task->sc) {
  1152. if (io_task->scsi_cmnd)
  1153. scsi_dma_unmap(io_task->scsi_cmnd);
  1154. return;
  1155. }
  1156. task->sc->result = (DID_OK << 16) | status;
  1157. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1158. task->sc->result = DID_ERROR << 16;
  1159. goto unmap;
  1160. }
  1161. /* bidi not initially supported */
  1162. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1163. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1164. task->sc->result = DID_ERROR << 16;
  1165. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1166. scsi_set_resid(task->sc, resid);
  1167. if (!status && (scsi_bufflen(task->sc) - resid <
  1168. task->sc->underflow))
  1169. task->sc->result = DID_ERROR << 16;
  1170. }
  1171. }
  1172. if (status == SAM_STAT_CHECK_CONDITION) {
  1173. u16 sense_len;
  1174. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1175. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1176. sense_len = be16_to_cpu(*slen);
  1177. memcpy(task->sc->sense_buffer, sense,
  1178. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1179. }
  1180. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1181. conn->rxdata_octets += resid;
  1182. unmap:
  1183. scsi_dma_unmap(io_task->scsi_cmnd);
  1184. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1185. }
  1186. static void
  1187. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1188. struct iscsi_task *task,
  1189. struct common_sol_cqe *csol_cqe)
  1190. {
  1191. struct iscsi_logout_rsp *hdr;
  1192. struct beiscsi_io_task *io_task = task->dd_data;
  1193. struct iscsi_conn *conn = beiscsi_conn->conn;
  1194. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1195. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1196. hdr->t2wait = 5;
  1197. hdr->t2retain = 0;
  1198. hdr->flags = csol_cqe->i_flags;
  1199. hdr->response = csol_cqe->i_resp;
  1200. hdr->exp_cmdsn = csol_cqe->exp_cmdsn;
  1201. hdr->max_cmdsn = (csol_cqe->exp_cmdsn + csol_cqe->cmd_wnd - 1);
  1202. hdr->dlength[0] = 0;
  1203. hdr->dlength[1] = 0;
  1204. hdr->dlength[2] = 0;
  1205. hdr->hlength = 0;
  1206. hdr->itt = io_task->libiscsi_itt;
  1207. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1208. }
  1209. static void
  1210. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1211. struct iscsi_task *task,
  1212. struct common_sol_cqe *csol_cqe)
  1213. {
  1214. struct iscsi_tm_rsp *hdr;
  1215. struct iscsi_conn *conn = beiscsi_conn->conn;
  1216. struct beiscsi_io_task *io_task = task->dd_data;
  1217. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1218. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1219. hdr->flags = csol_cqe->i_flags;
  1220. hdr->response = csol_cqe->i_resp;
  1221. hdr->exp_cmdsn = csol_cqe->exp_cmdsn;
  1222. hdr->max_cmdsn = (csol_cqe->exp_cmdsn +
  1223. csol_cqe->cmd_wnd - 1);
  1224. hdr->itt = io_task->libiscsi_itt;
  1225. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1226. }
  1227. static void
  1228. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1229. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1230. {
  1231. struct hwi_wrb_context *pwrb_context;
  1232. struct wrb_handle *pwrb_handle = NULL;
  1233. struct hwi_controller *phwi_ctrlr;
  1234. struct iscsi_task *task;
  1235. struct beiscsi_io_task *io_task;
  1236. struct iscsi_conn *conn = beiscsi_conn->conn;
  1237. struct iscsi_session *session = conn->session;
  1238. uint16_t wrb_index, cid;
  1239. phwi_ctrlr = phba->phwi_ctrlr;
  1240. if (chip_skh_r(phba->pcidev)) {
  1241. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1242. wrb_idx, psol);
  1243. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1244. cid, psol);
  1245. } else {
  1246. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1247. wrb_idx, psol);
  1248. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1249. cid, psol);
  1250. }
  1251. pwrb_context = &phwi_ctrlr->wrb_context[
  1252. cid - phba->fw_config.iscsi_cid_start];
  1253. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1254. task = pwrb_handle->pio_handle;
  1255. io_task = task->dd_data;
  1256. spin_lock_bh(&phba->mgmt_sgl_lock);
  1257. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1258. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1259. spin_lock_bh(&session->lock);
  1260. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1261. spin_unlock_bh(&session->lock);
  1262. }
  1263. static void
  1264. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1265. struct iscsi_task *task,
  1266. struct common_sol_cqe *csol_cqe)
  1267. {
  1268. struct iscsi_nopin *hdr;
  1269. struct iscsi_conn *conn = beiscsi_conn->conn;
  1270. struct beiscsi_io_task *io_task = task->dd_data;
  1271. hdr = (struct iscsi_nopin *)task->hdr;
  1272. hdr->flags = csol_cqe->i_flags;
  1273. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1274. hdr->max_cmdsn = be32_to_cpu(hdr->exp_cmdsn +
  1275. csol_cqe->cmd_wnd - 1);
  1276. hdr->opcode = ISCSI_OP_NOOP_IN;
  1277. hdr->itt = io_task->libiscsi_itt;
  1278. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1279. }
  1280. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1281. struct sol_cqe *psol,
  1282. struct common_sol_cqe *csol_cqe)
  1283. {
  1284. if (chip_skh_r(phba->pcidev)) {
  1285. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1286. i_exp_cmd_sn, psol);
  1287. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1288. i_res_cnt, psol);
  1289. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1290. wrb_index, psol);
  1291. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1292. cid, psol);
  1293. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1294. hw_sts, psol);
  1295. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1296. i_cmd_wnd, psol);
  1297. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1298. cmd_cmpl, psol))
  1299. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1300. i_sts, psol);
  1301. else
  1302. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1303. i_sts, psol);
  1304. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1305. u, psol))
  1306. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1307. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1308. o, psol))
  1309. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1310. } else {
  1311. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1312. i_exp_cmd_sn, psol);
  1313. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1314. i_res_cnt, psol);
  1315. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1316. i_cmd_wnd, psol);
  1317. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1318. wrb_index, psol);
  1319. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1320. cid, psol);
  1321. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1322. hw_sts, psol);
  1323. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1324. i_resp, psol);
  1325. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1326. i_sts, psol);
  1327. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1328. i_flags, psol);
  1329. }
  1330. }
  1331. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1332. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1333. {
  1334. struct hwi_wrb_context *pwrb_context;
  1335. struct wrb_handle *pwrb_handle;
  1336. struct iscsi_wrb *pwrb = NULL;
  1337. struct hwi_controller *phwi_ctrlr;
  1338. struct iscsi_task *task;
  1339. unsigned int type;
  1340. struct iscsi_conn *conn = beiscsi_conn->conn;
  1341. struct iscsi_session *session = conn->session;
  1342. struct common_sol_cqe csol_cqe = {0};
  1343. phwi_ctrlr = phba->phwi_ctrlr;
  1344. /* Copy the elements to a common structure */
  1345. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1346. pwrb_context = &phwi_ctrlr->wrb_context[
  1347. csol_cqe.cid - phba->fw_config.iscsi_cid_start];
  1348. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1349. csol_cqe.wrb_index];
  1350. task = pwrb_handle->pio_handle;
  1351. pwrb = pwrb_handle->pwrb;
  1352. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1353. spin_lock_bh(&session->lock);
  1354. switch (type) {
  1355. case HWH_TYPE_IO:
  1356. case HWH_TYPE_IO_RD:
  1357. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1358. ISCSI_OP_NOOP_OUT)
  1359. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1360. else
  1361. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1362. break;
  1363. case HWH_TYPE_LOGOUT:
  1364. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1365. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1366. else
  1367. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1368. break;
  1369. case HWH_TYPE_LOGIN:
  1370. beiscsi_log(phba, KERN_ERR,
  1371. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1372. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1373. " hwi_complete_cmd- Solicited path\n");
  1374. break;
  1375. case HWH_TYPE_NOP:
  1376. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1377. break;
  1378. default:
  1379. beiscsi_log(phba, KERN_WARNING,
  1380. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1381. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1382. "wrb_index 0x%x CID 0x%x\n", type,
  1383. csol_cqe.wrb_index,
  1384. csol_cqe.cid);
  1385. break;
  1386. }
  1387. spin_unlock_bh(&session->lock);
  1388. }
  1389. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1390. *pasync_ctx, unsigned int is_header,
  1391. unsigned int host_write_ptr)
  1392. {
  1393. if (is_header)
  1394. return &pasync_ctx->async_entry[host_write_ptr].
  1395. header_busy_list;
  1396. else
  1397. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1398. }
  1399. static struct async_pdu_handle *
  1400. hwi_get_async_handle(struct beiscsi_hba *phba,
  1401. struct beiscsi_conn *beiscsi_conn,
  1402. struct hwi_async_pdu_context *pasync_ctx,
  1403. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1404. {
  1405. struct be_bus_address phys_addr;
  1406. struct list_head *pbusy_list;
  1407. struct async_pdu_handle *pasync_handle = NULL;
  1408. unsigned char is_header = 0;
  1409. unsigned int index, dpl;
  1410. if (chip_skh_r(phba->pcidev)) {
  1411. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1412. dpl, pdpdu_cqe);
  1413. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1414. index, pdpdu_cqe);
  1415. } else {
  1416. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1417. dpl, pdpdu_cqe);
  1418. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1419. index, pdpdu_cqe);
  1420. }
  1421. phys_addr.u.a32.address_lo =
  1422. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1423. db_addr_lo) / 32] - dpl);
  1424. phys_addr.u.a32.address_hi =
  1425. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1426. db_addr_hi) / 32];
  1427. phys_addr.u.a64.address =
  1428. *((unsigned long long *)(&phys_addr.u.a64.address));
  1429. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1430. & PDUCQE_CODE_MASK) {
  1431. case UNSOL_HDR_NOTIFY:
  1432. is_header = 1;
  1433. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1434. is_header, index);
  1435. break;
  1436. case UNSOL_DATA_NOTIFY:
  1437. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1438. is_header, index);
  1439. break;
  1440. default:
  1441. pbusy_list = NULL;
  1442. beiscsi_log(phba, KERN_WARNING,
  1443. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1444. "BM_%d : Unexpected code=%d\n",
  1445. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1446. code) / 32] & PDUCQE_CODE_MASK);
  1447. return NULL;
  1448. }
  1449. WARN_ON(list_empty(pbusy_list));
  1450. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1451. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1452. break;
  1453. }
  1454. WARN_ON(!pasync_handle);
  1455. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1456. phba->fw_config.iscsi_cid_start;
  1457. pasync_handle->is_header = is_header;
  1458. pasync_handle->buffer_len = dpl;
  1459. *pcq_index = index;
  1460. return pasync_handle;
  1461. }
  1462. static unsigned int
  1463. hwi_update_async_writables(struct beiscsi_hba *phba,
  1464. struct hwi_async_pdu_context *pasync_ctx,
  1465. unsigned int is_header, unsigned int cq_index)
  1466. {
  1467. struct list_head *pbusy_list;
  1468. struct async_pdu_handle *pasync_handle;
  1469. unsigned int num_entries, writables = 0;
  1470. unsigned int *pep_read_ptr, *pwritables;
  1471. num_entries = pasync_ctx->num_entries;
  1472. if (is_header) {
  1473. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1474. pwritables = &pasync_ctx->async_header.writables;
  1475. } else {
  1476. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1477. pwritables = &pasync_ctx->async_data.writables;
  1478. }
  1479. while ((*pep_read_ptr) != cq_index) {
  1480. (*pep_read_ptr)++;
  1481. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1482. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1483. *pep_read_ptr);
  1484. if (writables == 0)
  1485. WARN_ON(list_empty(pbusy_list));
  1486. if (!list_empty(pbusy_list)) {
  1487. pasync_handle = list_entry(pbusy_list->next,
  1488. struct async_pdu_handle,
  1489. link);
  1490. WARN_ON(!pasync_handle);
  1491. pasync_handle->consumed = 1;
  1492. }
  1493. writables++;
  1494. }
  1495. if (!writables) {
  1496. beiscsi_log(phba, KERN_ERR,
  1497. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1498. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1499. cq_index);
  1500. WARN_ON(1);
  1501. }
  1502. *pwritables = *pwritables + writables;
  1503. return 0;
  1504. }
  1505. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1506. unsigned int cri)
  1507. {
  1508. struct hwi_controller *phwi_ctrlr;
  1509. struct hwi_async_pdu_context *pasync_ctx;
  1510. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1511. struct list_head *plist;
  1512. phwi_ctrlr = phba->phwi_ctrlr;
  1513. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1514. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1515. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1516. list_del(&pasync_handle->link);
  1517. if (pasync_handle->is_header) {
  1518. list_add_tail(&pasync_handle->link,
  1519. &pasync_ctx->async_header.free_list);
  1520. pasync_ctx->async_header.free_entries++;
  1521. } else {
  1522. list_add_tail(&pasync_handle->link,
  1523. &pasync_ctx->async_data.free_list);
  1524. pasync_ctx->async_data.free_entries++;
  1525. }
  1526. }
  1527. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1528. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1529. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1530. }
  1531. static struct phys_addr *
  1532. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1533. unsigned int is_header, unsigned int host_write_ptr)
  1534. {
  1535. struct phys_addr *pasync_sge = NULL;
  1536. if (is_header)
  1537. pasync_sge = pasync_ctx->async_header.ring_base;
  1538. else
  1539. pasync_sge = pasync_ctx->async_data.ring_base;
  1540. return pasync_sge + host_write_ptr;
  1541. }
  1542. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1543. unsigned int is_header)
  1544. {
  1545. struct hwi_controller *phwi_ctrlr;
  1546. struct hwi_async_pdu_context *pasync_ctx;
  1547. struct async_pdu_handle *pasync_handle;
  1548. struct list_head *pfree_link, *pbusy_list;
  1549. struct phys_addr *pasync_sge;
  1550. unsigned int ring_id, num_entries;
  1551. unsigned int host_write_num;
  1552. unsigned int writables;
  1553. unsigned int i = 0;
  1554. u32 doorbell = 0;
  1555. phwi_ctrlr = phba->phwi_ctrlr;
  1556. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1557. num_entries = pasync_ctx->num_entries;
  1558. if (is_header) {
  1559. writables = min(pasync_ctx->async_header.writables,
  1560. pasync_ctx->async_header.free_entries);
  1561. pfree_link = pasync_ctx->async_header.free_list.next;
  1562. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1563. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1564. } else {
  1565. writables = min(pasync_ctx->async_data.writables,
  1566. pasync_ctx->async_data.free_entries);
  1567. pfree_link = pasync_ctx->async_data.free_list.next;
  1568. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1569. ring_id = phwi_ctrlr->default_pdu_data.id;
  1570. }
  1571. writables = (writables / 8) * 8;
  1572. if (writables) {
  1573. for (i = 0; i < writables; i++) {
  1574. pbusy_list =
  1575. hwi_get_async_busy_list(pasync_ctx, is_header,
  1576. host_write_num);
  1577. pasync_handle =
  1578. list_entry(pfree_link, struct async_pdu_handle,
  1579. link);
  1580. WARN_ON(!pasync_handle);
  1581. pasync_handle->consumed = 0;
  1582. pfree_link = pfree_link->next;
  1583. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1584. is_header, host_write_num);
  1585. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1586. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1587. list_move(&pasync_handle->link, pbusy_list);
  1588. host_write_num++;
  1589. host_write_num = host_write_num % num_entries;
  1590. }
  1591. if (is_header) {
  1592. pasync_ctx->async_header.host_write_ptr =
  1593. host_write_num;
  1594. pasync_ctx->async_header.free_entries -= writables;
  1595. pasync_ctx->async_header.writables -= writables;
  1596. pasync_ctx->async_header.busy_entries += writables;
  1597. } else {
  1598. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1599. pasync_ctx->async_data.free_entries -= writables;
  1600. pasync_ctx->async_data.writables -= writables;
  1601. pasync_ctx->async_data.busy_entries += writables;
  1602. }
  1603. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1604. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1605. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1606. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1607. << DB_DEF_PDU_CQPROC_SHIFT;
  1608. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1609. }
  1610. }
  1611. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1612. struct beiscsi_conn *beiscsi_conn,
  1613. struct i_t_dpdu_cqe *pdpdu_cqe)
  1614. {
  1615. struct hwi_controller *phwi_ctrlr;
  1616. struct hwi_async_pdu_context *pasync_ctx;
  1617. struct async_pdu_handle *pasync_handle = NULL;
  1618. unsigned int cq_index = -1;
  1619. phwi_ctrlr = phba->phwi_ctrlr;
  1620. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1621. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1622. pdpdu_cqe, &cq_index);
  1623. BUG_ON(pasync_handle->is_header != 0);
  1624. if (pasync_handle->consumed == 0)
  1625. hwi_update_async_writables(phba, pasync_ctx,
  1626. pasync_handle->is_header, cq_index);
  1627. hwi_free_async_msg(phba, pasync_handle->cri);
  1628. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1629. }
  1630. static unsigned int
  1631. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1632. struct beiscsi_hba *phba,
  1633. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1634. {
  1635. struct list_head *plist;
  1636. struct async_pdu_handle *pasync_handle;
  1637. void *phdr = NULL;
  1638. unsigned int hdr_len = 0, buf_len = 0;
  1639. unsigned int status, index = 0, offset = 0;
  1640. void *pfirst_buffer = NULL;
  1641. unsigned int num_buf = 0;
  1642. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1643. list_for_each_entry(pasync_handle, plist, link) {
  1644. if (index == 0) {
  1645. phdr = pasync_handle->pbuffer;
  1646. hdr_len = pasync_handle->buffer_len;
  1647. } else {
  1648. buf_len = pasync_handle->buffer_len;
  1649. if (!num_buf) {
  1650. pfirst_buffer = pasync_handle->pbuffer;
  1651. num_buf++;
  1652. }
  1653. memcpy(pfirst_buffer + offset,
  1654. pasync_handle->pbuffer, buf_len);
  1655. offset += buf_len;
  1656. }
  1657. index++;
  1658. }
  1659. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1660. (beiscsi_conn->beiscsi_conn_cid -
  1661. phba->fw_config.iscsi_cid_start),
  1662. phdr, hdr_len, pfirst_buffer,
  1663. offset);
  1664. hwi_free_async_msg(phba, cri);
  1665. return 0;
  1666. }
  1667. static unsigned int
  1668. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1669. struct beiscsi_hba *phba,
  1670. struct async_pdu_handle *pasync_handle)
  1671. {
  1672. struct hwi_async_pdu_context *pasync_ctx;
  1673. struct hwi_controller *phwi_ctrlr;
  1674. unsigned int bytes_needed = 0, status = 0;
  1675. unsigned short cri = pasync_handle->cri;
  1676. struct pdu_base *ppdu;
  1677. phwi_ctrlr = phba->phwi_ctrlr;
  1678. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1679. list_del(&pasync_handle->link);
  1680. if (pasync_handle->is_header) {
  1681. pasync_ctx->async_header.busy_entries--;
  1682. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1683. hwi_free_async_msg(phba, cri);
  1684. BUG();
  1685. }
  1686. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1687. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1688. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1689. (unsigned short)pasync_handle->buffer_len;
  1690. list_add_tail(&pasync_handle->link,
  1691. &pasync_ctx->async_entry[cri].wait_queue.list);
  1692. ppdu = pasync_handle->pbuffer;
  1693. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1694. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1695. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1696. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1697. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1698. if (status == 0) {
  1699. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1700. bytes_needed;
  1701. if (bytes_needed == 0)
  1702. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1703. pasync_ctx, cri);
  1704. }
  1705. } else {
  1706. pasync_ctx->async_data.busy_entries--;
  1707. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1708. list_add_tail(&pasync_handle->link,
  1709. &pasync_ctx->async_entry[cri].wait_queue.
  1710. list);
  1711. pasync_ctx->async_entry[cri].wait_queue.
  1712. bytes_received +=
  1713. (unsigned short)pasync_handle->buffer_len;
  1714. if (pasync_ctx->async_entry[cri].wait_queue.
  1715. bytes_received >=
  1716. pasync_ctx->async_entry[cri].wait_queue.
  1717. bytes_needed)
  1718. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1719. pasync_ctx, cri);
  1720. }
  1721. }
  1722. return status;
  1723. }
  1724. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1725. struct beiscsi_hba *phba,
  1726. struct i_t_dpdu_cqe *pdpdu_cqe)
  1727. {
  1728. struct hwi_controller *phwi_ctrlr;
  1729. struct hwi_async_pdu_context *pasync_ctx;
  1730. struct async_pdu_handle *pasync_handle = NULL;
  1731. unsigned int cq_index = -1;
  1732. phwi_ctrlr = phba->phwi_ctrlr;
  1733. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1734. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1735. pdpdu_cqe, &cq_index);
  1736. if (pasync_handle->consumed == 0)
  1737. hwi_update_async_writables(phba, pasync_ctx,
  1738. pasync_handle->is_header, cq_index);
  1739. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1740. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1741. }
  1742. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1743. {
  1744. struct be_queue_info *mcc_cq;
  1745. struct be_mcc_compl *mcc_compl;
  1746. unsigned int num_processed = 0;
  1747. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1748. mcc_compl = queue_tail_node(mcc_cq);
  1749. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1750. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1751. if (num_processed >= 32) {
  1752. hwi_ring_cq_db(phba, mcc_cq->id,
  1753. num_processed, 0, 0);
  1754. num_processed = 0;
  1755. }
  1756. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1757. /* Interpret flags as an async trailer */
  1758. if (is_link_state_evt(mcc_compl->flags))
  1759. /* Interpret compl as a async link evt */
  1760. beiscsi_async_link_state_process(phba,
  1761. (struct be_async_event_link_state *) mcc_compl);
  1762. else
  1763. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1764. "BM_%d : Unsupported Async Event, flags"
  1765. " = 0x%08x\n",
  1766. mcc_compl->flags);
  1767. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1768. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1769. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1770. }
  1771. mcc_compl->flags = 0;
  1772. queue_tail_inc(mcc_cq);
  1773. mcc_compl = queue_tail_node(mcc_cq);
  1774. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1775. num_processed++;
  1776. }
  1777. if (num_processed > 0)
  1778. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1779. }
  1780. /**
  1781. * beiscsi_process_cq()- Process the Completion Queue
  1782. * @pbe_eq: Event Q on which the Completion has come
  1783. *
  1784. * return
  1785. * Number of Completion Entries processed.
  1786. **/
  1787. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1788. {
  1789. struct be_queue_info *cq;
  1790. struct sol_cqe *sol;
  1791. struct dmsg_cqe *dmsg;
  1792. unsigned int num_processed = 0;
  1793. unsigned int tot_nump = 0;
  1794. unsigned short code = 0, cid = 0;
  1795. struct beiscsi_conn *beiscsi_conn;
  1796. struct beiscsi_endpoint *beiscsi_ep;
  1797. struct iscsi_endpoint *ep;
  1798. struct beiscsi_hba *phba;
  1799. cq = pbe_eq->cq;
  1800. sol = queue_tail_node(cq);
  1801. phba = pbe_eq->phba;
  1802. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1803. CQE_VALID_MASK) {
  1804. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1805. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1806. 32] & CQE_CODE_MASK);
  1807. /* Get the CID */
  1808. if (chip_skh_r(phba->pcidev)) {
  1809. if ((code == DRIVERMSG_NOTIFY) ||
  1810. (code == UNSOL_HDR_NOTIFY) ||
  1811. (code == UNSOL_DATA_NOTIFY))
  1812. cid = AMAP_GET_BITS(
  1813. struct amap_i_t_dpdu_cqe_v2,
  1814. cid, sol);
  1815. else
  1816. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1817. cid, sol);
  1818. } else
  1819. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1820. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1821. beiscsi_ep = ep->dd_data;
  1822. beiscsi_conn = beiscsi_ep->conn;
  1823. if (num_processed >= 32) {
  1824. hwi_ring_cq_db(phba, cq->id,
  1825. num_processed, 0, 0);
  1826. tot_nump += num_processed;
  1827. num_processed = 0;
  1828. }
  1829. switch (code) {
  1830. case SOL_CMD_COMPLETE:
  1831. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1832. break;
  1833. case DRIVERMSG_NOTIFY:
  1834. beiscsi_log(phba, KERN_INFO,
  1835. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1836. "BM_%d : Received %s[%d] on CID : %d\n",
  1837. cqe_desc[code], code, cid);
  1838. dmsg = (struct dmsg_cqe *)sol;
  1839. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1840. break;
  1841. case UNSOL_HDR_NOTIFY:
  1842. beiscsi_log(phba, KERN_INFO,
  1843. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1844. "BM_%d : Received %s[%d] on CID : %d\n",
  1845. cqe_desc[code], code, cid);
  1846. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1847. (struct i_t_dpdu_cqe *)sol);
  1848. break;
  1849. case UNSOL_DATA_NOTIFY:
  1850. beiscsi_log(phba, KERN_INFO,
  1851. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1852. "BM_%d : Received %s[%d] on CID : %d\n",
  1853. cqe_desc[code], code, cid);
  1854. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1855. (struct i_t_dpdu_cqe *)sol);
  1856. break;
  1857. case CXN_INVALIDATE_INDEX_NOTIFY:
  1858. case CMD_INVALIDATED_NOTIFY:
  1859. case CXN_INVALIDATE_NOTIFY:
  1860. beiscsi_log(phba, KERN_ERR,
  1861. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1862. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1863. cqe_desc[code], code, cid);
  1864. break;
  1865. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1866. case CMD_KILLED_INVALID_STATSN_RCVD:
  1867. case CMD_KILLED_INVALID_R2T_RCVD:
  1868. case CMD_CXN_KILLED_LUN_INVALID:
  1869. case CMD_CXN_KILLED_ICD_INVALID:
  1870. case CMD_CXN_KILLED_ITT_INVALID:
  1871. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1872. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1873. beiscsi_log(phba, KERN_ERR,
  1874. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1875. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1876. cqe_desc[code], code, cid);
  1877. break;
  1878. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1879. beiscsi_log(phba, KERN_ERR,
  1880. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1881. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1882. cqe_desc[code], code, cid);
  1883. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1884. (struct i_t_dpdu_cqe *) sol);
  1885. break;
  1886. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1887. case CXN_KILLED_BURST_LEN_MISMATCH:
  1888. case CXN_KILLED_AHS_RCVD:
  1889. case CXN_KILLED_HDR_DIGEST_ERR:
  1890. case CXN_KILLED_UNKNOWN_HDR:
  1891. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1892. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1893. case CXN_KILLED_TIMED_OUT:
  1894. case CXN_KILLED_FIN_RCVD:
  1895. case CXN_KILLED_RST_SENT:
  1896. case CXN_KILLED_RST_RCVD:
  1897. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1898. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1899. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1900. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1901. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1902. beiscsi_log(phba, KERN_ERR,
  1903. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1904. "BM_%d : Event %s[%d] received on CID : %d\n",
  1905. cqe_desc[code], code, cid);
  1906. if (beiscsi_conn)
  1907. iscsi_conn_failure(beiscsi_conn->conn,
  1908. ISCSI_ERR_CONN_FAILED);
  1909. break;
  1910. default:
  1911. beiscsi_log(phba, KERN_ERR,
  1912. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1913. "BM_%d : Invalid CQE Event Received Code : %d"
  1914. "CID 0x%x...\n",
  1915. code, cid);
  1916. break;
  1917. }
  1918. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1919. queue_tail_inc(cq);
  1920. sol = queue_tail_node(cq);
  1921. num_processed++;
  1922. }
  1923. if (num_processed > 0) {
  1924. tot_nump += num_processed;
  1925. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1926. }
  1927. return tot_nump;
  1928. }
  1929. void beiscsi_process_all_cqs(struct work_struct *work)
  1930. {
  1931. unsigned long flags;
  1932. struct hwi_controller *phwi_ctrlr;
  1933. struct hwi_context_memory *phwi_context;
  1934. struct beiscsi_hba *phba;
  1935. struct be_eq_obj *pbe_eq =
  1936. container_of(work, struct be_eq_obj, work_cqs);
  1937. phba = pbe_eq->phba;
  1938. phwi_ctrlr = phba->phwi_ctrlr;
  1939. phwi_context = phwi_ctrlr->phwi_ctxt;
  1940. if (pbe_eq->todo_mcc_cq) {
  1941. spin_lock_irqsave(&phba->isr_lock, flags);
  1942. pbe_eq->todo_mcc_cq = false;
  1943. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1944. beiscsi_process_mcc_isr(phba);
  1945. }
  1946. if (pbe_eq->todo_cq) {
  1947. spin_lock_irqsave(&phba->isr_lock, flags);
  1948. pbe_eq->todo_cq = false;
  1949. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1950. beiscsi_process_cq(pbe_eq);
  1951. }
  1952. /* rearm EQ for further interrupts */
  1953. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1954. }
  1955. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1956. {
  1957. static unsigned int ret;
  1958. struct beiscsi_hba *phba;
  1959. struct be_eq_obj *pbe_eq;
  1960. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1961. ret = beiscsi_process_cq(pbe_eq);
  1962. if (ret < budget) {
  1963. phba = pbe_eq->phba;
  1964. blk_iopoll_complete(iop);
  1965. beiscsi_log(phba, KERN_INFO,
  1966. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1967. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1968. pbe_eq->q.id);
  1969. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1970. }
  1971. return ret;
  1972. }
  1973. static void
  1974. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1975. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1976. {
  1977. struct iscsi_sge *psgl;
  1978. unsigned int sg_len, index;
  1979. unsigned int sge_len = 0;
  1980. unsigned long long addr;
  1981. struct scatterlist *l_sg;
  1982. unsigned int offset;
  1983. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  1984. io_task->bhs_pa.u.a32.address_lo);
  1985. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  1986. io_task->bhs_pa.u.a32.address_hi);
  1987. l_sg = sg;
  1988. for (index = 0; (index < num_sg) && (index < 2); index++,
  1989. sg = sg_next(sg)) {
  1990. if (index == 0) {
  1991. sg_len = sg_dma_len(sg);
  1992. addr = (u64) sg_dma_address(sg);
  1993. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  1994. sge0_addr_lo, pwrb,
  1995. lower_32_bits(addr));
  1996. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  1997. sge0_addr_hi, pwrb,
  1998. upper_32_bits(addr));
  1999. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2000. sge0_len, pwrb,
  2001. sg_len);
  2002. sge_len = sg_len;
  2003. } else {
  2004. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2005. pwrb, sge_len);
  2006. sg_len = sg_dma_len(sg);
  2007. addr = (u64) sg_dma_address(sg);
  2008. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2009. sge1_addr_lo, pwrb,
  2010. lower_32_bits(addr));
  2011. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2012. sge1_addr_hi, pwrb,
  2013. upper_32_bits(addr));
  2014. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2015. sge1_len, pwrb,
  2016. sg_len);
  2017. }
  2018. }
  2019. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2020. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2021. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2022. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2023. io_task->bhs_pa.u.a32.address_hi);
  2024. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2025. io_task->bhs_pa.u.a32.address_lo);
  2026. if (num_sg == 1) {
  2027. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2028. 1);
  2029. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2030. 0);
  2031. } else if (num_sg == 2) {
  2032. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2033. 0);
  2034. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2035. 1);
  2036. } else {
  2037. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2038. 0);
  2039. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2040. 0);
  2041. }
  2042. sg = l_sg;
  2043. psgl++;
  2044. psgl++;
  2045. offset = 0;
  2046. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2047. sg_len = sg_dma_len(sg);
  2048. addr = (u64) sg_dma_address(sg);
  2049. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2050. lower_32_bits(addr));
  2051. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2052. upper_32_bits(addr));
  2053. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2054. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2056. offset += sg_len;
  2057. }
  2058. psgl--;
  2059. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2060. }
  2061. static void
  2062. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2063. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2064. {
  2065. struct iscsi_sge *psgl;
  2066. unsigned int sg_len, index;
  2067. unsigned int sge_len = 0;
  2068. unsigned long long addr;
  2069. struct scatterlist *l_sg;
  2070. unsigned int offset;
  2071. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2072. io_task->bhs_pa.u.a32.address_lo);
  2073. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2074. io_task->bhs_pa.u.a32.address_hi);
  2075. l_sg = sg;
  2076. for (index = 0; (index < num_sg) && (index < 2); index++,
  2077. sg = sg_next(sg)) {
  2078. if (index == 0) {
  2079. sg_len = sg_dma_len(sg);
  2080. addr = (u64) sg_dma_address(sg);
  2081. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2082. ((u32)(addr & 0xFFFFFFFF)));
  2083. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2084. ((u32)(addr >> 32)));
  2085. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2086. sg_len);
  2087. sge_len = sg_len;
  2088. } else {
  2089. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2090. pwrb, sge_len);
  2091. sg_len = sg_dma_len(sg);
  2092. addr = (u64) sg_dma_address(sg);
  2093. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2094. ((u32)(addr & 0xFFFFFFFF)));
  2095. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2096. ((u32)(addr >> 32)));
  2097. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2098. sg_len);
  2099. }
  2100. }
  2101. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2102. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2103. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2104. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2105. io_task->bhs_pa.u.a32.address_hi);
  2106. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2107. io_task->bhs_pa.u.a32.address_lo);
  2108. if (num_sg == 1) {
  2109. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2110. 1);
  2111. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2112. 0);
  2113. } else if (num_sg == 2) {
  2114. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2115. 0);
  2116. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2117. 1);
  2118. } else {
  2119. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2120. 0);
  2121. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2122. 0);
  2123. }
  2124. sg = l_sg;
  2125. psgl++;
  2126. psgl++;
  2127. offset = 0;
  2128. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2129. sg_len = sg_dma_len(sg);
  2130. addr = (u64) sg_dma_address(sg);
  2131. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2132. (addr & 0xFFFFFFFF));
  2133. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2134. (addr >> 32));
  2135. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2136. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2137. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2138. offset += sg_len;
  2139. }
  2140. psgl--;
  2141. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2142. }
  2143. /**
  2144. * hwi_write_buffer()- Populate the WRB with task info
  2145. * @pwrb: ptr to the WRB entry
  2146. * @task: iscsi task which is to be executed
  2147. **/
  2148. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2149. {
  2150. struct iscsi_sge *psgl;
  2151. struct beiscsi_io_task *io_task = task->dd_data;
  2152. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2153. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2154. uint8_t dsp_value = 0;
  2155. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2156. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2157. io_task->bhs_pa.u.a32.address_lo);
  2158. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2159. io_task->bhs_pa.u.a32.address_hi);
  2160. if (task->data) {
  2161. /* Check for the data_count */
  2162. dsp_value = (task->data_count) ? 1 : 0;
  2163. if (chip_skh_r(phba->pcidev))
  2164. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2165. pwrb, dsp_value);
  2166. else
  2167. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2168. pwrb, dsp_value);
  2169. /* Map addr only if there is data_count */
  2170. if (dsp_value) {
  2171. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2172. task->data,
  2173. task->data_count,
  2174. PCI_DMA_TODEVICE);
  2175. io_task->mtask_data_count = task->data_count;
  2176. } else
  2177. io_task->mtask_addr = 0;
  2178. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2179. lower_32_bits(io_task->mtask_addr));
  2180. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2181. upper_32_bits(io_task->mtask_addr));
  2182. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2183. task->data_count);
  2184. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2185. } else {
  2186. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2187. io_task->mtask_addr = 0;
  2188. }
  2189. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2190. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2191. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2192. io_task->bhs_pa.u.a32.address_hi);
  2193. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2194. io_task->bhs_pa.u.a32.address_lo);
  2195. if (task->data) {
  2196. psgl++;
  2197. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2198. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2199. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2200. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2201. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2202. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2203. psgl++;
  2204. if (task->data) {
  2205. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2206. lower_32_bits(io_task->mtask_addr));
  2207. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2208. upper_32_bits(io_task->mtask_addr));
  2209. }
  2210. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2211. }
  2212. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2213. }
  2214. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2215. {
  2216. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2217. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2218. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2219. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2220. sizeof(struct sol_cqe));
  2221. num_async_pdu_buf_pages =
  2222. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2223. phba->params.defpdu_hdr_sz);
  2224. num_async_pdu_buf_sgl_pages =
  2225. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2226. sizeof(struct phys_addr));
  2227. num_async_pdu_data_pages =
  2228. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2229. phba->params.defpdu_data_sz);
  2230. num_async_pdu_data_sgl_pages =
  2231. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2232. sizeof(struct phys_addr));
  2233. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2234. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2235. BE_ISCSI_PDU_HEADER_SIZE;
  2236. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2237. sizeof(struct hwi_context_memory);
  2238. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2239. * (phba->params.wrbs_per_cxn)
  2240. * phba->params.cxns_per_ctrl;
  2241. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2242. (phba->params.wrbs_per_cxn);
  2243. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2244. phba->params.cxns_per_ctrl);
  2245. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2246. phba->params.icds_per_ctrl;
  2247. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2248. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2249. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2250. num_async_pdu_buf_pages * PAGE_SIZE;
  2251. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2252. num_async_pdu_data_pages * PAGE_SIZE;
  2253. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2254. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2255. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2256. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2257. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2258. phba->params.asyncpdus_per_ctrl *
  2259. sizeof(struct async_pdu_handle);
  2260. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2261. phba->params.asyncpdus_per_ctrl *
  2262. sizeof(struct async_pdu_handle);
  2263. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2264. sizeof(struct hwi_async_pdu_context) +
  2265. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2266. }
  2267. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2268. {
  2269. struct be_mem_descriptor *mem_descr;
  2270. dma_addr_t bus_add;
  2271. struct mem_array *mem_arr, *mem_arr_orig;
  2272. unsigned int i, j, alloc_size, curr_alloc_size;
  2273. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2274. if (!phba->phwi_ctrlr)
  2275. return -ENOMEM;
  2276. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2277. GFP_KERNEL);
  2278. if (!phba->init_mem) {
  2279. kfree(phba->phwi_ctrlr);
  2280. return -ENOMEM;
  2281. }
  2282. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2283. GFP_KERNEL);
  2284. if (!mem_arr_orig) {
  2285. kfree(phba->init_mem);
  2286. kfree(phba->phwi_ctrlr);
  2287. return -ENOMEM;
  2288. }
  2289. mem_descr = phba->init_mem;
  2290. for (i = 0; i < SE_MEM_MAX; i++) {
  2291. j = 0;
  2292. mem_arr = mem_arr_orig;
  2293. alloc_size = phba->mem_req[i];
  2294. memset(mem_arr, 0, sizeof(struct mem_array) *
  2295. BEISCSI_MAX_FRAGS_INIT);
  2296. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2297. do {
  2298. mem_arr->virtual_address = pci_alloc_consistent(
  2299. phba->pcidev,
  2300. curr_alloc_size,
  2301. &bus_add);
  2302. if (!mem_arr->virtual_address) {
  2303. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2304. goto free_mem;
  2305. if (curr_alloc_size -
  2306. rounddown_pow_of_two(curr_alloc_size))
  2307. curr_alloc_size = rounddown_pow_of_two
  2308. (curr_alloc_size);
  2309. else
  2310. curr_alloc_size = curr_alloc_size / 2;
  2311. } else {
  2312. mem_arr->bus_address.u.
  2313. a64.address = (__u64) bus_add;
  2314. mem_arr->size = curr_alloc_size;
  2315. alloc_size -= curr_alloc_size;
  2316. curr_alloc_size = min(be_max_phys_size *
  2317. 1024, alloc_size);
  2318. j++;
  2319. mem_arr++;
  2320. }
  2321. } while (alloc_size);
  2322. mem_descr->num_elements = j;
  2323. mem_descr->size_in_bytes = phba->mem_req[i];
  2324. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2325. GFP_KERNEL);
  2326. if (!mem_descr->mem_array)
  2327. goto free_mem;
  2328. memcpy(mem_descr->mem_array, mem_arr_orig,
  2329. sizeof(struct mem_array) * j);
  2330. mem_descr++;
  2331. }
  2332. kfree(mem_arr_orig);
  2333. return 0;
  2334. free_mem:
  2335. mem_descr->num_elements = j;
  2336. while ((i) || (j)) {
  2337. for (j = mem_descr->num_elements; j > 0; j--) {
  2338. pci_free_consistent(phba->pcidev,
  2339. mem_descr->mem_array[j - 1].size,
  2340. mem_descr->mem_array[j - 1].
  2341. virtual_address,
  2342. (unsigned long)mem_descr->
  2343. mem_array[j - 1].
  2344. bus_address.u.a64.address);
  2345. }
  2346. if (i) {
  2347. i--;
  2348. kfree(mem_descr->mem_array);
  2349. mem_descr--;
  2350. }
  2351. }
  2352. kfree(mem_arr_orig);
  2353. kfree(phba->init_mem);
  2354. kfree(phba->phwi_ctrlr);
  2355. return -ENOMEM;
  2356. }
  2357. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2358. {
  2359. beiscsi_find_mem_req(phba);
  2360. return beiscsi_alloc_mem(phba);
  2361. }
  2362. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2363. {
  2364. struct pdu_data_out *pdata_out;
  2365. struct pdu_nop_out *pnop_out;
  2366. struct be_mem_descriptor *mem_descr;
  2367. mem_descr = phba->init_mem;
  2368. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2369. pdata_out =
  2370. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2371. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2372. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2373. IIOC_SCSI_DATA);
  2374. pnop_out =
  2375. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2376. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2377. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2378. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2379. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2380. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2381. }
  2382. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2383. {
  2384. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2385. struct wrb_handle *pwrb_handle = NULL;
  2386. struct hwi_controller *phwi_ctrlr;
  2387. struct hwi_wrb_context *pwrb_context;
  2388. struct iscsi_wrb *pwrb = NULL;
  2389. unsigned int num_cxn_wrbh = 0;
  2390. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2391. mem_descr_wrbh = phba->init_mem;
  2392. mem_descr_wrbh += HWI_MEM_WRBH;
  2393. mem_descr_wrb = phba->init_mem;
  2394. mem_descr_wrb += HWI_MEM_WRB;
  2395. phwi_ctrlr = phba->phwi_ctrlr;
  2396. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2397. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2398. pwrb_context->pwrb_handle_base =
  2399. kzalloc(sizeof(struct wrb_handle *) *
  2400. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2401. if (!pwrb_context->pwrb_handle_base) {
  2402. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2403. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2404. goto init_wrb_hndl_failed;
  2405. }
  2406. pwrb_context->pwrb_handle_basestd =
  2407. kzalloc(sizeof(struct wrb_handle *) *
  2408. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2409. if (!pwrb_context->pwrb_handle_basestd) {
  2410. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2411. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2412. goto init_wrb_hndl_failed;
  2413. }
  2414. if (!num_cxn_wrbh) {
  2415. pwrb_handle =
  2416. mem_descr_wrbh->mem_array[idx].virtual_address;
  2417. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2418. ((sizeof(struct wrb_handle)) *
  2419. phba->params.wrbs_per_cxn));
  2420. idx++;
  2421. }
  2422. pwrb_context->alloc_index = 0;
  2423. pwrb_context->wrb_handles_available = 0;
  2424. pwrb_context->free_index = 0;
  2425. if (num_cxn_wrbh) {
  2426. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2427. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2428. pwrb_context->pwrb_handle_basestd[j] =
  2429. pwrb_handle;
  2430. pwrb_context->wrb_handles_available++;
  2431. pwrb_handle->wrb_index = j;
  2432. pwrb_handle++;
  2433. }
  2434. num_cxn_wrbh--;
  2435. }
  2436. }
  2437. idx = 0;
  2438. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2439. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2440. if (!num_cxn_wrb) {
  2441. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2442. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2443. ((sizeof(struct iscsi_wrb) *
  2444. phba->params.wrbs_per_cxn));
  2445. idx++;
  2446. }
  2447. if (num_cxn_wrb) {
  2448. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2449. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2450. pwrb_handle->pwrb = pwrb;
  2451. pwrb++;
  2452. }
  2453. num_cxn_wrb--;
  2454. }
  2455. }
  2456. return 0;
  2457. init_wrb_hndl_failed:
  2458. for (j = index; j > 0; j--) {
  2459. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2460. kfree(pwrb_context->pwrb_handle_base);
  2461. kfree(pwrb_context->pwrb_handle_basestd);
  2462. }
  2463. return -ENOMEM;
  2464. }
  2465. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2466. {
  2467. struct hwi_controller *phwi_ctrlr;
  2468. struct hba_parameters *p = &phba->params;
  2469. struct hwi_async_pdu_context *pasync_ctx;
  2470. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2471. unsigned int index, idx, num_per_mem, num_async_data;
  2472. struct be_mem_descriptor *mem_descr;
  2473. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2474. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2475. phwi_ctrlr = phba->phwi_ctrlr;
  2476. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2477. mem_descr->mem_array[0].virtual_address;
  2478. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2479. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2480. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2481. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2482. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2483. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2484. if (mem_descr->mem_array[0].virtual_address) {
  2485. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2486. "BM_%d : hwi_init_async_pdu_ctx"
  2487. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2488. mem_descr->mem_array[0].virtual_address);
  2489. } else
  2490. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2491. "BM_%d : No Virtual address\n");
  2492. pasync_ctx->async_header.va_base =
  2493. mem_descr->mem_array[0].virtual_address;
  2494. pasync_ctx->async_header.pa_base.u.a64.address =
  2495. mem_descr->mem_array[0].bus_address.u.a64.address;
  2496. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2497. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2498. if (mem_descr->mem_array[0].virtual_address) {
  2499. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2500. "BM_%d : hwi_init_async_pdu_ctx"
  2501. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2502. mem_descr->mem_array[0].virtual_address);
  2503. } else
  2504. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2505. "BM_%d : No Virtual address\n");
  2506. pasync_ctx->async_header.ring_base =
  2507. mem_descr->mem_array[0].virtual_address;
  2508. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2509. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2510. if (mem_descr->mem_array[0].virtual_address) {
  2511. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2512. "BM_%d : hwi_init_async_pdu_ctx"
  2513. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2514. mem_descr->mem_array[0].virtual_address);
  2515. } else
  2516. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2517. "BM_%d : No Virtual address\n");
  2518. pasync_ctx->async_header.handle_base =
  2519. mem_descr->mem_array[0].virtual_address;
  2520. pasync_ctx->async_header.writables = 0;
  2521. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2522. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2523. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2524. if (mem_descr->mem_array[0].virtual_address) {
  2525. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2526. "BM_%d : hwi_init_async_pdu_ctx"
  2527. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2528. mem_descr->mem_array[0].virtual_address);
  2529. } else
  2530. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2531. "BM_%d : No Virtual address\n");
  2532. pasync_ctx->async_data.ring_base =
  2533. mem_descr->mem_array[0].virtual_address;
  2534. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2535. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2536. if (!mem_descr->mem_array[0].virtual_address)
  2537. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2538. "BM_%d : No Virtual address\n");
  2539. pasync_ctx->async_data.handle_base =
  2540. mem_descr->mem_array[0].virtual_address;
  2541. pasync_ctx->async_data.writables = 0;
  2542. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2543. pasync_header_h =
  2544. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2545. pasync_data_h =
  2546. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2547. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2548. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2549. if (mem_descr->mem_array[0].virtual_address) {
  2550. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2551. "BM_%d : hwi_init_async_pdu_ctx"
  2552. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2553. mem_descr->mem_array[0].virtual_address);
  2554. } else
  2555. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2556. "BM_%d : No Virtual address\n");
  2557. idx = 0;
  2558. pasync_ctx->async_data.va_base =
  2559. mem_descr->mem_array[idx].virtual_address;
  2560. pasync_ctx->async_data.pa_base.u.a64.address =
  2561. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2562. num_async_data = ((mem_descr->mem_array[idx].size) /
  2563. phba->params.defpdu_data_sz);
  2564. num_per_mem = 0;
  2565. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2566. pasync_header_h->cri = -1;
  2567. pasync_header_h->index = (char)index;
  2568. INIT_LIST_HEAD(&pasync_header_h->link);
  2569. pasync_header_h->pbuffer =
  2570. (void *)((unsigned long)
  2571. (pasync_ctx->async_header.va_base) +
  2572. (p->defpdu_hdr_sz * index));
  2573. pasync_header_h->pa.u.a64.address =
  2574. pasync_ctx->async_header.pa_base.u.a64.address +
  2575. (p->defpdu_hdr_sz * index);
  2576. list_add_tail(&pasync_header_h->link,
  2577. &pasync_ctx->async_header.free_list);
  2578. pasync_header_h++;
  2579. pasync_ctx->async_header.free_entries++;
  2580. pasync_ctx->async_header.writables++;
  2581. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2582. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2583. header_busy_list);
  2584. pasync_data_h->cri = -1;
  2585. pasync_data_h->index = (char)index;
  2586. INIT_LIST_HEAD(&pasync_data_h->link);
  2587. if (!num_async_data) {
  2588. num_per_mem = 0;
  2589. idx++;
  2590. pasync_ctx->async_data.va_base =
  2591. mem_descr->mem_array[idx].virtual_address;
  2592. pasync_ctx->async_data.pa_base.u.a64.address =
  2593. mem_descr->mem_array[idx].
  2594. bus_address.u.a64.address;
  2595. num_async_data = ((mem_descr->mem_array[idx].size) /
  2596. phba->params.defpdu_data_sz);
  2597. }
  2598. pasync_data_h->pbuffer =
  2599. (void *)((unsigned long)
  2600. (pasync_ctx->async_data.va_base) +
  2601. (p->defpdu_data_sz * num_per_mem));
  2602. pasync_data_h->pa.u.a64.address =
  2603. pasync_ctx->async_data.pa_base.u.a64.address +
  2604. (p->defpdu_data_sz * num_per_mem);
  2605. num_per_mem++;
  2606. num_async_data--;
  2607. list_add_tail(&pasync_data_h->link,
  2608. &pasync_ctx->async_data.free_list);
  2609. pasync_data_h++;
  2610. pasync_ctx->async_data.free_entries++;
  2611. pasync_ctx->async_data.writables++;
  2612. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2613. }
  2614. pasync_ctx->async_header.host_write_ptr = 0;
  2615. pasync_ctx->async_header.ep_read_ptr = -1;
  2616. pasync_ctx->async_data.host_write_ptr = 0;
  2617. pasync_ctx->async_data.ep_read_ptr = -1;
  2618. }
  2619. static int
  2620. be_sgl_create_contiguous(void *virtual_address,
  2621. u64 physical_address, u32 length,
  2622. struct be_dma_mem *sgl)
  2623. {
  2624. WARN_ON(!virtual_address);
  2625. WARN_ON(!physical_address);
  2626. WARN_ON(!length > 0);
  2627. WARN_ON(!sgl);
  2628. sgl->va = virtual_address;
  2629. sgl->dma = (unsigned long)physical_address;
  2630. sgl->size = length;
  2631. return 0;
  2632. }
  2633. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2634. {
  2635. memset(sgl, 0, sizeof(*sgl));
  2636. }
  2637. static void
  2638. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2639. struct mem_array *pmem, struct be_dma_mem *sgl)
  2640. {
  2641. if (sgl->va)
  2642. be_sgl_destroy_contiguous(sgl);
  2643. be_sgl_create_contiguous(pmem->virtual_address,
  2644. pmem->bus_address.u.a64.address,
  2645. pmem->size, sgl);
  2646. }
  2647. static void
  2648. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2649. struct mem_array *pmem, struct be_dma_mem *sgl)
  2650. {
  2651. if (sgl->va)
  2652. be_sgl_destroy_contiguous(sgl);
  2653. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2654. pmem->bus_address.u.a64.address,
  2655. pmem->size, sgl);
  2656. }
  2657. static int be_fill_queue(struct be_queue_info *q,
  2658. u16 len, u16 entry_size, void *vaddress)
  2659. {
  2660. struct be_dma_mem *mem = &q->dma_mem;
  2661. memset(q, 0, sizeof(*q));
  2662. q->len = len;
  2663. q->entry_size = entry_size;
  2664. mem->size = len * entry_size;
  2665. mem->va = vaddress;
  2666. if (!mem->va)
  2667. return -ENOMEM;
  2668. memset(mem->va, 0, mem->size);
  2669. return 0;
  2670. }
  2671. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2672. struct hwi_context_memory *phwi_context)
  2673. {
  2674. unsigned int i, num_eq_pages;
  2675. int ret = 0, eq_for_mcc;
  2676. struct be_queue_info *eq;
  2677. struct be_dma_mem *mem;
  2678. void *eq_vaddress;
  2679. dma_addr_t paddr;
  2680. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2681. sizeof(struct be_eq_entry));
  2682. if (phba->msix_enabled)
  2683. eq_for_mcc = 1;
  2684. else
  2685. eq_for_mcc = 0;
  2686. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2687. eq = &phwi_context->be_eq[i].q;
  2688. mem = &eq->dma_mem;
  2689. phwi_context->be_eq[i].phba = phba;
  2690. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2691. num_eq_pages * PAGE_SIZE,
  2692. &paddr);
  2693. if (!eq_vaddress)
  2694. goto create_eq_error;
  2695. mem->va = eq_vaddress;
  2696. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2697. sizeof(struct be_eq_entry), eq_vaddress);
  2698. if (ret) {
  2699. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2700. "BM_%d : be_fill_queue Failed for EQ\n");
  2701. goto create_eq_error;
  2702. }
  2703. mem->dma = paddr;
  2704. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2705. phwi_context->cur_eqd);
  2706. if (ret) {
  2707. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2708. "BM_%d : beiscsi_cmd_eq_create"
  2709. "Failed for EQ\n");
  2710. goto create_eq_error;
  2711. }
  2712. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2713. "BM_%d : eqid = %d\n",
  2714. phwi_context->be_eq[i].q.id);
  2715. }
  2716. return 0;
  2717. create_eq_error:
  2718. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2719. eq = &phwi_context->be_eq[i].q;
  2720. mem = &eq->dma_mem;
  2721. if (mem->va)
  2722. pci_free_consistent(phba->pcidev, num_eq_pages
  2723. * PAGE_SIZE,
  2724. mem->va, mem->dma);
  2725. }
  2726. return ret;
  2727. }
  2728. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2729. struct hwi_context_memory *phwi_context)
  2730. {
  2731. unsigned int i, num_cq_pages;
  2732. int ret = 0;
  2733. struct be_queue_info *cq, *eq;
  2734. struct be_dma_mem *mem;
  2735. struct be_eq_obj *pbe_eq;
  2736. void *cq_vaddress;
  2737. dma_addr_t paddr;
  2738. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2739. sizeof(struct sol_cqe));
  2740. for (i = 0; i < phba->num_cpus; i++) {
  2741. cq = &phwi_context->be_cq[i];
  2742. eq = &phwi_context->be_eq[i].q;
  2743. pbe_eq = &phwi_context->be_eq[i];
  2744. pbe_eq->cq = cq;
  2745. pbe_eq->phba = phba;
  2746. mem = &cq->dma_mem;
  2747. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2748. num_cq_pages * PAGE_SIZE,
  2749. &paddr);
  2750. if (!cq_vaddress)
  2751. goto create_cq_error;
  2752. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2753. sizeof(struct sol_cqe), cq_vaddress);
  2754. if (ret) {
  2755. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2756. "BM_%d : be_fill_queue Failed "
  2757. "for ISCSI CQ\n");
  2758. goto create_cq_error;
  2759. }
  2760. mem->dma = paddr;
  2761. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2762. false, 0);
  2763. if (ret) {
  2764. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2765. "BM_%d : beiscsi_cmd_eq_create"
  2766. "Failed for ISCSI CQ\n");
  2767. goto create_cq_error;
  2768. }
  2769. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2770. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2771. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2772. }
  2773. return 0;
  2774. create_cq_error:
  2775. for (i = 0; i < phba->num_cpus; i++) {
  2776. cq = &phwi_context->be_cq[i];
  2777. mem = &cq->dma_mem;
  2778. if (mem->va)
  2779. pci_free_consistent(phba->pcidev, num_cq_pages
  2780. * PAGE_SIZE,
  2781. mem->va, mem->dma);
  2782. }
  2783. return ret;
  2784. }
  2785. static int
  2786. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2787. struct hwi_context_memory *phwi_context,
  2788. struct hwi_controller *phwi_ctrlr,
  2789. unsigned int def_pdu_ring_sz)
  2790. {
  2791. unsigned int idx;
  2792. int ret;
  2793. struct be_queue_info *dq, *cq;
  2794. struct be_dma_mem *mem;
  2795. struct be_mem_descriptor *mem_descr;
  2796. void *dq_vaddress;
  2797. idx = 0;
  2798. dq = &phwi_context->be_def_hdrq;
  2799. cq = &phwi_context->be_cq[0];
  2800. mem = &dq->dma_mem;
  2801. mem_descr = phba->init_mem;
  2802. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2803. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2804. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2805. sizeof(struct phys_addr),
  2806. sizeof(struct phys_addr), dq_vaddress);
  2807. if (ret) {
  2808. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2809. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2810. return ret;
  2811. }
  2812. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2813. bus_address.u.a64.address;
  2814. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2815. def_pdu_ring_sz,
  2816. phba->params.defpdu_hdr_sz);
  2817. if (ret) {
  2818. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2819. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2820. return ret;
  2821. }
  2822. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2823. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2824. "BM_%d : iscsi def pdu id is %d\n",
  2825. phwi_context->be_def_hdrq.id);
  2826. hwi_post_async_buffers(phba, 1);
  2827. return 0;
  2828. }
  2829. static int
  2830. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2831. struct hwi_context_memory *phwi_context,
  2832. struct hwi_controller *phwi_ctrlr,
  2833. unsigned int def_pdu_ring_sz)
  2834. {
  2835. unsigned int idx;
  2836. int ret;
  2837. struct be_queue_info *dataq, *cq;
  2838. struct be_dma_mem *mem;
  2839. struct be_mem_descriptor *mem_descr;
  2840. void *dq_vaddress;
  2841. idx = 0;
  2842. dataq = &phwi_context->be_def_dataq;
  2843. cq = &phwi_context->be_cq[0];
  2844. mem = &dataq->dma_mem;
  2845. mem_descr = phba->init_mem;
  2846. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2847. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2848. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2849. sizeof(struct phys_addr),
  2850. sizeof(struct phys_addr), dq_vaddress);
  2851. if (ret) {
  2852. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2853. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2854. return ret;
  2855. }
  2856. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2857. bus_address.u.a64.address;
  2858. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2859. def_pdu_ring_sz,
  2860. phba->params.defpdu_data_sz);
  2861. if (ret) {
  2862. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2863. "BM_%d be_cmd_create_default_pdu_queue"
  2864. " Failed for DEF PDU DATA\n");
  2865. return ret;
  2866. }
  2867. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2868. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2869. "BM_%d : iscsi def data id is %d\n",
  2870. phwi_context->be_def_dataq.id);
  2871. hwi_post_async_buffers(phba, 0);
  2872. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2873. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2874. return 0;
  2875. }
  2876. static int
  2877. beiscsi_post_pages(struct beiscsi_hba *phba)
  2878. {
  2879. struct be_mem_descriptor *mem_descr;
  2880. struct mem_array *pm_arr;
  2881. unsigned int page_offset, i;
  2882. struct be_dma_mem sgl;
  2883. int status;
  2884. mem_descr = phba->init_mem;
  2885. mem_descr += HWI_MEM_SGE;
  2886. pm_arr = mem_descr->mem_array;
  2887. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2888. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2889. for (i = 0; i < mem_descr->num_elements; i++) {
  2890. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2891. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2892. page_offset,
  2893. (pm_arr->size / PAGE_SIZE));
  2894. page_offset += pm_arr->size / PAGE_SIZE;
  2895. if (status != 0) {
  2896. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2897. "BM_%d : post sgl failed.\n");
  2898. return status;
  2899. }
  2900. pm_arr++;
  2901. }
  2902. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2903. "BM_%d : POSTED PAGES\n");
  2904. return 0;
  2905. }
  2906. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2907. {
  2908. struct be_dma_mem *mem = &q->dma_mem;
  2909. if (mem->va) {
  2910. pci_free_consistent(phba->pcidev, mem->size,
  2911. mem->va, mem->dma);
  2912. mem->va = NULL;
  2913. }
  2914. }
  2915. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2916. u16 len, u16 entry_size)
  2917. {
  2918. struct be_dma_mem *mem = &q->dma_mem;
  2919. memset(q, 0, sizeof(*q));
  2920. q->len = len;
  2921. q->entry_size = entry_size;
  2922. mem->size = len * entry_size;
  2923. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2924. if (!mem->va)
  2925. return -ENOMEM;
  2926. memset(mem->va, 0, mem->size);
  2927. return 0;
  2928. }
  2929. static int
  2930. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2931. struct hwi_context_memory *phwi_context,
  2932. struct hwi_controller *phwi_ctrlr)
  2933. {
  2934. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2935. u64 pa_addr_lo;
  2936. unsigned int idx, num, i;
  2937. struct mem_array *pwrb_arr;
  2938. void *wrb_vaddr;
  2939. struct be_dma_mem sgl;
  2940. struct be_mem_descriptor *mem_descr;
  2941. int status;
  2942. idx = 0;
  2943. mem_descr = phba->init_mem;
  2944. mem_descr += HWI_MEM_WRB;
  2945. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2946. GFP_KERNEL);
  2947. if (!pwrb_arr) {
  2948. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2949. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2950. return -ENOMEM;
  2951. }
  2952. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2953. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2954. num_wrb_rings = mem_descr->mem_array[idx].size /
  2955. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2956. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2957. if (num_wrb_rings) {
  2958. pwrb_arr[num].virtual_address = wrb_vaddr;
  2959. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2960. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2961. sizeof(struct iscsi_wrb);
  2962. wrb_vaddr += pwrb_arr[num].size;
  2963. pa_addr_lo += pwrb_arr[num].size;
  2964. num_wrb_rings--;
  2965. } else {
  2966. idx++;
  2967. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2968. pa_addr_lo = mem_descr->mem_array[idx].\
  2969. bus_address.u.a64.address;
  2970. num_wrb_rings = mem_descr->mem_array[idx].size /
  2971. (phba->params.wrbs_per_cxn *
  2972. sizeof(struct iscsi_wrb));
  2973. pwrb_arr[num].virtual_address = wrb_vaddr;
  2974. pwrb_arr[num].bus_address.u.a64.address\
  2975. = pa_addr_lo;
  2976. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2977. sizeof(struct iscsi_wrb);
  2978. wrb_vaddr += pwrb_arr[num].size;
  2979. pa_addr_lo += pwrb_arr[num].size;
  2980. num_wrb_rings--;
  2981. }
  2982. }
  2983. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2984. wrb_mem_index = 0;
  2985. offset = 0;
  2986. size = 0;
  2987. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2988. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2989. &phwi_context->be_wrbq[i]);
  2990. if (status != 0) {
  2991. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2992. "BM_%d : wrbq create failed.");
  2993. kfree(pwrb_arr);
  2994. return status;
  2995. }
  2996. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2997. id;
  2998. }
  2999. kfree(pwrb_arr);
  3000. return 0;
  3001. }
  3002. static void free_wrb_handles(struct beiscsi_hba *phba)
  3003. {
  3004. unsigned int index;
  3005. struct hwi_controller *phwi_ctrlr;
  3006. struct hwi_wrb_context *pwrb_context;
  3007. phwi_ctrlr = phba->phwi_ctrlr;
  3008. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  3009. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3010. kfree(pwrb_context->pwrb_handle_base);
  3011. kfree(pwrb_context->pwrb_handle_basestd);
  3012. }
  3013. }
  3014. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3015. {
  3016. struct be_queue_info *q;
  3017. struct be_ctrl_info *ctrl = &phba->ctrl;
  3018. q = &phba->ctrl.mcc_obj.q;
  3019. if (q->created)
  3020. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3021. be_queue_free(phba, q);
  3022. q = &phba->ctrl.mcc_obj.cq;
  3023. if (q->created)
  3024. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3025. be_queue_free(phba, q);
  3026. }
  3027. static void hwi_cleanup(struct beiscsi_hba *phba)
  3028. {
  3029. struct be_queue_info *q;
  3030. struct be_ctrl_info *ctrl = &phba->ctrl;
  3031. struct hwi_controller *phwi_ctrlr;
  3032. struct hwi_context_memory *phwi_context;
  3033. int i, eq_num;
  3034. phwi_ctrlr = phba->phwi_ctrlr;
  3035. phwi_context = phwi_ctrlr->phwi_ctxt;
  3036. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3037. q = &phwi_context->be_wrbq[i];
  3038. if (q->created)
  3039. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3040. }
  3041. free_wrb_handles(phba);
  3042. q = &phwi_context->be_def_hdrq;
  3043. if (q->created)
  3044. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3045. q = &phwi_context->be_def_dataq;
  3046. if (q->created)
  3047. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3048. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3049. for (i = 0; i < (phba->num_cpus); i++) {
  3050. q = &phwi_context->be_cq[i];
  3051. if (q->created)
  3052. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3053. }
  3054. if (phba->msix_enabled)
  3055. eq_num = 1;
  3056. else
  3057. eq_num = 0;
  3058. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3059. q = &phwi_context->be_eq[i].q;
  3060. if (q->created)
  3061. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3062. }
  3063. be_mcc_queues_destroy(phba);
  3064. }
  3065. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3066. struct hwi_context_memory *phwi_context)
  3067. {
  3068. struct be_queue_info *q, *cq;
  3069. struct be_ctrl_info *ctrl = &phba->ctrl;
  3070. /* Alloc MCC compl queue */
  3071. cq = &phba->ctrl.mcc_obj.cq;
  3072. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3073. sizeof(struct be_mcc_compl)))
  3074. goto err;
  3075. /* Ask BE to create MCC compl queue; */
  3076. if (phba->msix_enabled) {
  3077. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3078. [phba->num_cpus].q, false, true, 0))
  3079. goto mcc_cq_free;
  3080. } else {
  3081. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3082. false, true, 0))
  3083. goto mcc_cq_free;
  3084. }
  3085. /* Alloc MCC queue */
  3086. q = &phba->ctrl.mcc_obj.q;
  3087. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3088. goto mcc_cq_destroy;
  3089. /* Ask BE to create MCC queue */
  3090. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3091. goto mcc_q_free;
  3092. return 0;
  3093. mcc_q_free:
  3094. be_queue_free(phba, q);
  3095. mcc_cq_destroy:
  3096. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3097. mcc_cq_free:
  3098. be_queue_free(phba, cq);
  3099. err:
  3100. return -ENOMEM;
  3101. }
  3102. /**
  3103. * find_num_cpus()- Get the CPU online count
  3104. * @phba: ptr to priv structure
  3105. *
  3106. * CPU count is used for creating EQ.
  3107. **/
  3108. static void find_num_cpus(struct beiscsi_hba *phba)
  3109. {
  3110. int num_cpus = 0;
  3111. num_cpus = num_online_cpus();
  3112. switch (phba->generation) {
  3113. case BE_GEN2:
  3114. case BE_GEN3:
  3115. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3116. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3117. break;
  3118. case BE_GEN4:
  3119. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3120. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3121. break;
  3122. default:
  3123. phba->num_cpus = 1;
  3124. }
  3125. }
  3126. static int hwi_init_port(struct beiscsi_hba *phba)
  3127. {
  3128. struct hwi_controller *phwi_ctrlr;
  3129. struct hwi_context_memory *phwi_context;
  3130. unsigned int def_pdu_ring_sz;
  3131. struct be_ctrl_info *ctrl = &phba->ctrl;
  3132. int status;
  3133. def_pdu_ring_sz =
  3134. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  3135. phwi_ctrlr = phba->phwi_ctrlr;
  3136. phwi_context = phwi_ctrlr->phwi_ctxt;
  3137. phwi_context->max_eqd = 0;
  3138. phwi_context->min_eqd = 0;
  3139. phwi_context->cur_eqd = 64;
  3140. be_cmd_fw_initialize(&phba->ctrl);
  3141. status = beiscsi_create_eqs(phba, phwi_context);
  3142. if (status != 0) {
  3143. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3144. "BM_%d : EQ not created\n");
  3145. goto error;
  3146. }
  3147. status = be_mcc_queues_create(phba, phwi_context);
  3148. if (status != 0)
  3149. goto error;
  3150. status = mgmt_check_supported_fw(ctrl, phba);
  3151. if (status != 0) {
  3152. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3153. "BM_%d : Unsupported fw version\n");
  3154. goto error;
  3155. }
  3156. status = beiscsi_create_cqs(phba, phwi_context);
  3157. if (status != 0) {
  3158. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3159. "BM_%d : CQ not created\n");
  3160. goto error;
  3161. }
  3162. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3163. def_pdu_ring_sz);
  3164. if (status != 0) {
  3165. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3166. "BM_%d : Default Header not created\n");
  3167. goto error;
  3168. }
  3169. status = beiscsi_create_def_data(phba, phwi_context,
  3170. phwi_ctrlr, def_pdu_ring_sz);
  3171. if (status != 0) {
  3172. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3173. "BM_%d : Default Data not created\n");
  3174. goto error;
  3175. }
  3176. status = beiscsi_post_pages(phba);
  3177. if (status != 0) {
  3178. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3179. "BM_%d : Post SGL Pages Failed\n");
  3180. goto error;
  3181. }
  3182. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3183. if (status != 0) {
  3184. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3185. "BM_%d : WRB Rings not created\n");
  3186. goto error;
  3187. }
  3188. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3189. "BM_%d : hwi_init_port success\n");
  3190. return 0;
  3191. error:
  3192. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3193. "BM_%d : hwi_init_port failed");
  3194. hwi_cleanup(phba);
  3195. return status;
  3196. }
  3197. static int hwi_init_controller(struct beiscsi_hba *phba)
  3198. {
  3199. struct hwi_controller *phwi_ctrlr;
  3200. phwi_ctrlr = phba->phwi_ctrlr;
  3201. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3202. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3203. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3204. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3205. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3206. phwi_ctrlr->phwi_ctxt);
  3207. } else {
  3208. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3209. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3210. "than one element.Failing to load\n");
  3211. return -ENOMEM;
  3212. }
  3213. iscsi_init_global_templates(phba);
  3214. if (beiscsi_init_wrb_handle(phba))
  3215. return -ENOMEM;
  3216. hwi_init_async_pdu_ctx(phba);
  3217. if (hwi_init_port(phba) != 0) {
  3218. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3219. "BM_%d : hwi_init_controller failed\n");
  3220. return -ENOMEM;
  3221. }
  3222. return 0;
  3223. }
  3224. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3225. {
  3226. struct be_mem_descriptor *mem_descr;
  3227. int i, j;
  3228. mem_descr = phba->init_mem;
  3229. i = 0;
  3230. j = 0;
  3231. for (i = 0; i < SE_MEM_MAX; i++) {
  3232. for (j = mem_descr->num_elements; j > 0; j--) {
  3233. pci_free_consistent(phba->pcidev,
  3234. mem_descr->mem_array[j - 1].size,
  3235. mem_descr->mem_array[j - 1].virtual_address,
  3236. (unsigned long)mem_descr->mem_array[j - 1].
  3237. bus_address.u.a64.address);
  3238. }
  3239. kfree(mem_descr->mem_array);
  3240. mem_descr++;
  3241. }
  3242. kfree(phba->init_mem);
  3243. kfree(phba->phwi_ctrlr);
  3244. }
  3245. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3246. {
  3247. int ret = -ENOMEM;
  3248. ret = beiscsi_get_memory(phba);
  3249. if (ret < 0) {
  3250. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3251. "BM_%d : beiscsi_dev_probe -"
  3252. "Failed in beiscsi_alloc_memory\n");
  3253. return ret;
  3254. }
  3255. ret = hwi_init_controller(phba);
  3256. if (ret)
  3257. goto free_init;
  3258. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3259. "BM_%d : Return success from beiscsi_init_controller");
  3260. return 0;
  3261. free_init:
  3262. beiscsi_free_mem(phba);
  3263. return ret;
  3264. }
  3265. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3266. {
  3267. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3268. struct sgl_handle *psgl_handle;
  3269. struct iscsi_sge *pfrag;
  3270. unsigned int arr_index, i, idx;
  3271. phba->io_sgl_hndl_avbl = 0;
  3272. phba->eh_sgl_hndl_avbl = 0;
  3273. mem_descr_sglh = phba->init_mem;
  3274. mem_descr_sglh += HWI_MEM_SGLH;
  3275. if (1 == mem_descr_sglh->num_elements) {
  3276. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3277. phba->params.ios_per_ctrl,
  3278. GFP_KERNEL);
  3279. if (!phba->io_sgl_hndl_base) {
  3280. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3281. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3282. return -ENOMEM;
  3283. }
  3284. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3285. (phba->params.icds_per_ctrl -
  3286. phba->params.ios_per_ctrl),
  3287. GFP_KERNEL);
  3288. if (!phba->eh_sgl_hndl_base) {
  3289. kfree(phba->io_sgl_hndl_base);
  3290. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3291. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3292. return -ENOMEM;
  3293. }
  3294. } else {
  3295. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3296. "BM_%d : HWI_MEM_SGLH is more than one element."
  3297. "Failing to load\n");
  3298. return -ENOMEM;
  3299. }
  3300. arr_index = 0;
  3301. idx = 0;
  3302. while (idx < mem_descr_sglh->num_elements) {
  3303. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3304. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3305. sizeof(struct sgl_handle)); i++) {
  3306. if (arr_index < phba->params.ios_per_ctrl) {
  3307. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3308. phba->io_sgl_hndl_avbl++;
  3309. arr_index++;
  3310. } else {
  3311. phba->eh_sgl_hndl_base[arr_index -
  3312. phba->params.ios_per_ctrl] =
  3313. psgl_handle;
  3314. arr_index++;
  3315. phba->eh_sgl_hndl_avbl++;
  3316. }
  3317. psgl_handle++;
  3318. }
  3319. idx++;
  3320. }
  3321. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3322. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3323. "phba->eh_sgl_hndl_avbl=%d\n",
  3324. phba->io_sgl_hndl_avbl,
  3325. phba->eh_sgl_hndl_avbl);
  3326. mem_descr_sg = phba->init_mem;
  3327. mem_descr_sg += HWI_MEM_SGE;
  3328. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3329. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3330. mem_descr_sg->num_elements);
  3331. arr_index = 0;
  3332. idx = 0;
  3333. while (idx < mem_descr_sg->num_elements) {
  3334. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3335. for (i = 0;
  3336. i < (mem_descr_sg->mem_array[idx].size) /
  3337. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3338. i++) {
  3339. if (arr_index < phba->params.ios_per_ctrl)
  3340. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3341. else
  3342. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3343. phba->params.ios_per_ctrl];
  3344. psgl_handle->pfrag = pfrag;
  3345. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3346. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3347. pfrag += phba->params.num_sge_per_io;
  3348. psgl_handle->sgl_index =
  3349. phba->fw_config.iscsi_icd_start + arr_index++;
  3350. }
  3351. idx++;
  3352. }
  3353. phba->io_sgl_free_index = 0;
  3354. phba->io_sgl_alloc_index = 0;
  3355. phba->eh_sgl_free_index = 0;
  3356. phba->eh_sgl_alloc_index = 0;
  3357. return 0;
  3358. }
  3359. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3360. {
  3361. int i, new_cid;
  3362. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3363. GFP_KERNEL);
  3364. if (!phba->cid_array) {
  3365. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3366. "BM_%d : Failed to allocate memory in "
  3367. "hba_setup_cid_tbls\n");
  3368. return -ENOMEM;
  3369. }
  3370. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3371. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3372. if (!phba->ep_array) {
  3373. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3374. "BM_%d : Failed to allocate memory in "
  3375. "hba_setup_cid_tbls\n");
  3376. kfree(phba->cid_array);
  3377. return -ENOMEM;
  3378. }
  3379. new_cid = phba->fw_config.iscsi_cid_start;
  3380. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3381. phba->cid_array[i] = new_cid;
  3382. new_cid += 2;
  3383. }
  3384. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3385. return 0;
  3386. }
  3387. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3388. {
  3389. struct be_ctrl_info *ctrl = &phba->ctrl;
  3390. struct hwi_controller *phwi_ctrlr;
  3391. struct hwi_context_memory *phwi_context;
  3392. struct be_queue_info *eq;
  3393. u8 __iomem *addr;
  3394. u32 reg, i;
  3395. u32 enabled;
  3396. phwi_ctrlr = phba->phwi_ctrlr;
  3397. phwi_context = phwi_ctrlr->phwi_ctxt;
  3398. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3399. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3400. reg = ioread32(addr);
  3401. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3402. if (!enabled) {
  3403. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3404. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3405. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3406. iowrite32(reg, addr);
  3407. }
  3408. if (!phba->msix_enabled) {
  3409. eq = &phwi_context->be_eq[0].q;
  3410. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3411. "BM_%d : eq->id=%d\n", eq->id);
  3412. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3413. } else {
  3414. for (i = 0; i <= phba->num_cpus; i++) {
  3415. eq = &phwi_context->be_eq[i].q;
  3416. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3417. "BM_%d : eq->id=%d\n", eq->id);
  3418. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3419. }
  3420. }
  3421. }
  3422. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3423. {
  3424. struct be_ctrl_info *ctrl = &phba->ctrl;
  3425. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3426. u32 reg = ioread32(addr);
  3427. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3428. if (enabled) {
  3429. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3430. iowrite32(reg, addr);
  3431. } else
  3432. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3433. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3434. }
  3435. /**
  3436. * beiscsi_get_boot_info()- Get the boot session info
  3437. * @phba: The device priv structure instance
  3438. *
  3439. * Get the boot target info and store in driver priv structure
  3440. *
  3441. * return values
  3442. * Success: 0
  3443. * Failure: Non-Zero Value
  3444. **/
  3445. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3446. {
  3447. struct be_cmd_get_session_resp *session_resp;
  3448. struct be_dma_mem nonemb_cmd;
  3449. unsigned int tag;
  3450. unsigned int s_handle;
  3451. int ret = -ENOMEM;
  3452. /* Get the session handle of the boot target */
  3453. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3454. if (ret) {
  3455. beiscsi_log(phba, KERN_ERR,
  3456. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3457. "BM_%d : No boot session\n");
  3458. return ret;
  3459. }
  3460. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3461. sizeof(*session_resp),
  3462. &nonemb_cmd.dma);
  3463. if (nonemb_cmd.va == NULL) {
  3464. beiscsi_log(phba, KERN_ERR,
  3465. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3466. "BM_%d : Failed to allocate memory for"
  3467. "beiscsi_get_session_info\n");
  3468. return -ENOMEM;
  3469. }
  3470. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3471. tag = mgmt_get_session_info(phba, s_handle,
  3472. &nonemb_cmd);
  3473. if (!tag) {
  3474. beiscsi_log(phba, KERN_ERR,
  3475. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3476. "BM_%d : beiscsi_get_session_info"
  3477. " Failed\n");
  3478. goto boot_freemem;
  3479. }
  3480. ret = beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  3481. if (ret) {
  3482. beiscsi_log(phba, KERN_ERR,
  3483. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3484. "BM_%d : beiscsi_get_session_info Failed");
  3485. goto boot_freemem;
  3486. }
  3487. session_resp = nonemb_cmd.va ;
  3488. memcpy(&phba->boot_sess, &session_resp->session_info,
  3489. sizeof(struct mgmt_session_info));
  3490. ret = 0;
  3491. boot_freemem:
  3492. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3493. nonemb_cmd.va, nonemb_cmd.dma);
  3494. return ret;
  3495. }
  3496. static void beiscsi_boot_release(void *data)
  3497. {
  3498. struct beiscsi_hba *phba = data;
  3499. scsi_host_put(phba->shost);
  3500. }
  3501. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3502. {
  3503. struct iscsi_boot_kobj *boot_kobj;
  3504. /* get boot info using mgmt cmd */
  3505. if (beiscsi_get_boot_info(phba))
  3506. /* Try to see if we can carry on without this */
  3507. return 0;
  3508. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3509. if (!phba->boot_kset)
  3510. return -ENOMEM;
  3511. /* get a ref because the show function will ref the phba */
  3512. if (!scsi_host_get(phba->shost))
  3513. goto free_kset;
  3514. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3515. beiscsi_show_boot_tgt_info,
  3516. beiscsi_tgt_get_attr_visibility,
  3517. beiscsi_boot_release);
  3518. if (!boot_kobj)
  3519. goto put_shost;
  3520. if (!scsi_host_get(phba->shost))
  3521. goto free_kset;
  3522. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3523. beiscsi_show_boot_ini_info,
  3524. beiscsi_ini_get_attr_visibility,
  3525. beiscsi_boot_release);
  3526. if (!boot_kobj)
  3527. goto put_shost;
  3528. if (!scsi_host_get(phba->shost))
  3529. goto free_kset;
  3530. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3531. beiscsi_show_boot_eth_info,
  3532. beiscsi_eth_get_attr_visibility,
  3533. beiscsi_boot_release);
  3534. if (!boot_kobj)
  3535. goto put_shost;
  3536. return 0;
  3537. put_shost:
  3538. scsi_host_put(phba->shost);
  3539. free_kset:
  3540. iscsi_boot_destroy_kset(phba->boot_kset);
  3541. return -ENOMEM;
  3542. }
  3543. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3544. {
  3545. int ret;
  3546. ret = beiscsi_init_controller(phba);
  3547. if (ret < 0) {
  3548. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3549. "BM_%d : beiscsi_dev_probe - Failed in"
  3550. "beiscsi_init_controller\n");
  3551. return ret;
  3552. }
  3553. ret = beiscsi_init_sgl_handle(phba);
  3554. if (ret < 0) {
  3555. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3556. "BM_%d : beiscsi_dev_probe - Failed in"
  3557. "beiscsi_init_sgl_handle\n");
  3558. goto do_cleanup_ctrlr;
  3559. }
  3560. if (hba_setup_cid_tbls(phba)) {
  3561. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3562. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3563. kfree(phba->io_sgl_hndl_base);
  3564. kfree(phba->eh_sgl_hndl_base);
  3565. goto do_cleanup_ctrlr;
  3566. }
  3567. return ret;
  3568. do_cleanup_ctrlr:
  3569. hwi_cleanup(phba);
  3570. return ret;
  3571. }
  3572. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3573. {
  3574. struct hwi_controller *phwi_ctrlr;
  3575. struct hwi_context_memory *phwi_context;
  3576. struct be_queue_info *eq;
  3577. struct be_eq_entry *eqe = NULL;
  3578. int i, eq_msix;
  3579. unsigned int num_processed;
  3580. phwi_ctrlr = phba->phwi_ctrlr;
  3581. phwi_context = phwi_ctrlr->phwi_ctxt;
  3582. if (phba->msix_enabled)
  3583. eq_msix = 1;
  3584. else
  3585. eq_msix = 0;
  3586. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3587. eq = &phwi_context->be_eq[i].q;
  3588. eqe = queue_tail_node(eq);
  3589. num_processed = 0;
  3590. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3591. & EQE_VALID_MASK) {
  3592. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3593. queue_tail_inc(eq);
  3594. eqe = queue_tail_node(eq);
  3595. num_processed++;
  3596. }
  3597. if (num_processed)
  3598. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3599. }
  3600. }
  3601. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3602. {
  3603. int mgmt_status;
  3604. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3605. if (mgmt_status)
  3606. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3607. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3608. hwi_purge_eq(phba);
  3609. hwi_cleanup(phba);
  3610. kfree(phba->io_sgl_hndl_base);
  3611. kfree(phba->eh_sgl_hndl_base);
  3612. kfree(phba->cid_array);
  3613. kfree(phba->ep_array);
  3614. }
  3615. /**
  3616. * beiscsi_cleanup_task()- Free driver resources of the task
  3617. * @task: ptr to the iscsi task
  3618. *
  3619. **/
  3620. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3621. {
  3622. struct beiscsi_io_task *io_task = task->dd_data;
  3623. struct iscsi_conn *conn = task->conn;
  3624. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3625. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3626. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3627. struct hwi_wrb_context *pwrb_context;
  3628. struct hwi_controller *phwi_ctrlr;
  3629. phwi_ctrlr = phba->phwi_ctrlr;
  3630. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3631. - phba->fw_config.iscsi_cid_start];
  3632. if (io_task->cmd_bhs) {
  3633. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3634. io_task->bhs_pa.u.a64.address);
  3635. io_task->cmd_bhs = NULL;
  3636. }
  3637. if (task->sc) {
  3638. if (io_task->pwrb_handle) {
  3639. free_wrb_handle(phba, pwrb_context,
  3640. io_task->pwrb_handle);
  3641. io_task->pwrb_handle = NULL;
  3642. }
  3643. if (io_task->psgl_handle) {
  3644. spin_lock(&phba->io_sgl_lock);
  3645. free_io_sgl_handle(phba, io_task->psgl_handle);
  3646. spin_unlock(&phba->io_sgl_lock);
  3647. io_task->psgl_handle = NULL;
  3648. }
  3649. } else {
  3650. if (!beiscsi_conn->login_in_progress) {
  3651. if (io_task->pwrb_handle) {
  3652. free_wrb_handle(phba, pwrb_context,
  3653. io_task->pwrb_handle);
  3654. io_task->pwrb_handle = NULL;
  3655. }
  3656. if (io_task->psgl_handle) {
  3657. spin_lock(&phba->mgmt_sgl_lock);
  3658. free_mgmt_sgl_handle(phba,
  3659. io_task->psgl_handle);
  3660. spin_unlock(&phba->mgmt_sgl_lock);
  3661. io_task->psgl_handle = NULL;
  3662. }
  3663. if (io_task->mtask_addr) {
  3664. pci_unmap_single(phba->pcidev,
  3665. io_task->mtask_addr,
  3666. io_task->mtask_data_count,
  3667. PCI_DMA_TODEVICE);
  3668. io_task->mtask_addr = 0;
  3669. }
  3670. }
  3671. }
  3672. }
  3673. void
  3674. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3675. struct beiscsi_offload_params *params)
  3676. {
  3677. struct wrb_handle *pwrb_handle;
  3678. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3679. struct iscsi_task *task = beiscsi_conn->task;
  3680. struct iscsi_session *session = task->conn->session;
  3681. u32 doorbell = 0;
  3682. /*
  3683. * We can always use 0 here because it is reserved by libiscsi for
  3684. * login/startup related tasks.
  3685. */
  3686. beiscsi_conn->login_in_progress = 0;
  3687. spin_lock_bh(&session->lock);
  3688. beiscsi_cleanup_task(task);
  3689. spin_unlock_bh(&session->lock);
  3690. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3691. phba->fw_config.iscsi_cid_start));
  3692. /* Check for the adapter family */
  3693. if (chip_skh_r(phba->pcidev))
  3694. beiscsi_offload_cxn_v2(params, pwrb_handle);
  3695. else
  3696. beiscsi_offload_cxn_v0(params, pwrb_handle,
  3697. phba->init_mem);
  3698. be_dws_le_to_cpu(pwrb_handle->pwrb,
  3699. sizeof(struct iscsi_target_context_update_wrb));
  3700. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3701. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3702. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3703. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3704. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3705. }
  3706. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3707. int *index, int *age)
  3708. {
  3709. *index = (int)itt;
  3710. if (age)
  3711. *age = conn->session->age;
  3712. }
  3713. /**
  3714. * beiscsi_alloc_pdu - allocates pdu and related resources
  3715. * @task: libiscsi task
  3716. * @opcode: opcode of pdu for task
  3717. *
  3718. * This is called with the session lock held. It will allocate
  3719. * the wrb and sgl if needed for the command. And it will prep
  3720. * the pdu's itt. beiscsi_parse_pdu will later translate
  3721. * the pdu itt to the libiscsi task itt.
  3722. */
  3723. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3724. {
  3725. struct beiscsi_io_task *io_task = task->dd_data;
  3726. struct iscsi_conn *conn = task->conn;
  3727. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3728. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3729. struct hwi_wrb_context *pwrb_context;
  3730. struct hwi_controller *phwi_ctrlr;
  3731. itt_t itt;
  3732. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3733. dma_addr_t paddr;
  3734. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3735. GFP_ATOMIC, &paddr);
  3736. if (!io_task->cmd_bhs)
  3737. return -ENOMEM;
  3738. io_task->bhs_pa.u.a64.address = paddr;
  3739. io_task->libiscsi_itt = (itt_t)task->itt;
  3740. io_task->conn = beiscsi_conn;
  3741. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3742. task->hdr_max = sizeof(struct be_cmd_bhs);
  3743. io_task->psgl_handle = NULL;
  3744. io_task->pwrb_handle = NULL;
  3745. if (task->sc) {
  3746. spin_lock(&phba->io_sgl_lock);
  3747. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3748. spin_unlock(&phba->io_sgl_lock);
  3749. if (!io_task->psgl_handle) {
  3750. beiscsi_log(phba, KERN_ERR,
  3751. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3752. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3753. "for the CID : %d\n",
  3754. beiscsi_conn->beiscsi_conn_cid);
  3755. goto free_hndls;
  3756. }
  3757. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3758. beiscsi_conn->beiscsi_conn_cid -
  3759. phba->fw_config.iscsi_cid_start);
  3760. if (!io_task->pwrb_handle) {
  3761. beiscsi_log(phba, KERN_ERR,
  3762. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3763. "BM_%d : Alloc of WRB_HANDLE Failed"
  3764. "for the CID : %d\n",
  3765. beiscsi_conn->beiscsi_conn_cid);
  3766. goto free_io_hndls;
  3767. }
  3768. } else {
  3769. io_task->scsi_cmnd = NULL;
  3770. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3771. if (!beiscsi_conn->login_in_progress) {
  3772. spin_lock(&phba->mgmt_sgl_lock);
  3773. io_task->psgl_handle = (struct sgl_handle *)
  3774. alloc_mgmt_sgl_handle(phba);
  3775. spin_unlock(&phba->mgmt_sgl_lock);
  3776. if (!io_task->psgl_handle) {
  3777. beiscsi_log(phba, KERN_ERR,
  3778. BEISCSI_LOG_IO |
  3779. BEISCSI_LOG_CONFIG,
  3780. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3781. "for the CID : %d\n",
  3782. beiscsi_conn->
  3783. beiscsi_conn_cid);
  3784. goto free_hndls;
  3785. }
  3786. beiscsi_conn->login_in_progress = 1;
  3787. beiscsi_conn->plogin_sgl_handle =
  3788. io_task->psgl_handle;
  3789. io_task->pwrb_handle =
  3790. alloc_wrb_handle(phba,
  3791. beiscsi_conn->beiscsi_conn_cid -
  3792. phba->fw_config.iscsi_cid_start);
  3793. if (!io_task->pwrb_handle) {
  3794. beiscsi_log(phba, KERN_ERR,
  3795. BEISCSI_LOG_IO |
  3796. BEISCSI_LOG_CONFIG,
  3797. "BM_%d : Alloc of WRB_HANDLE Failed"
  3798. "for the CID : %d\n",
  3799. beiscsi_conn->
  3800. beiscsi_conn_cid);
  3801. goto free_mgmt_hndls;
  3802. }
  3803. beiscsi_conn->plogin_wrb_handle =
  3804. io_task->pwrb_handle;
  3805. } else {
  3806. io_task->psgl_handle =
  3807. beiscsi_conn->plogin_sgl_handle;
  3808. io_task->pwrb_handle =
  3809. beiscsi_conn->plogin_wrb_handle;
  3810. }
  3811. beiscsi_conn->task = task;
  3812. } else {
  3813. spin_lock(&phba->mgmt_sgl_lock);
  3814. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3815. spin_unlock(&phba->mgmt_sgl_lock);
  3816. if (!io_task->psgl_handle) {
  3817. beiscsi_log(phba, KERN_ERR,
  3818. BEISCSI_LOG_IO |
  3819. BEISCSI_LOG_CONFIG,
  3820. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3821. "for the CID : %d\n",
  3822. beiscsi_conn->
  3823. beiscsi_conn_cid);
  3824. goto free_hndls;
  3825. }
  3826. io_task->pwrb_handle =
  3827. alloc_wrb_handle(phba,
  3828. beiscsi_conn->beiscsi_conn_cid -
  3829. phba->fw_config.iscsi_cid_start);
  3830. if (!io_task->pwrb_handle) {
  3831. beiscsi_log(phba, KERN_ERR,
  3832. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3833. "BM_%d : Alloc of WRB_HANDLE Failed"
  3834. "for the CID : %d\n",
  3835. beiscsi_conn->beiscsi_conn_cid);
  3836. goto free_mgmt_hndls;
  3837. }
  3838. }
  3839. }
  3840. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3841. wrb_index << 16) | (unsigned int)
  3842. (io_task->psgl_handle->sgl_index));
  3843. io_task->pwrb_handle->pio_handle = task;
  3844. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3845. return 0;
  3846. free_io_hndls:
  3847. spin_lock(&phba->io_sgl_lock);
  3848. free_io_sgl_handle(phba, io_task->psgl_handle);
  3849. spin_unlock(&phba->io_sgl_lock);
  3850. goto free_hndls;
  3851. free_mgmt_hndls:
  3852. spin_lock(&phba->mgmt_sgl_lock);
  3853. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3854. spin_unlock(&phba->mgmt_sgl_lock);
  3855. free_hndls:
  3856. phwi_ctrlr = phba->phwi_ctrlr;
  3857. pwrb_context = &phwi_ctrlr->wrb_context[
  3858. beiscsi_conn->beiscsi_conn_cid -
  3859. phba->fw_config.iscsi_cid_start];
  3860. if (io_task->pwrb_handle)
  3861. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3862. io_task->pwrb_handle = NULL;
  3863. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3864. io_task->bhs_pa.u.a64.address);
  3865. io_task->cmd_bhs = NULL;
  3866. return -ENOMEM;
  3867. }
  3868. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  3869. unsigned int num_sg, unsigned int xferlen,
  3870. unsigned int writedir)
  3871. {
  3872. struct beiscsi_io_task *io_task = task->dd_data;
  3873. struct iscsi_conn *conn = task->conn;
  3874. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3875. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3876. struct iscsi_wrb *pwrb = NULL;
  3877. unsigned int doorbell = 0;
  3878. pwrb = io_task->pwrb_handle->pwrb;
  3879. memset(pwrb, 0, sizeof(*pwrb));
  3880. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3881. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3882. if (writedir) {
  3883. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3884. INI_WR_CMD);
  3885. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  3886. } else {
  3887. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3888. INI_RD_CMD);
  3889. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  3890. }
  3891. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  3892. type, pwrb);
  3893. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  3894. cpu_to_be16(*(unsigned short *)
  3895. &io_task->cmd_bhs->iscsi_hdr.lun));
  3896. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  3897. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3898. io_task->pwrb_handle->wrb_index);
  3899. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3900. be32_to_cpu(task->cmdsn));
  3901. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3902. io_task->psgl_handle->sgl_index);
  3903. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  3904. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  3905. io_task->pwrb_handle->nxt_wrb_index);
  3906. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3907. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3908. doorbell |= (io_task->pwrb_handle->wrb_index &
  3909. DB_DEF_PDU_WRB_INDEX_MASK) <<
  3910. DB_DEF_PDU_WRB_INDEX_SHIFT;
  3911. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3912. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3913. return 0;
  3914. }
  3915. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3916. unsigned int num_sg, unsigned int xferlen,
  3917. unsigned int writedir)
  3918. {
  3919. struct beiscsi_io_task *io_task = task->dd_data;
  3920. struct iscsi_conn *conn = task->conn;
  3921. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3922. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3923. struct iscsi_wrb *pwrb = NULL;
  3924. unsigned int doorbell = 0;
  3925. pwrb = io_task->pwrb_handle->pwrb;
  3926. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3927. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3928. if (writedir) {
  3929. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3930. INI_WR_CMD);
  3931. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3932. } else {
  3933. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3934. INI_RD_CMD);
  3935. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3936. }
  3937. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  3938. type, pwrb);
  3939. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3940. cpu_to_be16(*(unsigned short *)
  3941. &io_task->cmd_bhs->iscsi_hdr.lun));
  3942. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3943. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3944. io_task->pwrb_handle->wrb_index);
  3945. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3946. be32_to_cpu(task->cmdsn));
  3947. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3948. io_task->psgl_handle->sgl_index);
  3949. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3950. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3951. io_task->pwrb_handle->nxt_wrb_index);
  3952. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3953. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3954. doorbell |= (io_task->pwrb_handle->wrb_index &
  3955. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3956. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3957. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3958. return 0;
  3959. }
  3960. static int beiscsi_mtask(struct iscsi_task *task)
  3961. {
  3962. struct beiscsi_io_task *io_task = task->dd_data;
  3963. struct iscsi_conn *conn = task->conn;
  3964. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3965. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3966. struct iscsi_wrb *pwrb = NULL;
  3967. unsigned int doorbell = 0;
  3968. unsigned int cid;
  3969. unsigned int pwrb_typeoffset = 0;
  3970. cid = beiscsi_conn->beiscsi_conn_cid;
  3971. pwrb = io_task->pwrb_handle->pwrb;
  3972. memset(pwrb, 0, sizeof(*pwrb));
  3973. if (chip_skh_r(phba->pcidev)) {
  3974. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3975. be32_to_cpu(task->cmdsn));
  3976. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3977. io_task->pwrb_handle->wrb_index);
  3978. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3979. io_task->psgl_handle->sgl_index);
  3980. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  3981. task->data_count);
  3982. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  3983. io_task->pwrb_handle->nxt_wrb_index);
  3984. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  3985. } else {
  3986. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3987. be32_to_cpu(task->cmdsn));
  3988. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3989. io_task->pwrb_handle->wrb_index);
  3990. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3991. io_task->psgl_handle->sgl_index);
  3992. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3993. task->data_count);
  3994. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3995. io_task->pwrb_handle->nxt_wrb_index);
  3996. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  3997. }
  3998. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3999. case ISCSI_OP_LOGIN:
  4000. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4001. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4002. hwi_write_buffer(pwrb, task);
  4003. break;
  4004. case ISCSI_OP_NOOP_OUT:
  4005. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4006. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4007. if (chip_skh_r(phba->pcidev))
  4008. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4009. dmsg, pwrb, 1);
  4010. else
  4011. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4012. dmsg, pwrb, 1);
  4013. } else {
  4014. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4015. if (chip_skh_r(phba->pcidev))
  4016. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4017. dmsg, pwrb, 0);
  4018. else
  4019. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4020. dmsg, pwrb, 0);
  4021. }
  4022. hwi_write_buffer(pwrb, task);
  4023. break;
  4024. case ISCSI_OP_TEXT:
  4025. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4026. hwi_write_buffer(pwrb, task);
  4027. break;
  4028. case ISCSI_OP_SCSI_TMFUNC:
  4029. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4030. hwi_write_buffer(pwrb, task);
  4031. break;
  4032. case ISCSI_OP_LOGOUT:
  4033. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4034. hwi_write_buffer(pwrb, task);
  4035. break;
  4036. default:
  4037. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4038. "BM_%d : opcode =%d Not supported\n",
  4039. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4040. return -EINVAL;
  4041. }
  4042. /* Set the task type */
  4043. io_task->wrb_type = (chip_skh_r(phba->pcidev)) ?
  4044. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb) :
  4045. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb);
  4046. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4047. doorbell |= (io_task->pwrb_handle->wrb_index &
  4048. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4049. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4050. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4051. return 0;
  4052. }
  4053. static int beiscsi_task_xmit(struct iscsi_task *task)
  4054. {
  4055. struct beiscsi_io_task *io_task = task->dd_data;
  4056. struct scsi_cmnd *sc = task->sc;
  4057. struct beiscsi_hba *phba = NULL;
  4058. struct scatterlist *sg;
  4059. int num_sg;
  4060. unsigned int writedir = 0, xferlen = 0;
  4061. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4062. if (!sc)
  4063. return beiscsi_mtask(task);
  4064. io_task->scsi_cmnd = sc;
  4065. num_sg = scsi_dma_map(sc);
  4066. if (num_sg < 0) {
  4067. struct iscsi_conn *conn = task->conn;
  4068. struct beiscsi_hba *phba = NULL;
  4069. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4070. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4071. "BM_%d : scsi_dma_map Failed\n");
  4072. return num_sg;
  4073. }
  4074. xferlen = scsi_bufflen(sc);
  4075. sg = scsi_sglist(sc);
  4076. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4077. writedir = 1;
  4078. else
  4079. writedir = 0;
  4080. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4081. }
  4082. /**
  4083. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4084. * @job: job to handle
  4085. */
  4086. static int beiscsi_bsg_request(struct bsg_job *job)
  4087. {
  4088. struct Scsi_Host *shost;
  4089. struct beiscsi_hba *phba;
  4090. struct iscsi_bsg_request *bsg_req = job->request;
  4091. int rc = -EINVAL;
  4092. unsigned int tag;
  4093. struct be_dma_mem nonemb_cmd;
  4094. struct be_cmd_resp_hdr *resp;
  4095. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4096. unsigned short status, extd_status;
  4097. shost = iscsi_job_to_shost(job);
  4098. phba = iscsi_host_priv(shost);
  4099. switch (bsg_req->msgcode) {
  4100. case ISCSI_BSG_HST_VENDOR:
  4101. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4102. job->request_payload.payload_len,
  4103. &nonemb_cmd.dma);
  4104. if (nonemb_cmd.va == NULL) {
  4105. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4106. "BM_%d : Failed to allocate memory for "
  4107. "beiscsi_bsg_request\n");
  4108. return -ENOMEM;
  4109. }
  4110. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4111. &nonemb_cmd);
  4112. if (!tag) {
  4113. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4114. "BM_%d : MBX Tag Allocation Failed\n");
  4115. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4116. nonemb_cmd.va, nonemb_cmd.dma);
  4117. return -EAGAIN;
  4118. }
  4119. rc = wait_event_interruptible_timeout(
  4120. phba->ctrl.mcc_wait[tag],
  4121. phba->ctrl.mcc_numtag[tag],
  4122. msecs_to_jiffies(
  4123. BEISCSI_HOST_MBX_TIMEOUT));
  4124. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4125. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4126. free_mcc_tag(&phba->ctrl, tag);
  4127. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4128. sg_copy_from_buffer(job->reply_payload.sg_list,
  4129. job->reply_payload.sg_cnt,
  4130. nonemb_cmd.va, (resp->response_length
  4131. + sizeof(*resp)));
  4132. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4133. bsg_reply->result = status;
  4134. bsg_job_done(job, bsg_reply->result,
  4135. bsg_reply->reply_payload_rcv_len);
  4136. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4137. nonemb_cmd.va, nonemb_cmd.dma);
  4138. if (status || extd_status) {
  4139. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4140. "BM_%d : MBX Cmd Failed"
  4141. " status = %d extd_status = %d\n",
  4142. status, extd_status);
  4143. return -EIO;
  4144. } else {
  4145. rc = 0;
  4146. }
  4147. break;
  4148. default:
  4149. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4150. "BM_%d : Unsupported bsg command: 0x%x\n",
  4151. bsg_req->msgcode);
  4152. break;
  4153. }
  4154. return rc;
  4155. }
  4156. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4157. {
  4158. /* Set the logging parameter */
  4159. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4160. }
  4161. /*
  4162. * beiscsi_quiesce()- Cleanup Driver resources
  4163. * @phba: Instance Priv structure
  4164. *
  4165. * Free the OS and HW resources held by the driver
  4166. **/
  4167. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4168. {
  4169. struct hwi_controller *phwi_ctrlr;
  4170. struct hwi_context_memory *phwi_context;
  4171. struct be_eq_obj *pbe_eq;
  4172. unsigned int i, msix_vec;
  4173. phwi_ctrlr = phba->phwi_ctrlr;
  4174. phwi_context = phwi_ctrlr->phwi_ctxt;
  4175. hwi_disable_intr(phba);
  4176. if (phba->msix_enabled) {
  4177. for (i = 0; i <= phba->num_cpus; i++) {
  4178. msix_vec = phba->msix_entries[i].vector;
  4179. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4180. kfree(phba->msi_name[i]);
  4181. }
  4182. } else
  4183. if (phba->pcidev->irq)
  4184. free_irq(phba->pcidev->irq, phba);
  4185. pci_disable_msix(phba->pcidev);
  4186. destroy_workqueue(phba->wq);
  4187. if (blk_iopoll_enabled)
  4188. for (i = 0; i < phba->num_cpus; i++) {
  4189. pbe_eq = &phwi_context->be_eq[i];
  4190. blk_iopoll_disable(&pbe_eq->iopoll);
  4191. }
  4192. beiscsi_clean_port(phba);
  4193. beiscsi_free_mem(phba);
  4194. beiscsi_unmap_pci_function(phba);
  4195. pci_free_consistent(phba->pcidev,
  4196. phba->ctrl.mbox_mem_alloced.size,
  4197. phba->ctrl.mbox_mem_alloced.va,
  4198. phba->ctrl.mbox_mem_alloced.dma);
  4199. cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
  4200. }
  4201. static void beiscsi_remove(struct pci_dev *pcidev)
  4202. {
  4203. struct beiscsi_hba *phba = NULL;
  4204. phba = pci_get_drvdata(pcidev);
  4205. if (!phba) {
  4206. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4207. return;
  4208. }
  4209. beiscsi_destroy_def_ifaces(phba);
  4210. beiscsi_quiesce(phba);
  4211. iscsi_boot_destroy_kset(phba->boot_kset);
  4212. iscsi_host_remove(phba->shost);
  4213. pci_dev_put(phba->pcidev);
  4214. iscsi_host_free(phba->shost);
  4215. pci_disable_device(pcidev);
  4216. }
  4217. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4218. {
  4219. struct beiscsi_hba *phba = NULL;
  4220. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4221. if (!phba) {
  4222. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4223. return;
  4224. }
  4225. beiscsi_quiesce(phba);
  4226. pci_disable_device(pcidev);
  4227. }
  4228. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4229. {
  4230. int i, status;
  4231. for (i = 0; i <= phba->num_cpus; i++)
  4232. phba->msix_entries[i].entry = i;
  4233. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4234. (phba->num_cpus + 1));
  4235. if (!status)
  4236. phba->msix_enabled = true;
  4237. return;
  4238. }
  4239. /*
  4240. * beiscsi_hw_health_check()- Check adapter health
  4241. * @work: work item to check HW health
  4242. *
  4243. * Check if adapter in an unrecoverable state or not.
  4244. **/
  4245. static void
  4246. beiscsi_hw_health_check(struct work_struct *work)
  4247. {
  4248. struct beiscsi_hba *phba =
  4249. container_of(work, struct beiscsi_hba,
  4250. beiscsi_hw_check_task.work);
  4251. beiscsi_ue_detect(phba);
  4252. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4253. msecs_to_jiffies(1000));
  4254. }
  4255. static int beiscsi_dev_probe(struct pci_dev *pcidev,
  4256. const struct pci_device_id *id)
  4257. {
  4258. struct beiscsi_hba *phba = NULL;
  4259. struct hwi_controller *phwi_ctrlr;
  4260. struct hwi_context_memory *phwi_context;
  4261. struct be_eq_obj *pbe_eq;
  4262. int ret, i;
  4263. ret = beiscsi_enable_pci(pcidev);
  4264. if (ret < 0) {
  4265. dev_err(&pcidev->dev,
  4266. "beiscsi_dev_probe - Failed to enable pci device\n");
  4267. return ret;
  4268. }
  4269. phba = beiscsi_hba_alloc(pcidev);
  4270. if (!phba) {
  4271. dev_err(&pcidev->dev,
  4272. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4273. goto disable_pci;
  4274. }
  4275. /* Initialize Driver configuration Paramters */
  4276. beiscsi_hba_attrs_init(phba);
  4277. phba->fw_timeout = false;
  4278. switch (pcidev->device) {
  4279. case BE_DEVICE_ID1:
  4280. case OC_DEVICE_ID1:
  4281. case OC_DEVICE_ID2:
  4282. phba->generation = BE_GEN2;
  4283. phba->iotask_fn = beiscsi_iotask;
  4284. break;
  4285. case BE_DEVICE_ID2:
  4286. case OC_DEVICE_ID3:
  4287. phba->generation = BE_GEN3;
  4288. phba->iotask_fn = beiscsi_iotask;
  4289. break;
  4290. case OC_SKH_ID1:
  4291. phba->generation = BE_GEN4;
  4292. phba->iotask_fn = beiscsi_iotask_v2;
  4293. default:
  4294. phba->generation = 0;
  4295. }
  4296. if (enable_msix)
  4297. find_num_cpus(phba);
  4298. else
  4299. phba->num_cpus = 1;
  4300. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4301. "BM_%d : num_cpus = %d\n",
  4302. phba->num_cpus);
  4303. if (enable_msix) {
  4304. beiscsi_msix_enable(phba);
  4305. if (!phba->msix_enabled)
  4306. phba->num_cpus = 1;
  4307. }
  4308. ret = be_ctrl_init(phba, pcidev);
  4309. if (ret) {
  4310. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4311. "BM_%d : beiscsi_dev_probe-"
  4312. "Failed in be_ctrl_init\n");
  4313. goto hba_free;
  4314. }
  4315. ret = beiscsi_cmd_reset_function(phba);
  4316. if (ret) {
  4317. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4318. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4319. goto hba_free;
  4320. }
  4321. ret = be_chk_reset_complete(phba);
  4322. if (ret) {
  4323. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4324. "BM_%d : Failed to get out of reset."
  4325. "Aborting Crashdump\n");
  4326. goto hba_free;
  4327. }
  4328. spin_lock_init(&phba->io_sgl_lock);
  4329. spin_lock_init(&phba->mgmt_sgl_lock);
  4330. spin_lock_init(&phba->isr_lock);
  4331. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4332. if (ret != 0) {
  4333. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4334. "BM_%d : Error getting fw config\n");
  4335. goto free_port;
  4336. }
  4337. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4338. beiscsi_get_params(phba);
  4339. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4340. ret = beiscsi_init_port(phba);
  4341. if (ret < 0) {
  4342. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4343. "BM_%d : beiscsi_dev_probe-"
  4344. "Failed in beiscsi_init_port\n");
  4345. goto free_port;
  4346. }
  4347. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4348. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4349. phba->ctrl.mcc_tag[i] = i + 1;
  4350. phba->ctrl.mcc_numtag[i + 1] = 0;
  4351. phba->ctrl.mcc_tag_available++;
  4352. }
  4353. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4354. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4355. phba->shost->host_no);
  4356. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4357. if (!phba->wq) {
  4358. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4359. "BM_%d : beiscsi_dev_probe-"
  4360. "Failed to allocate work queue\n");
  4361. goto free_twq;
  4362. }
  4363. INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
  4364. beiscsi_hw_health_check);
  4365. phwi_ctrlr = phba->phwi_ctrlr;
  4366. phwi_context = phwi_ctrlr->phwi_ctxt;
  4367. if (blk_iopoll_enabled) {
  4368. for (i = 0; i < phba->num_cpus; i++) {
  4369. pbe_eq = &phwi_context->be_eq[i];
  4370. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4371. be_iopoll);
  4372. blk_iopoll_enable(&pbe_eq->iopoll);
  4373. }
  4374. i = (phba->msix_enabled) ? i : 0;
  4375. /* Work item for MCC handling */
  4376. pbe_eq = &phwi_context->be_eq[i];
  4377. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4378. } else {
  4379. if (phba->msix_enabled) {
  4380. for (i = 0; i <= phba->num_cpus; i++) {
  4381. pbe_eq = &phwi_context->be_eq[i];
  4382. INIT_WORK(&pbe_eq->work_cqs,
  4383. beiscsi_process_all_cqs);
  4384. }
  4385. } else {
  4386. pbe_eq = &phwi_context->be_eq[0];
  4387. INIT_WORK(&pbe_eq->work_cqs,
  4388. beiscsi_process_all_cqs);
  4389. }
  4390. }
  4391. ret = beiscsi_init_irqs(phba);
  4392. if (ret < 0) {
  4393. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4394. "BM_%d : beiscsi_dev_probe-"
  4395. "Failed to beiscsi_init_irqs\n");
  4396. goto free_blkenbld;
  4397. }
  4398. hwi_enable_intr(phba);
  4399. if (beiscsi_setup_boot_info(phba))
  4400. /*
  4401. * log error but continue, because we may not be using
  4402. * iscsi boot.
  4403. */
  4404. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4405. "BM_%d : Could not set up "
  4406. "iSCSI boot info.\n");
  4407. beiscsi_create_def_ifaces(phba);
  4408. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4409. msecs_to_jiffies(1000));
  4410. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4411. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4412. return 0;
  4413. free_blkenbld:
  4414. destroy_workqueue(phba->wq);
  4415. if (blk_iopoll_enabled)
  4416. for (i = 0; i < phba->num_cpus; i++) {
  4417. pbe_eq = &phwi_context->be_eq[i];
  4418. blk_iopoll_disable(&pbe_eq->iopoll);
  4419. }
  4420. free_twq:
  4421. beiscsi_clean_port(phba);
  4422. beiscsi_free_mem(phba);
  4423. free_port:
  4424. pci_free_consistent(phba->pcidev,
  4425. phba->ctrl.mbox_mem_alloced.size,
  4426. phba->ctrl.mbox_mem_alloced.va,
  4427. phba->ctrl.mbox_mem_alloced.dma);
  4428. beiscsi_unmap_pci_function(phba);
  4429. hba_free:
  4430. if (phba->msix_enabled)
  4431. pci_disable_msix(phba->pcidev);
  4432. iscsi_host_remove(phba->shost);
  4433. pci_dev_put(phba->pcidev);
  4434. iscsi_host_free(phba->shost);
  4435. disable_pci:
  4436. pci_disable_device(pcidev);
  4437. return ret;
  4438. }
  4439. struct iscsi_transport beiscsi_iscsi_transport = {
  4440. .owner = THIS_MODULE,
  4441. .name = DRV_NAME,
  4442. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4443. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4444. .create_session = beiscsi_session_create,
  4445. .destroy_session = beiscsi_session_destroy,
  4446. .create_conn = beiscsi_conn_create,
  4447. .bind_conn = beiscsi_conn_bind,
  4448. .destroy_conn = iscsi_conn_teardown,
  4449. .attr_is_visible = be2iscsi_attr_is_visible,
  4450. .set_iface_param = be2iscsi_iface_set_param,
  4451. .get_iface_param = be2iscsi_iface_get_param,
  4452. .set_param = beiscsi_set_param,
  4453. .get_conn_param = iscsi_conn_get_param,
  4454. .get_session_param = iscsi_session_get_param,
  4455. .get_host_param = beiscsi_get_host_param,
  4456. .start_conn = beiscsi_conn_start,
  4457. .stop_conn = iscsi_conn_stop,
  4458. .send_pdu = iscsi_conn_send_pdu,
  4459. .xmit_task = beiscsi_task_xmit,
  4460. .cleanup_task = beiscsi_cleanup_task,
  4461. .alloc_pdu = beiscsi_alloc_pdu,
  4462. .parse_pdu_itt = beiscsi_parse_pdu,
  4463. .get_stats = beiscsi_conn_get_stats,
  4464. .get_ep_param = beiscsi_ep_get_param,
  4465. .ep_connect = beiscsi_ep_connect,
  4466. .ep_poll = beiscsi_ep_poll,
  4467. .ep_disconnect = beiscsi_ep_disconnect,
  4468. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4469. .bsg_request = beiscsi_bsg_request,
  4470. };
  4471. static struct pci_driver beiscsi_pci_driver = {
  4472. .name = DRV_NAME,
  4473. .probe = beiscsi_dev_probe,
  4474. .remove = beiscsi_remove,
  4475. .shutdown = beiscsi_shutdown,
  4476. .id_table = beiscsi_pci_id_table
  4477. };
  4478. static int __init beiscsi_module_init(void)
  4479. {
  4480. int ret;
  4481. beiscsi_scsi_transport =
  4482. iscsi_register_transport(&beiscsi_iscsi_transport);
  4483. if (!beiscsi_scsi_transport) {
  4484. printk(KERN_ERR
  4485. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4486. return -ENOMEM;
  4487. }
  4488. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4489. &beiscsi_iscsi_transport);
  4490. ret = pci_register_driver(&beiscsi_pci_driver);
  4491. if (ret) {
  4492. printk(KERN_ERR
  4493. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4494. goto unregister_iscsi_transport;
  4495. }
  4496. return 0;
  4497. unregister_iscsi_transport:
  4498. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4499. return ret;
  4500. }
  4501. static void __exit beiscsi_module_exit(void)
  4502. {
  4503. pci_unregister_driver(&beiscsi_pci_driver);
  4504. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4505. }
  4506. module_init(beiscsi_module_init);
  4507. module_exit(beiscsi_module_exit);