lp3972.c 15 KB

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  1. /*
  2. * Regulator driver for National Semiconductors LP3972 PMIC chip
  3. *
  4. * Based on lp3971.c
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/bug.h>
  12. #include <linux/err.h>
  13. #include <linux/i2c.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/regulator/driver.h>
  17. #include <linux/regulator/lp3972.h>
  18. #include <linux/slab.h>
  19. struct lp3972 {
  20. struct device *dev;
  21. struct mutex io_lock;
  22. struct i2c_client *i2c;
  23. int num_regulators;
  24. struct regulator_dev **rdev;
  25. };
  26. /* LP3972 Control Registers */
  27. #define LP3972_SCR_REG 0x07
  28. #define LP3972_OVER1_REG 0x10
  29. #define LP3972_OVSR1_REG 0x11
  30. #define LP3972_OVER2_REG 0x12
  31. #define LP3972_OVSR2_REG 0x13
  32. #define LP3972_VCC1_REG 0x20
  33. #define LP3972_ADTV1_REG 0x23
  34. #define LP3972_ADTV2_REG 0x24
  35. #define LP3972_AVRC_REG 0x25
  36. #define LP3972_CDTC1_REG 0x26
  37. #define LP3972_CDTC2_REG 0x27
  38. #define LP3972_SDTV1_REG 0x29
  39. #define LP3972_SDTV2_REG 0x2A
  40. #define LP3972_MDTV1_REG 0x32
  41. #define LP3972_MDTV2_REG 0x33
  42. #define LP3972_L2VCR_REG 0x39
  43. #define LP3972_L34VCR_REG 0x3A
  44. #define LP3972_SCR1_REG 0x80
  45. #define LP3972_SCR2_REG 0x81
  46. #define LP3972_OEN3_REG 0x82
  47. #define LP3972_OSR3_REG 0x83
  48. #define LP3972_LOER4_REG 0x84
  49. #define LP3972_B2TV_REG 0x85
  50. #define LP3972_B3TV_REG 0x86
  51. #define LP3972_B32RC_REG 0x87
  52. #define LP3972_ISRA_REG 0x88
  53. #define LP3972_BCCR_REG 0x89
  54. #define LP3972_II1RR_REG 0x8E
  55. #define LP3972_II2RR_REG 0x8F
  56. #define LP3972_SYS_CONTROL1_REG LP3972_SCR1_REG
  57. /* System control register 1 initial value,
  58. * bits 5, 6 and 7 are EPROM programmable */
  59. #define SYS_CONTROL1_INIT_VAL 0x02
  60. #define SYS_CONTROL1_INIT_MASK 0x1F
  61. #define LP3972_VOL_CHANGE_REG LP3972_VCC1_REG
  62. #define LP3972_VOL_CHANGE_FLAG_GO 0x01
  63. #define LP3972_VOL_CHANGE_FLAG_MASK 0x03
  64. /* LDO output enable mask */
  65. #define LP3972_OEN3_L1EN BIT(0)
  66. #define LP3972_OVER2_LDO2_EN BIT(2)
  67. #define LP3972_OVER2_LDO3_EN BIT(3)
  68. #define LP3972_OVER2_LDO4_EN BIT(4)
  69. #define LP3972_OVER1_S_EN BIT(2)
  70. static const unsigned int ldo1_voltage_map[] = {
  71. 1700000, 1725000, 1750000, 1775000, 1800000, 1825000, 1850000, 1875000,
  72. 1900000, 1925000, 1950000, 1975000, 2000000,
  73. };
  74. static const unsigned int ldo23_voltage_map[] = {
  75. 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
  76. 2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
  77. };
  78. static const unsigned int ldo4_voltage_map[] = {
  79. 1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, 1350000,
  80. 1400000, 1500000, 1800000, 1900000, 2500000, 2800000, 3000000, 3300000,
  81. };
  82. static const unsigned int ldo5_voltage_map[] = {
  83. 0, 0, 0, 0, 0, 850000, 875000, 900000,
  84. 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000, 1100000,
  85. 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000,
  86. 1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, 1500000,
  87. };
  88. static const unsigned int buck1_voltage_map[] = {
  89. 725000, 750000, 775000, 800000, 825000, 850000, 875000, 900000,
  90. 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000, 1100000,
  91. 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000,
  92. 1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, 1500000,
  93. };
  94. static const unsigned int buck23_voltage_map[] = {
  95. 0, 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000,
  96. 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
  97. 1550000, 1600000, 1650000, 1700000, 1800000, 1900000, 2500000, 2800000,
  98. 3000000, 3300000,
  99. };
  100. static const int ldo_output_enable_mask[] = {
  101. LP3972_OEN3_L1EN,
  102. LP3972_OVER2_LDO2_EN,
  103. LP3972_OVER2_LDO3_EN,
  104. LP3972_OVER2_LDO4_EN,
  105. LP3972_OVER1_S_EN,
  106. };
  107. static const int ldo_output_enable_addr[] = {
  108. LP3972_OEN3_REG,
  109. LP3972_OVER2_REG,
  110. LP3972_OVER2_REG,
  111. LP3972_OVER2_REG,
  112. LP3972_OVER1_REG,
  113. };
  114. static const int ldo_vol_ctl_addr[] = {
  115. LP3972_MDTV1_REG,
  116. LP3972_L2VCR_REG,
  117. LP3972_L34VCR_REG,
  118. LP3972_L34VCR_REG,
  119. LP3972_SDTV1_REG,
  120. };
  121. static const int buck_vol_enable_addr[] = {
  122. LP3972_OVER1_REG,
  123. LP3972_OEN3_REG,
  124. LP3972_OEN3_REG,
  125. };
  126. static const int buck_base_addr[] = {
  127. LP3972_ADTV1_REG,
  128. LP3972_B2TV_REG,
  129. LP3972_B3TV_REG,
  130. };
  131. #define LP3972_LDO_OUTPUT_ENABLE_MASK(x) (ldo_output_enable_mask[x])
  132. #define LP3972_LDO_OUTPUT_ENABLE_REG(x) (ldo_output_enable_addr[x])
  133. /* LDO voltage control registers shift:
  134. LP3972_LDO1 -> 0, LP3972_LDO2 -> 4
  135. LP3972_LDO3 -> 0, LP3972_LDO4 -> 4
  136. LP3972_LDO5 -> 0
  137. */
  138. #define LP3972_LDO_VOL_CONTR_SHIFT(x) (((x) & 1) << 2)
  139. #define LP3972_LDO_VOL_CONTR_REG(x) (ldo_vol_ctl_addr[x])
  140. #define LP3972_LDO_VOL_CHANGE_SHIFT(x) ((x) ? 4 : 6)
  141. #define LP3972_LDO_VOL_MASK(x) (((x) % 4) ? 0x0f : 0x1f)
  142. #define LP3972_LDO_VOL_MIN_IDX(x) (((x) == 4) ? 0x05 : 0x00)
  143. #define LP3972_LDO_VOL_MAX_IDX(x) ((x) ? (((x) == 4) ? 0x1f : 0x0f) : 0x0c)
  144. #define LP3972_BUCK_VOL_ENABLE_REG(x) (buck_vol_enable_addr[x])
  145. #define LP3972_BUCK_VOL1_REG(x) (buck_base_addr[x])
  146. #define LP3972_BUCK_VOL_MASK 0x1f
  147. static int lp3972_i2c_read(struct i2c_client *i2c, char reg, int count,
  148. u16 *dest)
  149. {
  150. int ret;
  151. if (count != 1)
  152. return -EIO;
  153. ret = i2c_smbus_read_byte_data(i2c, reg);
  154. if (ret < 0)
  155. return ret;
  156. *dest = ret;
  157. return 0;
  158. }
  159. static int lp3972_i2c_write(struct i2c_client *i2c, char reg, int count,
  160. const u16 *src)
  161. {
  162. if (count != 1)
  163. return -EIO;
  164. return i2c_smbus_write_byte_data(i2c, reg, *src);
  165. }
  166. static u8 lp3972_reg_read(struct lp3972 *lp3972, u8 reg)
  167. {
  168. u16 val = 0;
  169. mutex_lock(&lp3972->io_lock);
  170. lp3972_i2c_read(lp3972->i2c, reg, 1, &val);
  171. dev_dbg(lp3972->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg,
  172. (unsigned)val & 0xff);
  173. mutex_unlock(&lp3972->io_lock);
  174. return val & 0xff;
  175. }
  176. static int lp3972_set_bits(struct lp3972 *lp3972, u8 reg, u16 mask, u16 val)
  177. {
  178. u16 tmp;
  179. int ret;
  180. mutex_lock(&lp3972->io_lock);
  181. ret = lp3972_i2c_read(lp3972->i2c, reg, 1, &tmp);
  182. tmp = (tmp & ~mask) | val;
  183. if (ret == 0) {
  184. ret = lp3972_i2c_write(lp3972->i2c, reg, 1, &tmp);
  185. dev_dbg(lp3972->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg,
  186. (unsigned)val & 0xff);
  187. }
  188. mutex_unlock(&lp3972->io_lock);
  189. return ret;
  190. }
  191. static int lp3972_ldo_is_enabled(struct regulator_dev *dev)
  192. {
  193. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  194. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  195. u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
  196. u16 val;
  197. val = lp3972_reg_read(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo));
  198. return !!(val & mask);
  199. }
  200. static int lp3972_ldo_enable(struct regulator_dev *dev)
  201. {
  202. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  203. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  204. u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
  205. return lp3972_set_bits(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo),
  206. mask, mask);
  207. }
  208. static int lp3972_ldo_disable(struct regulator_dev *dev)
  209. {
  210. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  211. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  212. u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
  213. return lp3972_set_bits(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo),
  214. mask, 0);
  215. }
  216. static int lp3972_ldo_get_voltage_sel(struct regulator_dev *dev)
  217. {
  218. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  219. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  220. u16 mask = LP3972_LDO_VOL_MASK(ldo);
  221. u16 val, reg;
  222. reg = lp3972_reg_read(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo));
  223. val = (reg >> LP3972_LDO_VOL_CONTR_SHIFT(ldo)) & mask;
  224. return val;
  225. }
  226. static int lp3972_ldo_set_voltage_sel(struct regulator_dev *dev,
  227. unsigned int selector)
  228. {
  229. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  230. int ldo = rdev_get_id(dev) - LP3972_LDO1;
  231. int shift, ret;
  232. shift = LP3972_LDO_VOL_CONTR_SHIFT(ldo);
  233. ret = lp3972_set_bits(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo),
  234. LP3972_LDO_VOL_MASK(ldo) << shift, selector << shift);
  235. if (ret)
  236. return ret;
  237. /*
  238. * LDO1 and LDO5 support voltage control by either target voltage1
  239. * or target voltage2 register.
  240. * We use target voltage1 register for LDO1 and LDO5 in this driver.
  241. * We need to update voltage change control register(0x20) to enable
  242. * LDO1 and LDO5 to change to their programmed target values.
  243. */
  244. switch (ldo) {
  245. case LP3972_LDO1:
  246. case LP3972_LDO5:
  247. shift = LP3972_LDO_VOL_CHANGE_SHIFT(ldo);
  248. ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  249. LP3972_VOL_CHANGE_FLAG_MASK << shift,
  250. LP3972_VOL_CHANGE_FLAG_GO << shift);
  251. if (ret)
  252. return ret;
  253. ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  254. LP3972_VOL_CHANGE_FLAG_MASK << shift, 0);
  255. break;
  256. }
  257. return ret;
  258. }
  259. static struct regulator_ops lp3972_ldo_ops = {
  260. .list_voltage = regulator_list_voltage_table,
  261. .is_enabled = lp3972_ldo_is_enabled,
  262. .enable = lp3972_ldo_enable,
  263. .disable = lp3972_ldo_disable,
  264. .get_voltage_sel = lp3972_ldo_get_voltage_sel,
  265. .set_voltage_sel = lp3972_ldo_set_voltage_sel,
  266. };
  267. static int lp3972_dcdc_is_enabled(struct regulator_dev *dev)
  268. {
  269. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  270. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  271. u16 mask = 1 << (buck * 2);
  272. u16 val;
  273. val = lp3972_reg_read(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck));
  274. return !!(val & mask);
  275. }
  276. static int lp3972_dcdc_enable(struct regulator_dev *dev)
  277. {
  278. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  279. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  280. u16 mask = 1 << (buck * 2);
  281. u16 val;
  282. val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck),
  283. mask, mask);
  284. return val;
  285. }
  286. static int lp3972_dcdc_disable(struct regulator_dev *dev)
  287. {
  288. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  289. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  290. u16 mask = 1 << (buck * 2);
  291. u16 val;
  292. val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck),
  293. mask, 0);
  294. return val;
  295. }
  296. static int lp3972_dcdc_get_voltage_sel(struct regulator_dev *dev)
  297. {
  298. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  299. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  300. u16 reg;
  301. reg = lp3972_reg_read(lp3972, LP3972_BUCK_VOL1_REG(buck));
  302. reg &= LP3972_BUCK_VOL_MASK;
  303. return reg;
  304. }
  305. static int lp3972_dcdc_set_voltage_sel(struct regulator_dev *dev,
  306. unsigned int selector)
  307. {
  308. struct lp3972 *lp3972 = rdev_get_drvdata(dev);
  309. int buck = rdev_get_id(dev) - LP3972_DCDC1;
  310. int ret;
  311. ret = lp3972_set_bits(lp3972, LP3972_BUCK_VOL1_REG(buck),
  312. LP3972_BUCK_VOL_MASK, selector);
  313. if (ret)
  314. return ret;
  315. if (buck != 0)
  316. return ret;
  317. ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  318. LP3972_VOL_CHANGE_FLAG_MASK, LP3972_VOL_CHANGE_FLAG_GO);
  319. if (ret)
  320. return ret;
  321. return lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
  322. LP3972_VOL_CHANGE_FLAG_MASK, 0);
  323. }
  324. static struct regulator_ops lp3972_dcdc_ops = {
  325. .list_voltage = regulator_list_voltage_table,
  326. .is_enabled = lp3972_dcdc_is_enabled,
  327. .enable = lp3972_dcdc_enable,
  328. .disable = lp3972_dcdc_disable,
  329. .get_voltage_sel = lp3972_dcdc_get_voltage_sel,
  330. .set_voltage_sel = lp3972_dcdc_set_voltage_sel,
  331. };
  332. static const struct regulator_desc regulators[] = {
  333. {
  334. .name = "LDO1",
  335. .id = LP3972_LDO1,
  336. .ops = &lp3972_ldo_ops,
  337. .n_voltages = ARRAY_SIZE(ldo1_voltage_map),
  338. .volt_table = ldo1_voltage_map,
  339. .type = REGULATOR_VOLTAGE,
  340. .owner = THIS_MODULE,
  341. },
  342. {
  343. .name = "LDO2",
  344. .id = LP3972_LDO2,
  345. .ops = &lp3972_ldo_ops,
  346. .n_voltages = ARRAY_SIZE(ldo23_voltage_map),
  347. .volt_table = ldo23_voltage_map,
  348. .type = REGULATOR_VOLTAGE,
  349. .owner = THIS_MODULE,
  350. },
  351. {
  352. .name = "LDO3",
  353. .id = LP3972_LDO3,
  354. .ops = &lp3972_ldo_ops,
  355. .n_voltages = ARRAY_SIZE(ldo23_voltage_map),
  356. .volt_table = ldo23_voltage_map,
  357. .type = REGULATOR_VOLTAGE,
  358. .owner = THIS_MODULE,
  359. },
  360. {
  361. .name = "LDO4",
  362. .id = LP3972_LDO4,
  363. .ops = &lp3972_ldo_ops,
  364. .n_voltages = ARRAY_SIZE(ldo4_voltage_map),
  365. .volt_table = ldo4_voltage_map,
  366. .type = REGULATOR_VOLTAGE,
  367. .owner = THIS_MODULE,
  368. },
  369. {
  370. .name = "LDO5",
  371. .id = LP3972_LDO5,
  372. .ops = &lp3972_ldo_ops,
  373. .n_voltages = ARRAY_SIZE(ldo5_voltage_map),
  374. .volt_table = ldo5_voltage_map,
  375. .type = REGULATOR_VOLTAGE,
  376. .owner = THIS_MODULE,
  377. },
  378. {
  379. .name = "DCDC1",
  380. .id = LP3972_DCDC1,
  381. .ops = &lp3972_dcdc_ops,
  382. .n_voltages = ARRAY_SIZE(buck1_voltage_map),
  383. .volt_table = buck1_voltage_map,
  384. .type = REGULATOR_VOLTAGE,
  385. .owner = THIS_MODULE,
  386. },
  387. {
  388. .name = "DCDC2",
  389. .id = LP3972_DCDC2,
  390. .ops = &lp3972_dcdc_ops,
  391. .n_voltages = ARRAY_SIZE(buck23_voltage_map),
  392. .volt_table = buck23_voltage_map,
  393. .type = REGULATOR_VOLTAGE,
  394. .owner = THIS_MODULE,
  395. },
  396. {
  397. .name = "DCDC3",
  398. .id = LP3972_DCDC3,
  399. .ops = &lp3972_dcdc_ops,
  400. .n_voltages = ARRAY_SIZE(buck23_voltage_map),
  401. .volt_table = buck23_voltage_map,
  402. .type = REGULATOR_VOLTAGE,
  403. .owner = THIS_MODULE,
  404. },
  405. };
  406. static int setup_regulators(struct lp3972 *lp3972,
  407. struct lp3972_platform_data *pdata)
  408. {
  409. int i, err;
  410. lp3972->num_regulators = pdata->num_regulators;
  411. lp3972->rdev = kcalloc(pdata->num_regulators,
  412. sizeof(struct regulator_dev *), GFP_KERNEL);
  413. if (!lp3972->rdev) {
  414. err = -ENOMEM;
  415. goto err_nomem;
  416. }
  417. /* Instantiate the regulators */
  418. for (i = 0; i < pdata->num_regulators; i++) {
  419. struct lp3972_regulator_subdev *reg = &pdata->regulators[i];
  420. struct regulator_config config = { };
  421. config.dev = lp3972->dev;
  422. config.init_data = reg->initdata;
  423. config.driver_data = lp3972;
  424. lp3972->rdev[i] = regulator_register(&regulators[reg->id],
  425. &config);
  426. if (IS_ERR(lp3972->rdev[i])) {
  427. err = PTR_ERR(lp3972->rdev[i]);
  428. dev_err(lp3972->dev, "regulator init failed: %d\n",
  429. err);
  430. goto error;
  431. }
  432. }
  433. return 0;
  434. error:
  435. while (--i >= 0)
  436. regulator_unregister(lp3972->rdev[i]);
  437. kfree(lp3972->rdev);
  438. lp3972->rdev = NULL;
  439. err_nomem:
  440. return err;
  441. }
  442. static int lp3972_i2c_probe(struct i2c_client *i2c,
  443. const struct i2c_device_id *id)
  444. {
  445. struct lp3972 *lp3972;
  446. struct lp3972_platform_data *pdata = i2c->dev.platform_data;
  447. int ret;
  448. u16 val;
  449. if (!pdata) {
  450. dev_dbg(&i2c->dev, "No platform init data supplied\n");
  451. return -ENODEV;
  452. }
  453. lp3972 = kzalloc(sizeof(struct lp3972), GFP_KERNEL);
  454. if (!lp3972)
  455. return -ENOMEM;
  456. lp3972->i2c = i2c;
  457. lp3972->dev = &i2c->dev;
  458. mutex_init(&lp3972->io_lock);
  459. /* Detect LP3972 */
  460. ret = lp3972_i2c_read(i2c, LP3972_SYS_CONTROL1_REG, 1, &val);
  461. if (ret == 0 &&
  462. (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL) {
  463. ret = -ENODEV;
  464. dev_err(&i2c->dev, "chip reported: val = 0x%x\n", val);
  465. }
  466. if (ret < 0) {
  467. dev_err(&i2c->dev, "failed to detect device. ret = %d\n", ret);
  468. goto err_detect;
  469. }
  470. ret = setup_regulators(lp3972, pdata);
  471. if (ret < 0)
  472. goto err_detect;
  473. i2c_set_clientdata(i2c, lp3972);
  474. return 0;
  475. err_detect:
  476. kfree(lp3972);
  477. return ret;
  478. }
  479. static int lp3972_i2c_remove(struct i2c_client *i2c)
  480. {
  481. struct lp3972 *lp3972 = i2c_get_clientdata(i2c);
  482. int i;
  483. for (i = 0; i < lp3972->num_regulators; i++)
  484. regulator_unregister(lp3972->rdev[i]);
  485. kfree(lp3972->rdev);
  486. kfree(lp3972);
  487. return 0;
  488. }
  489. static const struct i2c_device_id lp3972_i2c_id[] = {
  490. { "lp3972", 0 },
  491. { }
  492. };
  493. MODULE_DEVICE_TABLE(i2c, lp3972_i2c_id);
  494. static struct i2c_driver lp3972_i2c_driver = {
  495. .driver = {
  496. .name = "lp3972",
  497. .owner = THIS_MODULE,
  498. },
  499. .probe = lp3972_i2c_probe,
  500. .remove = lp3972_i2c_remove,
  501. .id_table = lp3972_i2c_id,
  502. };
  503. static int __init lp3972_module_init(void)
  504. {
  505. return i2c_add_driver(&lp3972_i2c_driver);
  506. }
  507. subsys_initcall(lp3972_module_init);
  508. static void __exit lp3972_module_exit(void)
  509. {
  510. i2c_del_driver(&lp3972_i2c_driver);
  511. }
  512. module_exit(lp3972_module_exit);
  513. MODULE_LICENSE("GPL");
  514. MODULE_AUTHOR("Axel Lin <axel.lin@gmail.com>");
  515. MODULE_DESCRIPTION("LP3972 PMIC driver");