portdrv_pci.c 11 KB

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  1. /*
  2. * File: portdrv_pci.c
  3. * Purpose: PCI Express Port Bus Driver
  4. *
  5. * Copyright (C) 2004 Intel
  6. * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
  7. */
  8. #include <linux/module.h>
  9. #include <linux/pci.h>
  10. #include <linux/kernel.h>
  11. #include <linux/errno.h>
  12. #include <linux/pm.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/init.h>
  15. #include <linux/pcieport_if.h>
  16. #include <linux/aer.h>
  17. #include <linux/dmi.h>
  18. #include <linux/pci-aspm.h>
  19. #include "portdrv.h"
  20. #include "aer/aerdrv.h"
  21. /*
  22. * Version Information
  23. */
  24. #define DRIVER_VERSION "v1.0"
  25. #define DRIVER_AUTHOR "tom.l.nguyen@intel.com"
  26. #define DRIVER_DESC "PCIe Port Bus Driver"
  27. MODULE_AUTHOR(DRIVER_AUTHOR);
  28. MODULE_DESCRIPTION(DRIVER_DESC);
  29. MODULE_LICENSE("GPL");
  30. /* If this switch is set, PCIe port native services should not be enabled. */
  31. bool pcie_ports_disabled;
  32. /*
  33. * If this switch is set, ACPI _OSC will be used to determine whether or not to
  34. * enable PCIe port native services.
  35. */
  36. bool pcie_ports_auto = true;
  37. static int __init pcie_port_setup(char *str)
  38. {
  39. if (!strncmp(str, "compat", 6)) {
  40. pcie_ports_disabled = true;
  41. } else if (!strncmp(str, "native", 6)) {
  42. pcie_ports_disabled = false;
  43. pcie_ports_auto = false;
  44. } else if (!strncmp(str, "auto", 4)) {
  45. pcie_ports_disabled = false;
  46. pcie_ports_auto = true;
  47. }
  48. return 1;
  49. }
  50. __setup("pcie_ports=", pcie_port_setup);
  51. /* global data */
  52. /**
  53. * pcie_clear_root_pme_status - Clear root port PME interrupt status.
  54. * @dev: PCIe root port or event collector.
  55. */
  56. void pcie_clear_root_pme_status(struct pci_dev *dev)
  57. {
  58. pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
  59. }
  60. static int pcie_portdrv_restore_config(struct pci_dev *dev)
  61. {
  62. int retval;
  63. retval = pci_enable_device(dev);
  64. if (retval)
  65. return retval;
  66. pci_set_master(dev);
  67. return 0;
  68. }
  69. #ifdef CONFIG_PM
  70. static int pcie_port_resume_noirq(struct device *dev)
  71. {
  72. struct pci_dev *pdev = to_pci_dev(dev);
  73. /*
  74. * Some BIOSes forget to clear Root PME Status bits after system wakeup
  75. * which breaks ACPI-based runtime wakeup on PCI Express, so clear those
  76. * bits now just in case (shouldn't hurt).
  77. */
  78. if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
  79. pcie_clear_root_pme_status(pdev);
  80. return 0;
  81. }
  82. #ifdef CONFIG_PM_RUNTIME
  83. struct d3cold_info {
  84. bool no_d3cold;
  85. unsigned int d3cold_delay;
  86. };
  87. static int pci_dev_d3cold_info(struct pci_dev *pdev, void *data)
  88. {
  89. struct d3cold_info *info = data;
  90. info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
  91. info->d3cold_delay);
  92. if (pdev->no_d3cold)
  93. info->no_d3cold = true;
  94. return 0;
  95. }
  96. static int pcie_port_runtime_suspend(struct device *dev)
  97. {
  98. struct pci_dev *pdev = to_pci_dev(dev);
  99. struct d3cold_info d3cold_info = {
  100. .no_d3cold = false,
  101. .d3cold_delay = PCI_PM_D3_WAIT,
  102. };
  103. /*
  104. * If any subordinate device disable D3cold, we should not put
  105. * the port into D3cold. The D3cold delay of port should be
  106. * the max of that of all subordinate devices.
  107. */
  108. pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
  109. pdev->no_d3cold = d3cold_info.no_d3cold;
  110. pdev->d3cold_delay = d3cold_info.d3cold_delay;
  111. return 0;
  112. }
  113. static int pcie_port_runtime_resume(struct device *dev)
  114. {
  115. return 0;
  116. }
  117. static int pci_dev_pme_poll(struct pci_dev *pdev, void *data)
  118. {
  119. bool *pme_poll = data;
  120. if (pdev->pme_poll)
  121. *pme_poll = true;
  122. return 0;
  123. }
  124. static int pcie_port_runtime_idle(struct device *dev)
  125. {
  126. struct pci_dev *pdev = to_pci_dev(dev);
  127. bool pme_poll = false;
  128. /*
  129. * If any subordinate device needs pme poll, we should keep
  130. * the port in D0, because we need port in D0 to poll it.
  131. */
  132. pci_walk_bus(pdev->subordinate, pci_dev_pme_poll, &pme_poll);
  133. /* Delay for a short while to prevent too frequent suspend/resume */
  134. if (!pme_poll)
  135. pm_schedule_suspend(dev, 10);
  136. return -EBUSY;
  137. }
  138. #else
  139. #define pcie_port_runtime_suspend NULL
  140. #define pcie_port_runtime_resume NULL
  141. #define pcie_port_runtime_idle NULL
  142. #endif
  143. static const struct dev_pm_ops pcie_portdrv_pm_ops = {
  144. .suspend = pcie_port_device_suspend,
  145. .resume = pcie_port_device_resume,
  146. .freeze = pcie_port_device_suspend,
  147. .thaw = pcie_port_device_resume,
  148. .poweroff = pcie_port_device_suspend,
  149. .restore = pcie_port_device_resume,
  150. .resume_noirq = pcie_port_resume_noirq,
  151. .runtime_suspend = pcie_port_runtime_suspend,
  152. .runtime_resume = pcie_port_runtime_resume,
  153. .runtime_idle = pcie_port_runtime_idle,
  154. };
  155. #define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
  156. #else /* !PM */
  157. #define PCIE_PORTDRV_PM_OPS NULL
  158. #endif /* !PM */
  159. /*
  160. * PCIe port runtime suspend is broken for some chipsets, so use a
  161. * black list to disable runtime PM for these chipsets.
  162. */
  163. static const struct pci_device_id port_runtime_pm_black_list[] = {
  164. { /* end: all zeroes */ }
  165. };
  166. /*
  167. * pcie_portdrv_probe - Probe PCI-Express port devices
  168. * @dev: PCI-Express port device being probed
  169. *
  170. * If detected invokes the pcie_port_device_register() method for
  171. * this port device.
  172. *
  173. */
  174. static int pcie_portdrv_probe(struct pci_dev *dev,
  175. const struct pci_device_id *id)
  176. {
  177. int status;
  178. if (!pci_is_pcie(dev) ||
  179. ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
  180. (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
  181. (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
  182. return -ENODEV;
  183. if (!dev->irq && dev->pin) {
  184. dev_warn(&dev->dev, "device [%04x:%04x] has invalid IRQ; "
  185. "check vendor BIOS\n", dev->vendor, dev->device);
  186. }
  187. status = pcie_port_device_register(dev);
  188. if (status)
  189. return status;
  190. pci_save_state(dev);
  191. /*
  192. * D3cold may not work properly on some PCIe port, so disable
  193. * it by default.
  194. */
  195. dev->d3cold_allowed = false;
  196. if (!pci_match_id(port_runtime_pm_black_list, dev))
  197. pm_runtime_put_noidle(&dev->dev);
  198. return 0;
  199. }
  200. static void pcie_portdrv_remove(struct pci_dev *dev)
  201. {
  202. if (!pci_match_id(port_runtime_pm_black_list, dev))
  203. pm_runtime_get_noresume(&dev->dev);
  204. pcie_port_device_remove(dev);
  205. pci_disable_device(dev);
  206. }
  207. static int error_detected_iter(struct device *device, void *data)
  208. {
  209. struct pcie_device *pcie_device;
  210. struct pcie_port_service_driver *driver;
  211. struct aer_broadcast_data *result_data;
  212. pci_ers_result_t status;
  213. result_data = (struct aer_broadcast_data *) data;
  214. if (device->bus == &pcie_port_bus_type && device->driver) {
  215. driver = to_service_driver(device->driver);
  216. if (!driver ||
  217. !driver->err_handler ||
  218. !driver->err_handler->error_detected)
  219. return 0;
  220. pcie_device = to_pcie_device(device);
  221. /* Forward error detected message to service drivers */
  222. status = driver->err_handler->error_detected(
  223. pcie_device->port,
  224. result_data->state);
  225. result_data->result =
  226. merge_result(result_data->result, status);
  227. }
  228. return 0;
  229. }
  230. static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
  231. enum pci_channel_state error)
  232. {
  233. struct aer_broadcast_data data = {error, PCI_ERS_RESULT_CAN_RECOVER};
  234. int ret;
  235. /* can not fail */
  236. ret = device_for_each_child(&dev->dev, &data, error_detected_iter);
  237. return data.result;
  238. }
  239. static int mmio_enabled_iter(struct device *device, void *data)
  240. {
  241. struct pcie_device *pcie_device;
  242. struct pcie_port_service_driver *driver;
  243. pci_ers_result_t status, *result;
  244. result = (pci_ers_result_t *) data;
  245. if (device->bus == &pcie_port_bus_type && device->driver) {
  246. driver = to_service_driver(device->driver);
  247. if (driver &&
  248. driver->err_handler &&
  249. driver->err_handler->mmio_enabled) {
  250. pcie_device = to_pcie_device(device);
  251. /* Forward error message to service drivers */
  252. status = driver->err_handler->mmio_enabled(
  253. pcie_device->port);
  254. *result = merge_result(*result, status);
  255. }
  256. }
  257. return 0;
  258. }
  259. static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
  260. {
  261. pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
  262. int retval;
  263. /* get true return value from &status */
  264. retval = device_for_each_child(&dev->dev, &status, mmio_enabled_iter);
  265. return status;
  266. }
  267. static int slot_reset_iter(struct device *device, void *data)
  268. {
  269. struct pcie_device *pcie_device;
  270. struct pcie_port_service_driver *driver;
  271. pci_ers_result_t status, *result;
  272. result = (pci_ers_result_t *) data;
  273. if (device->bus == &pcie_port_bus_type && device->driver) {
  274. driver = to_service_driver(device->driver);
  275. if (driver &&
  276. driver->err_handler &&
  277. driver->err_handler->slot_reset) {
  278. pcie_device = to_pcie_device(device);
  279. /* Forward error message to service drivers */
  280. status = driver->err_handler->slot_reset(
  281. pcie_device->port);
  282. *result = merge_result(*result, status);
  283. }
  284. }
  285. return 0;
  286. }
  287. static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
  288. {
  289. pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
  290. int retval;
  291. /* If fatal, restore cfg space for possible link reset at upstream */
  292. if (dev->error_state == pci_channel_io_frozen) {
  293. dev->state_saved = true;
  294. pci_restore_state(dev);
  295. pcie_portdrv_restore_config(dev);
  296. pci_enable_pcie_error_reporting(dev);
  297. }
  298. /* get true return value from &status */
  299. retval = device_for_each_child(&dev->dev, &status, slot_reset_iter);
  300. return status;
  301. }
  302. static int resume_iter(struct device *device, void *data)
  303. {
  304. struct pcie_device *pcie_device;
  305. struct pcie_port_service_driver *driver;
  306. if (device->bus == &pcie_port_bus_type && device->driver) {
  307. driver = to_service_driver(device->driver);
  308. if (driver &&
  309. driver->err_handler &&
  310. driver->err_handler->resume) {
  311. pcie_device = to_pcie_device(device);
  312. /* Forward error message to service drivers */
  313. driver->err_handler->resume(pcie_device->port);
  314. }
  315. }
  316. return 0;
  317. }
  318. static void pcie_portdrv_err_resume(struct pci_dev *dev)
  319. {
  320. int retval;
  321. /* nothing to do with error value, if it ever happens */
  322. retval = device_for_each_child(&dev->dev, NULL, resume_iter);
  323. }
  324. /*
  325. * LINUX Device Driver Model
  326. */
  327. static const struct pci_device_id port_pci_ids[] = { {
  328. /* handle any PCI-Express port */
  329. PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0),
  330. }, { /* end: all zeroes */ }
  331. };
  332. MODULE_DEVICE_TABLE(pci, port_pci_ids);
  333. static const struct pci_error_handlers pcie_portdrv_err_handler = {
  334. .error_detected = pcie_portdrv_error_detected,
  335. .mmio_enabled = pcie_portdrv_mmio_enabled,
  336. .slot_reset = pcie_portdrv_slot_reset,
  337. .resume = pcie_portdrv_err_resume,
  338. };
  339. static struct pci_driver pcie_portdriver = {
  340. .name = "pcieport",
  341. .id_table = &port_pci_ids[0],
  342. .probe = pcie_portdrv_probe,
  343. .remove = pcie_portdrv_remove,
  344. .err_handler = &pcie_portdrv_err_handler,
  345. .driver.pm = PCIE_PORTDRV_PM_OPS,
  346. };
  347. static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
  348. {
  349. pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
  350. d->ident);
  351. pcie_pme_disable_msi();
  352. return 0;
  353. }
  354. static struct dmi_system_id __initdata pcie_portdrv_dmi_table[] = {
  355. /*
  356. * Boxes that should not use MSI for PCIe PME signaling.
  357. */
  358. {
  359. .callback = dmi_pcie_pme_disable_msi,
  360. .ident = "MSI Wind U-100",
  361. .matches = {
  362. DMI_MATCH(DMI_SYS_VENDOR,
  363. "MICRO-STAR INTERNATIONAL CO., LTD"),
  364. DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
  365. },
  366. },
  367. {}
  368. };
  369. static int __init pcie_portdrv_init(void)
  370. {
  371. int retval;
  372. if (pcie_ports_disabled)
  373. return pci_register_driver(&pcie_portdriver);
  374. dmi_check_system(pcie_portdrv_dmi_table);
  375. retval = pcie_port_bus_register();
  376. if (retval) {
  377. printk(KERN_WARNING "PCIE: bus_register error: %d\n", retval);
  378. goto out;
  379. }
  380. retval = pci_register_driver(&pcie_portdriver);
  381. if (retval)
  382. pcie_port_bus_unregister();
  383. out:
  384. return retval;
  385. }
  386. module_init(pcie_portdrv_init);