parport_serial.c 20 KB

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  1. /*
  2. * Support for common PCI multi-I/O cards (which is most of them)
  3. *
  4. * Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. *
  12. * Multi-function PCI cards are supposed to present separate logical
  13. * devices on the bus. A common thing to do seems to be to just use
  14. * one logical device with lots of base address registers for both
  15. * parallel ports and serial ports. This driver is for dealing with
  16. * that.
  17. *
  18. */
  19. #include <linux/types.h>
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/slab.h>
  23. #include <linux/pci.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/parport.h>
  26. #include <linux/parport_pc.h>
  27. #include <linux/8250_pci.h>
  28. enum parport_pc_pci_cards {
  29. titan_110l = 0,
  30. titan_210l,
  31. netmos_9xx5_combo,
  32. netmos_9855,
  33. netmos_9855_2p,
  34. netmos_9900,
  35. netmos_9900_2p,
  36. netmos_99xx_1p,
  37. avlab_1s1p,
  38. avlab_1s2p,
  39. avlab_2s1p,
  40. siig_1s1p_10x,
  41. siig_2s1p_10x,
  42. siig_2p1s_20x,
  43. siig_1s1p_20x,
  44. siig_2s1p_20x,
  45. timedia_4078a,
  46. timedia_4079h,
  47. timedia_4085h,
  48. timedia_4088a,
  49. timedia_4089a,
  50. timedia_4095a,
  51. timedia_4096a,
  52. timedia_4078u,
  53. timedia_4079a,
  54. timedia_4085u,
  55. timedia_4079r,
  56. timedia_4079s,
  57. timedia_4079d,
  58. timedia_4079e,
  59. timedia_4079f,
  60. timedia_9079a,
  61. timedia_9079b,
  62. timedia_9079c,
  63. wch_ch353_2s1p,
  64. sunix_2s1p,
  65. };
  66. /* each element directly indexed from enum list, above */
  67. struct parport_pc_pci {
  68. int numports;
  69. struct { /* BAR (base address registers) numbers in the config
  70. space header */
  71. int lo;
  72. int hi; /* -1 if not there, >6 for offset-method (max
  73. BAR is 6) */
  74. } addr[4];
  75. /* If set, this is called immediately after pci_enable_device.
  76. * If it returns non-zero, no probing will take place and the
  77. * ports will not be used. */
  78. int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
  79. int autoirq, int autodma);
  80. /* If set, this is called after probing for ports. If 'failed'
  81. * is non-zero we couldn't use any of the ports. */
  82. void (*postinit_hook) (struct pci_dev *pdev,
  83. struct parport_pc_pci *card, int failed);
  84. };
  85. static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
  86. int autoirq, int autodma)
  87. {
  88. /* the rule described below doesn't hold for this device */
  89. if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
  90. dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  91. dev->subsystem_device == 0x0299)
  92. return -ENODEV;
  93. if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
  94. par->numports = 1;
  95. } else {
  96. /*
  97. * Netmos uses the subdevice ID to indicate the number of parallel
  98. * and serial ports. The form is 0x00PS, where <P> is the number of
  99. * parallel ports and <S> is the number of serial ports.
  100. */
  101. par->numports = (dev->subsystem_device & 0xf0) >> 4;
  102. if (par->numports > ARRAY_SIZE(par->addr))
  103. par->numports = ARRAY_SIZE(par->addr);
  104. }
  105. return 0;
  106. }
  107. static struct parport_pc_pci cards[] = {
  108. /* titan_110l */ { 1, { { 3, -1 }, } },
  109. /* titan_210l */ { 1, { { 3, -1 }, } },
  110. /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
  111. /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
  112. /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
  113. /* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
  114. /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
  115. /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
  116. /* avlab_1s1p */ { 1, { { 1, 2}, } },
  117. /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
  118. /* avlab_2s1p */ { 1, { { 2, 3}, } },
  119. /* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
  120. /* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
  121. /* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
  122. /* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
  123. /* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
  124. /* timedia_4078a */ { 1, { { 2, -1 }, } },
  125. /* timedia_4079h */ { 1, { { 2, 3 }, } },
  126. /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
  127. /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  128. /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  129. /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  130. /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  131. /* timedia_4078u */ { 1, { { 2, -1 }, } },
  132. /* timedia_4079a */ { 1, { { 2, 3 }, } },
  133. /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
  134. /* timedia_4079r */ { 1, { { 2, 3 }, } },
  135. /* timedia_4079s */ { 1, { { 2, 3 }, } },
  136. /* timedia_4079d */ { 1, { { 2, 3 }, } },
  137. /* timedia_4079e */ { 1, { { 2, 3 }, } },
  138. /* timedia_4079f */ { 1, { { 2, 3 }, } },
  139. /* timedia_9079a */ { 1, { { 2, 3 }, } },
  140. /* timedia_9079b */ { 1, { { 2, 3 }, } },
  141. /* timedia_9079c */ { 1, { { 2, 3 }, } },
  142. /* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
  143. /* sunix_2s1p */ { 1, { { 3, -1 }, } },
  144. };
  145. #define PCI_VENDOR_ID_SUNIX 0x1fd4
  146. #define PCI_DEVICE_ID_SUNIX_1999 0x1999
  147. static struct pci_device_id parport_serial_pci_tbl[] = {
  148. /* PCI cards */
  149. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
  150. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
  151. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
  152. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
  153. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
  154. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  155. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
  156. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  157. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
  158. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  159. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
  160. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  161. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  162. 0x1000, 0x0020, 0, 0, netmos_9855_2p },
  163. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  164. 0x1000, 0x0022, 0, 0, netmos_9855_2p },
  165. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  166. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
  167. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  168. 0xA000, 0x3011, 0, 0, netmos_9900 },
  169. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  170. 0xA000, 0x3012, 0, 0, netmos_9900 },
  171. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  172. 0xA000, 0x3020, 0, 0, netmos_9900_2p },
  173. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  174. 0xA000, 0x2000, 0, 0, netmos_99xx_1p },
  175. /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
  176. { PCI_VENDOR_ID_AFAVLAB, 0x2110,
  177. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  178. { PCI_VENDOR_ID_AFAVLAB, 0x2111,
  179. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  180. { PCI_VENDOR_ID_AFAVLAB, 0x2112,
  181. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  182. { PCI_VENDOR_ID_AFAVLAB, 0x2140,
  183. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  184. { PCI_VENDOR_ID_AFAVLAB, 0x2141,
  185. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  186. { PCI_VENDOR_ID_AFAVLAB, 0x2142,
  187. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  188. { PCI_VENDOR_ID_AFAVLAB, 0x2160,
  189. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  190. { PCI_VENDOR_ID_AFAVLAB, 0x2161,
  191. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  192. { PCI_VENDOR_ID_AFAVLAB, 0x2162,
  193. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  194. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
  195. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  196. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
  197. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  198. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
  199. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  200. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
  201. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  202. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
  203. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  204. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
  205. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  206. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
  207. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  208. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
  209. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  210. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
  211. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  212. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
  213. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  214. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
  215. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  216. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
  217. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  218. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
  219. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  220. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
  221. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  222. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
  223. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  224. /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
  225. { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
  226. { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
  227. { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
  228. { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
  229. { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
  230. { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
  231. { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
  232. { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
  233. { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
  234. { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
  235. { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
  236. { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
  237. { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
  238. { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
  239. { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
  240. { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
  241. { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
  242. { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
  243. /* WCH CARDS */
  244. { 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
  245. /*
  246. * More SUNIX variations. At least one of these has part number
  247. * '5079A but subdevice 0x102. That board reports 0x0708 as
  248. * its PCI Class.
  249. */
  250. { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
  251. 0x0102, 0, 0, sunix_2s1p },
  252. { 0, } /* terminate list */
  253. };
  254. MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
  255. /*
  256. * This table describes the serial "geometry" of these boards. Any
  257. * quirks for these can be found in drivers/serial/8250_pci.c
  258. *
  259. * Cards not tested are marked n/t
  260. * If you have one of these cards and it works for you, please tell me..
  261. */
  262. static struct pciserial_board pci_parport_serial_boards[] = {
  263. [titan_110l] = {
  264. .flags = FL_BASE1 | FL_BASE_BARS,
  265. .num_ports = 1,
  266. .base_baud = 921600,
  267. .uart_offset = 8,
  268. },
  269. [titan_210l] = {
  270. .flags = FL_BASE1 | FL_BASE_BARS,
  271. .num_ports = 2,
  272. .base_baud = 921600,
  273. .uart_offset = 8,
  274. },
  275. [netmos_9xx5_combo] = {
  276. .flags = FL_BASE0 | FL_BASE_BARS,
  277. .num_ports = 1,
  278. .base_baud = 115200,
  279. .uart_offset = 8,
  280. },
  281. [netmos_9855] = {
  282. .flags = FL_BASE2 | FL_BASE_BARS,
  283. .num_ports = 1,
  284. .base_baud = 115200,
  285. .uart_offset = 8,
  286. },
  287. [netmos_9855_2p] = {
  288. .flags = FL_BASE4 | FL_BASE_BARS,
  289. .num_ports = 1,
  290. .base_baud = 115200,
  291. .uart_offset = 8,
  292. },
  293. [netmos_9900] = { /* n/t */
  294. .flags = FL_BASE0 | FL_BASE_BARS,
  295. .num_ports = 1,
  296. .base_baud = 115200,
  297. .uart_offset = 8,
  298. },
  299. [netmos_9900_2p] = { /* parallel only */ /* n/t */
  300. .flags = FL_BASE0,
  301. .num_ports = 0,
  302. .base_baud = 115200,
  303. .uart_offset = 8,
  304. },
  305. [netmos_99xx_1p] = { /* parallel only */ /* n/t */
  306. .flags = FL_BASE0,
  307. .num_ports = 0,
  308. .base_baud = 115200,
  309. .uart_offset = 8,
  310. },
  311. [avlab_1s1p] = { /* n/t */
  312. .flags = FL_BASE0 | FL_BASE_BARS,
  313. .num_ports = 1,
  314. .base_baud = 115200,
  315. .uart_offset = 8,
  316. },
  317. [avlab_1s2p] = { /* n/t */
  318. .flags = FL_BASE0 | FL_BASE_BARS,
  319. .num_ports = 1,
  320. .base_baud = 115200,
  321. .uart_offset = 8,
  322. },
  323. [avlab_2s1p] = { /* n/t */
  324. .flags = FL_BASE0 | FL_BASE_BARS,
  325. .num_ports = 2,
  326. .base_baud = 115200,
  327. .uart_offset = 8,
  328. },
  329. [siig_1s1p_10x] = {
  330. .flags = FL_BASE2,
  331. .num_ports = 1,
  332. .base_baud = 460800,
  333. .uart_offset = 8,
  334. },
  335. [siig_2s1p_10x] = {
  336. .flags = FL_BASE2,
  337. .num_ports = 1,
  338. .base_baud = 921600,
  339. .uart_offset = 8,
  340. },
  341. [siig_2p1s_20x] = {
  342. .flags = FL_BASE0,
  343. .num_ports = 1,
  344. .base_baud = 921600,
  345. .uart_offset = 8,
  346. },
  347. [siig_1s1p_20x] = {
  348. .flags = FL_BASE0,
  349. .num_ports = 1,
  350. .base_baud = 921600,
  351. .uart_offset = 8,
  352. },
  353. [siig_2s1p_20x] = {
  354. .flags = FL_BASE0,
  355. .num_ports = 1,
  356. .base_baud = 921600,
  357. .uart_offset = 8,
  358. },
  359. [timedia_4078a] = {
  360. .flags = FL_BASE0|FL_BASE_BARS,
  361. .num_ports = 1,
  362. .base_baud = 921600,
  363. .uart_offset = 8,
  364. },
  365. [timedia_4079h] = {
  366. .flags = FL_BASE0|FL_BASE_BARS,
  367. .num_ports = 1,
  368. .base_baud = 921600,
  369. .uart_offset = 8,
  370. },
  371. [timedia_4085h] = {
  372. .flags = FL_BASE0|FL_BASE_BARS,
  373. .num_ports = 1,
  374. .base_baud = 921600,
  375. .uart_offset = 8,
  376. },
  377. [timedia_4088a] = {
  378. .flags = FL_BASE0|FL_BASE_BARS,
  379. .num_ports = 1,
  380. .base_baud = 921600,
  381. .uart_offset = 8,
  382. },
  383. [timedia_4089a] = {
  384. .flags = FL_BASE0|FL_BASE_BARS,
  385. .num_ports = 1,
  386. .base_baud = 921600,
  387. .uart_offset = 8,
  388. },
  389. [timedia_4095a] = {
  390. .flags = FL_BASE0|FL_BASE_BARS,
  391. .num_ports = 1,
  392. .base_baud = 921600,
  393. .uart_offset = 8,
  394. },
  395. [timedia_4096a] = {
  396. .flags = FL_BASE0|FL_BASE_BARS,
  397. .num_ports = 1,
  398. .base_baud = 921600,
  399. .uart_offset = 8,
  400. },
  401. [timedia_4078u] = {
  402. .flags = FL_BASE0|FL_BASE_BARS,
  403. .num_ports = 1,
  404. .base_baud = 921600,
  405. .uart_offset = 8,
  406. },
  407. [timedia_4079a] = {
  408. .flags = FL_BASE0|FL_BASE_BARS,
  409. .num_ports = 1,
  410. .base_baud = 921600,
  411. .uart_offset = 8,
  412. },
  413. [timedia_4085u] = {
  414. .flags = FL_BASE0|FL_BASE_BARS,
  415. .num_ports = 1,
  416. .base_baud = 921600,
  417. .uart_offset = 8,
  418. },
  419. [timedia_4079r] = {
  420. .flags = FL_BASE0|FL_BASE_BARS,
  421. .num_ports = 1,
  422. .base_baud = 921600,
  423. .uart_offset = 8,
  424. },
  425. [timedia_4079s] = {
  426. .flags = FL_BASE0|FL_BASE_BARS,
  427. .num_ports = 1,
  428. .base_baud = 921600,
  429. .uart_offset = 8,
  430. },
  431. [timedia_4079d] = {
  432. .flags = FL_BASE0|FL_BASE_BARS,
  433. .num_ports = 1,
  434. .base_baud = 921600,
  435. .uart_offset = 8,
  436. },
  437. [timedia_4079e] = {
  438. .flags = FL_BASE0|FL_BASE_BARS,
  439. .num_ports = 1,
  440. .base_baud = 921600,
  441. .uart_offset = 8,
  442. },
  443. [timedia_4079f] = {
  444. .flags = FL_BASE0|FL_BASE_BARS,
  445. .num_ports = 1,
  446. .base_baud = 921600,
  447. .uart_offset = 8,
  448. },
  449. [timedia_9079a] = {
  450. .flags = FL_BASE0|FL_BASE_BARS,
  451. .num_ports = 1,
  452. .base_baud = 921600,
  453. .uart_offset = 8,
  454. },
  455. [timedia_9079b] = {
  456. .flags = FL_BASE0|FL_BASE_BARS,
  457. .num_ports = 1,
  458. .base_baud = 921600,
  459. .uart_offset = 8,
  460. },
  461. [timedia_9079c] = {
  462. .flags = FL_BASE0|FL_BASE_BARS,
  463. .num_ports = 1,
  464. .base_baud = 921600,
  465. .uart_offset = 8,
  466. },
  467. [wch_ch353_2s1p] = {
  468. .flags = FL_BASE0|FL_BASE_BARS,
  469. .num_ports = 2,
  470. .base_baud = 115200,
  471. .uart_offset = 8,
  472. },
  473. [sunix_2s1p] = {
  474. .flags = FL_BASE0|FL_BASE_BARS,
  475. .num_ports = 2,
  476. .base_baud = 921600,
  477. .uart_offset = 8,
  478. },
  479. };
  480. struct parport_serial_private {
  481. struct serial_private *serial;
  482. int num_par;
  483. struct parport *port[PARPORT_MAX];
  484. struct parport_pc_pci par;
  485. };
  486. /* Register the serial port(s) of a PCI card. */
  487. static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
  488. {
  489. struct parport_serial_private *priv = pci_get_drvdata (dev);
  490. struct pciserial_board *board;
  491. struct serial_private *serial;
  492. board = &pci_parport_serial_boards[id->driver_data];
  493. if (board->num_ports == 0)
  494. return 0;
  495. serial = pciserial_init_ports(dev, board);
  496. if (IS_ERR(serial))
  497. return PTR_ERR(serial);
  498. priv->serial = serial;
  499. return 0;
  500. }
  501. /* Register the parallel port(s) of a PCI card. */
  502. static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
  503. {
  504. struct parport_pc_pci *card;
  505. struct parport_serial_private *priv = pci_get_drvdata (dev);
  506. int n, success = 0;
  507. priv->par = cards[id->driver_data];
  508. card = &priv->par;
  509. if (card->preinit_hook &&
  510. card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
  511. return -ENODEV;
  512. for (n = 0; n < card->numports; n++) {
  513. struct parport *port;
  514. int lo = card->addr[n].lo;
  515. int hi = card->addr[n].hi;
  516. unsigned long io_lo, io_hi;
  517. int irq;
  518. if (priv->num_par == ARRAY_SIZE (priv->port)) {
  519. printk (KERN_WARNING
  520. "parport_serial: %s: only %zu parallel ports "
  521. "supported (%d reported)\n", pci_name (dev),
  522. ARRAY_SIZE(priv->port), card->numports);
  523. break;
  524. }
  525. io_lo = pci_resource_start (dev, lo);
  526. io_hi = 0;
  527. if ((hi >= 0) && (hi <= 6))
  528. io_hi = pci_resource_start (dev, hi);
  529. else if (hi > 6)
  530. io_lo += hi; /* Reinterpret the meaning of
  531. "hi" as an offset (see SYBA
  532. def.) */
  533. /* TODO: test if sharing interrupts works */
  534. irq = dev->irq;
  535. if (irq == IRQ_NONE) {
  536. dev_dbg(&dev->dev,
  537. "PCI parallel port detected: I/O at %#lx(%#lx)\n",
  538. io_lo, io_hi);
  539. irq = PARPORT_IRQ_NONE;
  540. } else {
  541. dev_dbg(&dev->dev,
  542. "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
  543. io_lo, io_hi, irq);
  544. }
  545. port = parport_pc_probe_port (io_lo, io_hi, irq,
  546. PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
  547. if (port) {
  548. priv->port[priv->num_par++] = port;
  549. success = 1;
  550. }
  551. }
  552. if (card->postinit_hook)
  553. card->postinit_hook (dev, card, !success);
  554. return 0;
  555. }
  556. static int parport_serial_pci_probe(struct pci_dev *dev,
  557. const struct pci_device_id *id)
  558. {
  559. struct parport_serial_private *priv;
  560. int err;
  561. priv = kzalloc (sizeof *priv, GFP_KERNEL);
  562. if (!priv)
  563. return -ENOMEM;
  564. pci_set_drvdata (dev, priv);
  565. err = pci_enable_device (dev);
  566. if (err) {
  567. pci_set_drvdata (dev, NULL);
  568. kfree (priv);
  569. return err;
  570. }
  571. if (parport_register (dev, id)) {
  572. pci_set_drvdata (dev, NULL);
  573. kfree (priv);
  574. return -ENODEV;
  575. }
  576. if (serial_register (dev, id)) {
  577. int i;
  578. for (i = 0; i < priv->num_par; i++)
  579. parport_pc_unregister_port (priv->port[i]);
  580. pci_set_drvdata (dev, NULL);
  581. kfree (priv);
  582. return -ENODEV;
  583. }
  584. return 0;
  585. }
  586. static void parport_serial_pci_remove(struct pci_dev *dev)
  587. {
  588. struct parport_serial_private *priv = pci_get_drvdata (dev);
  589. int i;
  590. pci_set_drvdata(dev, NULL);
  591. // Serial ports
  592. if (priv->serial)
  593. pciserial_remove_ports(priv->serial);
  594. // Parallel ports
  595. for (i = 0; i < priv->num_par; i++)
  596. parport_pc_unregister_port (priv->port[i]);
  597. kfree (priv);
  598. return;
  599. }
  600. #ifdef CONFIG_PM
  601. static int parport_serial_pci_suspend(struct pci_dev *dev, pm_message_t state)
  602. {
  603. struct parport_serial_private *priv = pci_get_drvdata(dev);
  604. if (priv->serial)
  605. pciserial_suspend_ports(priv->serial);
  606. /* FIXME: What about parport? */
  607. pci_save_state(dev);
  608. pci_set_power_state(dev, pci_choose_state(dev, state));
  609. return 0;
  610. }
  611. static int parport_serial_pci_resume(struct pci_dev *dev)
  612. {
  613. struct parport_serial_private *priv = pci_get_drvdata(dev);
  614. int err;
  615. pci_set_power_state(dev, PCI_D0);
  616. pci_restore_state(dev);
  617. /*
  618. * The device may have been disabled. Re-enable it.
  619. */
  620. err = pci_enable_device(dev);
  621. if (err) {
  622. printk(KERN_ERR "parport_serial: %s: error enabling "
  623. "device for resume (%d)\n", pci_name(dev), err);
  624. return err;
  625. }
  626. if (priv->serial)
  627. pciserial_resume_ports(priv->serial);
  628. /* FIXME: What about parport? */
  629. return 0;
  630. }
  631. #endif
  632. static struct pci_driver parport_serial_pci_driver = {
  633. .name = "parport_serial",
  634. .id_table = parport_serial_pci_tbl,
  635. .probe = parport_serial_pci_probe,
  636. .remove = parport_serial_pci_remove,
  637. #ifdef CONFIG_PM
  638. .suspend = parport_serial_pci_suspend,
  639. .resume = parport_serial_pci_resume,
  640. #endif
  641. };
  642. static int __init parport_serial_init (void)
  643. {
  644. return pci_register_driver (&parport_serial_pci_driver);
  645. }
  646. static void __exit parport_serial_exit (void)
  647. {
  648. pci_unregister_driver (&parport_serial_pci_driver);
  649. return;
  650. }
  651. MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
  652. MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
  653. MODULE_LICENSE("GPL");
  654. module_init(parport_serial_init);
  655. module_exit(parport_serial_exit);