sw.c 12 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include <linux/vmalloc.h>
  31. #include <linux/module.h>
  32. #include "../core.h"
  33. #include "../pci.h"
  34. #include "reg.h"
  35. #include "def.h"
  36. #include "phy.h"
  37. #include "dm.h"
  38. #include "hw.h"
  39. #include "sw.h"
  40. #include "trx.h"
  41. #include "led.h"
  42. #include "table.h"
  43. #include "hal_btc.h"
  44. static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
  45. {
  46. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  47. /*close ASPM for AMD defaultly */
  48. rtlpci->const_amdpci_aspm = 0;
  49. /* ASPM PS mode.
  50. * 0 - Disable ASPM,
  51. * 1 - Enable ASPM without Clock Req,
  52. * 2 - Enable ASPM with Clock Req,
  53. * 3 - Alwyas Enable ASPM with Clock Req,
  54. * 4 - Always Enable ASPM without Clock Req.
  55. * set defult to RTL8192CE:3 RTL8192E:2
  56. */
  57. rtlpci->const_pci_aspm = 3;
  58. /*Setting for PCI-E device */
  59. rtlpci->const_devicepci_aspm_setting = 0x03;
  60. /*Setting for PCI-E bridge */
  61. rtlpci->const_hostpci_aspm_setting = 0x02;
  62. /* In Hw/Sw Radio Off situation.
  63. * 0 - Default,
  64. * 1 - From ASPM setting without low Mac Pwr,
  65. * 2 - From ASPM setting with low Mac Pwr,
  66. * 3 - Bus D3
  67. * set default to RTL8192CE:0 RTL8192SE:2
  68. */
  69. rtlpci->const_hwsw_rfoff_d3 = 0;
  70. /* This setting works for those device with
  71. * backdoor ASPM setting such as EPHY setting.
  72. * 0 - Not support ASPM,
  73. * 1 - Support ASPM,
  74. * 2 - According to chipset.
  75. */
  76. rtlpci->const_support_pciaspm = 1;
  77. }
  78. int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
  79. {
  80. struct rtl_priv *rtlpriv = rtl_priv(hw);
  81. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  82. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  83. int err;
  84. rtl8723ae_bt_reg_init(hw);
  85. rtlpriv->dm.dm_initialgain_enable = 1;
  86. rtlpriv->dm.dm_flag = 0;
  87. rtlpriv->dm.disable_framebursting = 0;
  88. rtlpriv->dm.thermalvalue = 0;
  89. rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
  90. /* compatible 5G band 88ce just 2.4G band & smsp */
  91. rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  92. rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  93. rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  94. rtlpci->receive_config = (RCR_APPFCS |
  95. RCR_APP_MIC |
  96. RCR_APP_ICV |
  97. RCR_APP_PHYST_RXFF |
  98. RCR_HTC_LOC_CTRL |
  99. RCR_AMF |
  100. RCR_ACF |
  101. RCR_ADF |
  102. RCR_AICV |
  103. RCR_AB |
  104. RCR_AM |
  105. RCR_APM |
  106. 0);
  107. rtlpci->irq_mask[0] =
  108. (u32) (PHIMR_ROK |
  109. PHIMR_RDU |
  110. PHIMR_VODOK |
  111. PHIMR_VIDOK |
  112. PHIMR_BEDOK |
  113. PHIMR_BKDOK |
  114. PHIMR_MGNTDOK |
  115. PHIMR_HIGHDOK |
  116. PHIMR_C2HCMD |
  117. PHIMR_HISRE_IND |
  118. PHIMR_TSF_BIT32_TOGGLE |
  119. PHIMR_TXBCNOK |
  120. PHIMR_PSTIMEOUT |
  121. 0);
  122. rtlpci->irq_mask[1] = (u32)(PHIMR_RXFOVW | 0);
  123. /* for debug level */
  124. rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
  125. /* for LPS & IPS */
  126. rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
  127. rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
  128. rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
  129. rtlpriv->psc.reg_fwctrl_lps = 3;
  130. rtlpriv->psc.reg_max_lps_awakeintvl = 5;
  131. /* for ASPM, you can close aspm through
  132. * set const_support_pciaspm = 0
  133. */
  134. rtl8723ae_init_aspm_vars(hw);
  135. if (rtlpriv->psc.reg_fwctrl_lps == 1)
  136. rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
  137. else if (rtlpriv->psc.reg_fwctrl_lps == 2)
  138. rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
  139. else if (rtlpriv->psc.reg_fwctrl_lps == 3)
  140. rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
  141. /* for firmware buf */
  142. rtlpriv->rtlhal.pfirmware = vmalloc(0x6000);
  143. if (!rtlpriv->rtlhal.pfirmware) {
  144. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  145. "Can't alloc buffer for fw.\n");
  146. return 1;
  147. }
  148. if (IS_VENDOR_8723_A_CUT(rtlhal->version))
  149. rtlpriv->cfg->fw_name = "rtlwifi/rtl8723fw.bin";
  150. else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
  151. rtlpriv->cfg->fw_name = "rtlwifi/rtl8723fw_B.bin";
  152. rtlpriv->max_fw_size = 0x6000;
  153. pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
  154. err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
  155. rtlpriv->io.dev, GFP_KERNEL, hw,
  156. rtl_fw_cb);
  157. if (err) {
  158. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  159. "Failed to request firmware!\n");
  160. return 1;
  161. }
  162. return 0;
  163. }
  164. void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw)
  165. {
  166. struct rtl_priv *rtlpriv = rtl_priv(hw);
  167. if (rtlpriv->rtlhal.pfirmware) {
  168. vfree(rtlpriv->rtlhal.pfirmware);
  169. rtlpriv->rtlhal.pfirmware = NULL;
  170. }
  171. }
  172. static struct rtl_hal_ops rtl8723ae_hal_ops = {
  173. .init_sw_vars = rtl8723ae_init_sw_vars,
  174. .deinit_sw_vars = rtl8723ae_deinit_sw_vars,
  175. .read_eeprom_info = rtl8723ae_read_eeprom_info,
  176. .interrupt_recognized = rtl8723ae_interrupt_recognized,
  177. .hw_init = rtl8723ae_hw_init,
  178. .hw_disable = rtl8723ae_card_disable,
  179. .hw_suspend = rtl8723ae_suspend,
  180. .hw_resume = rtl8723ae_resume,
  181. .enable_interrupt = rtl8723ae_enable_interrupt,
  182. .disable_interrupt = rtl8723ae_disable_interrupt,
  183. .set_network_type = rtl8723ae_set_network_type,
  184. .set_chk_bssid = rtl8723ae_set_check_bssid,
  185. .set_qos = rtl8723ae_set_qos,
  186. .set_bcn_reg = rtl8723ae_set_beacon_related_registers,
  187. .set_bcn_intv = rtl8723ae_set_beacon_interval,
  188. .update_interrupt_mask = rtl8723ae_update_interrupt_mask,
  189. .get_hw_reg = rtl8723ae_get_hw_reg,
  190. .set_hw_reg = rtl8723ae_set_hw_reg,
  191. .update_rate_tbl = rtl8723ae_update_hal_rate_tbl,
  192. .fill_tx_desc = rtl8723ae_tx_fill_desc,
  193. .fill_tx_cmddesc = rtl8723ae_tx_fill_cmddesc,
  194. .query_rx_desc = rtl8723ae_rx_query_desc,
  195. .set_channel_access = rtl8723ae_update_channel_access_setting,
  196. .radio_onoff_checking = rtl8723ae_gpio_radio_on_off_checking,
  197. .set_bw_mode = rtl8723ae_phy_set_bw_mode,
  198. .switch_channel = rtl8723ae_phy_sw_chnl,
  199. .dm_watchdog = rtl8723ae_dm_watchdog,
  200. .scan_operation_backup = rtl8723ae_phy_scan_operation_backup,
  201. .set_rf_power_state = rtl8723ae_phy_set_rf_power_state,
  202. .led_control = rtl8723ae_led_control,
  203. .set_desc = rtl8723ae_set_desc,
  204. .get_desc = rtl8723ae_get_desc,
  205. .tx_polling = rtl8723ae_tx_polling,
  206. .enable_hw_sec = rtl8723ae_enable_hw_security_config,
  207. .set_key = rtl8723ae_set_key,
  208. .init_sw_leds = rtl8723ae_init_sw_leds,
  209. .allow_all_destaddr = rtl8723ae_allow_all_destaddr,
  210. .get_bbreg = rtl8723ae_phy_query_bb_reg,
  211. .set_bbreg = rtl8723ae_phy_set_bb_reg,
  212. .get_rfreg = rtl8723ae_phy_query_rf_reg,
  213. .set_rfreg = rtl8723ae_phy_set_rf_reg,
  214. .c2h_command_handle = rtl_8723e_c2h_command_handle,
  215. .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
  216. .bt_coex_off_before_lps = rtl8723ae_bt_coex_off_before_lps,
  217. };
  218. static struct rtl_mod_params rtl8723ae_mod_params = {
  219. .sw_crypto = false,
  220. .inactiveps = true,
  221. .swctrl_lps = false,
  222. .fwctrl_lps = true,
  223. .debug = DBG_EMERG,
  224. };
  225. static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
  226. .bar_id = 2,
  227. .write_readback = true,
  228. .name = "rtl8723ae_pci",
  229. .fw_name = "rtlwifi/rtl8723aefw.bin",
  230. .ops = &rtl8723ae_hal_ops,
  231. .mod_params = &rtl8723ae_mod_params,
  232. .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
  233. .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
  234. .maps[SYS_CLK] = REG_SYS_CLKR,
  235. .maps[MAC_RCR_AM] = AM,
  236. .maps[MAC_RCR_AB] = AB,
  237. .maps[MAC_RCR_ACRC32] = ACRC32,
  238. .maps[MAC_RCR_ACF] = ACF,
  239. .maps[MAC_RCR_AAP] = AAP,
  240. .maps[EFUSE_TEST] = REG_EFUSE_TEST,
  241. .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
  242. .maps[EFUSE_CLK] = 0,
  243. .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
  244. .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
  245. .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
  246. .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
  247. .maps[EFUSE_ANA8M] = ANA8M,
  248. .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
  249. .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
  250. .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
  251. .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
  252. .maps[RWCAM] = REG_CAMCMD,
  253. .maps[WCAMI] = REG_CAMWRITE,
  254. .maps[RCAMO] = REG_CAMREAD,
  255. .maps[CAMDBG] = REG_CAMDBG,
  256. .maps[SECR] = REG_SECCFG,
  257. .maps[SEC_CAM_NONE] = CAM_NONE,
  258. .maps[SEC_CAM_WEP40] = CAM_WEP40,
  259. .maps[SEC_CAM_TKIP] = CAM_TKIP,
  260. .maps[SEC_CAM_AES] = CAM_AES,
  261. .maps[SEC_CAM_WEP104] = CAM_WEP104,
  262. .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
  263. .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
  264. .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
  265. .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
  266. .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
  267. .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
  268. .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
  269. .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
  270. .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
  271. .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
  272. .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
  273. .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
  274. .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
  275. .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
  276. .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
  277. .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
  278. .maps[RTL_IMR_TXFOVW] = PHIMR_TXFOVW,
  279. .maps[RTL_IMR_PSTIMEOUT] = PHIMR_PSTIMEOUT,
  280. .maps[RTL_IMR_BcnInt] = PHIMR_BCNDMAINT0,
  281. .maps[RTL_IMR_RXFOVW] = PHIMR_RXFOVW,
  282. .maps[RTL_IMR_RDU] = PHIMR_RDU,
  283. .maps[RTL_IMR_ATIMEND] = PHIMR_ATIMEND_E,
  284. .maps[RTL_IMR_BDOK] = PHIMR_BCNDOK0,
  285. .maps[RTL_IMR_MGNTDOK] = PHIMR_MGNTDOK,
  286. .maps[RTL_IMR_TBDER] = PHIMR_TXBCNERR,
  287. .maps[RTL_IMR_HIGHDOK] = PHIMR_HIGHDOK,
  288. .maps[RTL_IMR_TBDOK] = PHIMR_TXBCNOK,
  289. .maps[RTL_IMR_BKDOK] = PHIMR_BKDOK,
  290. .maps[RTL_IMR_BEDOK] = PHIMR_BEDOK,
  291. .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
  292. .maps[RTL_IMR_VODOK] = PHIMR_VODOK,
  293. .maps[RTL_IMR_ROK] = PHIMR_ROK,
  294. .maps[RTL_IBSS_INT_MASKS] = (PHIMR_BCNDMAINT0 |
  295. PHIMR_TXBCNOK | PHIMR_TXBCNERR),
  296. .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
  297. .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
  298. .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
  299. .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
  300. .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
  301. .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
  302. .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
  303. .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
  304. .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
  305. .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
  306. .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
  307. .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
  308. .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
  309. .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
  310. .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
  311. };
  312. static struct pci_device_id rtl8723ae_pci_ids[] = {
  313. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723ae_hal_cfg)},
  314. {},
  315. };
  316. MODULE_DEVICE_TABLE(pci, rtl8723ae_pci_ids);
  317. MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
  318. MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
  319. MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
  320. MODULE_LICENSE("GPL");
  321. MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
  322. MODULE_FIRMWARE("rtlwifi/rtl8723aefw.bin");
  323. MODULE_FIRMWARE("rtlwifi/rtl8723aefw_B.bin");
  324. module_param_named(swenc, rtl8723ae_mod_params.sw_crypto, bool, 0444);
  325. module_param_named(debug, rtl8723ae_mod_params.debug, int, 0444);
  326. module_param_named(ips, rtl8723ae_mod_params.inactiveps, bool, 0444);
  327. module_param_named(swlps, rtl8723ae_mod_params.swctrl_lps, bool, 0444);
  328. module_param_named(fwlps, rtl8723ae_mod_params.fwctrl_lps, bool, 0444);
  329. MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
  330. MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
  331. MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
  332. MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
  333. MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
  334. static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
  335. static struct pci_driver rtl8723ae_driver = {
  336. .name = KBUILD_MODNAME,
  337. .id_table = rtl8723ae_pci_ids,
  338. .probe = rtl_pci_probe,
  339. .remove = rtl_pci_disconnect,
  340. .driver.pm = &rtlwifi_pm_ops,
  341. };
  342. module_pci_driver(rtl8723ae_driver);