pwrseqcmd.c 4.0 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "pwrseq.h"
  30. /* Description:
  31. * This routine deals with the Power Configuration CMD
  32. * parsing for RTL8723/RTL8188E Series IC.
  33. * Assumption:
  34. * We should follow specific format that was released from HW SD.
  35. */
  36. bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
  37. u8 faversion, u8 interface_type,
  38. struct wlan_pwr_cfg pwrcfgcmd[])
  39. {
  40. struct wlan_pwr_cfg cfg_cmd = {0};
  41. bool polling_bit = false;
  42. u32 ary_idx = 0;
  43. u8 value = 0;
  44. u32 offset = 0;
  45. u32 polling_count = 0;
  46. u32 max_polling_cnt = 5000;
  47. do {
  48. cfg_cmd = pwrcfgcmd[ary_idx];
  49. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  50. "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x),"
  51. "interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
  52. GET_PWR_CFG_OFFSET(cfg_cmd),
  53. GET_PWR_CFG_CUT_MASK(cfg_cmd),
  54. GET_PWR_CFG_FAB_MASK(cfg_cmd),
  55. GET_PWR_CFG_INTF_MASK(cfg_cmd),
  56. GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
  57. GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
  58. if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) &&
  59. (GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) &&
  60. (GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) {
  61. switch (GET_PWR_CFG_CMD(cfg_cmd)) {
  62. case PWR_CMD_READ:
  63. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  64. "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
  65. break;
  66. case PWR_CMD_WRITE:
  67. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  68. "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
  69. offset = GET_PWR_CFG_OFFSET(cfg_cmd);
  70. /*Read the value from system register*/
  71. value = rtl_read_byte(rtlpriv, offset);
  72. value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
  73. value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
  74. GET_PWR_CFG_MASK(cfg_cmd));
  75. /*Write the value back to sytem register*/
  76. rtl_write_byte(rtlpriv, offset, value);
  77. break;
  78. case PWR_CMD_POLLING:
  79. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  80. "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
  81. polling_bit = false;
  82. offset = GET_PWR_CFG_OFFSET(cfg_cmd);
  83. do {
  84. value = rtl_read_byte(rtlpriv, offset);
  85. value &= GET_PWR_CFG_MASK(cfg_cmd);
  86. if (value ==
  87. (GET_PWR_CFG_VALUE(cfg_cmd)
  88. & GET_PWR_CFG_MASK(cfg_cmd)))
  89. polling_bit = true;
  90. else
  91. udelay(10);
  92. if (polling_count++ > max_polling_cnt)
  93. return false;
  94. } while (!polling_bit);
  95. break;
  96. case PWR_CMD_DELAY:
  97. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  98. "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
  99. if (GET_PWR_CFG_VALUE(cfg_cmd) ==
  100. PWRSEQ_DELAY_US)
  101. udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
  102. else
  103. mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
  104. break;
  105. case PWR_CMD_END:
  106. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  107. "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
  108. return true;
  109. default:
  110. RT_ASSERT(false,
  111. "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
  112. break;
  113. }
  114. }
  115. ary_idx++;
  116. } while (1);
  117. return true;
  118. }