common.c 141 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/types.h>
  34. #include <linux/lockdep.h>
  35. #include <linux/init.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/delay.h>
  39. #include <linux/skbuff.h>
  40. #include <net/mac80211.h>
  41. #include "common.h"
  42. int
  43. _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
  44. {
  45. const int interval = 10; /* microseconds */
  46. int t = 0;
  47. do {
  48. if ((_il_rd(il, addr) & mask) == (bits & mask))
  49. return t;
  50. udelay(interval);
  51. t += interval;
  52. } while (t < timeout);
  53. return -ETIMEDOUT;
  54. }
  55. EXPORT_SYMBOL(_il_poll_bit);
  56. void
  57. il_set_bit(struct il_priv *p, u32 r, u32 m)
  58. {
  59. unsigned long reg_flags;
  60. spin_lock_irqsave(&p->reg_lock, reg_flags);
  61. _il_set_bit(p, r, m);
  62. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  63. }
  64. EXPORT_SYMBOL(il_set_bit);
  65. void
  66. il_clear_bit(struct il_priv *p, u32 r, u32 m)
  67. {
  68. unsigned long reg_flags;
  69. spin_lock_irqsave(&p->reg_lock, reg_flags);
  70. _il_clear_bit(p, r, m);
  71. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  72. }
  73. EXPORT_SYMBOL(il_clear_bit);
  74. bool
  75. _il_grab_nic_access(struct il_priv *il)
  76. {
  77. int ret;
  78. u32 val;
  79. /* this bit wakes up the NIC */
  80. _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  81. /*
  82. * These bits say the device is running, and should keep running for
  83. * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  84. * but they do not indicate that embedded SRAM is restored yet;
  85. * 3945 and 4965 have volatile SRAM, and must save/restore contents
  86. * to/from host DRAM when sleeping/waking for power-saving.
  87. * Each direction takes approximately 1/4 millisecond; with this
  88. * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  89. * series of register accesses are expected (e.g. reading Event Log),
  90. * to keep device from sleeping.
  91. *
  92. * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
  93. * SRAM is okay/restored. We don't check that here because this call
  94. * is just for hardware register access; but GP1 MAC_SLEEP check is a
  95. * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
  96. *
  97. */
  98. ret =
  99. _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
  100. (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
  101. CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
  102. if (unlikely(ret < 0)) {
  103. val = _il_rd(il, CSR_GP_CNTRL);
  104. WARN_ONCE(1, "Timeout waiting for ucode processor access "
  105. "(CSR_GP_CNTRL 0x%08x)\n", val);
  106. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
  107. return false;
  108. }
  109. return true;
  110. }
  111. EXPORT_SYMBOL_GPL(_il_grab_nic_access);
  112. int
  113. il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
  114. {
  115. const int interval = 10; /* microseconds */
  116. int t = 0;
  117. do {
  118. if ((il_rd(il, addr) & mask) == mask)
  119. return t;
  120. udelay(interval);
  121. t += interval;
  122. } while (t < timeout);
  123. return -ETIMEDOUT;
  124. }
  125. EXPORT_SYMBOL(il_poll_bit);
  126. u32
  127. il_rd_prph(struct il_priv *il, u32 reg)
  128. {
  129. unsigned long reg_flags;
  130. u32 val;
  131. spin_lock_irqsave(&il->reg_lock, reg_flags);
  132. _il_grab_nic_access(il);
  133. val = _il_rd_prph(il, reg);
  134. _il_release_nic_access(il);
  135. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  136. return val;
  137. }
  138. EXPORT_SYMBOL(il_rd_prph);
  139. void
  140. il_wr_prph(struct il_priv *il, u32 addr, u32 val)
  141. {
  142. unsigned long reg_flags;
  143. spin_lock_irqsave(&il->reg_lock, reg_flags);
  144. if (likely(_il_grab_nic_access(il))) {
  145. _il_wr_prph(il, addr, val);
  146. _il_release_nic_access(il);
  147. }
  148. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  149. }
  150. EXPORT_SYMBOL(il_wr_prph);
  151. u32
  152. il_read_targ_mem(struct il_priv *il, u32 addr)
  153. {
  154. unsigned long reg_flags;
  155. u32 value;
  156. spin_lock_irqsave(&il->reg_lock, reg_flags);
  157. _il_grab_nic_access(il);
  158. _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
  159. value = _il_rd(il, HBUS_TARG_MEM_RDAT);
  160. _il_release_nic_access(il);
  161. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  162. return value;
  163. }
  164. EXPORT_SYMBOL(il_read_targ_mem);
  165. void
  166. il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
  167. {
  168. unsigned long reg_flags;
  169. spin_lock_irqsave(&il->reg_lock, reg_flags);
  170. if (likely(_il_grab_nic_access(il))) {
  171. _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
  172. _il_wr(il, HBUS_TARG_MEM_WDAT, val);
  173. _il_release_nic_access(il);
  174. }
  175. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  176. }
  177. EXPORT_SYMBOL(il_write_targ_mem);
  178. const char *
  179. il_get_cmd_string(u8 cmd)
  180. {
  181. switch (cmd) {
  182. IL_CMD(N_ALIVE);
  183. IL_CMD(N_ERROR);
  184. IL_CMD(C_RXON);
  185. IL_CMD(C_RXON_ASSOC);
  186. IL_CMD(C_QOS_PARAM);
  187. IL_CMD(C_RXON_TIMING);
  188. IL_CMD(C_ADD_STA);
  189. IL_CMD(C_REM_STA);
  190. IL_CMD(C_WEPKEY);
  191. IL_CMD(N_3945_RX);
  192. IL_CMD(C_TX);
  193. IL_CMD(C_RATE_SCALE);
  194. IL_CMD(C_LEDS);
  195. IL_CMD(C_TX_LINK_QUALITY_CMD);
  196. IL_CMD(C_CHANNEL_SWITCH);
  197. IL_CMD(N_CHANNEL_SWITCH);
  198. IL_CMD(C_SPECTRUM_MEASUREMENT);
  199. IL_CMD(N_SPECTRUM_MEASUREMENT);
  200. IL_CMD(C_POWER_TBL);
  201. IL_CMD(N_PM_SLEEP);
  202. IL_CMD(N_PM_DEBUG_STATS);
  203. IL_CMD(C_SCAN);
  204. IL_CMD(C_SCAN_ABORT);
  205. IL_CMD(N_SCAN_START);
  206. IL_CMD(N_SCAN_RESULTS);
  207. IL_CMD(N_SCAN_COMPLETE);
  208. IL_CMD(N_BEACON);
  209. IL_CMD(C_TX_BEACON);
  210. IL_CMD(C_TX_PWR_TBL);
  211. IL_CMD(C_BT_CONFIG);
  212. IL_CMD(C_STATS);
  213. IL_CMD(N_STATS);
  214. IL_CMD(N_CARD_STATE);
  215. IL_CMD(N_MISSED_BEACONS);
  216. IL_CMD(C_CT_KILL_CONFIG);
  217. IL_CMD(C_SENSITIVITY);
  218. IL_CMD(C_PHY_CALIBRATION);
  219. IL_CMD(N_RX_PHY);
  220. IL_CMD(N_RX_MPDU);
  221. IL_CMD(N_RX);
  222. IL_CMD(N_COMPRESSED_BA);
  223. default:
  224. return "UNKNOWN";
  225. }
  226. }
  227. EXPORT_SYMBOL(il_get_cmd_string);
  228. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  229. static void
  230. il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
  231. struct il_rx_pkt *pkt)
  232. {
  233. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  234. IL_ERR("Bad return from %s (0x%08X)\n",
  235. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  236. return;
  237. }
  238. #ifdef CONFIG_IWLEGACY_DEBUG
  239. switch (cmd->hdr.cmd) {
  240. case C_TX_LINK_QUALITY_CMD:
  241. case C_SENSITIVITY:
  242. D_HC_DUMP("back from %s (0x%08X)\n",
  243. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  244. break;
  245. default:
  246. D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
  247. pkt->hdr.flags);
  248. }
  249. #endif
  250. }
  251. static int
  252. il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
  253. {
  254. int ret;
  255. BUG_ON(!(cmd->flags & CMD_ASYNC));
  256. /* An asynchronous command can not expect an SKB to be set. */
  257. BUG_ON(cmd->flags & CMD_WANT_SKB);
  258. /* Assign a generic callback if one is not provided */
  259. if (!cmd->callback)
  260. cmd->callback = il_generic_cmd_callback;
  261. if (test_bit(S_EXIT_PENDING, &il->status))
  262. return -EBUSY;
  263. ret = il_enqueue_hcmd(il, cmd);
  264. if (ret < 0) {
  265. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  266. il_get_cmd_string(cmd->id), ret);
  267. return ret;
  268. }
  269. return 0;
  270. }
  271. int
  272. il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
  273. {
  274. int cmd_idx;
  275. int ret;
  276. lockdep_assert_held(&il->mutex);
  277. BUG_ON(cmd->flags & CMD_ASYNC);
  278. /* A synchronous command can not have a callback set. */
  279. BUG_ON(cmd->callback);
  280. D_INFO("Attempting to send sync command %s\n",
  281. il_get_cmd_string(cmd->id));
  282. set_bit(S_HCMD_ACTIVE, &il->status);
  283. D_INFO("Setting HCMD_ACTIVE for command %s\n",
  284. il_get_cmd_string(cmd->id));
  285. cmd_idx = il_enqueue_hcmd(il, cmd);
  286. if (cmd_idx < 0) {
  287. ret = cmd_idx;
  288. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  289. il_get_cmd_string(cmd->id), ret);
  290. goto out;
  291. }
  292. ret = wait_event_timeout(il->wait_command_queue,
  293. !test_bit(S_HCMD_ACTIVE, &il->status),
  294. HOST_COMPLETE_TIMEOUT);
  295. if (!ret) {
  296. if (test_bit(S_HCMD_ACTIVE, &il->status)) {
  297. IL_ERR("Error sending %s: time out after %dms.\n",
  298. il_get_cmd_string(cmd->id),
  299. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  300. clear_bit(S_HCMD_ACTIVE, &il->status);
  301. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  302. il_get_cmd_string(cmd->id));
  303. ret = -ETIMEDOUT;
  304. goto cancel;
  305. }
  306. }
  307. if (test_bit(S_RFKILL, &il->status)) {
  308. IL_ERR("Command %s aborted: RF KILL Switch\n",
  309. il_get_cmd_string(cmd->id));
  310. ret = -ECANCELED;
  311. goto fail;
  312. }
  313. if (test_bit(S_FW_ERROR, &il->status)) {
  314. IL_ERR("Command %s failed: FW Error\n",
  315. il_get_cmd_string(cmd->id));
  316. ret = -EIO;
  317. goto fail;
  318. }
  319. if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
  320. IL_ERR("Error: Response NULL in '%s'\n",
  321. il_get_cmd_string(cmd->id));
  322. ret = -EIO;
  323. goto cancel;
  324. }
  325. ret = 0;
  326. goto out;
  327. cancel:
  328. if (cmd->flags & CMD_WANT_SKB) {
  329. /*
  330. * Cancel the CMD_WANT_SKB flag for the cmd in the
  331. * TX cmd queue. Otherwise in case the cmd comes
  332. * in later, it will possibly set an invalid
  333. * address (cmd->meta.source).
  334. */
  335. il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
  336. }
  337. fail:
  338. if (cmd->reply_page) {
  339. il_free_pages(il, cmd->reply_page);
  340. cmd->reply_page = 0;
  341. }
  342. out:
  343. return ret;
  344. }
  345. EXPORT_SYMBOL(il_send_cmd_sync);
  346. int
  347. il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
  348. {
  349. if (cmd->flags & CMD_ASYNC)
  350. return il_send_cmd_async(il, cmd);
  351. return il_send_cmd_sync(il, cmd);
  352. }
  353. EXPORT_SYMBOL(il_send_cmd);
  354. int
  355. il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
  356. {
  357. struct il_host_cmd cmd = {
  358. .id = id,
  359. .len = len,
  360. .data = data,
  361. };
  362. return il_send_cmd_sync(il, &cmd);
  363. }
  364. EXPORT_SYMBOL(il_send_cmd_pdu);
  365. int
  366. il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
  367. void (*callback) (struct il_priv *il,
  368. struct il_device_cmd *cmd,
  369. struct il_rx_pkt *pkt))
  370. {
  371. struct il_host_cmd cmd = {
  372. .id = id,
  373. .len = len,
  374. .data = data,
  375. };
  376. cmd.flags |= CMD_ASYNC;
  377. cmd.callback = callback;
  378. return il_send_cmd_async(il, &cmd);
  379. }
  380. EXPORT_SYMBOL(il_send_cmd_pdu_async);
  381. /* default: IL_LED_BLINK(0) using blinking idx table */
  382. static int led_mode;
  383. module_param(led_mode, int, S_IRUGO);
  384. MODULE_PARM_DESC(led_mode,
  385. "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
  386. /* Throughput OFF time(ms) ON time (ms)
  387. * >300 25 25
  388. * >200 to 300 40 40
  389. * >100 to 200 55 55
  390. * >70 to 100 65 65
  391. * >50 to 70 75 75
  392. * >20 to 50 85 85
  393. * >10 to 20 95 95
  394. * >5 to 10 110 110
  395. * >1 to 5 130 130
  396. * >0 to 1 167 167
  397. * <=0 SOLID ON
  398. */
  399. static const struct ieee80211_tpt_blink il_blink[] = {
  400. {.throughput = 0, .blink_time = 334},
  401. {.throughput = 1 * 1024 - 1, .blink_time = 260},
  402. {.throughput = 5 * 1024 - 1, .blink_time = 220},
  403. {.throughput = 10 * 1024 - 1, .blink_time = 190},
  404. {.throughput = 20 * 1024 - 1, .blink_time = 170},
  405. {.throughput = 50 * 1024 - 1, .blink_time = 150},
  406. {.throughput = 70 * 1024 - 1, .blink_time = 130},
  407. {.throughput = 100 * 1024 - 1, .blink_time = 110},
  408. {.throughput = 200 * 1024 - 1, .blink_time = 80},
  409. {.throughput = 300 * 1024 - 1, .blink_time = 50},
  410. };
  411. /*
  412. * Adjust led blink rate to compensate on a MAC Clock difference on every HW
  413. * Led blink rate analysis showed an average deviation of 0% on 3945,
  414. * 5% on 4965 HW.
  415. * Need to compensate on the led on/off time per HW according to the deviation
  416. * to achieve the desired led frequency
  417. * The calculation is: (100-averageDeviation)/100 * blinkTime
  418. * For code efficiency the calculation will be:
  419. * compensation = (100 - averageDeviation) * 64 / 100
  420. * NewBlinkTime = (compensation * BlinkTime) / 64
  421. */
  422. static inline u8
  423. il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
  424. {
  425. if (!compensation) {
  426. IL_ERR("undefined blink compensation: "
  427. "use pre-defined blinking time\n");
  428. return time;
  429. }
  430. return (u8) ((time * compensation) >> 6);
  431. }
  432. /* Set led pattern command */
  433. static int
  434. il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
  435. {
  436. struct il_led_cmd led_cmd = {
  437. .id = IL_LED_LINK,
  438. .interval = IL_DEF_LED_INTRVL
  439. };
  440. int ret;
  441. if (!test_bit(S_READY, &il->status))
  442. return -EBUSY;
  443. if (il->blink_on == on && il->blink_off == off)
  444. return 0;
  445. if (off == 0) {
  446. /* led is SOLID_ON */
  447. on = IL_LED_SOLID;
  448. }
  449. D_LED("Led blink time compensation=%u\n",
  450. il->cfg->led_compensation);
  451. led_cmd.on =
  452. il_blink_compensation(il, on,
  453. il->cfg->led_compensation);
  454. led_cmd.off =
  455. il_blink_compensation(il, off,
  456. il->cfg->led_compensation);
  457. ret = il->ops->send_led_cmd(il, &led_cmd);
  458. if (!ret) {
  459. il->blink_on = on;
  460. il->blink_off = off;
  461. }
  462. return ret;
  463. }
  464. static void
  465. il_led_brightness_set(struct led_classdev *led_cdev,
  466. enum led_brightness brightness)
  467. {
  468. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  469. unsigned long on = 0;
  470. if (brightness > 0)
  471. on = IL_LED_SOLID;
  472. il_led_cmd(il, on, 0);
  473. }
  474. static int
  475. il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
  476. unsigned long *delay_off)
  477. {
  478. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  479. return il_led_cmd(il, *delay_on, *delay_off);
  480. }
  481. void
  482. il_leds_init(struct il_priv *il)
  483. {
  484. int mode = led_mode;
  485. int ret;
  486. if (mode == IL_LED_DEFAULT)
  487. mode = il->cfg->led_mode;
  488. il->led.name =
  489. kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
  490. il->led.brightness_set = il_led_brightness_set;
  491. il->led.blink_set = il_led_blink_set;
  492. il->led.max_brightness = 1;
  493. switch (mode) {
  494. case IL_LED_DEFAULT:
  495. WARN_ON(1);
  496. break;
  497. case IL_LED_BLINK:
  498. il->led.default_trigger =
  499. ieee80211_create_tpt_led_trigger(il->hw,
  500. IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
  501. il_blink,
  502. ARRAY_SIZE(il_blink));
  503. break;
  504. case IL_LED_RF_STATE:
  505. il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
  506. break;
  507. }
  508. ret = led_classdev_register(&il->pci_dev->dev, &il->led);
  509. if (ret) {
  510. kfree(il->led.name);
  511. return;
  512. }
  513. il->led_registered = true;
  514. }
  515. EXPORT_SYMBOL(il_leds_init);
  516. void
  517. il_leds_exit(struct il_priv *il)
  518. {
  519. if (!il->led_registered)
  520. return;
  521. led_classdev_unregister(&il->led);
  522. kfree(il->led.name);
  523. }
  524. EXPORT_SYMBOL(il_leds_exit);
  525. /************************** EEPROM BANDS ****************************
  526. *
  527. * The il_eeprom_band definitions below provide the mapping from the
  528. * EEPROM contents to the specific channel number supported for each
  529. * band.
  530. *
  531. * For example, il_priv->eeprom.band_3_channels[4] from the band_3
  532. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  533. * The specific geography and calibration information for that channel
  534. * is contained in the eeprom map itself.
  535. *
  536. * During init, we copy the eeprom information and channel map
  537. * information into il->channel_info_24/52 and il->channel_map_24/52
  538. *
  539. * channel_map_24/52 provides the idx in the channel_info array for a
  540. * given channel. We have to have two separate maps as there is channel
  541. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  542. * band_2
  543. *
  544. * A value of 0xff stored in the channel_map indicates that the channel
  545. * is not supported by the hardware at all.
  546. *
  547. * A value of 0xfe in the channel_map indicates that the channel is not
  548. * valid for Tx with the current hardware. This means that
  549. * while the system can tune and receive on a given channel, it may not
  550. * be able to associate or transmit any frames on that
  551. * channel. There is no corresponding channel information for that
  552. * entry.
  553. *
  554. *********************************************************************/
  555. /* 2.4 GHz */
  556. const u8 il_eeprom_band_1[14] = {
  557. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  558. };
  559. /* 5.2 GHz bands */
  560. static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
  561. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  562. };
  563. static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
  564. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  565. };
  566. static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
  567. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  568. };
  569. static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
  570. 145, 149, 153, 157, 161, 165
  571. };
  572. static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
  573. 1, 2, 3, 4, 5, 6, 7
  574. };
  575. static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
  576. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  577. };
  578. /******************************************************************************
  579. *
  580. * EEPROM related functions
  581. *
  582. ******************************************************************************/
  583. static int
  584. il_eeprom_verify_signature(struct il_priv *il)
  585. {
  586. u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
  587. int ret = 0;
  588. D_EEPROM("EEPROM signature=0x%08x\n", gp);
  589. switch (gp) {
  590. case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
  591. case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
  592. break;
  593. default:
  594. IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
  595. ret = -ENOENT;
  596. break;
  597. }
  598. return ret;
  599. }
  600. const u8 *
  601. il_eeprom_query_addr(const struct il_priv *il, size_t offset)
  602. {
  603. BUG_ON(offset >= il->cfg->eeprom_size);
  604. return &il->eeprom[offset];
  605. }
  606. EXPORT_SYMBOL(il_eeprom_query_addr);
  607. u16
  608. il_eeprom_query16(const struct il_priv *il, size_t offset)
  609. {
  610. if (!il->eeprom)
  611. return 0;
  612. return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
  613. }
  614. EXPORT_SYMBOL(il_eeprom_query16);
  615. /**
  616. * il_eeprom_init - read EEPROM contents
  617. *
  618. * Load the EEPROM contents from adapter into il->eeprom
  619. *
  620. * NOTE: This routine uses the non-debug IO access functions.
  621. */
  622. int
  623. il_eeprom_init(struct il_priv *il)
  624. {
  625. __le16 *e;
  626. u32 gp = _il_rd(il, CSR_EEPROM_GP);
  627. int sz;
  628. int ret;
  629. u16 addr;
  630. /* allocate eeprom */
  631. sz = il->cfg->eeprom_size;
  632. D_EEPROM("NVM size = %d\n", sz);
  633. il->eeprom = kzalloc(sz, GFP_KERNEL);
  634. if (!il->eeprom) {
  635. ret = -ENOMEM;
  636. goto alloc_err;
  637. }
  638. e = (__le16 *) il->eeprom;
  639. il->ops->apm_init(il);
  640. ret = il_eeprom_verify_signature(il);
  641. if (ret < 0) {
  642. IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  643. ret = -ENOENT;
  644. goto err;
  645. }
  646. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  647. ret = il->ops->eeprom_acquire_semaphore(il);
  648. if (ret < 0) {
  649. IL_ERR("Failed to acquire EEPROM semaphore.\n");
  650. ret = -ENOENT;
  651. goto err;
  652. }
  653. /* eeprom is an array of 16bit values */
  654. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  655. u32 r;
  656. _il_wr(il, CSR_EEPROM_REG,
  657. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  658. ret =
  659. _il_poll_bit(il, CSR_EEPROM_REG,
  660. CSR_EEPROM_REG_READ_VALID_MSK,
  661. CSR_EEPROM_REG_READ_VALID_MSK,
  662. IL_EEPROM_ACCESS_TIMEOUT);
  663. if (ret < 0) {
  664. IL_ERR("Time out reading EEPROM[%d]\n", addr);
  665. goto done;
  666. }
  667. r = _il_rd(il, CSR_EEPROM_REG);
  668. e[addr / 2] = cpu_to_le16(r >> 16);
  669. }
  670. D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
  671. il_eeprom_query16(il, EEPROM_VERSION));
  672. ret = 0;
  673. done:
  674. il->ops->eeprom_release_semaphore(il);
  675. err:
  676. if (ret)
  677. il_eeprom_free(il);
  678. /* Reset chip to save power until we load uCode during "up". */
  679. il_apm_stop(il);
  680. alloc_err:
  681. return ret;
  682. }
  683. EXPORT_SYMBOL(il_eeprom_init);
  684. void
  685. il_eeprom_free(struct il_priv *il)
  686. {
  687. kfree(il->eeprom);
  688. il->eeprom = NULL;
  689. }
  690. EXPORT_SYMBOL(il_eeprom_free);
  691. static void
  692. il_init_band_reference(const struct il_priv *il, int eep_band,
  693. int *eeprom_ch_count,
  694. const struct il_eeprom_channel **eeprom_ch_info,
  695. const u8 **eeprom_ch_idx)
  696. {
  697. u32 offset = il->cfg->regulatory_bands[eep_band - 1];
  698. switch (eep_band) {
  699. case 1: /* 2.4GHz band */
  700. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
  701. *eeprom_ch_info =
  702. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  703. offset);
  704. *eeprom_ch_idx = il_eeprom_band_1;
  705. break;
  706. case 2: /* 4.9GHz band */
  707. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
  708. *eeprom_ch_info =
  709. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  710. offset);
  711. *eeprom_ch_idx = il_eeprom_band_2;
  712. break;
  713. case 3: /* 5.2GHz band */
  714. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
  715. *eeprom_ch_info =
  716. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  717. offset);
  718. *eeprom_ch_idx = il_eeprom_band_3;
  719. break;
  720. case 4: /* 5.5GHz band */
  721. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
  722. *eeprom_ch_info =
  723. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  724. offset);
  725. *eeprom_ch_idx = il_eeprom_band_4;
  726. break;
  727. case 5: /* 5.7GHz band */
  728. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
  729. *eeprom_ch_info =
  730. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  731. offset);
  732. *eeprom_ch_idx = il_eeprom_band_5;
  733. break;
  734. case 6: /* 2.4GHz ht40 channels */
  735. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
  736. *eeprom_ch_info =
  737. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  738. offset);
  739. *eeprom_ch_idx = il_eeprom_band_6;
  740. break;
  741. case 7: /* 5 GHz ht40 channels */
  742. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
  743. *eeprom_ch_info =
  744. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  745. offset);
  746. *eeprom_ch_idx = il_eeprom_band_7;
  747. break;
  748. default:
  749. BUG();
  750. }
  751. }
  752. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  753. ? # x " " : "")
  754. /**
  755. * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
  756. *
  757. * Does not set up a command, or touch hardware.
  758. */
  759. static int
  760. il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
  761. const struct il_eeprom_channel *eeprom_ch,
  762. u8 clear_ht40_extension_channel)
  763. {
  764. struct il_channel_info *ch_info;
  765. ch_info =
  766. (struct il_channel_info *)il_get_channel_info(il, band, channel);
  767. if (!il_is_channel_valid(ch_info))
  768. return -1;
  769. D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
  770. " Ad-Hoc %ssupported\n", ch_info->channel,
  771. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  772. CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
  773. CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
  774. CHECK_AND_PRINT(DFS), eeprom_ch->flags,
  775. eeprom_ch->max_power_avg,
  776. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
  777. !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
  778. ch_info->ht40_eeprom = *eeprom_ch;
  779. ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
  780. ch_info->ht40_flags = eeprom_ch->flags;
  781. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  782. ch_info->ht40_extension_channel &=
  783. ~clear_ht40_extension_channel;
  784. return 0;
  785. }
  786. #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  787. ? # x " " : "")
  788. /**
  789. * il_init_channel_map - Set up driver's info for all possible channels
  790. */
  791. int
  792. il_init_channel_map(struct il_priv *il)
  793. {
  794. int eeprom_ch_count = 0;
  795. const u8 *eeprom_ch_idx = NULL;
  796. const struct il_eeprom_channel *eeprom_ch_info = NULL;
  797. int band, ch;
  798. struct il_channel_info *ch_info;
  799. if (il->channel_count) {
  800. D_EEPROM("Channel map already initialized.\n");
  801. return 0;
  802. }
  803. D_EEPROM("Initializing regulatory info from EEPROM\n");
  804. il->channel_count =
  805. ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
  806. ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
  807. ARRAY_SIZE(il_eeprom_band_5);
  808. D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
  809. il->channel_info =
  810. kzalloc(sizeof(struct il_channel_info) * il->channel_count,
  811. GFP_KERNEL);
  812. if (!il->channel_info) {
  813. IL_ERR("Could not allocate channel_info\n");
  814. il->channel_count = 0;
  815. return -ENOMEM;
  816. }
  817. ch_info = il->channel_info;
  818. /* Loop through the 5 EEPROM bands adding them in order to the
  819. * channel map we maintain (that contains additional information than
  820. * what just in the EEPROM) */
  821. for (band = 1; band <= 5; band++) {
  822. il_init_band_reference(il, band, &eeprom_ch_count,
  823. &eeprom_ch_info, &eeprom_ch_idx);
  824. /* Loop through each band adding each of the channels */
  825. for (ch = 0; ch < eeprom_ch_count; ch++) {
  826. ch_info->channel = eeprom_ch_idx[ch];
  827. ch_info->band =
  828. (band ==
  829. 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  830. /* permanently store EEPROM's channel regulatory flags
  831. * and max power in channel info database. */
  832. ch_info->eeprom = eeprom_ch_info[ch];
  833. /* Copy the run-time flags so they are there even on
  834. * invalid channels */
  835. ch_info->flags = eeprom_ch_info[ch].flags;
  836. /* First write that ht40 is not enabled, and then enable
  837. * one by one */
  838. ch_info->ht40_extension_channel =
  839. IEEE80211_CHAN_NO_HT40;
  840. if (!(il_is_channel_valid(ch_info))) {
  841. D_EEPROM("Ch. %d Flags %x [%sGHz] - "
  842. "No traffic\n", ch_info->channel,
  843. ch_info->flags,
  844. il_is_channel_a_band(ch_info) ? "5.2" :
  845. "2.4");
  846. ch_info++;
  847. continue;
  848. }
  849. /* Initialize regulatory-based run-time data */
  850. ch_info->max_power_avg = ch_info->curr_txpow =
  851. eeprom_ch_info[ch].max_power_avg;
  852. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  853. ch_info->min_power = 0;
  854. D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
  855. " Ad-Hoc %ssupported\n", ch_info->channel,
  856. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  857. CHECK_AND_PRINT_I(VALID),
  858. CHECK_AND_PRINT_I(IBSS),
  859. CHECK_AND_PRINT_I(ACTIVE),
  860. CHECK_AND_PRINT_I(RADAR),
  861. CHECK_AND_PRINT_I(WIDE),
  862. CHECK_AND_PRINT_I(DFS),
  863. eeprom_ch_info[ch].flags,
  864. eeprom_ch_info[ch].max_power_avg,
  865. ((eeprom_ch_info[ch].
  866. flags & EEPROM_CHANNEL_IBSS) &&
  867. !(eeprom_ch_info[ch].
  868. flags & EEPROM_CHANNEL_RADAR)) ? "" :
  869. "not ");
  870. ch_info++;
  871. }
  872. }
  873. /* Check if we do have HT40 channels */
  874. if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
  875. il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
  876. return 0;
  877. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  878. for (band = 6; band <= 7; band++) {
  879. enum ieee80211_band ieeeband;
  880. il_init_band_reference(il, band, &eeprom_ch_count,
  881. &eeprom_ch_info, &eeprom_ch_idx);
  882. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  883. ieeeband =
  884. (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  885. /* Loop through each band adding each of the channels */
  886. for (ch = 0; ch < eeprom_ch_count; ch++) {
  887. /* Set up driver's info for lower half */
  888. il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
  889. &eeprom_ch_info[ch],
  890. IEEE80211_CHAN_NO_HT40PLUS);
  891. /* Set up driver's info for upper half */
  892. il_mod_ht40_chan_info(il, ieeeband,
  893. eeprom_ch_idx[ch] + 4,
  894. &eeprom_ch_info[ch],
  895. IEEE80211_CHAN_NO_HT40MINUS);
  896. }
  897. }
  898. return 0;
  899. }
  900. EXPORT_SYMBOL(il_init_channel_map);
  901. /*
  902. * il_free_channel_map - undo allocations in il_init_channel_map
  903. */
  904. void
  905. il_free_channel_map(struct il_priv *il)
  906. {
  907. kfree(il->channel_info);
  908. il->channel_count = 0;
  909. }
  910. EXPORT_SYMBOL(il_free_channel_map);
  911. /**
  912. * il_get_channel_info - Find driver's ilate channel info
  913. *
  914. * Based on band and channel number.
  915. */
  916. const struct il_channel_info *
  917. il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
  918. u16 channel)
  919. {
  920. int i;
  921. switch (band) {
  922. case IEEE80211_BAND_5GHZ:
  923. for (i = 14; i < il->channel_count; i++) {
  924. if (il->channel_info[i].channel == channel)
  925. return &il->channel_info[i];
  926. }
  927. break;
  928. case IEEE80211_BAND_2GHZ:
  929. if (channel >= 1 && channel <= 14)
  930. return &il->channel_info[channel - 1];
  931. break;
  932. default:
  933. BUG();
  934. }
  935. return NULL;
  936. }
  937. EXPORT_SYMBOL(il_get_channel_info);
  938. /*
  939. * Setting power level allows the card to go to sleep when not busy.
  940. *
  941. * We calculate a sleep command based on the required latency, which
  942. * we get from mac80211. In order to handle thermal throttling, we can
  943. * also use pre-defined power levels.
  944. */
  945. /*
  946. * This defines the old power levels. They are still used by default
  947. * (level 1) and for thermal throttle (levels 3 through 5)
  948. */
  949. struct il_power_vec_entry {
  950. struct il_powertable_cmd cmd;
  951. u8 no_dtim; /* number of skip dtim */
  952. };
  953. static void
  954. il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
  955. {
  956. memset(cmd, 0, sizeof(*cmd));
  957. if (il->power_data.pci_pm)
  958. cmd->flags |= IL_POWER_PCI_PM_MSK;
  959. D_POWER("Sleep command for CAM\n");
  960. }
  961. static int
  962. il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
  963. {
  964. D_POWER("Sending power/sleep command\n");
  965. D_POWER("Flags value = 0x%08X\n", cmd->flags);
  966. D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  967. D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  968. D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  969. le32_to_cpu(cmd->sleep_interval[0]),
  970. le32_to_cpu(cmd->sleep_interval[1]),
  971. le32_to_cpu(cmd->sleep_interval[2]),
  972. le32_to_cpu(cmd->sleep_interval[3]),
  973. le32_to_cpu(cmd->sleep_interval[4]));
  974. return il_send_cmd_pdu(il, C_POWER_TBL,
  975. sizeof(struct il_powertable_cmd), cmd);
  976. }
  977. int
  978. il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
  979. {
  980. int ret;
  981. bool update_chains;
  982. lockdep_assert_held(&il->mutex);
  983. /* Don't update the RX chain when chain noise calibration is running */
  984. update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
  985. il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
  986. if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  987. return 0;
  988. if (!il_is_ready_rf(il))
  989. return -EIO;
  990. /* scan complete use sleep_power_next, need to be updated */
  991. memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  992. if (test_bit(S_SCANNING, &il->status) && !force) {
  993. D_INFO("Defer power set mode while scanning\n");
  994. return 0;
  995. }
  996. if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  997. set_bit(S_POWER_PMI, &il->status);
  998. ret = il_set_power(il, cmd);
  999. if (!ret) {
  1000. if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  1001. clear_bit(S_POWER_PMI, &il->status);
  1002. if (il->ops->update_chain_flags && update_chains)
  1003. il->ops->update_chain_flags(il);
  1004. else if (il->ops->update_chain_flags)
  1005. D_POWER("Cannot update the power, chain noise "
  1006. "calibration running: %d\n",
  1007. il->chain_noise_data.state);
  1008. memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
  1009. } else
  1010. IL_ERR("set power fail, ret = %d", ret);
  1011. return ret;
  1012. }
  1013. int
  1014. il_power_update_mode(struct il_priv *il, bool force)
  1015. {
  1016. struct il_powertable_cmd cmd;
  1017. il_power_sleep_cam_cmd(il, &cmd);
  1018. return il_power_set_mode(il, &cmd, force);
  1019. }
  1020. EXPORT_SYMBOL(il_power_update_mode);
  1021. /* initialize to default */
  1022. void
  1023. il_power_initialize(struct il_priv *il)
  1024. {
  1025. u16 lctl;
  1026. pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  1027. il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
  1028. il->power_data.debug_sleep_level_override = -1;
  1029. memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
  1030. }
  1031. EXPORT_SYMBOL(il_power_initialize);
  1032. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  1033. * sending probe req. This should be set long enough to hear probe responses
  1034. * from more than one AP. */
  1035. #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  1036. #define IL_ACTIVE_DWELL_TIME_52 (20)
  1037. #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  1038. #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  1039. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  1040. * Must be set longer than active dwell time.
  1041. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  1042. #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  1043. #define IL_PASSIVE_DWELL_TIME_52 (10)
  1044. #define IL_PASSIVE_DWELL_BASE (100)
  1045. #define IL_CHANNEL_TUNE_TIME 5
  1046. static int
  1047. il_send_scan_abort(struct il_priv *il)
  1048. {
  1049. int ret;
  1050. struct il_rx_pkt *pkt;
  1051. struct il_host_cmd cmd = {
  1052. .id = C_SCAN_ABORT,
  1053. .flags = CMD_WANT_SKB,
  1054. };
  1055. /* Exit instantly with error when device is not ready
  1056. * to receive scan abort command or it does not perform
  1057. * hardware scan currently */
  1058. if (!test_bit(S_READY, &il->status) ||
  1059. !test_bit(S_GEO_CONFIGURED, &il->status) ||
  1060. !test_bit(S_SCAN_HW, &il->status) ||
  1061. test_bit(S_FW_ERROR, &il->status) ||
  1062. test_bit(S_EXIT_PENDING, &il->status))
  1063. return -EIO;
  1064. ret = il_send_cmd_sync(il, &cmd);
  1065. if (ret)
  1066. return ret;
  1067. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1068. if (pkt->u.status != CAN_ABORT_STATUS) {
  1069. /* The scan abort will return 1 for success or
  1070. * 2 for "failure". A failure condition can be
  1071. * due to simply not being in an active scan which
  1072. * can occur if we send the scan abort before we
  1073. * the microcode has notified us that a scan is
  1074. * completed. */
  1075. D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
  1076. ret = -EIO;
  1077. }
  1078. il_free_pages(il, cmd.reply_page);
  1079. return ret;
  1080. }
  1081. static void
  1082. il_complete_scan(struct il_priv *il, bool aborted)
  1083. {
  1084. /* check if scan was requested from mac80211 */
  1085. if (il->scan_request) {
  1086. D_SCAN("Complete scan in mac80211\n");
  1087. ieee80211_scan_completed(il->hw, aborted);
  1088. }
  1089. il->scan_vif = NULL;
  1090. il->scan_request = NULL;
  1091. }
  1092. void
  1093. il_force_scan_end(struct il_priv *il)
  1094. {
  1095. lockdep_assert_held(&il->mutex);
  1096. if (!test_bit(S_SCANNING, &il->status)) {
  1097. D_SCAN("Forcing scan end while not scanning\n");
  1098. return;
  1099. }
  1100. D_SCAN("Forcing scan end\n");
  1101. clear_bit(S_SCANNING, &il->status);
  1102. clear_bit(S_SCAN_HW, &il->status);
  1103. clear_bit(S_SCAN_ABORTING, &il->status);
  1104. il_complete_scan(il, true);
  1105. }
  1106. static void
  1107. il_do_scan_abort(struct il_priv *il)
  1108. {
  1109. int ret;
  1110. lockdep_assert_held(&il->mutex);
  1111. if (!test_bit(S_SCANNING, &il->status)) {
  1112. D_SCAN("Not performing scan to abort\n");
  1113. return;
  1114. }
  1115. if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
  1116. D_SCAN("Scan abort in progress\n");
  1117. return;
  1118. }
  1119. ret = il_send_scan_abort(il);
  1120. if (ret) {
  1121. D_SCAN("Send scan abort failed %d\n", ret);
  1122. il_force_scan_end(il);
  1123. } else
  1124. D_SCAN("Successfully send scan abort\n");
  1125. }
  1126. /**
  1127. * il_scan_cancel - Cancel any currently executing HW scan
  1128. */
  1129. int
  1130. il_scan_cancel(struct il_priv *il)
  1131. {
  1132. D_SCAN("Queuing abort scan\n");
  1133. queue_work(il->workqueue, &il->abort_scan);
  1134. return 0;
  1135. }
  1136. EXPORT_SYMBOL(il_scan_cancel);
  1137. /**
  1138. * il_scan_cancel_timeout - Cancel any currently executing HW scan
  1139. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1140. *
  1141. */
  1142. int
  1143. il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
  1144. {
  1145. unsigned long timeout = jiffies + msecs_to_jiffies(ms);
  1146. lockdep_assert_held(&il->mutex);
  1147. D_SCAN("Scan cancel timeout\n");
  1148. il_do_scan_abort(il);
  1149. while (time_before_eq(jiffies, timeout)) {
  1150. if (!test_bit(S_SCAN_HW, &il->status))
  1151. break;
  1152. msleep(20);
  1153. }
  1154. return test_bit(S_SCAN_HW, &il->status);
  1155. }
  1156. EXPORT_SYMBOL(il_scan_cancel_timeout);
  1157. /* Service response to C_SCAN (0x80) */
  1158. static void
  1159. il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
  1160. {
  1161. #ifdef CONFIG_IWLEGACY_DEBUG
  1162. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1163. struct il_scanreq_notification *notif =
  1164. (struct il_scanreq_notification *)pkt->u.raw;
  1165. D_SCAN("Scan request status = 0x%x\n", notif->status);
  1166. #endif
  1167. }
  1168. /* Service N_SCAN_START (0x82) */
  1169. static void
  1170. il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
  1171. {
  1172. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1173. struct il_scanstart_notification *notif =
  1174. (struct il_scanstart_notification *)pkt->u.raw;
  1175. il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  1176. D_SCAN("Scan start: " "%d [802.11%s] "
  1177. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
  1178. notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
  1179. le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
  1180. }
  1181. /* Service N_SCAN_RESULTS (0x83) */
  1182. static void
  1183. il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
  1184. {
  1185. #ifdef CONFIG_IWLEGACY_DEBUG
  1186. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1187. struct il_scanresults_notification *notif =
  1188. (struct il_scanresults_notification *)pkt->u.raw;
  1189. D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
  1190. "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
  1191. le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
  1192. le32_to_cpu(notif->stats[0]),
  1193. le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
  1194. #endif
  1195. }
  1196. /* Service N_SCAN_COMPLETE (0x84) */
  1197. static void
  1198. il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
  1199. {
  1200. #ifdef CONFIG_IWLEGACY_DEBUG
  1201. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1202. struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  1203. #endif
  1204. D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  1205. scan_notif->scanned_channels, scan_notif->tsf_low,
  1206. scan_notif->tsf_high, scan_notif->status);
  1207. /* The HW is no longer scanning */
  1208. clear_bit(S_SCAN_HW, &il->status);
  1209. D_SCAN("Scan on %sGHz took %dms\n",
  1210. (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
  1211. jiffies_to_msecs(jiffies - il->scan_start));
  1212. queue_work(il->workqueue, &il->scan_completed);
  1213. }
  1214. void
  1215. il_setup_rx_scan_handlers(struct il_priv *il)
  1216. {
  1217. /* scan handlers */
  1218. il->handlers[C_SCAN] = il_hdl_scan;
  1219. il->handlers[N_SCAN_START] = il_hdl_scan_start;
  1220. il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
  1221. il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
  1222. }
  1223. EXPORT_SYMBOL(il_setup_rx_scan_handlers);
  1224. inline u16
  1225. il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
  1226. u8 n_probes)
  1227. {
  1228. if (band == IEEE80211_BAND_5GHZ)
  1229. return IL_ACTIVE_DWELL_TIME_52 +
  1230. IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  1231. else
  1232. return IL_ACTIVE_DWELL_TIME_24 +
  1233. IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  1234. }
  1235. EXPORT_SYMBOL(il_get_active_dwell_time);
  1236. u16
  1237. il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
  1238. struct ieee80211_vif *vif)
  1239. {
  1240. u16 value;
  1241. u16 passive =
  1242. (band ==
  1243. IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
  1244. IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
  1245. IL_PASSIVE_DWELL_TIME_52;
  1246. if (il_is_any_associated(il)) {
  1247. /*
  1248. * If we're associated, we clamp the maximum passive
  1249. * dwell time to be 98% of the smallest beacon interval
  1250. * (minus 2 * channel tune time)
  1251. */
  1252. value = il->vif ? il->vif->bss_conf.beacon_int : 0;
  1253. if (value > IL_PASSIVE_DWELL_BASE || !value)
  1254. value = IL_PASSIVE_DWELL_BASE;
  1255. value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
  1256. passive = min(value, passive);
  1257. }
  1258. return passive;
  1259. }
  1260. EXPORT_SYMBOL(il_get_passive_dwell_time);
  1261. void
  1262. il_init_scan_params(struct il_priv *il)
  1263. {
  1264. u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
  1265. if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
  1266. il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
  1267. if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
  1268. il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
  1269. }
  1270. EXPORT_SYMBOL(il_init_scan_params);
  1271. static int
  1272. il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
  1273. {
  1274. int ret;
  1275. lockdep_assert_held(&il->mutex);
  1276. cancel_delayed_work(&il->scan_check);
  1277. if (!il_is_ready_rf(il)) {
  1278. IL_WARN("Request scan called when driver not ready.\n");
  1279. return -EIO;
  1280. }
  1281. if (test_bit(S_SCAN_HW, &il->status)) {
  1282. D_SCAN("Multiple concurrent scan requests in parallel.\n");
  1283. return -EBUSY;
  1284. }
  1285. if (test_bit(S_SCAN_ABORTING, &il->status)) {
  1286. D_SCAN("Scan request while abort pending.\n");
  1287. return -EBUSY;
  1288. }
  1289. D_SCAN("Starting scan...\n");
  1290. set_bit(S_SCANNING, &il->status);
  1291. il->scan_start = jiffies;
  1292. ret = il->ops->request_scan(il, vif);
  1293. if (ret) {
  1294. clear_bit(S_SCANNING, &il->status);
  1295. return ret;
  1296. }
  1297. queue_delayed_work(il->workqueue, &il->scan_check,
  1298. IL_SCAN_CHECK_WATCHDOG);
  1299. return 0;
  1300. }
  1301. int
  1302. il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1303. struct cfg80211_scan_request *req)
  1304. {
  1305. struct il_priv *il = hw->priv;
  1306. int ret;
  1307. if (req->n_channels == 0) {
  1308. IL_ERR("Can not scan on no channels.\n");
  1309. return -EINVAL;
  1310. }
  1311. mutex_lock(&il->mutex);
  1312. D_MAC80211("enter\n");
  1313. if (test_bit(S_SCANNING, &il->status)) {
  1314. D_SCAN("Scan already in progress.\n");
  1315. ret = -EAGAIN;
  1316. goto out_unlock;
  1317. }
  1318. /* mac80211 will only ask for one band at a time */
  1319. il->scan_request = req;
  1320. il->scan_vif = vif;
  1321. il->scan_band = req->channels[0]->band;
  1322. ret = il_scan_initiate(il, vif);
  1323. out_unlock:
  1324. D_MAC80211("leave ret %d\n", ret);
  1325. mutex_unlock(&il->mutex);
  1326. return ret;
  1327. }
  1328. EXPORT_SYMBOL(il_mac_hw_scan);
  1329. static void
  1330. il_bg_scan_check(struct work_struct *data)
  1331. {
  1332. struct il_priv *il =
  1333. container_of(data, struct il_priv, scan_check.work);
  1334. D_SCAN("Scan check work\n");
  1335. /* Since we are here firmware does not finish scan and
  1336. * most likely is in bad shape, so we don't bother to
  1337. * send abort command, just force scan complete to mac80211 */
  1338. mutex_lock(&il->mutex);
  1339. il_force_scan_end(il);
  1340. mutex_unlock(&il->mutex);
  1341. }
  1342. /**
  1343. * il_fill_probe_req - fill in all required fields and IE for probe request
  1344. */
  1345. u16
  1346. il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
  1347. const u8 *ta, const u8 *ies, int ie_len, int left)
  1348. {
  1349. int len = 0;
  1350. u8 *pos = NULL;
  1351. /* Make sure there is enough space for the probe request,
  1352. * two mandatory IEs and the data */
  1353. left -= 24;
  1354. if (left < 0)
  1355. return 0;
  1356. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1357. eth_broadcast_addr(frame->da);
  1358. memcpy(frame->sa, ta, ETH_ALEN);
  1359. eth_broadcast_addr(frame->bssid);
  1360. frame->seq_ctrl = 0;
  1361. len += 24;
  1362. /* ...next IE... */
  1363. pos = &frame->u.probe_req.variable[0];
  1364. /* fill in our indirect SSID IE */
  1365. left -= 2;
  1366. if (left < 0)
  1367. return 0;
  1368. *pos++ = WLAN_EID_SSID;
  1369. *pos++ = 0;
  1370. len += 2;
  1371. if (WARN_ON(left < ie_len))
  1372. return len;
  1373. if (ies && ie_len) {
  1374. memcpy(pos, ies, ie_len);
  1375. len += ie_len;
  1376. }
  1377. return (u16) len;
  1378. }
  1379. EXPORT_SYMBOL(il_fill_probe_req);
  1380. static void
  1381. il_bg_abort_scan(struct work_struct *work)
  1382. {
  1383. struct il_priv *il = container_of(work, struct il_priv, abort_scan);
  1384. D_SCAN("Abort scan work\n");
  1385. /* We keep scan_check work queued in case when firmware will not
  1386. * report back scan completed notification */
  1387. mutex_lock(&il->mutex);
  1388. il_scan_cancel_timeout(il, 200);
  1389. mutex_unlock(&il->mutex);
  1390. }
  1391. static void
  1392. il_bg_scan_completed(struct work_struct *work)
  1393. {
  1394. struct il_priv *il = container_of(work, struct il_priv, scan_completed);
  1395. bool aborted;
  1396. D_SCAN("Completed scan.\n");
  1397. cancel_delayed_work(&il->scan_check);
  1398. mutex_lock(&il->mutex);
  1399. aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
  1400. if (aborted)
  1401. D_SCAN("Aborted scan completed.\n");
  1402. if (!test_and_clear_bit(S_SCANNING, &il->status)) {
  1403. D_SCAN("Scan already completed.\n");
  1404. goto out_settings;
  1405. }
  1406. il_complete_scan(il, aborted);
  1407. out_settings:
  1408. /* Can we still talk to firmware ? */
  1409. if (!il_is_ready_rf(il))
  1410. goto out;
  1411. /*
  1412. * We do not commit power settings while scan is pending,
  1413. * do it now if the settings changed.
  1414. */
  1415. il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
  1416. il_set_tx_power(il, il->tx_power_next, false);
  1417. il->ops->post_scan(il);
  1418. out:
  1419. mutex_unlock(&il->mutex);
  1420. }
  1421. void
  1422. il_setup_scan_deferred_work(struct il_priv *il)
  1423. {
  1424. INIT_WORK(&il->scan_completed, il_bg_scan_completed);
  1425. INIT_WORK(&il->abort_scan, il_bg_abort_scan);
  1426. INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
  1427. }
  1428. EXPORT_SYMBOL(il_setup_scan_deferred_work);
  1429. void
  1430. il_cancel_scan_deferred_work(struct il_priv *il)
  1431. {
  1432. cancel_work_sync(&il->abort_scan);
  1433. cancel_work_sync(&il->scan_completed);
  1434. if (cancel_delayed_work_sync(&il->scan_check)) {
  1435. mutex_lock(&il->mutex);
  1436. il_force_scan_end(il);
  1437. mutex_unlock(&il->mutex);
  1438. }
  1439. }
  1440. EXPORT_SYMBOL(il_cancel_scan_deferred_work);
  1441. /* il->sta_lock must be held */
  1442. static void
  1443. il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
  1444. {
  1445. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
  1446. IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
  1447. sta_id, il->stations[sta_id].sta.sta.addr);
  1448. if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
  1449. D_ASSOC("STA id %u addr %pM already present"
  1450. " in uCode (according to driver)\n", sta_id,
  1451. il->stations[sta_id].sta.sta.addr);
  1452. } else {
  1453. il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
  1454. D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
  1455. il->stations[sta_id].sta.sta.addr);
  1456. }
  1457. }
  1458. static int
  1459. il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
  1460. struct il_rx_pkt *pkt, bool sync)
  1461. {
  1462. u8 sta_id = addsta->sta.sta_id;
  1463. unsigned long flags;
  1464. int ret = -EIO;
  1465. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1466. IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
  1467. return ret;
  1468. }
  1469. D_INFO("Processing response for adding station %u\n", sta_id);
  1470. spin_lock_irqsave(&il->sta_lock, flags);
  1471. switch (pkt->u.add_sta.status) {
  1472. case ADD_STA_SUCCESS_MSK:
  1473. D_INFO("C_ADD_STA PASSED\n");
  1474. il_sta_ucode_activate(il, sta_id);
  1475. ret = 0;
  1476. break;
  1477. case ADD_STA_NO_ROOM_IN_TBL:
  1478. IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
  1479. break;
  1480. case ADD_STA_NO_BLOCK_ACK_RESOURCE:
  1481. IL_ERR("Adding station %d failed, no block ack resource.\n",
  1482. sta_id);
  1483. break;
  1484. case ADD_STA_MODIFY_NON_EXIST_STA:
  1485. IL_ERR("Attempting to modify non-existing station %d\n",
  1486. sta_id);
  1487. break;
  1488. default:
  1489. D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
  1490. break;
  1491. }
  1492. D_INFO("%s station id %u addr %pM\n",
  1493. il->stations[sta_id].sta.mode ==
  1494. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
  1495. il->stations[sta_id].sta.sta.addr);
  1496. /*
  1497. * XXX: The MAC address in the command buffer is often changed from
  1498. * the original sent to the device. That is, the MAC address
  1499. * written to the command buffer often is not the same MAC address
  1500. * read from the command buffer when the command returns. This
  1501. * issue has not yet been resolved and this debugging is left to
  1502. * observe the problem.
  1503. */
  1504. D_INFO("%s station according to cmd buffer %pM\n",
  1505. il->stations[sta_id].sta.mode ==
  1506. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
  1507. spin_unlock_irqrestore(&il->sta_lock, flags);
  1508. return ret;
  1509. }
  1510. static void
  1511. il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
  1512. struct il_rx_pkt *pkt)
  1513. {
  1514. struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
  1515. il_process_add_sta_resp(il, addsta, pkt, false);
  1516. }
  1517. int
  1518. il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
  1519. {
  1520. struct il_rx_pkt *pkt = NULL;
  1521. int ret = 0;
  1522. u8 data[sizeof(*sta)];
  1523. struct il_host_cmd cmd = {
  1524. .id = C_ADD_STA,
  1525. .flags = flags,
  1526. .data = data,
  1527. };
  1528. u8 sta_id __maybe_unused = sta->sta.sta_id;
  1529. D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
  1530. flags & CMD_ASYNC ? "a" : "");
  1531. if (flags & CMD_ASYNC)
  1532. cmd.callback = il_add_sta_callback;
  1533. else {
  1534. cmd.flags |= CMD_WANT_SKB;
  1535. might_sleep();
  1536. }
  1537. cmd.len = il->ops->build_addsta_hcmd(sta, data);
  1538. ret = il_send_cmd(il, &cmd);
  1539. if (ret || (flags & CMD_ASYNC))
  1540. return ret;
  1541. if (ret == 0) {
  1542. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1543. ret = il_process_add_sta_resp(il, sta, pkt, true);
  1544. }
  1545. il_free_pages(il, cmd.reply_page);
  1546. return ret;
  1547. }
  1548. EXPORT_SYMBOL(il_send_add_sta);
  1549. static void
  1550. il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
  1551. {
  1552. struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
  1553. __le32 sta_flags;
  1554. if (!sta || !sta_ht_inf->ht_supported)
  1555. goto done;
  1556. D_ASSOC("spatial multiplexing power save mode: %s\n",
  1557. (sta->smps_mode == IEEE80211_SMPS_STATIC) ? "static" :
  1558. (sta->smps_mode == IEEE80211_SMPS_DYNAMIC) ? "dynamic" :
  1559. "disabled");
  1560. sta_flags = il->stations[idx].sta.station_flags;
  1561. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  1562. switch (sta->smps_mode) {
  1563. case IEEE80211_SMPS_STATIC:
  1564. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  1565. break;
  1566. case IEEE80211_SMPS_DYNAMIC:
  1567. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  1568. break;
  1569. case IEEE80211_SMPS_OFF:
  1570. break;
  1571. default:
  1572. IL_WARN("Invalid MIMO PS mode %d\n", sta->smps_mode);
  1573. break;
  1574. }
  1575. sta_flags |=
  1576. cpu_to_le32((u32) sta_ht_inf->
  1577. ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  1578. sta_flags |=
  1579. cpu_to_le32((u32) sta_ht_inf->
  1580. ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  1581. if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
  1582. sta_flags |= STA_FLG_HT40_EN_MSK;
  1583. else
  1584. sta_flags &= ~STA_FLG_HT40_EN_MSK;
  1585. il->stations[idx].sta.station_flags = sta_flags;
  1586. done:
  1587. return;
  1588. }
  1589. /**
  1590. * il_prep_station - Prepare station information for addition
  1591. *
  1592. * should be called with sta_lock held
  1593. */
  1594. u8
  1595. il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
  1596. struct ieee80211_sta *sta)
  1597. {
  1598. struct il_station_entry *station;
  1599. int i;
  1600. u8 sta_id = IL_INVALID_STATION;
  1601. u16 rate;
  1602. if (is_ap)
  1603. sta_id = IL_AP_ID;
  1604. else if (is_broadcast_ether_addr(addr))
  1605. sta_id = il->hw_params.bcast_id;
  1606. else
  1607. for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
  1608. if (ether_addr_equal(il->stations[i].sta.sta.addr,
  1609. addr)) {
  1610. sta_id = i;
  1611. break;
  1612. }
  1613. if (!il->stations[i].used &&
  1614. sta_id == IL_INVALID_STATION)
  1615. sta_id = i;
  1616. }
  1617. /*
  1618. * These two conditions have the same outcome, but keep them
  1619. * separate
  1620. */
  1621. if (unlikely(sta_id == IL_INVALID_STATION))
  1622. return sta_id;
  1623. /*
  1624. * uCode is not able to deal with multiple requests to add a
  1625. * station. Keep track if one is in progress so that we do not send
  1626. * another.
  1627. */
  1628. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1629. D_INFO("STA %d already in process of being added.\n", sta_id);
  1630. return sta_id;
  1631. }
  1632. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1633. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
  1634. ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
  1635. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1636. sta_id, addr);
  1637. return sta_id;
  1638. }
  1639. station = &il->stations[sta_id];
  1640. station->used = IL_STA_DRIVER_ACTIVE;
  1641. D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
  1642. il->num_stations++;
  1643. /* Set up the C_ADD_STA command to send to device */
  1644. memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
  1645. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  1646. station->sta.mode = 0;
  1647. station->sta.sta.sta_id = sta_id;
  1648. station->sta.station_flags = 0;
  1649. /*
  1650. * OK to call unconditionally, since local stations (IBSS BSSID
  1651. * STA and broadcast STA) pass in a NULL sta, and mac80211
  1652. * doesn't allow HT IBSS.
  1653. */
  1654. il_set_ht_add_station(il, sta_id, sta);
  1655. /* 3945 only */
  1656. rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
  1657. /* Turn on both antennas for the station... */
  1658. station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
  1659. return sta_id;
  1660. }
  1661. EXPORT_SYMBOL_GPL(il_prep_station);
  1662. #define STA_WAIT_TIMEOUT (HZ/2)
  1663. /**
  1664. * il_add_station_common -
  1665. */
  1666. int
  1667. il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
  1668. struct ieee80211_sta *sta, u8 *sta_id_r)
  1669. {
  1670. unsigned long flags_spin;
  1671. int ret = 0;
  1672. u8 sta_id;
  1673. struct il_addsta_cmd sta_cmd;
  1674. *sta_id_r = 0;
  1675. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1676. sta_id = il_prep_station(il, addr, is_ap, sta);
  1677. if (sta_id == IL_INVALID_STATION) {
  1678. IL_ERR("Unable to prepare station %pM for addition\n", addr);
  1679. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1680. return -EINVAL;
  1681. }
  1682. /*
  1683. * uCode is not able to deal with multiple requests to add a
  1684. * station. Keep track if one is in progress so that we do not send
  1685. * another.
  1686. */
  1687. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1688. D_INFO("STA %d already in process of being added.\n", sta_id);
  1689. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1690. return -EEXIST;
  1691. }
  1692. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1693. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1694. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1695. sta_id, addr);
  1696. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1697. return -EEXIST;
  1698. }
  1699. il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
  1700. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  1701. sizeof(struct il_addsta_cmd));
  1702. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1703. /* Add station to device's station table */
  1704. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1705. if (ret) {
  1706. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1707. IL_ERR("Adding station %pM failed.\n",
  1708. il->stations[sta_id].sta.sta.addr);
  1709. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1710. il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1711. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1712. }
  1713. *sta_id_r = sta_id;
  1714. return ret;
  1715. }
  1716. EXPORT_SYMBOL(il_add_station_common);
  1717. /**
  1718. * il_sta_ucode_deactivate - deactivate ucode status for a station
  1719. *
  1720. * il->sta_lock must be held
  1721. */
  1722. static void
  1723. il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
  1724. {
  1725. /* Ucode must be active and driver must be non active */
  1726. if ((il->stations[sta_id].
  1727. used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
  1728. IL_STA_UCODE_ACTIVE)
  1729. IL_ERR("removed non active STA %u\n", sta_id);
  1730. il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
  1731. memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
  1732. D_ASSOC("Removed STA %u\n", sta_id);
  1733. }
  1734. static int
  1735. il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
  1736. bool temporary)
  1737. {
  1738. struct il_rx_pkt *pkt;
  1739. int ret;
  1740. unsigned long flags_spin;
  1741. struct il_rem_sta_cmd rm_sta_cmd;
  1742. struct il_host_cmd cmd = {
  1743. .id = C_REM_STA,
  1744. .len = sizeof(struct il_rem_sta_cmd),
  1745. .flags = CMD_SYNC,
  1746. .data = &rm_sta_cmd,
  1747. };
  1748. memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
  1749. rm_sta_cmd.num_sta = 1;
  1750. memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
  1751. cmd.flags |= CMD_WANT_SKB;
  1752. ret = il_send_cmd(il, &cmd);
  1753. if (ret)
  1754. return ret;
  1755. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1756. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1757. IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
  1758. ret = -EIO;
  1759. }
  1760. if (!ret) {
  1761. switch (pkt->u.rem_sta.status) {
  1762. case REM_STA_SUCCESS_MSK:
  1763. if (!temporary) {
  1764. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1765. il_sta_ucode_deactivate(il, sta_id);
  1766. spin_unlock_irqrestore(&il->sta_lock,
  1767. flags_spin);
  1768. }
  1769. D_ASSOC("C_REM_STA PASSED\n");
  1770. break;
  1771. default:
  1772. ret = -EIO;
  1773. IL_ERR("C_REM_STA failed\n");
  1774. break;
  1775. }
  1776. }
  1777. il_free_pages(il, cmd.reply_page);
  1778. return ret;
  1779. }
  1780. /**
  1781. * il_remove_station - Remove driver's knowledge of station.
  1782. */
  1783. int
  1784. il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
  1785. {
  1786. unsigned long flags;
  1787. if (!il_is_ready(il)) {
  1788. D_INFO("Unable to remove station %pM, device not ready.\n",
  1789. addr);
  1790. /*
  1791. * It is typical for stations to be removed when we are
  1792. * going down. Return success since device will be down
  1793. * soon anyway
  1794. */
  1795. return 0;
  1796. }
  1797. D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
  1798. if (WARN_ON(sta_id == IL_INVALID_STATION))
  1799. return -EINVAL;
  1800. spin_lock_irqsave(&il->sta_lock, flags);
  1801. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1802. D_INFO("Removing %pM but non DRIVER active\n", addr);
  1803. goto out_err;
  1804. }
  1805. if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1806. D_INFO("Removing %pM but non UCODE active\n", addr);
  1807. goto out_err;
  1808. }
  1809. if (il->stations[sta_id].used & IL_STA_LOCAL) {
  1810. kfree(il->stations[sta_id].lq);
  1811. il->stations[sta_id].lq = NULL;
  1812. }
  1813. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1814. il->num_stations--;
  1815. BUG_ON(il->num_stations < 0);
  1816. spin_unlock_irqrestore(&il->sta_lock, flags);
  1817. return il_send_remove_station(il, addr, sta_id, false);
  1818. out_err:
  1819. spin_unlock_irqrestore(&il->sta_lock, flags);
  1820. return -EINVAL;
  1821. }
  1822. EXPORT_SYMBOL_GPL(il_remove_station);
  1823. /**
  1824. * il_clear_ucode_stations - clear ucode station table bits
  1825. *
  1826. * This function clears all the bits in the driver indicating
  1827. * which stations are active in the ucode. Call when something
  1828. * other than explicit station management would cause this in
  1829. * the ucode, e.g. unassociated RXON.
  1830. */
  1831. void
  1832. il_clear_ucode_stations(struct il_priv *il)
  1833. {
  1834. int i;
  1835. unsigned long flags_spin;
  1836. bool cleared = false;
  1837. D_INFO("Clearing ucode stations in driver\n");
  1838. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1839. for (i = 0; i < il->hw_params.max_stations; i++) {
  1840. if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
  1841. D_INFO("Clearing ucode active for station %d\n", i);
  1842. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1843. cleared = true;
  1844. }
  1845. }
  1846. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1847. if (!cleared)
  1848. D_INFO("No active stations found to be cleared\n");
  1849. }
  1850. EXPORT_SYMBOL(il_clear_ucode_stations);
  1851. /**
  1852. * il_restore_stations() - Restore driver known stations to device
  1853. *
  1854. * All stations considered active by driver, but not present in ucode, is
  1855. * restored.
  1856. *
  1857. * Function sleeps.
  1858. */
  1859. void
  1860. il_restore_stations(struct il_priv *il)
  1861. {
  1862. struct il_addsta_cmd sta_cmd;
  1863. struct il_link_quality_cmd lq;
  1864. unsigned long flags_spin;
  1865. int i;
  1866. bool found = false;
  1867. int ret;
  1868. bool send_lq;
  1869. if (!il_is_ready(il)) {
  1870. D_INFO("Not ready yet, not restoring any stations.\n");
  1871. return;
  1872. }
  1873. D_ASSOC("Restoring all known stations ... start.\n");
  1874. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1875. for (i = 0; i < il->hw_params.max_stations; i++) {
  1876. if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
  1877. !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
  1878. D_ASSOC("Restoring sta %pM\n",
  1879. il->stations[i].sta.sta.addr);
  1880. il->stations[i].sta.mode = 0;
  1881. il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
  1882. found = true;
  1883. }
  1884. }
  1885. for (i = 0; i < il->hw_params.max_stations; i++) {
  1886. if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
  1887. memcpy(&sta_cmd, &il->stations[i].sta,
  1888. sizeof(struct il_addsta_cmd));
  1889. send_lq = false;
  1890. if (il->stations[i].lq) {
  1891. memcpy(&lq, il->stations[i].lq,
  1892. sizeof(struct il_link_quality_cmd));
  1893. send_lq = true;
  1894. }
  1895. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1896. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1897. if (ret) {
  1898. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1899. IL_ERR("Adding station %pM failed.\n",
  1900. il->stations[i].sta.sta.addr);
  1901. il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
  1902. il->stations[i].used &=
  1903. ~IL_STA_UCODE_INPROGRESS;
  1904. spin_unlock_irqrestore(&il->sta_lock,
  1905. flags_spin);
  1906. }
  1907. /*
  1908. * Rate scaling has already been initialized, send
  1909. * current LQ command
  1910. */
  1911. if (send_lq)
  1912. il_send_lq_cmd(il, &lq, CMD_SYNC, true);
  1913. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1914. il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
  1915. }
  1916. }
  1917. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1918. if (!found)
  1919. D_INFO("Restoring all known stations"
  1920. " .... no stations to be restored.\n");
  1921. else
  1922. D_INFO("Restoring all known stations" " .... complete.\n");
  1923. }
  1924. EXPORT_SYMBOL(il_restore_stations);
  1925. int
  1926. il_get_free_ucode_key_idx(struct il_priv *il)
  1927. {
  1928. int i;
  1929. for (i = 0; i < il->sta_key_max_num; i++)
  1930. if (!test_and_set_bit(i, &il->ucode_key_table))
  1931. return i;
  1932. return WEP_INVALID_OFFSET;
  1933. }
  1934. EXPORT_SYMBOL(il_get_free_ucode_key_idx);
  1935. void
  1936. il_dealloc_bcast_stations(struct il_priv *il)
  1937. {
  1938. unsigned long flags;
  1939. int i;
  1940. spin_lock_irqsave(&il->sta_lock, flags);
  1941. for (i = 0; i < il->hw_params.max_stations; i++) {
  1942. if (!(il->stations[i].used & IL_STA_BCAST))
  1943. continue;
  1944. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1945. il->num_stations--;
  1946. BUG_ON(il->num_stations < 0);
  1947. kfree(il->stations[i].lq);
  1948. il->stations[i].lq = NULL;
  1949. }
  1950. spin_unlock_irqrestore(&il->sta_lock, flags);
  1951. }
  1952. EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
  1953. #ifdef CONFIG_IWLEGACY_DEBUG
  1954. static void
  1955. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1956. {
  1957. int i;
  1958. D_RATE("lq station id 0x%x\n", lq->sta_id);
  1959. D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
  1960. lq->general_params.dual_stream_ant_msk);
  1961. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  1962. D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
  1963. }
  1964. #else
  1965. static inline void
  1966. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1967. {
  1968. }
  1969. #endif
  1970. /**
  1971. * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
  1972. *
  1973. * It sometimes happens when a HT rate has been in use and we
  1974. * loose connectivity with AP then mac80211 will first tell us that the
  1975. * current channel is not HT anymore before removing the station. In such a
  1976. * scenario the RXON flags will be updated to indicate we are not
  1977. * communicating HT anymore, but the LQ command may still contain HT rates.
  1978. * Test for this to prevent driver from sending LQ command between the time
  1979. * RXON flags are updated and when LQ command is updated.
  1980. */
  1981. static bool
  1982. il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
  1983. {
  1984. int i;
  1985. if (il->ht.enabled)
  1986. return true;
  1987. D_INFO("Channel %u is not an HT channel\n", il->active.channel);
  1988. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  1989. if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
  1990. D_INFO("idx %d of LQ expects HT channel\n", i);
  1991. return false;
  1992. }
  1993. }
  1994. return true;
  1995. }
  1996. /**
  1997. * il_send_lq_cmd() - Send link quality command
  1998. * @init: This command is sent as part of station initialization right
  1999. * after station has been added.
  2000. *
  2001. * The link quality command is sent as the last step of station creation.
  2002. * This is the special case in which init is set and we call a callback in
  2003. * this case to clear the state indicating that station creation is in
  2004. * progress.
  2005. */
  2006. int
  2007. il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
  2008. u8 flags, bool init)
  2009. {
  2010. int ret = 0;
  2011. unsigned long flags_spin;
  2012. struct il_host_cmd cmd = {
  2013. .id = C_TX_LINK_QUALITY_CMD,
  2014. .len = sizeof(struct il_link_quality_cmd),
  2015. .flags = flags,
  2016. .data = lq,
  2017. };
  2018. if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
  2019. return -EINVAL;
  2020. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2021. if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  2022. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2023. return -EINVAL;
  2024. }
  2025. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2026. il_dump_lq_cmd(il, lq);
  2027. BUG_ON(init && (cmd.flags & CMD_ASYNC));
  2028. if (il_is_lq_table_valid(il, lq))
  2029. ret = il_send_cmd(il, &cmd);
  2030. else
  2031. ret = -EINVAL;
  2032. if (cmd.flags & CMD_ASYNC)
  2033. return ret;
  2034. if (init) {
  2035. D_INFO("init LQ command complete,"
  2036. " clearing sta addition status for sta %d\n",
  2037. lq->sta_id);
  2038. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2039. il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  2040. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2041. }
  2042. return ret;
  2043. }
  2044. EXPORT_SYMBOL(il_send_lq_cmd);
  2045. int
  2046. il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2047. struct ieee80211_sta *sta)
  2048. {
  2049. struct il_priv *il = hw->priv;
  2050. struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
  2051. int ret;
  2052. mutex_lock(&il->mutex);
  2053. D_MAC80211("enter station %pM\n", sta->addr);
  2054. ret = il_remove_station(il, sta_common->sta_id, sta->addr);
  2055. if (ret)
  2056. IL_ERR("Error removing station %pM\n", sta->addr);
  2057. D_MAC80211("leave ret %d\n", ret);
  2058. mutex_unlock(&il->mutex);
  2059. return ret;
  2060. }
  2061. EXPORT_SYMBOL(il_mac_sta_remove);
  2062. /************************** RX-FUNCTIONS ****************************/
  2063. /*
  2064. * Rx theory of operation
  2065. *
  2066. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  2067. * each of which point to Receive Buffers to be filled by the NIC. These get
  2068. * used not only for Rx frames, but for any command response or notification
  2069. * from the NIC. The driver and NIC manage the Rx buffers by means
  2070. * of idxes into the circular buffer.
  2071. *
  2072. * Rx Queue Indexes
  2073. * The host/firmware share two idx registers for managing the Rx buffers.
  2074. *
  2075. * The READ idx maps to the first position that the firmware may be writing
  2076. * to -- the driver can read up to (but not including) this position and get
  2077. * good data.
  2078. * The READ idx is managed by the firmware once the card is enabled.
  2079. *
  2080. * The WRITE idx maps to the last position the driver has read from -- the
  2081. * position preceding WRITE is the last slot the firmware can place a packet.
  2082. *
  2083. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2084. * WRITE = READ.
  2085. *
  2086. * During initialization, the host sets up the READ queue position to the first
  2087. * IDX position, and WRITE to the last (READ - 1 wrapped)
  2088. *
  2089. * When the firmware places a packet in a buffer, it will advance the READ idx
  2090. * and fire the RX interrupt. The driver can then query the READ idx and
  2091. * process as many packets as possible, moving the WRITE idx forward as it
  2092. * resets the Rx queue buffers with new memory.
  2093. *
  2094. * The management in the driver is as follows:
  2095. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2096. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2097. * to replenish the iwl->rxq->rx_free.
  2098. * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
  2099. * iwl->rxq is replenished and the READ IDX is updated (updating the
  2100. * 'processed' and 'read' driver idxes as well)
  2101. * + A received packet is processed and handed to the kernel network stack,
  2102. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  2103. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2104. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2105. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  2106. * were enough free buffers and RX_STALLED is set it is cleared.
  2107. *
  2108. *
  2109. * Driver sequence:
  2110. *
  2111. * il_rx_queue_alloc() Allocates rx_free
  2112. * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2113. * il_rx_queue_restock
  2114. * il_rx_queue_restock() Moves available buffers from rx_free into Rx
  2115. * queue, updates firmware pointers, and updates
  2116. * the WRITE idx. If insufficient rx_free buffers
  2117. * are available, schedules il_rx_replenish
  2118. *
  2119. * -- enable interrupts --
  2120. * ISR - il_rx() Detach il_rx_bufs from pool up to the
  2121. * READ IDX, detaching the SKB from the pool.
  2122. * Moves the packet buffer from queue to rx_used.
  2123. * Calls il_rx_queue_restock to refill any empty
  2124. * slots.
  2125. * ...
  2126. *
  2127. */
  2128. /**
  2129. * il_rx_queue_space - Return number of free slots available in queue.
  2130. */
  2131. int
  2132. il_rx_queue_space(const struct il_rx_queue *q)
  2133. {
  2134. int s = q->read - q->write;
  2135. if (s <= 0)
  2136. s += RX_QUEUE_SIZE;
  2137. /* keep some buffer to not confuse full and empty queue */
  2138. s -= 2;
  2139. if (s < 0)
  2140. s = 0;
  2141. return s;
  2142. }
  2143. EXPORT_SYMBOL(il_rx_queue_space);
  2144. /**
  2145. * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2146. */
  2147. void
  2148. il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
  2149. {
  2150. unsigned long flags;
  2151. u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
  2152. u32 reg;
  2153. spin_lock_irqsave(&q->lock, flags);
  2154. if (q->need_update == 0)
  2155. goto exit_unlock;
  2156. /* If power-saving is in use, make sure device is awake */
  2157. if (test_bit(S_POWER_PMI, &il->status)) {
  2158. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2159. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2160. D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
  2161. reg);
  2162. il_set_bit(il, CSR_GP_CNTRL,
  2163. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2164. goto exit_unlock;
  2165. }
  2166. q->write_actual = (q->write & ~0x7);
  2167. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2168. /* Else device is assumed to be awake */
  2169. } else {
  2170. /* Device expects a multiple of 8 */
  2171. q->write_actual = (q->write & ~0x7);
  2172. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2173. }
  2174. q->need_update = 0;
  2175. exit_unlock:
  2176. spin_unlock_irqrestore(&q->lock, flags);
  2177. }
  2178. EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
  2179. int
  2180. il_rx_queue_alloc(struct il_priv *il)
  2181. {
  2182. struct il_rx_queue *rxq = &il->rxq;
  2183. struct device *dev = &il->pci_dev->dev;
  2184. int i;
  2185. spin_lock_init(&rxq->lock);
  2186. INIT_LIST_HEAD(&rxq->rx_free);
  2187. INIT_LIST_HEAD(&rxq->rx_used);
  2188. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2189. rxq->bd =
  2190. dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
  2191. GFP_KERNEL);
  2192. if (!rxq->bd)
  2193. goto err_bd;
  2194. rxq->rb_stts =
  2195. dma_alloc_coherent(dev, sizeof(struct il_rb_status),
  2196. &rxq->rb_stts_dma, GFP_KERNEL);
  2197. if (!rxq->rb_stts)
  2198. goto err_rb;
  2199. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2200. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2201. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2202. /* Set us so that we have processed and used all buffers, but have
  2203. * not restocked the Rx queue with fresh buffers */
  2204. rxq->read = rxq->write = 0;
  2205. rxq->write_actual = 0;
  2206. rxq->free_count = 0;
  2207. rxq->need_update = 0;
  2208. return 0;
  2209. err_rb:
  2210. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2211. rxq->bd_dma);
  2212. err_bd:
  2213. return -ENOMEM;
  2214. }
  2215. EXPORT_SYMBOL(il_rx_queue_alloc);
  2216. void
  2217. il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
  2218. {
  2219. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2220. struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2221. if (!report->state) {
  2222. D_11H("Spectrum Measure Notification: Start\n");
  2223. return;
  2224. }
  2225. memcpy(&il->measure_report, report, sizeof(*report));
  2226. il->measurement_status |= MEASUREMENT_READY;
  2227. }
  2228. EXPORT_SYMBOL(il_hdl_spectrum_measurement);
  2229. /*
  2230. * returns non-zero if packet should be dropped
  2231. */
  2232. int
  2233. il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
  2234. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2235. {
  2236. u16 fc = le16_to_cpu(hdr->frame_control);
  2237. /*
  2238. * All contexts have the same setting here due to it being
  2239. * a module parameter, so OK to check any context.
  2240. */
  2241. if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2242. return 0;
  2243. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2244. return 0;
  2245. D_RX("decrypt_res:0x%x\n", decrypt_res);
  2246. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2247. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2248. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2249. * Decryption will be done in SW. */
  2250. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2251. RX_RES_STATUS_BAD_KEY_TTAK)
  2252. break;
  2253. case RX_RES_STATUS_SEC_TYPE_WEP:
  2254. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2255. RX_RES_STATUS_BAD_ICV_MIC) {
  2256. /* bad ICV, the packet is destroyed since the
  2257. * decryption is inplace, drop it */
  2258. D_RX("Packet destroyed\n");
  2259. return -1;
  2260. }
  2261. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2262. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2263. RX_RES_STATUS_DECRYPT_OK) {
  2264. D_RX("hw decrypt successfully!!!\n");
  2265. stats->flag |= RX_FLAG_DECRYPTED;
  2266. }
  2267. break;
  2268. default:
  2269. break;
  2270. }
  2271. return 0;
  2272. }
  2273. EXPORT_SYMBOL(il_set_decrypted_flag);
  2274. /**
  2275. * il_txq_update_write_ptr - Send new write idx to hardware
  2276. */
  2277. void
  2278. il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
  2279. {
  2280. u32 reg = 0;
  2281. int txq_id = txq->q.id;
  2282. if (txq->need_update == 0)
  2283. return;
  2284. /* if we're trying to save power */
  2285. if (test_bit(S_POWER_PMI, &il->status)) {
  2286. /* wake up nic if it's powered down ...
  2287. * uCode will wake up, and interrupt us again, so next
  2288. * time we'll skip this part. */
  2289. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2290. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2291. D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
  2292. txq_id, reg);
  2293. il_set_bit(il, CSR_GP_CNTRL,
  2294. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2295. return;
  2296. }
  2297. il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2298. /*
  2299. * else not in power-save mode,
  2300. * uCode will never sleep when we're
  2301. * trying to tx (during RFKILL, we're not trying to tx).
  2302. */
  2303. } else
  2304. _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2305. txq->need_update = 0;
  2306. }
  2307. EXPORT_SYMBOL(il_txq_update_write_ptr);
  2308. /**
  2309. * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  2310. */
  2311. void
  2312. il_tx_queue_unmap(struct il_priv *il, int txq_id)
  2313. {
  2314. struct il_tx_queue *txq = &il->txq[txq_id];
  2315. struct il_queue *q = &txq->q;
  2316. if (q->n_bd == 0)
  2317. return;
  2318. while (q->write_ptr != q->read_ptr) {
  2319. il->ops->txq_free_tfd(il, txq);
  2320. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2321. }
  2322. }
  2323. EXPORT_SYMBOL(il_tx_queue_unmap);
  2324. /**
  2325. * il_tx_queue_free - Deallocate DMA queue.
  2326. * @txq: Transmit queue to deallocate.
  2327. *
  2328. * Empty queue by removing and destroying all BD's.
  2329. * Free all buffers.
  2330. * 0-fill, but do not free "txq" descriptor structure.
  2331. */
  2332. void
  2333. il_tx_queue_free(struct il_priv *il, int txq_id)
  2334. {
  2335. struct il_tx_queue *txq = &il->txq[txq_id];
  2336. struct device *dev = &il->pci_dev->dev;
  2337. int i;
  2338. il_tx_queue_unmap(il, txq_id);
  2339. /* De-alloc array of command/tx buffers */
  2340. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  2341. kfree(txq->cmd[i]);
  2342. /* De-alloc circular buffer of TFDs */
  2343. if (txq->q.n_bd)
  2344. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2345. txq->tfds, txq->q.dma_addr);
  2346. /* De-alloc array of per-TFD driver data */
  2347. kfree(txq->skbs);
  2348. txq->skbs = NULL;
  2349. /* deallocate arrays */
  2350. kfree(txq->cmd);
  2351. kfree(txq->meta);
  2352. txq->cmd = NULL;
  2353. txq->meta = NULL;
  2354. /* 0-fill queue descriptor structure */
  2355. memset(txq, 0, sizeof(*txq));
  2356. }
  2357. EXPORT_SYMBOL(il_tx_queue_free);
  2358. /**
  2359. * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  2360. */
  2361. void
  2362. il_cmd_queue_unmap(struct il_priv *il)
  2363. {
  2364. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2365. struct il_queue *q = &txq->q;
  2366. int i;
  2367. if (q->n_bd == 0)
  2368. return;
  2369. while (q->read_ptr != q->write_ptr) {
  2370. i = il_get_cmd_idx(q, q->read_ptr, 0);
  2371. if (txq->meta[i].flags & CMD_MAPPED) {
  2372. pci_unmap_single(il->pci_dev,
  2373. dma_unmap_addr(&txq->meta[i], mapping),
  2374. dma_unmap_len(&txq->meta[i], len),
  2375. PCI_DMA_BIDIRECTIONAL);
  2376. txq->meta[i].flags = 0;
  2377. }
  2378. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2379. }
  2380. i = q->n_win;
  2381. if (txq->meta[i].flags & CMD_MAPPED) {
  2382. pci_unmap_single(il->pci_dev,
  2383. dma_unmap_addr(&txq->meta[i], mapping),
  2384. dma_unmap_len(&txq->meta[i], len),
  2385. PCI_DMA_BIDIRECTIONAL);
  2386. txq->meta[i].flags = 0;
  2387. }
  2388. }
  2389. EXPORT_SYMBOL(il_cmd_queue_unmap);
  2390. /**
  2391. * il_cmd_queue_free - Deallocate DMA queue.
  2392. * @txq: Transmit queue to deallocate.
  2393. *
  2394. * Empty queue by removing and destroying all BD's.
  2395. * Free all buffers.
  2396. * 0-fill, but do not free "txq" descriptor structure.
  2397. */
  2398. void
  2399. il_cmd_queue_free(struct il_priv *il)
  2400. {
  2401. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2402. struct device *dev = &il->pci_dev->dev;
  2403. int i;
  2404. il_cmd_queue_unmap(il);
  2405. /* De-alloc array of command/tx buffers */
  2406. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  2407. kfree(txq->cmd[i]);
  2408. /* De-alloc circular buffer of TFDs */
  2409. if (txq->q.n_bd)
  2410. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2411. txq->tfds, txq->q.dma_addr);
  2412. /* deallocate arrays */
  2413. kfree(txq->cmd);
  2414. kfree(txq->meta);
  2415. txq->cmd = NULL;
  2416. txq->meta = NULL;
  2417. /* 0-fill queue descriptor structure */
  2418. memset(txq, 0, sizeof(*txq));
  2419. }
  2420. EXPORT_SYMBOL(il_cmd_queue_free);
  2421. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  2422. * DMA services
  2423. *
  2424. * Theory of operation
  2425. *
  2426. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  2427. * of buffer descriptors, each of which points to one or more data buffers for
  2428. * the device to read from or fill. Driver and device exchange status of each
  2429. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  2430. * entries in each circular buffer, to protect against confusing empty and full
  2431. * queue states.
  2432. *
  2433. * The device reads or writes the data in the queues via the device's several
  2434. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  2435. *
  2436. * For Tx queue, there are low mark and high mark limits. If, after queuing
  2437. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  2438. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  2439. * Tx queue resumed.
  2440. *
  2441. * See more detailed info in 4965.h.
  2442. ***************************************************/
  2443. int
  2444. il_queue_space(const struct il_queue *q)
  2445. {
  2446. int s = q->read_ptr - q->write_ptr;
  2447. if (q->read_ptr > q->write_ptr)
  2448. s -= q->n_bd;
  2449. if (s <= 0)
  2450. s += q->n_win;
  2451. /* keep some reserve to not confuse empty and full situations */
  2452. s -= 2;
  2453. if (s < 0)
  2454. s = 0;
  2455. return s;
  2456. }
  2457. EXPORT_SYMBOL(il_queue_space);
  2458. /**
  2459. * il_queue_init - Initialize queue's high/low-water and read/write idxes
  2460. */
  2461. static int
  2462. il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
  2463. {
  2464. /*
  2465. * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  2466. * il_queue_inc_wrap and il_queue_dec_wrap are broken.
  2467. */
  2468. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  2469. /* FIXME: remove q->n_bd */
  2470. q->n_bd = TFD_QUEUE_SIZE_MAX;
  2471. q->n_win = slots;
  2472. q->id = id;
  2473. /* slots_must be power-of-two size, otherwise
  2474. * il_get_cmd_idx is broken. */
  2475. BUG_ON(!is_power_of_2(slots));
  2476. q->low_mark = q->n_win / 4;
  2477. if (q->low_mark < 4)
  2478. q->low_mark = 4;
  2479. q->high_mark = q->n_win / 8;
  2480. if (q->high_mark < 2)
  2481. q->high_mark = 2;
  2482. q->write_ptr = q->read_ptr = 0;
  2483. return 0;
  2484. }
  2485. /**
  2486. * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  2487. */
  2488. static int
  2489. il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
  2490. {
  2491. struct device *dev = &il->pci_dev->dev;
  2492. size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  2493. /* Driver ilate data, only for Tx (not command) queues,
  2494. * not shared with device. */
  2495. if (id != il->cmd_queue) {
  2496. txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *),
  2497. GFP_KERNEL);
  2498. if (!txq->skbs) {
  2499. IL_ERR("Fail to alloc skbs\n");
  2500. goto error;
  2501. }
  2502. } else
  2503. txq->skbs = NULL;
  2504. /* Circular buffer of transmit frame descriptors (TFDs),
  2505. * shared with device */
  2506. txq->tfds =
  2507. dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
  2508. if (!txq->tfds) {
  2509. IL_ERR("Fail to alloc TFDs\n");
  2510. goto error;
  2511. }
  2512. txq->q.id = id;
  2513. return 0;
  2514. error:
  2515. kfree(txq->skbs);
  2516. txq->skbs = NULL;
  2517. return -ENOMEM;
  2518. }
  2519. /**
  2520. * il_tx_queue_init - Allocate and initialize one tx/cmd queue
  2521. */
  2522. int
  2523. il_tx_queue_init(struct il_priv *il, u32 txq_id)
  2524. {
  2525. int i, len, ret;
  2526. int slots, actual_slots;
  2527. struct il_tx_queue *txq = &il->txq[txq_id];
  2528. /*
  2529. * Alloc buffer array for commands (Tx or other types of commands).
  2530. * For the command queue (#4/#9), allocate command space + one big
  2531. * command for scan, since scan command is very huge; the system will
  2532. * not have two scans at the same time, so only one is needed.
  2533. * For normal Tx queues (all other queues), no super-size command
  2534. * space is needed.
  2535. */
  2536. if (txq_id == il->cmd_queue) {
  2537. slots = TFD_CMD_SLOTS;
  2538. actual_slots = slots + 1;
  2539. } else {
  2540. slots = TFD_TX_CMD_SLOTS;
  2541. actual_slots = slots;
  2542. }
  2543. txq->meta =
  2544. kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
  2545. txq->cmd =
  2546. kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
  2547. if (!txq->meta || !txq->cmd)
  2548. goto out_free_arrays;
  2549. len = sizeof(struct il_device_cmd);
  2550. for (i = 0; i < actual_slots; i++) {
  2551. /* only happens for cmd queue */
  2552. if (i == slots)
  2553. len = IL_MAX_CMD_SIZE;
  2554. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  2555. if (!txq->cmd[i])
  2556. goto err;
  2557. }
  2558. /* Alloc driver data array and TFD circular buffer */
  2559. ret = il_tx_queue_alloc(il, txq, txq_id);
  2560. if (ret)
  2561. goto err;
  2562. txq->need_update = 0;
  2563. /*
  2564. * For the default queues 0-3, set up the swq_id
  2565. * already -- all others need to get one later
  2566. * (if they need one at all).
  2567. */
  2568. if (txq_id < 4)
  2569. il_set_swq_id(txq, txq_id, txq_id);
  2570. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2571. il_queue_init(il, &txq->q, slots, txq_id);
  2572. /* Tell device where to find queue */
  2573. il->ops->txq_init(il, txq);
  2574. return 0;
  2575. err:
  2576. for (i = 0; i < actual_slots; i++)
  2577. kfree(txq->cmd[i]);
  2578. out_free_arrays:
  2579. kfree(txq->meta);
  2580. kfree(txq->cmd);
  2581. return -ENOMEM;
  2582. }
  2583. EXPORT_SYMBOL(il_tx_queue_init);
  2584. void
  2585. il_tx_queue_reset(struct il_priv *il, u32 txq_id)
  2586. {
  2587. int slots, actual_slots;
  2588. struct il_tx_queue *txq = &il->txq[txq_id];
  2589. if (txq_id == il->cmd_queue) {
  2590. slots = TFD_CMD_SLOTS;
  2591. actual_slots = TFD_CMD_SLOTS + 1;
  2592. } else {
  2593. slots = TFD_TX_CMD_SLOTS;
  2594. actual_slots = TFD_TX_CMD_SLOTS;
  2595. }
  2596. memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
  2597. txq->need_update = 0;
  2598. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2599. il_queue_init(il, &txq->q, slots, txq_id);
  2600. /* Tell device where to find queue */
  2601. il->ops->txq_init(il, txq);
  2602. }
  2603. EXPORT_SYMBOL(il_tx_queue_reset);
  2604. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  2605. /**
  2606. * il_enqueue_hcmd - enqueue a uCode command
  2607. * @il: device ilate data point
  2608. * @cmd: a point to the ucode command structure
  2609. *
  2610. * The function returns < 0 values to indicate the operation is
  2611. * failed. On success, it turns the idx (> 0) of command in the
  2612. * command queue.
  2613. */
  2614. int
  2615. il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
  2616. {
  2617. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2618. struct il_queue *q = &txq->q;
  2619. struct il_device_cmd *out_cmd;
  2620. struct il_cmd_meta *out_meta;
  2621. dma_addr_t phys_addr;
  2622. unsigned long flags;
  2623. int len;
  2624. u32 idx;
  2625. u16 fix_size;
  2626. cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
  2627. fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
  2628. /* If any of the command structures end up being larger than
  2629. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  2630. * we will need to increase the size of the TFD entries
  2631. * Also, check to see if command buffer should not exceed the size
  2632. * of device_cmd and max_cmd_size. */
  2633. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  2634. !(cmd->flags & CMD_SIZE_HUGE));
  2635. BUG_ON(fix_size > IL_MAX_CMD_SIZE);
  2636. if (il_is_rfkill(il) || il_is_ctkill(il)) {
  2637. IL_WARN("Not sending command - %s KILL\n",
  2638. il_is_rfkill(il) ? "RF" : "CT");
  2639. return -EIO;
  2640. }
  2641. spin_lock_irqsave(&il->hcmd_lock, flags);
  2642. if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  2643. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2644. IL_ERR("Restarting adapter due to command queue full\n");
  2645. queue_work(il->workqueue, &il->restart);
  2646. return -ENOSPC;
  2647. }
  2648. idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  2649. out_cmd = txq->cmd[idx];
  2650. out_meta = &txq->meta[idx];
  2651. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  2652. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2653. return -ENOSPC;
  2654. }
  2655. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  2656. out_meta->flags = cmd->flags | CMD_MAPPED;
  2657. if (cmd->flags & CMD_WANT_SKB)
  2658. out_meta->source = cmd;
  2659. if (cmd->flags & CMD_ASYNC)
  2660. out_meta->callback = cmd->callback;
  2661. out_cmd->hdr.cmd = cmd->id;
  2662. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  2663. /* At this point, the out_cmd now has all of the incoming cmd
  2664. * information */
  2665. out_cmd->hdr.flags = 0;
  2666. out_cmd->hdr.sequence =
  2667. cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
  2668. if (cmd->flags & CMD_SIZE_HUGE)
  2669. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  2670. len = sizeof(struct il_device_cmd);
  2671. if (idx == TFD_CMD_SLOTS)
  2672. len = IL_MAX_CMD_SIZE;
  2673. #ifdef CONFIG_IWLEGACY_DEBUG
  2674. switch (out_cmd->hdr.cmd) {
  2675. case C_TX_LINK_QUALITY_CMD:
  2676. case C_SENSITIVITY:
  2677. D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
  2678. "%d bytes at %d[%d]:%d\n",
  2679. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2680. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2681. q->write_ptr, idx, il->cmd_queue);
  2682. break;
  2683. default:
  2684. D_HC("Sending command %s (#%x), seq: 0x%04X, "
  2685. "%d bytes at %d[%d]:%d\n",
  2686. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2687. le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
  2688. idx, il->cmd_queue);
  2689. }
  2690. #endif
  2691. phys_addr =
  2692. pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
  2693. PCI_DMA_BIDIRECTIONAL);
  2694. if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr))) {
  2695. idx = -ENOMEM;
  2696. goto out;
  2697. }
  2698. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  2699. dma_unmap_len_set(out_meta, len, fix_size);
  2700. txq->need_update = 1;
  2701. if (il->ops->txq_update_byte_cnt_tbl)
  2702. /* Set up entry in queue's byte count circular buffer */
  2703. il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
  2704. il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
  2705. U32_PAD(cmd->len));
  2706. /* Increment and update queue's write idx */
  2707. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  2708. il_txq_update_write_ptr(il, txq);
  2709. out:
  2710. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2711. return idx;
  2712. }
  2713. /**
  2714. * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  2715. *
  2716. * When FW advances 'R' idx, all entries between old and new 'R' idx
  2717. * need to be reclaimed. As result, some free space forms. If there is
  2718. * enough free space (> low mark), wake the stack that feeds us.
  2719. */
  2720. static void
  2721. il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
  2722. {
  2723. struct il_tx_queue *txq = &il->txq[txq_id];
  2724. struct il_queue *q = &txq->q;
  2725. int nfreed = 0;
  2726. if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
  2727. IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
  2728. "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
  2729. q->write_ptr, q->read_ptr);
  2730. return;
  2731. }
  2732. for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  2733. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2734. if (nfreed++ > 0) {
  2735. IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
  2736. q->write_ptr, q->read_ptr);
  2737. queue_work(il->workqueue, &il->restart);
  2738. }
  2739. }
  2740. }
  2741. /**
  2742. * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2743. * @rxb: Rx buffer to reclaim
  2744. *
  2745. * If an Rx buffer has an async callback associated with it the callback
  2746. * will be executed. The attached skb (if present) will only be freed
  2747. * if the callback returns 1
  2748. */
  2749. void
  2750. il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
  2751. {
  2752. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2753. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2754. int txq_id = SEQ_TO_QUEUE(sequence);
  2755. int idx = SEQ_TO_IDX(sequence);
  2756. int cmd_idx;
  2757. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2758. struct il_device_cmd *cmd;
  2759. struct il_cmd_meta *meta;
  2760. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2761. unsigned long flags;
  2762. /* If a Tx command is being handled and it isn't in the actual
  2763. * command queue then there a command routing bug has been introduced
  2764. * in the queue management code. */
  2765. if (WARN
  2766. (txq_id != il->cmd_queue,
  2767. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  2768. txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
  2769. il->txq[il->cmd_queue].q.write_ptr)) {
  2770. il_print_hex_error(il, pkt, 32);
  2771. return;
  2772. }
  2773. cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
  2774. cmd = txq->cmd[cmd_idx];
  2775. meta = &txq->meta[cmd_idx];
  2776. txq->time_stamp = jiffies;
  2777. pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
  2778. dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
  2779. /* Input error checking is done when commands are added to queue. */
  2780. if (meta->flags & CMD_WANT_SKB) {
  2781. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  2782. rxb->page = NULL;
  2783. } else if (meta->callback)
  2784. meta->callback(il, cmd, pkt);
  2785. spin_lock_irqsave(&il->hcmd_lock, flags);
  2786. il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
  2787. if (!(meta->flags & CMD_ASYNC)) {
  2788. clear_bit(S_HCMD_ACTIVE, &il->status);
  2789. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  2790. il_get_cmd_string(cmd->hdr.cmd));
  2791. wake_up(&il->wait_command_queue);
  2792. }
  2793. /* Mark as unmapped */
  2794. meta->flags = 0;
  2795. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2796. }
  2797. EXPORT_SYMBOL(il_tx_cmd_complete);
  2798. MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
  2799. MODULE_VERSION(IWLWIFI_VERSION);
  2800. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  2801. MODULE_LICENSE("GPL");
  2802. /*
  2803. * set bt_coex_active to true, uCode will do kill/defer
  2804. * every time the priority line is asserted (BT is sending signals on the
  2805. * priority line in the PCIx).
  2806. * set bt_coex_active to false, uCode will ignore the BT activity and
  2807. * perform the normal operation
  2808. *
  2809. * User might experience transmit issue on some platform due to WiFi/BT
  2810. * co-exist problem. The possible behaviors are:
  2811. * Able to scan and finding all the available AP
  2812. * Not able to associate with any AP
  2813. * On those platforms, WiFi communication can be restored by set
  2814. * "bt_coex_active" module parameter to "false"
  2815. *
  2816. * default: bt_coex_active = true (BT_COEX_ENABLE)
  2817. */
  2818. static bool bt_coex_active = true;
  2819. module_param(bt_coex_active, bool, S_IRUGO);
  2820. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  2821. u32 il_debug_level;
  2822. EXPORT_SYMBOL(il_debug_level);
  2823. const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  2824. EXPORT_SYMBOL(il_bcast_addr);
  2825. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  2826. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  2827. static void
  2828. il_init_ht_hw_capab(const struct il_priv *il,
  2829. struct ieee80211_sta_ht_cap *ht_info,
  2830. enum ieee80211_band band)
  2831. {
  2832. u16 max_bit_rate = 0;
  2833. u8 rx_chains_num = il->hw_params.rx_chains_num;
  2834. u8 tx_chains_num = il->hw_params.tx_chains_num;
  2835. ht_info->cap = 0;
  2836. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  2837. ht_info->ht_supported = true;
  2838. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  2839. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  2840. if (il->hw_params.ht40_channel & BIT(band)) {
  2841. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  2842. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  2843. ht_info->mcs.rx_mask[4] = 0x01;
  2844. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  2845. }
  2846. if (il->cfg->mod_params->amsdu_size_8K)
  2847. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  2848. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2849. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2850. ht_info->mcs.rx_mask[0] = 0xFF;
  2851. if (rx_chains_num >= 2)
  2852. ht_info->mcs.rx_mask[1] = 0xFF;
  2853. if (rx_chains_num >= 3)
  2854. ht_info->mcs.rx_mask[2] = 0xFF;
  2855. /* Highest supported Rx data rate */
  2856. max_bit_rate *= rx_chains_num;
  2857. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  2858. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  2859. /* Tx MCS capabilities */
  2860. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  2861. if (tx_chains_num != rx_chains_num) {
  2862. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  2863. ht_info->mcs.tx_params |=
  2864. ((tx_chains_num -
  2865. 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2866. }
  2867. }
  2868. /**
  2869. * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
  2870. */
  2871. int
  2872. il_init_geos(struct il_priv *il)
  2873. {
  2874. struct il_channel_info *ch;
  2875. struct ieee80211_supported_band *sband;
  2876. struct ieee80211_channel *channels;
  2877. struct ieee80211_channel *geo_ch;
  2878. struct ieee80211_rate *rates;
  2879. int i = 0;
  2880. s8 max_tx_power = 0;
  2881. if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  2882. il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  2883. D_INFO("Geography modes already initialized.\n");
  2884. set_bit(S_GEO_CONFIGURED, &il->status);
  2885. return 0;
  2886. }
  2887. channels =
  2888. kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
  2889. GFP_KERNEL);
  2890. if (!channels)
  2891. return -ENOMEM;
  2892. rates =
  2893. kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
  2894. GFP_KERNEL);
  2895. if (!rates) {
  2896. kfree(channels);
  2897. return -ENOMEM;
  2898. }
  2899. /* 5.2GHz channels start after the 2.4GHz channels */
  2900. sband = &il->bands[IEEE80211_BAND_5GHZ];
  2901. sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
  2902. /* just OFDM */
  2903. sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
  2904. sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
  2905. if (il->cfg->sku & IL_SKU_N)
  2906. il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
  2907. sband = &il->bands[IEEE80211_BAND_2GHZ];
  2908. sband->channels = channels;
  2909. /* OFDM & CCK */
  2910. sband->bitrates = rates;
  2911. sband->n_bitrates = RATE_COUNT_LEGACY;
  2912. if (il->cfg->sku & IL_SKU_N)
  2913. il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
  2914. il->ieee_channels = channels;
  2915. il->ieee_rates = rates;
  2916. for (i = 0; i < il->channel_count; i++) {
  2917. ch = &il->channel_info[i];
  2918. if (!il_is_channel_valid(ch))
  2919. continue;
  2920. sband = &il->bands[ch->band];
  2921. geo_ch = &sband->channels[sband->n_channels++];
  2922. geo_ch->center_freq =
  2923. ieee80211_channel_to_frequency(ch->channel, ch->band);
  2924. geo_ch->max_power = ch->max_power_avg;
  2925. geo_ch->max_antenna_gain = 0xff;
  2926. geo_ch->hw_value = ch->channel;
  2927. if (il_is_channel_valid(ch)) {
  2928. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2929. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  2930. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2931. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2932. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2933. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2934. geo_ch->flags |= ch->ht40_extension_channel;
  2935. if (ch->max_power_avg > max_tx_power)
  2936. max_tx_power = ch->max_power_avg;
  2937. } else {
  2938. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  2939. }
  2940. D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
  2941. geo_ch->center_freq,
  2942. il_is_channel_a_band(ch) ? "5.2" : "2.4",
  2943. geo_ch->
  2944. flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
  2945. geo_ch->flags);
  2946. }
  2947. il->tx_power_device_lmt = max_tx_power;
  2948. il->tx_power_user_lmt = max_tx_power;
  2949. il->tx_power_next = max_tx_power;
  2950. if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
  2951. (il->cfg->sku & IL_SKU_A)) {
  2952. IL_INFO("Incorrectly detected BG card as ABG. "
  2953. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  2954. il->pci_dev->device, il->pci_dev->subsystem_device);
  2955. il->cfg->sku &= ~IL_SKU_A;
  2956. }
  2957. IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  2958. il->bands[IEEE80211_BAND_2GHZ].n_channels,
  2959. il->bands[IEEE80211_BAND_5GHZ].n_channels);
  2960. set_bit(S_GEO_CONFIGURED, &il->status);
  2961. return 0;
  2962. }
  2963. EXPORT_SYMBOL(il_init_geos);
  2964. /*
  2965. * il_free_geos - undo allocations in il_init_geos
  2966. */
  2967. void
  2968. il_free_geos(struct il_priv *il)
  2969. {
  2970. kfree(il->ieee_channels);
  2971. kfree(il->ieee_rates);
  2972. clear_bit(S_GEO_CONFIGURED, &il->status);
  2973. }
  2974. EXPORT_SYMBOL(il_free_geos);
  2975. static bool
  2976. il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
  2977. u16 channel, u8 extension_chan_offset)
  2978. {
  2979. const struct il_channel_info *ch_info;
  2980. ch_info = il_get_channel_info(il, band, channel);
  2981. if (!il_is_channel_valid(ch_info))
  2982. return false;
  2983. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  2984. return !(ch_info->
  2985. ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
  2986. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  2987. return !(ch_info->
  2988. ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
  2989. return false;
  2990. }
  2991. bool
  2992. il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
  2993. {
  2994. if (!il->ht.enabled || !il->ht.is_40mhz)
  2995. return false;
  2996. /*
  2997. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  2998. * the bit will not set if it is pure 40MHz case
  2999. */
  3000. if (ht_cap && !ht_cap->ht_supported)
  3001. return false;
  3002. #ifdef CONFIG_IWLEGACY_DEBUGFS
  3003. if (il->disable_ht40)
  3004. return false;
  3005. #endif
  3006. return il_is_channel_extension(il, il->band,
  3007. le16_to_cpu(il->staging.channel),
  3008. il->ht.extension_chan_offset);
  3009. }
  3010. EXPORT_SYMBOL(il_is_ht40_tx_allowed);
  3011. static u16
  3012. il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  3013. {
  3014. u16 new_val;
  3015. u16 beacon_factor;
  3016. /*
  3017. * If mac80211 hasn't given us a beacon interval, program
  3018. * the default into the device.
  3019. */
  3020. if (!beacon_val)
  3021. return DEFAULT_BEACON_INTERVAL;
  3022. /*
  3023. * If the beacon interval we obtained from the peer
  3024. * is too large, we'll have to wake up more often
  3025. * (and in IBSS case, we'll beacon too much)
  3026. *
  3027. * For example, if max_beacon_val is 4096, and the
  3028. * requested beacon interval is 7000, we'll have to
  3029. * use 3500 to be able to wake up on the beacons.
  3030. *
  3031. * This could badly influence beacon detection stats.
  3032. */
  3033. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  3034. new_val = beacon_val / beacon_factor;
  3035. if (!new_val)
  3036. new_val = max_beacon_val;
  3037. return new_val;
  3038. }
  3039. int
  3040. il_send_rxon_timing(struct il_priv *il)
  3041. {
  3042. u64 tsf;
  3043. s32 interval_tm, rem;
  3044. struct ieee80211_conf *conf = NULL;
  3045. u16 beacon_int;
  3046. struct ieee80211_vif *vif = il->vif;
  3047. conf = &il->hw->conf;
  3048. lockdep_assert_held(&il->mutex);
  3049. memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
  3050. il->timing.timestamp = cpu_to_le64(il->timestamp);
  3051. il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  3052. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  3053. /*
  3054. * TODO: For IBSS we need to get atim_win from mac80211,
  3055. * for now just always use 0
  3056. */
  3057. il->timing.atim_win = 0;
  3058. beacon_int =
  3059. il_adjust_beacon_interval(beacon_int,
  3060. il->hw_params.max_beacon_itrvl *
  3061. TIME_UNIT);
  3062. il->timing.beacon_interval = cpu_to_le16(beacon_int);
  3063. tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
  3064. interval_tm = beacon_int * TIME_UNIT;
  3065. rem = do_div(tsf, interval_tm);
  3066. il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  3067. il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
  3068. D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
  3069. le16_to_cpu(il->timing.beacon_interval),
  3070. le32_to_cpu(il->timing.beacon_init_val),
  3071. le16_to_cpu(il->timing.atim_win));
  3072. return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
  3073. &il->timing);
  3074. }
  3075. EXPORT_SYMBOL(il_send_rxon_timing);
  3076. void
  3077. il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
  3078. {
  3079. struct il_rxon_cmd *rxon = &il->staging;
  3080. if (hw_decrypt)
  3081. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  3082. else
  3083. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  3084. }
  3085. EXPORT_SYMBOL(il_set_rxon_hwcrypto);
  3086. /* validate RXON structure is valid */
  3087. int
  3088. il_check_rxon_cmd(struct il_priv *il)
  3089. {
  3090. struct il_rxon_cmd *rxon = &il->staging;
  3091. bool error = false;
  3092. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  3093. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  3094. IL_WARN("check 2.4G: wrong narrow\n");
  3095. error = true;
  3096. }
  3097. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  3098. IL_WARN("check 2.4G: wrong radar\n");
  3099. error = true;
  3100. }
  3101. } else {
  3102. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  3103. IL_WARN("check 5.2G: not short slot!\n");
  3104. error = true;
  3105. }
  3106. if (rxon->flags & RXON_FLG_CCK_MSK) {
  3107. IL_WARN("check 5.2G: CCK!\n");
  3108. error = true;
  3109. }
  3110. }
  3111. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  3112. IL_WARN("mac/bssid mcast!\n");
  3113. error = true;
  3114. }
  3115. /* make sure basic rates 6Mbps and 1Mbps are supported */
  3116. if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
  3117. (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
  3118. IL_WARN("neither 1 nor 6 are basic\n");
  3119. error = true;
  3120. }
  3121. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  3122. IL_WARN("aid > 2007\n");
  3123. error = true;
  3124. }
  3125. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
  3126. (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  3127. IL_WARN("CCK and short slot\n");
  3128. error = true;
  3129. }
  3130. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
  3131. (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  3132. IL_WARN("CCK and auto detect");
  3133. error = true;
  3134. }
  3135. if ((rxon->
  3136. flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
  3137. RXON_FLG_TGG_PROTECT_MSK) {
  3138. IL_WARN("TGg but no auto-detect\n");
  3139. error = true;
  3140. }
  3141. if (error)
  3142. IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
  3143. if (error) {
  3144. IL_ERR("Invalid RXON\n");
  3145. return -EINVAL;
  3146. }
  3147. return 0;
  3148. }
  3149. EXPORT_SYMBOL(il_check_rxon_cmd);
  3150. /**
  3151. * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  3152. * @il: staging_rxon is compared to active_rxon
  3153. *
  3154. * If the RXON structure is changing enough to require a new tune,
  3155. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  3156. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  3157. */
  3158. int
  3159. il_full_rxon_required(struct il_priv *il)
  3160. {
  3161. const struct il_rxon_cmd *staging = &il->staging;
  3162. const struct il_rxon_cmd *active = &il->active;
  3163. #define CHK(cond) \
  3164. if ((cond)) { \
  3165. D_INFO("need full RXON - " #cond "\n"); \
  3166. return 1; \
  3167. }
  3168. #define CHK_NEQ(c1, c2) \
  3169. if ((c1) != (c2)) { \
  3170. D_INFO("need full RXON - " \
  3171. #c1 " != " #c2 " - %d != %d\n", \
  3172. (c1), (c2)); \
  3173. return 1; \
  3174. }
  3175. /* These items are only settable from the full RXON command */
  3176. CHK(!il_is_associated(il));
  3177. CHK(!ether_addr_equal(staging->bssid_addr, active->bssid_addr));
  3178. CHK(!ether_addr_equal(staging->node_addr, active->node_addr));
  3179. CHK(!ether_addr_equal(staging->wlap_bssid_addr,
  3180. active->wlap_bssid_addr));
  3181. CHK_NEQ(staging->dev_type, active->dev_type);
  3182. CHK_NEQ(staging->channel, active->channel);
  3183. CHK_NEQ(staging->air_propagation, active->air_propagation);
  3184. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  3185. active->ofdm_ht_single_stream_basic_rates);
  3186. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  3187. active->ofdm_ht_dual_stream_basic_rates);
  3188. CHK_NEQ(staging->assoc_id, active->assoc_id);
  3189. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  3190. * be updated with the RXON_ASSOC command -- however only some
  3191. * flag transitions are allowed using RXON_ASSOC */
  3192. /* Check if we are not switching bands */
  3193. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  3194. active->flags & RXON_FLG_BAND_24G_MSK);
  3195. /* Check if we are switching association toggle */
  3196. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  3197. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  3198. #undef CHK
  3199. #undef CHK_NEQ
  3200. return 0;
  3201. }
  3202. EXPORT_SYMBOL(il_full_rxon_required);
  3203. u8
  3204. il_get_lowest_plcp(struct il_priv *il)
  3205. {
  3206. /*
  3207. * Assign the lowest rate -- should really get this from
  3208. * the beacon skb from mac80211.
  3209. */
  3210. if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
  3211. return RATE_1M_PLCP;
  3212. else
  3213. return RATE_6M_PLCP;
  3214. }
  3215. EXPORT_SYMBOL(il_get_lowest_plcp);
  3216. static void
  3217. _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3218. {
  3219. struct il_rxon_cmd *rxon = &il->staging;
  3220. if (!il->ht.enabled) {
  3221. rxon->flags &=
  3222. ~(RXON_FLG_CHANNEL_MODE_MSK |
  3223. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
  3224. | RXON_FLG_HT_PROT_MSK);
  3225. return;
  3226. }
  3227. rxon->flags |=
  3228. cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
  3229. /* Set up channel bandwidth:
  3230. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  3231. /* clear the HT channel mode before set the mode */
  3232. rxon->flags &=
  3233. ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3234. if (il_is_ht40_tx_allowed(il, NULL)) {
  3235. /* pure ht40 */
  3236. if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  3237. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  3238. /* Note: control channel is opposite of extension channel */
  3239. switch (il->ht.extension_chan_offset) {
  3240. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3241. rxon->flags &=
  3242. ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3243. break;
  3244. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3245. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3246. break;
  3247. }
  3248. } else {
  3249. /* Note: control channel is opposite of extension channel */
  3250. switch (il->ht.extension_chan_offset) {
  3251. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3252. rxon->flags &=
  3253. ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3254. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3255. break;
  3256. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3257. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3258. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3259. break;
  3260. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  3261. default:
  3262. /* channel location only valid if in Mixed mode */
  3263. IL_ERR("invalid extension channel offset\n");
  3264. break;
  3265. }
  3266. }
  3267. } else {
  3268. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  3269. }
  3270. if (il->ops->set_rxon_chain)
  3271. il->ops->set_rxon_chain(il);
  3272. D_ASSOC("rxon flags 0x%X operation mode :0x%X "
  3273. "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
  3274. il->ht.protection, il->ht.extension_chan_offset);
  3275. }
  3276. void
  3277. il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3278. {
  3279. _il_set_rxon_ht(il, ht_conf);
  3280. }
  3281. EXPORT_SYMBOL(il_set_rxon_ht);
  3282. /* Return valid, unused, channel for a passive scan to reset the RF */
  3283. u8
  3284. il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
  3285. {
  3286. const struct il_channel_info *ch_info;
  3287. int i;
  3288. u8 channel = 0;
  3289. u8 min, max;
  3290. if (band == IEEE80211_BAND_5GHZ) {
  3291. min = 14;
  3292. max = il->channel_count;
  3293. } else {
  3294. min = 0;
  3295. max = 14;
  3296. }
  3297. for (i = min; i < max; i++) {
  3298. channel = il->channel_info[i].channel;
  3299. if (channel == le16_to_cpu(il->staging.channel))
  3300. continue;
  3301. ch_info = il_get_channel_info(il, band, channel);
  3302. if (il_is_channel_valid(ch_info))
  3303. break;
  3304. }
  3305. return channel;
  3306. }
  3307. EXPORT_SYMBOL(il_get_single_channel_number);
  3308. /**
  3309. * il_set_rxon_channel - Set the band and channel values in staging RXON
  3310. * @ch: requested channel as a pointer to struct ieee80211_channel
  3311. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  3312. * in the staging RXON flag structure based on the ch->band
  3313. */
  3314. int
  3315. il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
  3316. {
  3317. enum ieee80211_band band = ch->band;
  3318. u16 channel = ch->hw_value;
  3319. if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
  3320. return 0;
  3321. il->staging.channel = cpu_to_le16(channel);
  3322. if (band == IEEE80211_BAND_5GHZ)
  3323. il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  3324. else
  3325. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3326. il->band = band;
  3327. D_INFO("Staging channel set to %d [%d]\n", channel, band);
  3328. return 0;
  3329. }
  3330. EXPORT_SYMBOL(il_set_rxon_channel);
  3331. void
  3332. il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
  3333. struct ieee80211_vif *vif)
  3334. {
  3335. if (band == IEEE80211_BAND_5GHZ) {
  3336. il->staging.flags &=
  3337. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
  3338. RXON_FLG_CCK_MSK);
  3339. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3340. } else {
  3341. /* Copied from il_post_associate() */
  3342. if (vif && vif->bss_conf.use_short_slot)
  3343. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3344. else
  3345. il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  3346. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3347. il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  3348. il->staging.flags &= ~RXON_FLG_CCK_MSK;
  3349. }
  3350. }
  3351. EXPORT_SYMBOL(il_set_flags_for_band);
  3352. /*
  3353. * initialize rxon structure with default values from eeprom
  3354. */
  3355. void
  3356. il_connection_init_rx_config(struct il_priv *il)
  3357. {
  3358. const struct il_channel_info *ch_info;
  3359. memset(&il->staging, 0, sizeof(il->staging));
  3360. switch (il->iw_mode) {
  3361. case NL80211_IFTYPE_UNSPECIFIED:
  3362. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3363. break;
  3364. case NL80211_IFTYPE_STATION:
  3365. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3366. il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  3367. break;
  3368. case NL80211_IFTYPE_ADHOC:
  3369. il->staging.dev_type = RXON_DEV_TYPE_IBSS;
  3370. il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  3371. il->staging.filter_flags =
  3372. RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  3373. break;
  3374. default:
  3375. IL_ERR("Unsupported interface type %d\n", il->vif->type);
  3376. return;
  3377. }
  3378. #if 0
  3379. /* TODO: Figure out when short_preamble would be set and cache from
  3380. * that */
  3381. if (!hw_to_local(il->hw)->short_preamble)
  3382. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  3383. else
  3384. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  3385. #endif
  3386. ch_info =
  3387. il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
  3388. if (!ch_info)
  3389. ch_info = &il->channel_info[0];
  3390. il->staging.channel = cpu_to_le16(ch_info->channel);
  3391. il->band = ch_info->band;
  3392. il_set_flags_for_band(il, il->band, il->vif);
  3393. il->staging.ofdm_basic_rates =
  3394. (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3395. il->staging.cck_basic_rates =
  3396. (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3397. /* clear both MIX and PURE40 mode flag */
  3398. il->staging.flags &=
  3399. ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
  3400. if (il->vif)
  3401. memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
  3402. il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  3403. il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  3404. }
  3405. EXPORT_SYMBOL(il_connection_init_rx_config);
  3406. void
  3407. il_set_rate(struct il_priv *il)
  3408. {
  3409. const struct ieee80211_supported_band *hw = NULL;
  3410. struct ieee80211_rate *rate;
  3411. int i;
  3412. hw = il_get_hw_mode(il, il->band);
  3413. if (!hw) {
  3414. IL_ERR("Failed to set rate: unable to get hw mode\n");
  3415. return;
  3416. }
  3417. il->active_rate = 0;
  3418. for (i = 0; i < hw->n_bitrates; i++) {
  3419. rate = &(hw->bitrates[i]);
  3420. if (rate->hw_value < RATE_COUNT_LEGACY)
  3421. il->active_rate |= (1 << rate->hw_value);
  3422. }
  3423. D_RATE("Set active_rate = %0x\n", il->active_rate);
  3424. il->staging.cck_basic_rates =
  3425. (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3426. il->staging.ofdm_basic_rates =
  3427. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3428. }
  3429. EXPORT_SYMBOL(il_set_rate);
  3430. void
  3431. il_chswitch_done(struct il_priv *il, bool is_success)
  3432. {
  3433. if (test_bit(S_EXIT_PENDING, &il->status))
  3434. return;
  3435. if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3436. ieee80211_chswitch_done(il->vif, is_success);
  3437. }
  3438. EXPORT_SYMBOL(il_chswitch_done);
  3439. void
  3440. il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
  3441. {
  3442. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3443. struct il_csa_notification *csa = &(pkt->u.csa_notif);
  3444. struct il_rxon_cmd *rxon = (void *)&il->active;
  3445. if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3446. return;
  3447. if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
  3448. rxon->channel = csa->channel;
  3449. il->staging.channel = csa->channel;
  3450. D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
  3451. il_chswitch_done(il, true);
  3452. } else {
  3453. IL_ERR("CSA notif (fail) : channel %d\n",
  3454. le16_to_cpu(csa->channel));
  3455. il_chswitch_done(il, false);
  3456. }
  3457. }
  3458. EXPORT_SYMBOL(il_hdl_csa);
  3459. #ifdef CONFIG_IWLEGACY_DEBUG
  3460. void
  3461. il_print_rx_config_cmd(struct il_priv *il)
  3462. {
  3463. struct il_rxon_cmd *rxon = &il->staging;
  3464. D_RADIO("RX CONFIG:\n");
  3465. il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3466. D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3467. D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3468. D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
  3469. D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3470. D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
  3471. D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3472. D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3473. D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3474. D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3475. }
  3476. EXPORT_SYMBOL(il_print_rx_config_cmd);
  3477. #endif
  3478. /**
  3479. * il_irq_handle_error - called for HW or SW error interrupt from card
  3480. */
  3481. void
  3482. il_irq_handle_error(struct il_priv *il)
  3483. {
  3484. /* Set the FW error flag -- cleared on il_down */
  3485. set_bit(S_FW_ERROR, &il->status);
  3486. /* Cancel currently queued command. */
  3487. clear_bit(S_HCMD_ACTIVE, &il->status);
  3488. IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
  3489. il->ops->dump_nic_error_log(il);
  3490. if (il->ops->dump_fh)
  3491. il->ops->dump_fh(il, NULL, false);
  3492. #ifdef CONFIG_IWLEGACY_DEBUG
  3493. if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
  3494. il_print_rx_config_cmd(il);
  3495. #endif
  3496. wake_up(&il->wait_command_queue);
  3497. /* Keep the restart process from trying to send host
  3498. * commands by clearing the INIT status bit */
  3499. clear_bit(S_READY, &il->status);
  3500. if (!test_bit(S_EXIT_PENDING, &il->status)) {
  3501. IL_DBG(IL_DL_FW_ERRORS,
  3502. "Restarting adapter due to uCode error.\n");
  3503. if (il->cfg->mod_params->restart_fw)
  3504. queue_work(il->workqueue, &il->restart);
  3505. }
  3506. }
  3507. EXPORT_SYMBOL(il_irq_handle_error);
  3508. static int
  3509. _il_apm_stop_master(struct il_priv *il)
  3510. {
  3511. int ret = 0;
  3512. /* stop device's busmaster DMA activity */
  3513. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  3514. ret =
  3515. _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  3516. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  3517. if (ret < 0)
  3518. IL_WARN("Master Disable Timed Out, 100 usec\n");
  3519. D_INFO("stop master\n");
  3520. return ret;
  3521. }
  3522. void
  3523. _il_apm_stop(struct il_priv *il)
  3524. {
  3525. lockdep_assert_held(&il->reg_lock);
  3526. D_INFO("Stop card, put in low power state\n");
  3527. /* Stop device's DMA activity */
  3528. _il_apm_stop_master(il);
  3529. /* Reset the entire device */
  3530. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  3531. udelay(10);
  3532. /*
  3533. * Clear "initialization complete" bit to move adapter from
  3534. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  3535. */
  3536. _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3537. }
  3538. EXPORT_SYMBOL(_il_apm_stop);
  3539. void
  3540. il_apm_stop(struct il_priv *il)
  3541. {
  3542. unsigned long flags;
  3543. spin_lock_irqsave(&il->reg_lock, flags);
  3544. _il_apm_stop(il);
  3545. spin_unlock_irqrestore(&il->reg_lock, flags);
  3546. }
  3547. EXPORT_SYMBOL(il_apm_stop);
  3548. /*
  3549. * Start up NIC's basic functionality after it has been reset
  3550. * (e.g. after platform boot, or shutdown via il_apm_stop())
  3551. * NOTE: This does not load uCode nor start the embedded processor
  3552. */
  3553. int
  3554. il_apm_init(struct il_priv *il)
  3555. {
  3556. int ret = 0;
  3557. u16 lctl;
  3558. D_INFO("Init card's basic functions\n");
  3559. /*
  3560. * Use "set_bit" below rather than "write", to preserve any hardware
  3561. * bits already set by default after reset.
  3562. */
  3563. /* Disable L0S exit timer (platform NMI Work/Around) */
  3564. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3565. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  3566. /*
  3567. * Disable L0s without affecting L1;
  3568. * don't wait for ICH L0s (ICH bug W/A)
  3569. */
  3570. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3571. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  3572. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  3573. il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  3574. /*
  3575. * Enable HAP INTA (interrupt from management bus) to
  3576. * wake device's PCI Express link L1a -> L0s
  3577. * NOTE: This is no-op for 3945 (non-existent bit)
  3578. */
  3579. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  3580. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  3581. /*
  3582. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  3583. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  3584. * If so (likely), disable L0S, so device moves directly L0->L1;
  3585. * costs negligible amount of power savings.
  3586. * If not (unlikely), enable L0S, so there is at least some
  3587. * power savings, even without L1.
  3588. */
  3589. if (il->cfg->set_l0s) {
  3590. pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  3591. if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
  3592. /* L1-ASPM enabled; disable(!) L0S */
  3593. il_set_bit(il, CSR_GIO_REG,
  3594. CSR_GIO_REG_VAL_L0S_ENABLED);
  3595. D_POWER("L1 Enabled; Disabling L0S\n");
  3596. } else {
  3597. /* L1-ASPM disabled; enable(!) L0S */
  3598. il_clear_bit(il, CSR_GIO_REG,
  3599. CSR_GIO_REG_VAL_L0S_ENABLED);
  3600. D_POWER("L1 Disabled; Enabling L0S\n");
  3601. }
  3602. }
  3603. /* Configure analog phase-lock-loop before activating to D0A */
  3604. if (il->cfg->pll_cfg_val)
  3605. il_set_bit(il, CSR_ANA_PLL_CFG,
  3606. il->cfg->pll_cfg_val);
  3607. /*
  3608. * Set "initialization complete" bit to move adapter from
  3609. * D0U* --> D0A* (powered-up active) state.
  3610. */
  3611. il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3612. /*
  3613. * Wait for clock stabilization; once stabilized, access to
  3614. * device-internal resources is supported, e.g. il_wr_prph()
  3615. * and accesses to uCode SRAM.
  3616. */
  3617. ret =
  3618. _il_poll_bit(il, CSR_GP_CNTRL,
  3619. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  3620. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  3621. if (ret < 0) {
  3622. D_INFO("Failed to init the card\n");
  3623. goto out;
  3624. }
  3625. /*
  3626. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  3627. * BSM (Boostrap State Machine) is only in 3945 and 4965.
  3628. *
  3629. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  3630. * do not disable clocks. This preserves any hardware bits already
  3631. * set by default in "CLK_CTRL_REG" after reset.
  3632. */
  3633. if (il->cfg->use_bsm)
  3634. il_wr_prph(il, APMG_CLK_EN_REG,
  3635. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  3636. else
  3637. il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  3638. udelay(20);
  3639. /* Disable L1-Active */
  3640. il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
  3641. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  3642. out:
  3643. return ret;
  3644. }
  3645. EXPORT_SYMBOL(il_apm_init);
  3646. int
  3647. il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
  3648. {
  3649. int ret;
  3650. s8 prev_tx_power;
  3651. bool defer;
  3652. lockdep_assert_held(&il->mutex);
  3653. if (il->tx_power_user_lmt == tx_power && !force)
  3654. return 0;
  3655. if (!il->ops->send_tx_power)
  3656. return -EOPNOTSUPP;
  3657. /* 0 dBm mean 1 milliwatt */
  3658. if (tx_power < 0) {
  3659. IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
  3660. return -EINVAL;
  3661. }
  3662. if (tx_power > il->tx_power_device_lmt) {
  3663. IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
  3664. tx_power, il->tx_power_device_lmt);
  3665. return -EINVAL;
  3666. }
  3667. if (!il_is_ready_rf(il))
  3668. return -EIO;
  3669. /* scan complete and commit_rxon use tx_power_next value,
  3670. * it always need to be updated for newest request */
  3671. il->tx_power_next = tx_power;
  3672. /* do not set tx power when scanning or channel changing */
  3673. defer = test_bit(S_SCANNING, &il->status) ||
  3674. memcmp(&il->active, &il->staging, sizeof(il->staging));
  3675. if (defer && !force) {
  3676. D_INFO("Deferring tx power set\n");
  3677. return 0;
  3678. }
  3679. prev_tx_power = il->tx_power_user_lmt;
  3680. il->tx_power_user_lmt = tx_power;
  3681. ret = il->ops->send_tx_power(il);
  3682. /* if fail to set tx_power, restore the orig. tx power */
  3683. if (ret) {
  3684. il->tx_power_user_lmt = prev_tx_power;
  3685. il->tx_power_next = prev_tx_power;
  3686. }
  3687. return ret;
  3688. }
  3689. EXPORT_SYMBOL(il_set_tx_power);
  3690. void
  3691. il_send_bt_config(struct il_priv *il)
  3692. {
  3693. struct il_bt_cmd bt_cmd = {
  3694. .lead_time = BT_LEAD_TIME_DEF,
  3695. .max_kill = BT_MAX_KILL_DEF,
  3696. .kill_ack_mask = 0,
  3697. .kill_cts_mask = 0,
  3698. };
  3699. if (!bt_coex_active)
  3700. bt_cmd.flags = BT_COEX_DISABLE;
  3701. else
  3702. bt_cmd.flags = BT_COEX_ENABLE;
  3703. D_INFO("BT coex %s\n",
  3704. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  3705. if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
  3706. IL_ERR("failed to send BT Coex Config\n");
  3707. }
  3708. EXPORT_SYMBOL(il_send_bt_config);
  3709. int
  3710. il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
  3711. {
  3712. struct il_stats_cmd stats_cmd = {
  3713. .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
  3714. };
  3715. if (flags & CMD_ASYNC)
  3716. return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
  3717. &stats_cmd, NULL);
  3718. else
  3719. return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
  3720. &stats_cmd);
  3721. }
  3722. EXPORT_SYMBOL(il_send_stats_request);
  3723. void
  3724. il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
  3725. {
  3726. #ifdef CONFIG_IWLEGACY_DEBUG
  3727. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3728. struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3729. D_RX("sleep mode: %d, src: %d\n",
  3730. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3731. #endif
  3732. }
  3733. EXPORT_SYMBOL(il_hdl_pm_sleep);
  3734. void
  3735. il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
  3736. {
  3737. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3738. u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
  3739. D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
  3740. il_get_cmd_string(pkt->hdr.cmd));
  3741. il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
  3742. }
  3743. EXPORT_SYMBOL(il_hdl_pm_debug_stats);
  3744. void
  3745. il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
  3746. {
  3747. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3748. IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3749. "seq 0x%04X ser 0x%08X\n",
  3750. le32_to_cpu(pkt->u.err_resp.error_type),
  3751. il_get_cmd_string(pkt->u.err_resp.cmd_id),
  3752. pkt->u.err_resp.cmd_id,
  3753. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3754. le32_to_cpu(pkt->u.err_resp.error_info));
  3755. }
  3756. EXPORT_SYMBOL(il_hdl_error);
  3757. void
  3758. il_clear_isr_stats(struct il_priv *il)
  3759. {
  3760. memset(&il->isr_stats, 0, sizeof(il->isr_stats));
  3761. }
  3762. int
  3763. il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
  3764. const struct ieee80211_tx_queue_params *params)
  3765. {
  3766. struct il_priv *il = hw->priv;
  3767. unsigned long flags;
  3768. int q;
  3769. D_MAC80211("enter\n");
  3770. if (!il_is_ready_rf(il)) {
  3771. D_MAC80211("leave - RF not ready\n");
  3772. return -EIO;
  3773. }
  3774. if (queue >= AC_NUM) {
  3775. D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  3776. return 0;
  3777. }
  3778. q = AC_NUM - 1 - queue;
  3779. spin_lock_irqsave(&il->lock, flags);
  3780. il->qos_data.def_qos_parm.ac[q].cw_min =
  3781. cpu_to_le16(params->cw_min);
  3782. il->qos_data.def_qos_parm.ac[q].cw_max =
  3783. cpu_to_le16(params->cw_max);
  3784. il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  3785. il->qos_data.def_qos_parm.ac[q].edca_txop =
  3786. cpu_to_le16((params->txop * 32));
  3787. il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  3788. spin_unlock_irqrestore(&il->lock, flags);
  3789. D_MAC80211("leave\n");
  3790. return 0;
  3791. }
  3792. EXPORT_SYMBOL(il_mac_conf_tx);
  3793. int
  3794. il_mac_tx_last_beacon(struct ieee80211_hw *hw)
  3795. {
  3796. struct il_priv *il = hw->priv;
  3797. int ret;
  3798. D_MAC80211("enter\n");
  3799. ret = (il->ibss_manager == IL_IBSS_MANAGER);
  3800. D_MAC80211("leave ret %d\n", ret);
  3801. return ret;
  3802. }
  3803. EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
  3804. static int
  3805. il_set_mode(struct il_priv *il)
  3806. {
  3807. il_connection_init_rx_config(il);
  3808. if (il->ops->set_rxon_chain)
  3809. il->ops->set_rxon_chain(il);
  3810. return il_commit_rxon(il);
  3811. }
  3812. int
  3813. il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3814. {
  3815. struct il_priv *il = hw->priv;
  3816. int err;
  3817. bool reset;
  3818. mutex_lock(&il->mutex);
  3819. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3820. if (!il_is_ready_rf(il)) {
  3821. IL_WARN("Try to add interface when device not ready\n");
  3822. err = -EINVAL;
  3823. goto out;
  3824. }
  3825. /*
  3826. * We do not support multiple virtual interfaces, but on hardware reset
  3827. * we have to add the same interface again.
  3828. */
  3829. reset = (il->vif == vif);
  3830. if (il->vif && !reset) {
  3831. err = -EOPNOTSUPP;
  3832. goto out;
  3833. }
  3834. il->vif = vif;
  3835. il->iw_mode = vif->type;
  3836. err = il_set_mode(il);
  3837. if (err) {
  3838. IL_WARN("Fail to set mode %d\n", vif->type);
  3839. if (!reset) {
  3840. il->vif = NULL;
  3841. il->iw_mode = NL80211_IFTYPE_STATION;
  3842. }
  3843. }
  3844. out:
  3845. D_MAC80211("leave err %d\n", err);
  3846. mutex_unlock(&il->mutex);
  3847. return err;
  3848. }
  3849. EXPORT_SYMBOL(il_mac_add_interface);
  3850. static void
  3851. il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif)
  3852. {
  3853. lockdep_assert_held(&il->mutex);
  3854. if (il->scan_vif == vif) {
  3855. il_scan_cancel_timeout(il, 200);
  3856. il_force_scan_end(il);
  3857. }
  3858. il_set_mode(il);
  3859. }
  3860. void
  3861. il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3862. {
  3863. struct il_priv *il = hw->priv;
  3864. mutex_lock(&il->mutex);
  3865. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3866. WARN_ON(il->vif != vif);
  3867. il->vif = NULL;
  3868. il->iw_mode = NL80211_IFTYPE_UNSPECIFIED;
  3869. il_teardown_interface(il, vif);
  3870. memset(il->bssid, 0, ETH_ALEN);
  3871. D_MAC80211("leave\n");
  3872. mutex_unlock(&il->mutex);
  3873. }
  3874. EXPORT_SYMBOL(il_mac_remove_interface);
  3875. int
  3876. il_alloc_txq_mem(struct il_priv *il)
  3877. {
  3878. if (!il->txq)
  3879. il->txq =
  3880. kzalloc(sizeof(struct il_tx_queue) *
  3881. il->cfg->num_of_queues, GFP_KERNEL);
  3882. if (!il->txq) {
  3883. IL_ERR("Not enough memory for txq\n");
  3884. return -ENOMEM;
  3885. }
  3886. return 0;
  3887. }
  3888. EXPORT_SYMBOL(il_alloc_txq_mem);
  3889. void
  3890. il_free_txq_mem(struct il_priv *il)
  3891. {
  3892. kfree(il->txq);
  3893. il->txq = NULL;
  3894. }
  3895. EXPORT_SYMBOL(il_free_txq_mem);
  3896. int
  3897. il_force_reset(struct il_priv *il, bool external)
  3898. {
  3899. struct il_force_reset *force_reset;
  3900. if (test_bit(S_EXIT_PENDING, &il->status))
  3901. return -EINVAL;
  3902. force_reset = &il->force_reset;
  3903. force_reset->reset_request_count++;
  3904. if (!external) {
  3905. if (force_reset->last_force_reset_jiffies &&
  3906. time_after(force_reset->last_force_reset_jiffies +
  3907. force_reset->reset_duration, jiffies)) {
  3908. D_INFO("force reset rejected\n");
  3909. force_reset->reset_reject_count++;
  3910. return -EAGAIN;
  3911. }
  3912. }
  3913. force_reset->reset_success_count++;
  3914. force_reset->last_force_reset_jiffies = jiffies;
  3915. /*
  3916. * if the request is from external(ex: debugfs),
  3917. * then always perform the request in regardless the module
  3918. * parameter setting
  3919. * if the request is from internal (uCode error or driver
  3920. * detect failure), then fw_restart module parameter
  3921. * need to be check before performing firmware reload
  3922. */
  3923. if (!external && !il->cfg->mod_params->restart_fw) {
  3924. D_INFO("Cancel firmware reload based on "
  3925. "module parameter setting\n");
  3926. return 0;
  3927. }
  3928. IL_ERR("On demand firmware reload\n");
  3929. /* Set the FW error flag -- cleared on il_down */
  3930. set_bit(S_FW_ERROR, &il->status);
  3931. wake_up(&il->wait_command_queue);
  3932. /*
  3933. * Keep the restart process from trying to send host
  3934. * commands by clearing the INIT status bit
  3935. */
  3936. clear_bit(S_READY, &il->status);
  3937. queue_work(il->workqueue, &il->restart);
  3938. return 0;
  3939. }
  3940. int
  3941. il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  3942. enum nl80211_iftype newtype, bool newp2p)
  3943. {
  3944. struct il_priv *il = hw->priv;
  3945. int err;
  3946. mutex_lock(&il->mutex);
  3947. D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
  3948. vif->type, vif->addr, newtype, newp2p);
  3949. if (newp2p) {
  3950. err = -EOPNOTSUPP;
  3951. goto out;
  3952. }
  3953. if (!il->vif || !il_is_ready_rf(il)) {
  3954. /*
  3955. * Huh? But wait ... this can maybe happen when
  3956. * we're in the middle of a firmware restart!
  3957. */
  3958. err = -EBUSY;
  3959. goto out;
  3960. }
  3961. /* success */
  3962. vif->type = newtype;
  3963. vif->p2p = false;
  3964. il->iw_mode = newtype;
  3965. il_teardown_interface(il, vif);
  3966. err = 0;
  3967. out:
  3968. D_MAC80211("leave err %d\n", err);
  3969. mutex_unlock(&il->mutex);
  3970. return err;
  3971. }
  3972. EXPORT_SYMBOL(il_mac_change_interface);
  3973. void
  3974. il_mac_flush(struct ieee80211_hw *hw, bool drop)
  3975. {
  3976. struct il_priv *il = hw->priv;
  3977. unsigned long timeout = jiffies + msecs_to_jiffies(500);
  3978. int i;
  3979. mutex_lock(&il->mutex);
  3980. D_MAC80211("enter\n");
  3981. if (il->txq == NULL)
  3982. goto out;
  3983. for (i = 0; i < il->hw_params.max_txq_num; i++) {
  3984. struct il_queue *q;
  3985. if (i == il->cmd_queue)
  3986. continue;
  3987. q = &il->txq[i].q;
  3988. if (q->read_ptr == q->write_ptr)
  3989. continue;
  3990. if (time_after(jiffies, timeout)) {
  3991. IL_ERR("Failed to flush queue %d\n", q->id);
  3992. break;
  3993. }
  3994. msleep(20);
  3995. }
  3996. out:
  3997. D_MAC80211("leave\n");
  3998. mutex_unlock(&il->mutex);
  3999. }
  4000. EXPORT_SYMBOL(il_mac_flush);
  4001. /*
  4002. * On every watchdog tick we check (latest) time stamp. If it does not
  4003. * change during timeout period and queue is not empty we reset firmware.
  4004. */
  4005. static int
  4006. il_check_stuck_queue(struct il_priv *il, int cnt)
  4007. {
  4008. struct il_tx_queue *txq = &il->txq[cnt];
  4009. struct il_queue *q = &txq->q;
  4010. unsigned long timeout;
  4011. unsigned long now = jiffies;
  4012. int ret;
  4013. if (q->read_ptr == q->write_ptr) {
  4014. txq->time_stamp = now;
  4015. return 0;
  4016. }
  4017. timeout =
  4018. txq->time_stamp +
  4019. msecs_to_jiffies(il->cfg->wd_timeout);
  4020. if (time_after(now, timeout)) {
  4021. IL_ERR("Queue %d stuck for %u ms.\n", q->id,
  4022. jiffies_to_msecs(now - txq->time_stamp));
  4023. ret = il_force_reset(il, false);
  4024. return (ret == -EAGAIN) ? 0 : 1;
  4025. }
  4026. return 0;
  4027. }
  4028. /*
  4029. * Making watchdog tick be a quarter of timeout assure we will
  4030. * discover the queue hung between timeout and 1.25*timeout
  4031. */
  4032. #define IL_WD_TICK(timeout) ((timeout) / 4)
  4033. /*
  4034. * Watchdog timer callback, we check each tx queue for stuck, if if hung
  4035. * we reset the firmware. If everything is fine just rearm the timer.
  4036. */
  4037. void
  4038. il_bg_watchdog(unsigned long data)
  4039. {
  4040. struct il_priv *il = (struct il_priv *)data;
  4041. int cnt;
  4042. unsigned long timeout;
  4043. if (test_bit(S_EXIT_PENDING, &il->status))
  4044. return;
  4045. timeout = il->cfg->wd_timeout;
  4046. if (timeout == 0)
  4047. return;
  4048. /* monitor and check for stuck cmd queue */
  4049. if (il_check_stuck_queue(il, il->cmd_queue))
  4050. return;
  4051. /* monitor and check for other stuck queues */
  4052. for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
  4053. /* skip as we already checked the command queue */
  4054. if (cnt == il->cmd_queue)
  4055. continue;
  4056. if (il_check_stuck_queue(il, cnt))
  4057. return;
  4058. }
  4059. mod_timer(&il->watchdog,
  4060. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4061. }
  4062. EXPORT_SYMBOL(il_bg_watchdog);
  4063. void
  4064. il_setup_watchdog(struct il_priv *il)
  4065. {
  4066. unsigned int timeout = il->cfg->wd_timeout;
  4067. if (timeout)
  4068. mod_timer(&il->watchdog,
  4069. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4070. else
  4071. del_timer(&il->watchdog);
  4072. }
  4073. EXPORT_SYMBOL(il_setup_watchdog);
  4074. /*
  4075. * extended beacon time format
  4076. * time in usec will be changed into a 32-bit value in extended:internal format
  4077. * the extended part is the beacon counts
  4078. * the internal part is the time in usec within one beacon interval
  4079. */
  4080. u32
  4081. il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
  4082. {
  4083. u32 quot;
  4084. u32 rem;
  4085. u32 interval = beacon_interval * TIME_UNIT;
  4086. if (!interval || !usec)
  4087. return 0;
  4088. quot =
  4089. (usec /
  4090. interval) & (il_beacon_time_mask_high(il,
  4091. il->hw_params.
  4092. beacon_time_tsf_bits) >> il->
  4093. hw_params.beacon_time_tsf_bits);
  4094. rem =
  4095. (usec % interval) & il_beacon_time_mask_low(il,
  4096. il->hw_params.
  4097. beacon_time_tsf_bits);
  4098. return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
  4099. }
  4100. EXPORT_SYMBOL(il_usecs_to_beacons);
  4101. /* base is usually what we get from ucode with each received frame,
  4102. * the same as HW timer counter counting down
  4103. */
  4104. __le32
  4105. il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
  4106. u32 beacon_interval)
  4107. {
  4108. u32 base_low = base & il_beacon_time_mask_low(il,
  4109. il->hw_params.
  4110. beacon_time_tsf_bits);
  4111. u32 addon_low = addon & il_beacon_time_mask_low(il,
  4112. il->hw_params.
  4113. beacon_time_tsf_bits);
  4114. u32 interval = beacon_interval * TIME_UNIT;
  4115. u32 res = (base & il_beacon_time_mask_high(il,
  4116. il->hw_params.
  4117. beacon_time_tsf_bits)) +
  4118. (addon & il_beacon_time_mask_high(il,
  4119. il->hw_params.
  4120. beacon_time_tsf_bits));
  4121. if (base_low > addon_low)
  4122. res += base_low - addon_low;
  4123. else if (base_low < addon_low) {
  4124. res += interval + base_low - addon_low;
  4125. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4126. } else
  4127. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4128. return cpu_to_le32(res);
  4129. }
  4130. EXPORT_SYMBOL(il_add_beacon_time);
  4131. #ifdef CONFIG_PM
  4132. static int
  4133. il_pci_suspend(struct device *device)
  4134. {
  4135. struct pci_dev *pdev = to_pci_dev(device);
  4136. struct il_priv *il = pci_get_drvdata(pdev);
  4137. /*
  4138. * This function is called when system goes into suspend state
  4139. * mac80211 will call il_mac_stop() from the mac80211 suspend function
  4140. * first but since il_mac_stop() has no knowledge of who the caller is,
  4141. * it will not call apm_ops.stop() to stop the DMA operation.
  4142. * Calling apm_ops.stop here to make sure we stop the DMA.
  4143. */
  4144. il_apm_stop(il);
  4145. return 0;
  4146. }
  4147. static int
  4148. il_pci_resume(struct device *device)
  4149. {
  4150. struct pci_dev *pdev = to_pci_dev(device);
  4151. struct il_priv *il = pci_get_drvdata(pdev);
  4152. bool hw_rfkill = false;
  4153. /*
  4154. * We disable the RETRY_TIMEOUT register (0x41) to keep
  4155. * PCI Tx retries from interfering with C3 CPU state.
  4156. */
  4157. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  4158. il_enable_interrupts(il);
  4159. if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4160. hw_rfkill = true;
  4161. if (hw_rfkill)
  4162. set_bit(S_RFKILL, &il->status);
  4163. else
  4164. clear_bit(S_RFKILL, &il->status);
  4165. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
  4166. return 0;
  4167. }
  4168. SIMPLE_DEV_PM_OPS(il_pm_ops, il_pci_suspend, il_pci_resume);
  4169. EXPORT_SYMBOL(il_pm_ops);
  4170. #endif /* CONFIG_PM */
  4171. static void
  4172. il_update_qos(struct il_priv *il)
  4173. {
  4174. if (test_bit(S_EXIT_PENDING, &il->status))
  4175. return;
  4176. il->qos_data.def_qos_parm.qos_flags = 0;
  4177. if (il->qos_data.qos_active)
  4178. il->qos_data.def_qos_parm.qos_flags |=
  4179. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  4180. if (il->ht.enabled)
  4181. il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  4182. D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  4183. il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
  4184. il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
  4185. &il->qos_data.def_qos_parm, NULL);
  4186. }
  4187. /**
  4188. * il_mac_config - mac80211 config callback
  4189. */
  4190. int
  4191. il_mac_config(struct ieee80211_hw *hw, u32 changed)
  4192. {
  4193. struct il_priv *il = hw->priv;
  4194. const struct il_channel_info *ch_info;
  4195. struct ieee80211_conf *conf = &hw->conf;
  4196. struct ieee80211_channel *channel = conf->channel;
  4197. struct il_ht_config *ht_conf = &il->current_ht_config;
  4198. unsigned long flags = 0;
  4199. int ret = 0;
  4200. u16 ch;
  4201. int scan_active = 0;
  4202. bool ht_changed = false;
  4203. mutex_lock(&il->mutex);
  4204. D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
  4205. changed);
  4206. if (unlikely(test_bit(S_SCANNING, &il->status))) {
  4207. scan_active = 1;
  4208. D_MAC80211("scan active\n");
  4209. }
  4210. if (changed &
  4211. (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
  4212. /* mac80211 uses static for non-HT which is what we want */
  4213. il->current_ht_config.smps = conf->smps_mode;
  4214. /*
  4215. * Recalculate chain counts.
  4216. *
  4217. * If monitor mode is enabled then mac80211 will
  4218. * set up the SM PS mode to OFF if an HT channel is
  4219. * configured.
  4220. */
  4221. if (il->ops->set_rxon_chain)
  4222. il->ops->set_rxon_chain(il);
  4223. }
  4224. /* during scanning mac80211 will delay channel setting until
  4225. * scan finish with changed = 0
  4226. */
  4227. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  4228. if (scan_active)
  4229. goto set_ch_out;
  4230. ch = channel->hw_value;
  4231. ch_info = il_get_channel_info(il, channel->band, ch);
  4232. if (!il_is_channel_valid(ch_info)) {
  4233. D_MAC80211("leave - invalid channel\n");
  4234. ret = -EINVAL;
  4235. goto set_ch_out;
  4236. }
  4237. if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
  4238. !il_is_channel_ibss(ch_info)) {
  4239. D_MAC80211("leave - not IBSS channel\n");
  4240. ret = -EINVAL;
  4241. goto set_ch_out;
  4242. }
  4243. spin_lock_irqsave(&il->lock, flags);
  4244. /* Configure HT40 channels */
  4245. if (il->ht.enabled != conf_is_ht(conf)) {
  4246. il->ht.enabled = conf_is_ht(conf);
  4247. ht_changed = true;
  4248. }
  4249. if (il->ht.enabled) {
  4250. if (conf_is_ht40_minus(conf)) {
  4251. il->ht.extension_chan_offset =
  4252. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  4253. il->ht.is_40mhz = true;
  4254. } else if (conf_is_ht40_plus(conf)) {
  4255. il->ht.extension_chan_offset =
  4256. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  4257. il->ht.is_40mhz = true;
  4258. } else {
  4259. il->ht.extension_chan_offset =
  4260. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  4261. il->ht.is_40mhz = false;
  4262. }
  4263. } else
  4264. il->ht.is_40mhz = false;
  4265. /*
  4266. * Default to no protection. Protection mode will
  4267. * later be set from BSS config in il_ht_conf
  4268. */
  4269. il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  4270. /* if we are switching from ht to 2.4 clear flags
  4271. * from any ht related info since 2.4 does not
  4272. * support ht */
  4273. if ((le16_to_cpu(il->staging.channel) != ch))
  4274. il->staging.flags = 0;
  4275. il_set_rxon_channel(il, channel);
  4276. il_set_rxon_ht(il, ht_conf);
  4277. il_set_flags_for_band(il, channel->band, il->vif);
  4278. spin_unlock_irqrestore(&il->lock, flags);
  4279. if (il->ops->update_bcast_stations)
  4280. ret = il->ops->update_bcast_stations(il);
  4281. set_ch_out:
  4282. /* The list of supported rates and rate mask can be different
  4283. * for each band; since the band may have changed, reset
  4284. * the rate mask to what mac80211 lists */
  4285. il_set_rate(il);
  4286. }
  4287. if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
  4288. ret = il_power_update_mode(il, false);
  4289. if (ret)
  4290. D_MAC80211("Error setting sleep level\n");
  4291. }
  4292. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  4293. D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
  4294. conf->power_level);
  4295. il_set_tx_power(il, conf->power_level, false);
  4296. }
  4297. if (!il_is_ready(il)) {
  4298. D_MAC80211("leave - not ready\n");
  4299. goto out;
  4300. }
  4301. if (scan_active)
  4302. goto out;
  4303. if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
  4304. il_commit_rxon(il);
  4305. else
  4306. D_INFO("Not re-sending same RXON configuration.\n");
  4307. if (ht_changed)
  4308. il_update_qos(il);
  4309. out:
  4310. D_MAC80211("leave ret %d\n", ret);
  4311. mutex_unlock(&il->mutex);
  4312. return ret;
  4313. }
  4314. EXPORT_SYMBOL(il_mac_config);
  4315. void
  4316. il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4317. {
  4318. struct il_priv *il = hw->priv;
  4319. unsigned long flags;
  4320. mutex_lock(&il->mutex);
  4321. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  4322. spin_lock_irqsave(&il->lock, flags);
  4323. memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
  4324. /* new association get rid of ibss beacon skb */
  4325. if (il->beacon_skb)
  4326. dev_kfree_skb(il->beacon_skb);
  4327. il->beacon_skb = NULL;
  4328. il->timestamp = 0;
  4329. spin_unlock_irqrestore(&il->lock, flags);
  4330. il_scan_cancel_timeout(il, 100);
  4331. if (!il_is_ready_rf(il)) {
  4332. D_MAC80211("leave - not ready\n");
  4333. mutex_unlock(&il->mutex);
  4334. return;
  4335. }
  4336. /* we are restarting association process */
  4337. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4338. il_commit_rxon(il);
  4339. il_set_rate(il);
  4340. D_MAC80211("leave\n");
  4341. mutex_unlock(&il->mutex);
  4342. }
  4343. EXPORT_SYMBOL(il_mac_reset_tsf);
  4344. static void
  4345. il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
  4346. {
  4347. struct il_ht_config *ht_conf = &il->current_ht_config;
  4348. struct ieee80211_sta *sta;
  4349. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  4350. D_ASSOC("enter:\n");
  4351. if (!il->ht.enabled)
  4352. return;
  4353. il->ht.protection =
  4354. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  4355. il->ht.non_gf_sta_present =
  4356. !!(bss_conf->
  4357. ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  4358. ht_conf->single_chain_sufficient = false;
  4359. switch (vif->type) {
  4360. case NL80211_IFTYPE_STATION:
  4361. rcu_read_lock();
  4362. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  4363. if (sta) {
  4364. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  4365. int maxstreams;
  4366. maxstreams =
  4367. (ht_cap->mcs.
  4368. tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  4369. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  4370. maxstreams += 1;
  4371. if (ht_cap->mcs.rx_mask[1] == 0 &&
  4372. ht_cap->mcs.rx_mask[2] == 0)
  4373. ht_conf->single_chain_sufficient = true;
  4374. if (maxstreams <= 1)
  4375. ht_conf->single_chain_sufficient = true;
  4376. } else {
  4377. /*
  4378. * If at all, this can only happen through a race
  4379. * when the AP disconnects us while we're still
  4380. * setting up the connection, in that case mac80211
  4381. * will soon tell us about that.
  4382. */
  4383. ht_conf->single_chain_sufficient = true;
  4384. }
  4385. rcu_read_unlock();
  4386. break;
  4387. case NL80211_IFTYPE_ADHOC:
  4388. ht_conf->single_chain_sufficient = true;
  4389. break;
  4390. default:
  4391. break;
  4392. }
  4393. D_ASSOC("leave\n");
  4394. }
  4395. static inline void
  4396. il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
  4397. {
  4398. /*
  4399. * inform the ucode that there is no longer an
  4400. * association and that no more packets should be
  4401. * sent
  4402. */
  4403. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4404. il->staging.assoc_id = 0;
  4405. il_commit_rxon(il);
  4406. }
  4407. static void
  4408. il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4409. {
  4410. struct il_priv *il = hw->priv;
  4411. unsigned long flags;
  4412. __le64 timestamp;
  4413. struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
  4414. if (!skb)
  4415. return;
  4416. D_MAC80211("enter\n");
  4417. lockdep_assert_held(&il->mutex);
  4418. if (!il->beacon_enabled) {
  4419. IL_ERR("update beacon with no beaconing enabled\n");
  4420. dev_kfree_skb(skb);
  4421. return;
  4422. }
  4423. spin_lock_irqsave(&il->lock, flags);
  4424. if (il->beacon_skb)
  4425. dev_kfree_skb(il->beacon_skb);
  4426. il->beacon_skb = skb;
  4427. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  4428. il->timestamp = le64_to_cpu(timestamp);
  4429. D_MAC80211("leave\n");
  4430. spin_unlock_irqrestore(&il->lock, flags);
  4431. if (!il_is_ready_rf(il)) {
  4432. D_MAC80211("leave - RF not ready\n");
  4433. return;
  4434. }
  4435. il->ops->post_associate(il);
  4436. }
  4437. void
  4438. il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4439. struct ieee80211_bss_conf *bss_conf, u32 changes)
  4440. {
  4441. struct il_priv *il = hw->priv;
  4442. int ret;
  4443. mutex_lock(&il->mutex);
  4444. D_MAC80211("enter: changes 0x%x\n", changes);
  4445. if (!il_is_alive(il)) {
  4446. D_MAC80211("leave - not alive\n");
  4447. mutex_unlock(&il->mutex);
  4448. return;
  4449. }
  4450. if (changes & BSS_CHANGED_QOS) {
  4451. unsigned long flags;
  4452. spin_lock_irqsave(&il->lock, flags);
  4453. il->qos_data.qos_active = bss_conf->qos;
  4454. il_update_qos(il);
  4455. spin_unlock_irqrestore(&il->lock, flags);
  4456. }
  4457. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4458. /* FIXME: can we remove beacon_enabled ? */
  4459. if (vif->bss_conf.enable_beacon)
  4460. il->beacon_enabled = true;
  4461. else
  4462. il->beacon_enabled = false;
  4463. }
  4464. if (changes & BSS_CHANGED_BSSID) {
  4465. D_MAC80211("BSSID %pM\n", bss_conf->bssid);
  4466. /*
  4467. * If there is currently a HW scan going on in the background,
  4468. * then we need to cancel it, otherwise sometimes we are not
  4469. * able to authenticate (FIXME: why ?)
  4470. */
  4471. if (il_scan_cancel_timeout(il, 100)) {
  4472. D_MAC80211("leave - scan abort failed\n");
  4473. mutex_unlock(&il->mutex);
  4474. return;
  4475. }
  4476. /* mac80211 only sets assoc when in STATION mode */
  4477. memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
  4478. /* FIXME: currently needed in a few places */
  4479. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4480. }
  4481. /*
  4482. * This needs to be after setting the BSSID in case
  4483. * mac80211 decides to do both changes at once because
  4484. * it will invoke post_associate.
  4485. */
  4486. if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
  4487. il_beacon_update(hw, vif);
  4488. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4489. D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
  4490. if (bss_conf->use_short_preamble)
  4491. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4492. else
  4493. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4494. }
  4495. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4496. D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  4497. if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
  4498. il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4499. else
  4500. il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4501. if (bss_conf->use_cts_prot)
  4502. il->staging.flags |= RXON_FLG_SELF_CTS_EN;
  4503. else
  4504. il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
  4505. }
  4506. if (changes & BSS_CHANGED_BASIC_RATES) {
  4507. /* XXX use this information
  4508. *
  4509. * To do that, remove code from il_set_rate() and put something
  4510. * like this here:
  4511. *
  4512. if (A-band)
  4513. il->staging.ofdm_basic_rates =
  4514. bss_conf->basic_rates;
  4515. else
  4516. il->staging.ofdm_basic_rates =
  4517. bss_conf->basic_rates >> 4;
  4518. il->staging.cck_basic_rates =
  4519. bss_conf->basic_rates & 0xF;
  4520. */
  4521. }
  4522. if (changes & BSS_CHANGED_HT) {
  4523. il_ht_conf(il, vif);
  4524. if (il->ops->set_rxon_chain)
  4525. il->ops->set_rxon_chain(il);
  4526. }
  4527. if (changes & BSS_CHANGED_ASSOC) {
  4528. D_MAC80211("ASSOC %d\n", bss_conf->assoc);
  4529. if (bss_conf->assoc) {
  4530. il->timestamp = bss_conf->sync_tsf;
  4531. if (!il_is_rfkill(il))
  4532. il->ops->post_associate(il);
  4533. } else
  4534. il_set_no_assoc(il, vif);
  4535. }
  4536. if (changes && il_is_associated(il) && bss_conf->aid) {
  4537. D_MAC80211("Changes (%#x) while associated\n", changes);
  4538. ret = il_send_rxon_assoc(il);
  4539. if (!ret) {
  4540. /* Sync active_rxon with latest change. */
  4541. memcpy((void *)&il->active, &il->staging,
  4542. sizeof(struct il_rxon_cmd));
  4543. }
  4544. }
  4545. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4546. if (vif->bss_conf.enable_beacon) {
  4547. memcpy(il->staging.bssid_addr, bss_conf->bssid,
  4548. ETH_ALEN);
  4549. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4550. il->ops->config_ap(il);
  4551. } else
  4552. il_set_no_assoc(il, vif);
  4553. }
  4554. if (changes & BSS_CHANGED_IBSS) {
  4555. ret = il->ops->manage_ibss_station(il, vif,
  4556. bss_conf->ibss_joined);
  4557. if (ret)
  4558. IL_ERR("failed to %s IBSS station %pM\n",
  4559. bss_conf->ibss_joined ? "add" : "remove",
  4560. bss_conf->bssid);
  4561. }
  4562. D_MAC80211("leave\n");
  4563. mutex_unlock(&il->mutex);
  4564. }
  4565. EXPORT_SYMBOL(il_mac_bss_info_changed);
  4566. irqreturn_t
  4567. il_isr(int irq, void *data)
  4568. {
  4569. struct il_priv *il = data;
  4570. u32 inta, inta_mask;
  4571. u32 inta_fh;
  4572. unsigned long flags;
  4573. if (!il)
  4574. return IRQ_NONE;
  4575. spin_lock_irqsave(&il->lock, flags);
  4576. /* Disable (but don't clear!) interrupts here to avoid
  4577. * back-to-back ISRs and sporadic interrupts from our NIC.
  4578. * If we have something to service, the tasklet will re-enable ints.
  4579. * If we *don't* have something, we'll re-enable before leaving here. */
  4580. inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
  4581. _il_wr(il, CSR_INT_MASK, 0x00000000);
  4582. /* Discover which interrupts are active/pending */
  4583. inta = _il_rd(il, CSR_INT);
  4584. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  4585. /* Ignore interrupt if there's nothing in NIC to service.
  4586. * This may be due to IRQ shared with another device,
  4587. * or due to sporadic interrupts thrown from our NIC. */
  4588. if (!inta && !inta_fh) {
  4589. D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4590. goto none;
  4591. }
  4592. if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
  4593. /* Hardware disappeared. It might have already raised
  4594. * an interrupt */
  4595. IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  4596. goto unplugged;
  4597. }
  4598. D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
  4599. inta_fh);
  4600. inta &= ~CSR_INT_BIT_SCD;
  4601. /* il_irq_tasklet() will service interrupts and re-enable them */
  4602. if (likely(inta || inta_fh))
  4603. tasklet_schedule(&il->irq_tasklet);
  4604. unplugged:
  4605. spin_unlock_irqrestore(&il->lock, flags);
  4606. return IRQ_HANDLED;
  4607. none:
  4608. /* re-enable interrupts here since we don't have anything to service. */
  4609. /* only Re-enable if disabled by irq */
  4610. if (test_bit(S_INT_ENABLED, &il->status))
  4611. il_enable_interrupts(il);
  4612. spin_unlock_irqrestore(&il->lock, flags);
  4613. return IRQ_NONE;
  4614. }
  4615. EXPORT_SYMBOL(il_isr);
  4616. /*
  4617. * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
  4618. * function.
  4619. */
  4620. void
  4621. il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
  4622. __le16 fc, __le32 *tx_flags)
  4623. {
  4624. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  4625. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  4626. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  4627. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4628. if (!ieee80211_is_mgmt(fc))
  4629. return;
  4630. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4631. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4632. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4633. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4634. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4635. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4636. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4637. break;
  4638. }
  4639. } else if (info->control.rates[0].
  4640. flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  4641. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4642. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4643. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4644. }
  4645. }
  4646. EXPORT_SYMBOL(il_tx_cmd_protection);