main.c 57 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_drain_all_txq(sc))
  168. ret = false;
  169. if (!ath_stoprecv(sc))
  170. ret = false;
  171. return ret;
  172. }
  173. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  174. {
  175. struct ath_hw *ah = sc->sc_ah;
  176. struct ath_common *common = ath9k_hw_common(ah);
  177. unsigned long flags;
  178. if (ath_startrecv(sc) != 0) {
  179. ath_err(common, "Unable to restart recv logic\n");
  180. return false;
  181. }
  182. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  183. sc->config.txpowlimit, &sc->curtxpow);
  184. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  185. ath9k_hw_set_interrupts(ah);
  186. ath9k_hw_enable_interrupts(ah);
  187. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  188. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  189. goto work;
  190. ath9k_set_beacon(sc);
  191. if (ah->opmode == NL80211_IFTYPE_STATION &&
  192. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  193. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  194. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  195. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  196. }
  197. work:
  198. ath_restart_work(sc);
  199. }
  200. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  201. ath_ant_comb_update(sc);
  202. ieee80211_wake_queues(sc->hw);
  203. return true;
  204. }
  205. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  206. {
  207. struct ath_hw *ah = sc->sc_ah;
  208. struct ath_common *common = ath9k_hw_common(ah);
  209. struct ath9k_hw_cal_data *caldata = NULL;
  210. bool fastcc = true;
  211. int r;
  212. __ath_cancel_work(sc);
  213. tasklet_disable(&sc->intr_tq);
  214. spin_lock_bh(&sc->sc_pcu_lock);
  215. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  216. fastcc = false;
  217. caldata = &sc->caldata;
  218. }
  219. if (!hchan) {
  220. fastcc = false;
  221. hchan = ah->curchan;
  222. }
  223. if (!ath_prepare_reset(sc))
  224. fastcc = false;
  225. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  226. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  227. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  228. if (r) {
  229. ath_err(common,
  230. "Unable to reset channel, reset status %d\n", r);
  231. goto out;
  232. }
  233. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  234. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  235. ath9k_mci_set_txpower(sc, true, false);
  236. if (!ath_complete_reset(sc, true))
  237. r = -EIO;
  238. out:
  239. spin_unlock_bh(&sc->sc_pcu_lock);
  240. tasklet_enable(&sc->intr_tq);
  241. return r;
  242. }
  243. /*
  244. * Set/change channels. If the channel is really being changed, it's done
  245. * by reseting the chip. To accomplish this we must first cleanup any pending
  246. * DMA, then restart stuff.
  247. */
  248. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  249. struct ath9k_channel *hchan)
  250. {
  251. int r;
  252. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  253. return -EIO;
  254. r = ath_reset_internal(sc, hchan);
  255. return r;
  256. }
  257. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  258. struct ieee80211_vif *vif)
  259. {
  260. struct ath_node *an;
  261. an = (struct ath_node *)sta->drv_priv;
  262. an->sc = sc;
  263. an->sta = sta;
  264. an->vif = vif;
  265. ath_tx_node_init(sc, an);
  266. if (sta->ht_cap.ht_supported) {
  267. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  268. sta->ht_cap.ampdu_factor);
  269. an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  270. }
  271. }
  272. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  273. {
  274. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  275. ath_tx_node_cleanup(sc, an);
  276. }
  277. void ath9k_tasklet(unsigned long data)
  278. {
  279. struct ath_softc *sc = (struct ath_softc *)data;
  280. struct ath_hw *ah = sc->sc_ah;
  281. struct ath_common *common = ath9k_hw_common(ah);
  282. enum ath_reset_type type;
  283. unsigned long flags;
  284. u32 status = sc->intrstatus;
  285. u32 rxmask;
  286. ath9k_ps_wakeup(sc);
  287. spin_lock(&sc->sc_pcu_lock);
  288. if ((status & ATH9K_INT_FATAL) ||
  289. (status & ATH9K_INT_BB_WATCHDOG)) {
  290. if (status & ATH9K_INT_FATAL)
  291. type = RESET_TYPE_FATAL_INT;
  292. else
  293. type = RESET_TYPE_BB_WATCHDOG;
  294. ath9k_queue_reset(sc, type);
  295. goto out;
  296. }
  297. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  298. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  299. /*
  300. * TSF sync does not look correct; remain awake to sync with
  301. * the next Beacon.
  302. */
  303. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  304. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  305. }
  306. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  307. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  308. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  309. ATH9K_INT_RXORN);
  310. else
  311. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  312. if (status & rxmask) {
  313. /* Check for high priority Rx first */
  314. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  315. (status & ATH9K_INT_RXHP))
  316. ath_rx_tasklet(sc, 0, true);
  317. ath_rx_tasklet(sc, 0, false);
  318. }
  319. if (status & ATH9K_INT_TX) {
  320. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  321. ath_tx_edma_tasklet(sc);
  322. else
  323. ath_tx_tasklet(sc);
  324. }
  325. ath9k_btcoex_handle_interrupt(sc, status);
  326. out:
  327. /* re-enable hardware interrupt */
  328. ath9k_hw_enable_interrupts(ah);
  329. spin_unlock(&sc->sc_pcu_lock);
  330. ath9k_ps_restore(sc);
  331. }
  332. irqreturn_t ath_isr(int irq, void *dev)
  333. {
  334. #define SCHED_INTR ( \
  335. ATH9K_INT_FATAL | \
  336. ATH9K_INT_BB_WATCHDOG | \
  337. ATH9K_INT_RXORN | \
  338. ATH9K_INT_RXEOL | \
  339. ATH9K_INT_RX | \
  340. ATH9K_INT_RXLP | \
  341. ATH9K_INT_RXHP | \
  342. ATH9K_INT_TX | \
  343. ATH9K_INT_BMISS | \
  344. ATH9K_INT_CST | \
  345. ATH9K_INT_TSFOOR | \
  346. ATH9K_INT_GENTIMER | \
  347. ATH9K_INT_MCI)
  348. struct ath_softc *sc = dev;
  349. struct ath_hw *ah = sc->sc_ah;
  350. struct ath_common *common = ath9k_hw_common(ah);
  351. enum ath9k_int status;
  352. bool sched = false;
  353. /*
  354. * The hardware is not ready/present, don't
  355. * touch anything. Note this can happen early
  356. * on if the IRQ is shared.
  357. */
  358. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  359. return IRQ_NONE;
  360. /* shared irq, not for us */
  361. if (!ath9k_hw_intrpend(ah))
  362. return IRQ_NONE;
  363. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  364. ath9k_hw_kill_interrupts(ah);
  365. return IRQ_HANDLED;
  366. }
  367. /*
  368. * Figure out the reason(s) for the interrupt. Note
  369. * that the hal returns a pseudo-ISR that may include
  370. * bits we haven't explicitly enabled so we mask the
  371. * value to insure we only process bits we requested.
  372. */
  373. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  374. status &= ah->imask; /* discard unasked-for bits */
  375. /*
  376. * If there are no status bits set, then this interrupt was not
  377. * for me (should have been caught above).
  378. */
  379. if (!status)
  380. return IRQ_NONE;
  381. /* Cache the status */
  382. sc->intrstatus = status;
  383. if (status & SCHED_INTR)
  384. sched = true;
  385. /*
  386. * If a FATAL or RXORN interrupt is received, we have to reset the
  387. * chip immediately.
  388. */
  389. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  390. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  391. goto chip_reset;
  392. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  393. (status & ATH9K_INT_BB_WATCHDOG)) {
  394. spin_lock(&common->cc_lock);
  395. ath_hw_cycle_counters_update(common);
  396. ar9003_hw_bb_watchdog_dbg_info(ah);
  397. spin_unlock(&common->cc_lock);
  398. goto chip_reset;
  399. }
  400. #ifdef CONFIG_PM_SLEEP
  401. if (status & ATH9K_INT_BMISS) {
  402. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  403. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  404. atomic_inc(&sc->wow_got_bmiss_intr);
  405. atomic_dec(&sc->wow_sleep_proc_intr);
  406. }
  407. }
  408. #endif
  409. if (status & ATH9K_INT_SWBA)
  410. tasklet_schedule(&sc->bcon_tasklet);
  411. if (status & ATH9K_INT_TXURN)
  412. ath9k_hw_updatetxtriglevel(ah, true);
  413. if (status & ATH9K_INT_RXEOL) {
  414. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  415. ath9k_hw_set_interrupts(ah);
  416. }
  417. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  418. if (status & ATH9K_INT_TIM_TIMER) {
  419. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  420. goto chip_reset;
  421. /* Clear RxAbort bit so that we can
  422. * receive frames */
  423. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  424. spin_lock(&sc->sc_pm_lock);
  425. ath9k_hw_setrxabort(sc->sc_ah, 0);
  426. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  427. spin_unlock(&sc->sc_pm_lock);
  428. }
  429. chip_reset:
  430. ath_debug_stat_interrupt(sc, status);
  431. if (sched) {
  432. /* turn off every interrupt */
  433. ath9k_hw_disable_interrupts(ah);
  434. tasklet_schedule(&sc->intr_tq);
  435. }
  436. return IRQ_HANDLED;
  437. #undef SCHED_INTR
  438. }
  439. static int ath_reset(struct ath_softc *sc)
  440. {
  441. int i, r;
  442. ath9k_ps_wakeup(sc);
  443. r = ath_reset_internal(sc, NULL);
  444. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  445. if (!ATH_TXQ_SETUP(sc, i))
  446. continue;
  447. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  448. ath_txq_schedule(sc, &sc->tx.txq[i]);
  449. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  450. }
  451. ath9k_ps_restore(sc);
  452. return r;
  453. }
  454. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  455. {
  456. #ifdef CONFIG_ATH9K_DEBUGFS
  457. RESET_STAT_INC(sc, type);
  458. #endif
  459. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  460. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  461. }
  462. void ath_reset_work(struct work_struct *work)
  463. {
  464. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  465. ath_reset(sc);
  466. }
  467. /**********************/
  468. /* mac80211 callbacks */
  469. /**********************/
  470. static int ath9k_start(struct ieee80211_hw *hw)
  471. {
  472. struct ath_softc *sc = hw->priv;
  473. struct ath_hw *ah = sc->sc_ah;
  474. struct ath_common *common = ath9k_hw_common(ah);
  475. struct ieee80211_channel *curchan = hw->conf.channel;
  476. struct ath9k_channel *init_channel;
  477. int r;
  478. ath_dbg(common, CONFIG,
  479. "Starting driver with initial channel: %d MHz\n",
  480. curchan->center_freq);
  481. ath9k_ps_wakeup(sc);
  482. mutex_lock(&sc->mutex);
  483. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  484. /* Reset SERDES registers */
  485. ath9k_hw_configpcipowersave(ah, false);
  486. /*
  487. * The basic interface to setting the hardware in a good
  488. * state is ``reset''. On return the hardware is known to
  489. * be powered up and with interrupts disabled. This must
  490. * be followed by initialization of the appropriate bits
  491. * and then setup of the interrupt mask.
  492. */
  493. spin_lock_bh(&sc->sc_pcu_lock);
  494. atomic_set(&ah->intr_ref_cnt, -1);
  495. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  496. if (r) {
  497. ath_err(common,
  498. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  499. r, curchan->center_freq);
  500. ah->reset_power_on = false;
  501. }
  502. /* Setup our intr mask. */
  503. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  504. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  505. ATH9K_INT_GLOBAL;
  506. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  507. ah->imask |= ATH9K_INT_RXHP |
  508. ATH9K_INT_RXLP |
  509. ATH9K_INT_BB_WATCHDOG;
  510. else
  511. ah->imask |= ATH9K_INT_RX;
  512. ah->imask |= ATH9K_INT_GTT;
  513. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  514. ah->imask |= ATH9K_INT_CST;
  515. ath_mci_enable(sc);
  516. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  517. sc->sc_ah->is_monitoring = false;
  518. if (!ath_complete_reset(sc, false))
  519. ah->reset_power_on = false;
  520. if (ah->led_pin >= 0) {
  521. ath9k_hw_cfg_output(ah, ah->led_pin,
  522. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  523. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  524. }
  525. /*
  526. * Reset key cache to sane defaults (all entries cleared) instead of
  527. * semi-random values after suspend/resume.
  528. */
  529. ath9k_cmn_init_crypto(sc->sc_ah);
  530. spin_unlock_bh(&sc->sc_pcu_lock);
  531. mutex_unlock(&sc->mutex);
  532. ath9k_ps_restore(sc);
  533. return 0;
  534. }
  535. static void ath9k_tx(struct ieee80211_hw *hw,
  536. struct ieee80211_tx_control *control,
  537. struct sk_buff *skb)
  538. {
  539. struct ath_softc *sc = hw->priv;
  540. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  541. struct ath_tx_control txctl;
  542. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  543. unsigned long flags;
  544. if (sc->ps_enabled) {
  545. /*
  546. * mac80211 does not set PM field for normal data frames, so we
  547. * need to update that based on the current PS mode.
  548. */
  549. if (ieee80211_is_data(hdr->frame_control) &&
  550. !ieee80211_is_nullfunc(hdr->frame_control) &&
  551. !ieee80211_has_pm(hdr->frame_control)) {
  552. ath_dbg(common, PS,
  553. "Add PM=1 for a TX frame while in PS mode\n");
  554. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  555. }
  556. }
  557. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  558. /*
  559. * We are using PS-Poll and mac80211 can request TX while in
  560. * power save mode. Need to wake up hardware for the TX to be
  561. * completed and if needed, also for RX of buffered frames.
  562. */
  563. ath9k_ps_wakeup(sc);
  564. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  565. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  566. ath9k_hw_setrxabort(sc->sc_ah, 0);
  567. if (ieee80211_is_pspoll(hdr->frame_control)) {
  568. ath_dbg(common, PS,
  569. "Sending PS-Poll to pick a buffered frame\n");
  570. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  571. } else {
  572. ath_dbg(common, PS, "Wake up to complete TX\n");
  573. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  574. }
  575. /*
  576. * The actual restore operation will happen only after
  577. * the ps_flags bit is cleared. We are just dropping
  578. * the ps_usecount here.
  579. */
  580. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  581. ath9k_ps_restore(sc);
  582. }
  583. /*
  584. * Cannot tx while the hardware is in full sleep, it first needs a full
  585. * chip reset to recover from that
  586. */
  587. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  588. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  589. goto exit;
  590. }
  591. memset(&txctl, 0, sizeof(struct ath_tx_control));
  592. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  593. txctl.sta = control->sta;
  594. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  595. if (ath_tx_start(hw, skb, &txctl) != 0) {
  596. ath_dbg(common, XMIT, "TX failed\n");
  597. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  598. goto exit;
  599. }
  600. return;
  601. exit:
  602. ieee80211_free_txskb(hw, skb);
  603. }
  604. static void ath9k_stop(struct ieee80211_hw *hw)
  605. {
  606. struct ath_softc *sc = hw->priv;
  607. struct ath_hw *ah = sc->sc_ah;
  608. struct ath_common *common = ath9k_hw_common(ah);
  609. bool prev_idle;
  610. mutex_lock(&sc->mutex);
  611. ath_cancel_work(sc);
  612. del_timer_sync(&sc->rx_poll_timer);
  613. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  614. ath_dbg(common, ANY, "Device not present\n");
  615. mutex_unlock(&sc->mutex);
  616. return;
  617. }
  618. /* Ensure HW is awake when we try to shut it down. */
  619. ath9k_ps_wakeup(sc);
  620. spin_lock_bh(&sc->sc_pcu_lock);
  621. /* prevent tasklets to enable interrupts once we disable them */
  622. ah->imask &= ~ATH9K_INT_GLOBAL;
  623. /* make sure h/w will not generate any interrupt
  624. * before setting the invalid flag. */
  625. ath9k_hw_disable_interrupts(ah);
  626. spin_unlock_bh(&sc->sc_pcu_lock);
  627. /* we can now sync irq and kill any running tasklets, since we already
  628. * disabled interrupts and not holding a spin lock */
  629. synchronize_irq(sc->irq);
  630. tasklet_kill(&sc->intr_tq);
  631. tasklet_kill(&sc->bcon_tasklet);
  632. prev_idle = sc->ps_idle;
  633. sc->ps_idle = true;
  634. spin_lock_bh(&sc->sc_pcu_lock);
  635. if (ah->led_pin >= 0) {
  636. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  637. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  638. }
  639. ath_prepare_reset(sc);
  640. if (sc->rx.frag) {
  641. dev_kfree_skb_any(sc->rx.frag);
  642. sc->rx.frag = NULL;
  643. }
  644. if (!ah->curchan)
  645. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  646. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  647. ath9k_hw_phy_disable(ah);
  648. ath9k_hw_configpcipowersave(ah, true);
  649. spin_unlock_bh(&sc->sc_pcu_lock);
  650. ath9k_ps_restore(sc);
  651. set_bit(SC_OP_INVALID, &sc->sc_flags);
  652. sc->ps_idle = prev_idle;
  653. mutex_unlock(&sc->mutex);
  654. ath_dbg(common, CONFIG, "Driver halt\n");
  655. }
  656. bool ath9k_uses_beacons(int type)
  657. {
  658. switch (type) {
  659. case NL80211_IFTYPE_AP:
  660. case NL80211_IFTYPE_ADHOC:
  661. case NL80211_IFTYPE_MESH_POINT:
  662. return true;
  663. default:
  664. return false;
  665. }
  666. }
  667. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  668. {
  669. struct ath9k_vif_iter_data *iter_data = data;
  670. int i;
  671. if (iter_data->hw_macaddr)
  672. for (i = 0; i < ETH_ALEN; i++)
  673. iter_data->mask[i] &=
  674. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  675. switch (vif->type) {
  676. case NL80211_IFTYPE_AP:
  677. iter_data->naps++;
  678. break;
  679. case NL80211_IFTYPE_STATION:
  680. iter_data->nstations++;
  681. break;
  682. case NL80211_IFTYPE_ADHOC:
  683. iter_data->nadhocs++;
  684. break;
  685. case NL80211_IFTYPE_MESH_POINT:
  686. iter_data->nmeshes++;
  687. break;
  688. case NL80211_IFTYPE_WDS:
  689. iter_data->nwds++;
  690. break;
  691. default:
  692. break;
  693. }
  694. }
  695. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  696. {
  697. struct ath_softc *sc = data;
  698. struct ath_vif *avp = (void *)vif->drv_priv;
  699. if (vif->type != NL80211_IFTYPE_STATION)
  700. return;
  701. if (avp->primary_sta_vif)
  702. ath9k_set_assoc_state(sc, vif);
  703. }
  704. /* Called with sc->mutex held. */
  705. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  706. struct ieee80211_vif *vif,
  707. struct ath9k_vif_iter_data *iter_data)
  708. {
  709. struct ath_softc *sc = hw->priv;
  710. struct ath_hw *ah = sc->sc_ah;
  711. struct ath_common *common = ath9k_hw_common(ah);
  712. /*
  713. * Use the hardware MAC address as reference, the hardware uses it
  714. * together with the BSSID mask when matching addresses.
  715. */
  716. memset(iter_data, 0, sizeof(*iter_data));
  717. iter_data->hw_macaddr = common->macaddr;
  718. memset(&iter_data->mask, 0xff, ETH_ALEN);
  719. if (vif)
  720. ath9k_vif_iter(iter_data, vif->addr, vif);
  721. /* Get list of all active MAC addresses */
  722. ieee80211_iterate_active_interfaces_atomic(
  723. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  724. ath9k_vif_iter, iter_data);
  725. }
  726. /* Called with sc->mutex held. */
  727. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  728. struct ieee80211_vif *vif)
  729. {
  730. struct ath_softc *sc = hw->priv;
  731. struct ath_hw *ah = sc->sc_ah;
  732. struct ath_common *common = ath9k_hw_common(ah);
  733. struct ath9k_vif_iter_data iter_data;
  734. enum nl80211_iftype old_opmode = ah->opmode;
  735. ath9k_calculate_iter_data(hw, vif, &iter_data);
  736. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  737. ath_hw_setbssidmask(common);
  738. if (iter_data.naps > 0) {
  739. ath9k_hw_set_tsfadjust(ah, true);
  740. ah->opmode = NL80211_IFTYPE_AP;
  741. } else {
  742. ath9k_hw_set_tsfadjust(ah, false);
  743. if (iter_data.nmeshes)
  744. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  745. else if (iter_data.nwds)
  746. ah->opmode = NL80211_IFTYPE_AP;
  747. else if (iter_data.nadhocs)
  748. ah->opmode = NL80211_IFTYPE_ADHOC;
  749. else
  750. ah->opmode = NL80211_IFTYPE_STATION;
  751. }
  752. ath9k_hw_setopmode(ah);
  753. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  754. ah->imask |= ATH9K_INT_TSFOOR;
  755. else
  756. ah->imask &= ~ATH9K_INT_TSFOOR;
  757. ath9k_hw_set_interrupts(ah);
  758. /*
  759. * If we are changing the opmode to STATION,
  760. * a beacon sync needs to be done.
  761. */
  762. if (ah->opmode == NL80211_IFTYPE_STATION &&
  763. old_opmode == NL80211_IFTYPE_AP &&
  764. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  765. ieee80211_iterate_active_interfaces_atomic(
  766. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  767. ath9k_sta_vif_iter, sc);
  768. }
  769. }
  770. static int ath9k_add_interface(struct ieee80211_hw *hw,
  771. struct ieee80211_vif *vif)
  772. {
  773. struct ath_softc *sc = hw->priv;
  774. struct ath_hw *ah = sc->sc_ah;
  775. struct ath_common *common = ath9k_hw_common(ah);
  776. mutex_lock(&sc->mutex);
  777. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  778. sc->nvifs++;
  779. ath9k_ps_wakeup(sc);
  780. ath9k_calculate_summary_state(hw, vif);
  781. ath9k_ps_restore(sc);
  782. if (ath9k_uses_beacons(vif->type))
  783. ath9k_beacon_assign_slot(sc, vif);
  784. mutex_unlock(&sc->mutex);
  785. return 0;
  786. }
  787. static int ath9k_change_interface(struct ieee80211_hw *hw,
  788. struct ieee80211_vif *vif,
  789. enum nl80211_iftype new_type,
  790. bool p2p)
  791. {
  792. struct ath_softc *sc = hw->priv;
  793. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  794. ath_dbg(common, CONFIG, "Change Interface\n");
  795. mutex_lock(&sc->mutex);
  796. if (ath9k_uses_beacons(vif->type))
  797. ath9k_beacon_remove_slot(sc, vif);
  798. vif->type = new_type;
  799. vif->p2p = p2p;
  800. ath9k_ps_wakeup(sc);
  801. ath9k_calculate_summary_state(hw, vif);
  802. ath9k_ps_restore(sc);
  803. if (ath9k_uses_beacons(vif->type))
  804. ath9k_beacon_assign_slot(sc, vif);
  805. mutex_unlock(&sc->mutex);
  806. return 0;
  807. }
  808. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  809. struct ieee80211_vif *vif)
  810. {
  811. struct ath_softc *sc = hw->priv;
  812. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  813. ath_dbg(common, CONFIG, "Detach Interface\n");
  814. mutex_lock(&sc->mutex);
  815. sc->nvifs--;
  816. if (ath9k_uses_beacons(vif->type))
  817. ath9k_beacon_remove_slot(sc, vif);
  818. ath9k_ps_wakeup(sc);
  819. ath9k_calculate_summary_state(hw, NULL);
  820. ath9k_ps_restore(sc);
  821. mutex_unlock(&sc->mutex);
  822. }
  823. static void ath9k_enable_ps(struct ath_softc *sc)
  824. {
  825. struct ath_hw *ah = sc->sc_ah;
  826. struct ath_common *common = ath9k_hw_common(ah);
  827. sc->ps_enabled = true;
  828. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  829. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  830. ah->imask |= ATH9K_INT_TIM_TIMER;
  831. ath9k_hw_set_interrupts(ah);
  832. }
  833. ath9k_hw_setrxabort(ah, 1);
  834. }
  835. ath_dbg(common, PS, "PowerSave enabled\n");
  836. }
  837. static void ath9k_disable_ps(struct ath_softc *sc)
  838. {
  839. struct ath_hw *ah = sc->sc_ah;
  840. struct ath_common *common = ath9k_hw_common(ah);
  841. sc->ps_enabled = false;
  842. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  843. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  844. ath9k_hw_setrxabort(ah, 0);
  845. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  846. PS_WAIT_FOR_CAB |
  847. PS_WAIT_FOR_PSPOLL_DATA |
  848. PS_WAIT_FOR_TX_ACK);
  849. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  850. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  851. ath9k_hw_set_interrupts(ah);
  852. }
  853. }
  854. ath_dbg(common, PS, "PowerSave disabled\n");
  855. }
  856. void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
  857. {
  858. struct ath_softc *sc = hw->priv;
  859. struct ath_hw *ah = sc->sc_ah;
  860. struct ath_common *common = ath9k_hw_common(ah);
  861. u32 rxfilter;
  862. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  863. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  864. return;
  865. }
  866. ath9k_ps_wakeup(sc);
  867. rxfilter = ath9k_hw_getrxfilter(ah);
  868. ath9k_hw_setrxfilter(ah, rxfilter |
  869. ATH9K_RX_FILTER_PHYRADAR |
  870. ATH9K_RX_FILTER_PHYERR);
  871. /* TODO: usually this should not be neccesary, but for some reason
  872. * (or in some mode?) the trigger must be called after the
  873. * configuration, otherwise the register will have its values reset
  874. * (on my ar9220 to value 0x01002310)
  875. */
  876. ath9k_spectral_scan_config(hw, sc->spectral_mode);
  877. ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
  878. ath9k_ps_restore(sc);
  879. }
  880. int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
  881. enum spectral_mode spectral_mode)
  882. {
  883. struct ath_softc *sc = hw->priv;
  884. struct ath_hw *ah = sc->sc_ah;
  885. struct ath_common *common = ath9k_hw_common(ah);
  886. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  887. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  888. return -1;
  889. }
  890. switch (spectral_mode) {
  891. case SPECTRAL_DISABLED:
  892. sc->spec_config.enabled = 0;
  893. break;
  894. case SPECTRAL_BACKGROUND:
  895. /* send endless samples.
  896. * TODO: is this really useful for "background"?
  897. */
  898. sc->spec_config.endless = 1;
  899. sc->spec_config.enabled = 1;
  900. break;
  901. case SPECTRAL_CHANSCAN:
  902. case SPECTRAL_MANUAL:
  903. sc->spec_config.endless = 0;
  904. sc->spec_config.enabled = 1;
  905. break;
  906. default:
  907. return -1;
  908. }
  909. ath9k_ps_wakeup(sc);
  910. ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
  911. ath9k_ps_restore(sc);
  912. sc->spectral_mode = spectral_mode;
  913. return 0;
  914. }
  915. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  916. {
  917. struct ath_softc *sc = hw->priv;
  918. struct ath_hw *ah = sc->sc_ah;
  919. struct ath_common *common = ath9k_hw_common(ah);
  920. struct ieee80211_conf *conf = &hw->conf;
  921. bool reset_channel = false;
  922. ath9k_ps_wakeup(sc);
  923. mutex_lock(&sc->mutex);
  924. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  925. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  926. if (sc->ps_idle) {
  927. ath_cancel_work(sc);
  928. ath9k_stop_btcoex(sc);
  929. } else {
  930. ath9k_start_btcoex(sc);
  931. /*
  932. * The chip needs a reset to properly wake up from
  933. * full sleep
  934. */
  935. reset_channel = ah->chip_fullsleep;
  936. }
  937. }
  938. /*
  939. * We just prepare to enable PS. We have to wait until our AP has
  940. * ACK'd our null data frame to disable RX otherwise we'll ignore
  941. * those ACKs and end up retransmitting the same null data frames.
  942. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  943. */
  944. if (changed & IEEE80211_CONF_CHANGE_PS) {
  945. unsigned long flags;
  946. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  947. if (conf->flags & IEEE80211_CONF_PS)
  948. ath9k_enable_ps(sc);
  949. else
  950. ath9k_disable_ps(sc);
  951. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  952. }
  953. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  954. if (conf->flags & IEEE80211_CONF_MONITOR) {
  955. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  956. sc->sc_ah->is_monitoring = true;
  957. } else {
  958. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  959. sc->sc_ah->is_monitoring = false;
  960. }
  961. }
  962. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  963. struct ieee80211_channel *curchan = hw->conf.channel;
  964. int pos = curchan->hw_value;
  965. int old_pos = -1;
  966. unsigned long flags;
  967. if (ah->curchan)
  968. old_pos = ah->curchan - &ah->channels[0];
  969. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  970. curchan->center_freq, conf->channel_type);
  971. /* update survey stats for the old channel before switching */
  972. spin_lock_irqsave(&common->cc_lock, flags);
  973. ath_update_survey_stats(sc);
  974. spin_unlock_irqrestore(&common->cc_lock, flags);
  975. /*
  976. * Preserve the current channel values, before updating
  977. * the same channel
  978. */
  979. if (ah->curchan && (old_pos == pos))
  980. ath9k_hw_getnf(ah, ah->curchan);
  981. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  982. curchan, conf->channel_type);
  983. /*
  984. * If the operating channel changes, change the survey in-use flags
  985. * along with it.
  986. * Reset the survey data for the new channel, unless we're switching
  987. * back to the operating channel from an off-channel operation.
  988. */
  989. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  990. sc->cur_survey != &sc->survey[pos]) {
  991. if (sc->cur_survey)
  992. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  993. sc->cur_survey = &sc->survey[pos];
  994. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  995. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  996. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  997. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  998. }
  999. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1000. ath_err(common, "Unable to set channel\n");
  1001. mutex_unlock(&sc->mutex);
  1002. ath9k_ps_restore(sc);
  1003. return -EINVAL;
  1004. }
  1005. /*
  1006. * The most recent snapshot of channel->noisefloor for the old
  1007. * channel is only available after the hardware reset. Copy it to
  1008. * the survey stats now.
  1009. */
  1010. if (old_pos >= 0)
  1011. ath_update_survey_nf(sc, old_pos);
  1012. /* perform spectral scan if requested. */
  1013. if (sc->scanning && sc->spectral_mode == SPECTRAL_CHANSCAN)
  1014. ath9k_spectral_scan_trigger(hw);
  1015. }
  1016. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1017. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1018. sc->config.txpowlimit = 2 * conf->power_level;
  1019. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1020. sc->config.txpowlimit, &sc->curtxpow);
  1021. }
  1022. mutex_unlock(&sc->mutex);
  1023. ath9k_ps_restore(sc);
  1024. return 0;
  1025. }
  1026. #define SUPPORTED_FILTERS \
  1027. (FIF_PROMISC_IN_BSS | \
  1028. FIF_ALLMULTI | \
  1029. FIF_CONTROL | \
  1030. FIF_PSPOLL | \
  1031. FIF_OTHER_BSS | \
  1032. FIF_BCN_PRBRESP_PROMISC | \
  1033. FIF_PROBE_REQ | \
  1034. FIF_FCSFAIL)
  1035. /* FIXME: sc->sc_full_reset ? */
  1036. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1037. unsigned int changed_flags,
  1038. unsigned int *total_flags,
  1039. u64 multicast)
  1040. {
  1041. struct ath_softc *sc = hw->priv;
  1042. u32 rfilt;
  1043. changed_flags &= SUPPORTED_FILTERS;
  1044. *total_flags &= SUPPORTED_FILTERS;
  1045. sc->rx.rxfilter = *total_flags;
  1046. ath9k_ps_wakeup(sc);
  1047. rfilt = ath_calcrxfilter(sc);
  1048. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1049. ath9k_ps_restore(sc);
  1050. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1051. rfilt);
  1052. }
  1053. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1054. struct ieee80211_vif *vif,
  1055. struct ieee80211_sta *sta)
  1056. {
  1057. struct ath_softc *sc = hw->priv;
  1058. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1059. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1060. struct ieee80211_key_conf ps_key = { };
  1061. ath_node_attach(sc, sta, vif);
  1062. if (vif->type != NL80211_IFTYPE_AP &&
  1063. vif->type != NL80211_IFTYPE_AP_VLAN)
  1064. return 0;
  1065. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1066. return 0;
  1067. }
  1068. static void ath9k_del_ps_key(struct ath_softc *sc,
  1069. struct ieee80211_vif *vif,
  1070. struct ieee80211_sta *sta)
  1071. {
  1072. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1073. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1074. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1075. if (!an->ps_key)
  1076. return;
  1077. ath_key_delete(common, &ps_key);
  1078. }
  1079. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1080. struct ieee80211_vif *vif,
  1081. struct ieee80211_sta *sta)
  1082. {
  1083. struct ath_softc *sc = hw->priv;
  1084. ath9k_del_ps_key(sc, vif, sta);
  1085. ath_node_detach(sc, sta);
  1086. return 0;
  1087. }
  1088. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1089. struct ieee80211_vif *vif,
  1090. enum sta_notify_cmd cmd,
  1091. struct ieee80211_sta *sta)
  1092. {
  1093. struct ath_softc *sc = hw->priv;
  1094. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1095. if (!sta->ht_cap.ht_supported)
  1096. return;
  1097. switch (cmd) {
  1098. case STA_NOTIFY_SLEEP:
  1099. an->sleeping = true;
  1100. ath_tx_aggr_sleep(sta, sc, an);
  1101. break;
  1102. case STA_NOTIFY_AWAKE:
  1103. an->sleeping = false;
  1104. ath_tx_aggr_wakeup(sc, an);
  1105. break;
  1106. }
  1107. }
  1108. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1109. struct ieee80211_vif *vif, u16 queue,
  1110. const struct ieee80211_tx_queue_params *params)
  1111. {
  1112. struct ath_softc *sc = hw->priv;
  1113. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1114. struct ath_txq *txq;
  1115. struct ath9k_tx_queue_info qi;
  1116. int ret = 0;
  1117. if (queue >= IEEE80211_NUM_ACS)
  1118. return 0;
  1119. txq = sc->tx.txq_map[queue];
  1120. ath9k_ps_wakeup(sc);
  1121. mutex_lock(&sc->mutex);
  1122. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1123. qi.tqi_aifs = params->aifs;
  1124. qi.tqi_cwmin = params->cw_min;
  1125. qi.tqi_cwmax = params->cw_max;
  1126. qi.tqi_burstTime = params->txop * 32;
  1127. ath_dbg(common, CONFIG,
  1128. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1129. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1130. params->cw_max, params->txop);
  1131. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1132. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1133. if (ret)
  1134. ath_err(common, "TXQ Update failed\n");
  1135. mutex_unlock(&sc->mutex);
  1136. ath9k_ps_restore(sc);
  1137. return ret;
  1138. }
  1139. static int ath9k_set_key(struct ieee80211_hw *hw,
  1140. enum set_key_cmd cmd,
  1141. struct ieee80211_vif *vif,
  1142. struct ieee80211_sta *sta,
  1143. struct ieee80211_key_conf *key)
  1144. {
  1145. struct ath_softc *sc = hw->priv;
  1146. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1147. int ret = 0;
  1148. if (ath9k_modparam_nohwcrypt)
  1149. return -ENOSPC;
  1150. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1151. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1152. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1153. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1154. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1155. /*
  1156. * For now, disable hw crypto for the RSN IBSS group keys. This
  1157. * could be optimized in the future to use a modified key cache
  1158. * design to support per-STA RX GTK, but until that gets
  1159. * implemented, use of software crypto for group addressed
  1160. * frames is a acceptable to allow RSN IBSS to be used.
  1161. */
  1162. return -EOPNOTSUPP;
  1163. }
  1164. mutex_lock(&sc->mutex);
  1165. ath9k_ps_wakeup(sc);
  1166. ath_dbg(common, CONFIG, "Set HW Key\n");
  1167. switch (cmd) {
  1168. case SET_KEY:
  1169. if (sta)
  1170. ath9k_del_ps_key(sc, vif, sta);
  1171. ret = ath_key_config(common, vif, sta, key);
  1172. if (ret >= 0) {
  1173. key->hw_key_idx = ret;
  1174. /* push IV and Michael MIC generation to stack */
  1175. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1176. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1177. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1178. if (sc->sc_ah->sw_mgmt_crypto &&
  1179. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1180. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1181. ret = 0;
  1182. }
  1183. break;
  1184. case DISABLE_KEY:
  1185. ath_key_delete(common, key);
  1186. break;
  1187. default:
  1188. ret = -EINVAL;
  1189. }
  1190. ath9k_ps_restore(sc);
  1191. mutex_unlock(&sc->mutex);
  1192. return ret;
  1193. }
  1194. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1195. struct ieee80211_vif *vif)
  1196. {
  1197. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1198. struct ath_vif *avp = (void *)vif->drv_priv;
  1199. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1200. unsigned long flags;
  1201. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1202. avp->primary_sta_vif = true;
  1203. /*
  1204. * Set the AID, BSSID and do beacon-sync only when
  1205. * the HW opmode is STATION.
  1206. *
  1207. * But the primary bit is set above in any case.
  1208. */
  1209. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1210. return;
  1211. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1212. common->curaid = bss_conf->aid;
  1213. ath9k_hw_write_associd(sc->sc_ah);
  1214. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1215. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1216. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1217. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1218. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1219. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1220. ath9k_mci_update_wlan_channels(sc, false);
  1221. ath_dbg(common, CONFIG,
  1222. "Primary Station interface: %pM, BSSID: %pM\n",
  1223. vif->addr, common->curbssid);
  1224. }
  1225. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1226. {
  1227. struct ath_softc *sc = data;
  1228. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1229. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1230. return;
  1231. if (bss_conf->assoc)
  1232. ath9k_set_assoc_state(sc, vif);
  1233. }
  1234. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1235. struct ieee80211_vif *vif,
  1236. struct ieee80211_bss_conf *bss_conf,
  1237. u32 changed)
  1238. {
  1239. #define CHECK_ANI \
  1240. (BSS_CHANGED_ASSOC | \
  1241. BSS_CHANGED_IBSS | \
  1242. BSS_CHANGED_BEACON_ENABLED)
  1243. struct ath_softc *sc = hw->priv;
  1244. struct ath_hw *ah = sc->sc_ah;
  1245. struct ath_common *common = ath9k_hw_common(ah);
  1246. struct ath_vif *avp = (void *)vif->drv_priv;
  1247. int slottime;
  1248. ath9k_ps_wakeup(sc);
  1249. mutex_lock(&sc->mutex);
  1250. if (changed & BSS_CHANGED_ASSOC) {
  1251. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1252. bss_conf->bssid, bss_conf->assoc);
  1253. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1254. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1255. avp->primary_sta_vif = false;
  1256. if (ah->opmode == NL80211_IFTYPE_STATION)
  1257. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1258. }
  1259. ieee80211_iterate_active_interfaces_atomic(
  1260. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1261. ath9k_bss_assoc_iter, sc);
  1262. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1263. ah->opmode == NL80211_IFTYPE_STATION) {
  1264. memset(common->curbssid, 0, ETH_ALEN);
  1265. common->curaid = 0;
  1266. ath9k_hw_write_associd(sc->sc_ah);
  1267. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1268. ath9k_mci_update_wlan_channels(sc, true);
  1269. }
  1270. }
  1271. if (changed & BSS_CHANGED_IBSS) {
  1272. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1273. common->curaid = bss_conf->aid;
  1274. ath9k_hw_write_associd(sc->sc_ah);
  1275. }
  1276. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1277. (changed & BSS_CHANGED_BEACON_INT)) {
  1278. if (ah->opmode == NL80211_IFTYPE_AP &&
  1279. bss_conf->enable_beacon)
  1280. ath9k_set_tsfadjust(sc, vif);
  1281. if (ath9k_allow_beacon_config(sc, vif))
  1282. ath9k_beacon_config(sc, vif, changed);
  1283. }
  1284. if (changed & BSS_CHANGED_ERP_SLOT) {
  1285. if (bss_conf->use_short_slot)
  1286. slottime = 9;
  1287. else
  1288. slottime = 20;
  1289. if (vif->type == NL80211_IFTYPE_AP) {
  1290. /*
  1291. * Defer update, so that connected stations can adjust
  1292. * their settings at the same time.
  1293. * See beacon.c for more details
  1294. */
  1295. sc->beacon.slottime = slottime;
  1296. sc->beacon.updateslot = UPDATE;
  1297. } else {
  1298. ah->slottime = slottime;
  1299. ath9k_hw_init_global_settings(ah);
  1300. }
  1301. }
  1302. if (changed & CHECK_ANI)
  1303. ath_check_ani(sc);
  1304. mutex_unlock(&sc->mutex);
  1305. ath9k_ps_restore(sc);
  1306. #undef CHECK_ANI
  1307. }
  1308. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1309. {
  1310. struct ath_softc *sc = hw->priv;
  1311. u64 tsf;
  1312. mutex_lock(&sc->mutex);
  1313. ath9k_ps_wakeup(sc);
  1314. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1315. ath9k_ps_restore(sc);
  1316. mutex_unlock(&sc->mutex);
  1317. return tsf;
  1318. }
  1319. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1320. struct ieee80211_vif *vif,
  1321. u64 tsf)
  1322. {
  1323. struct ath_softc *sc = hw->priv;
  1324. mutex_lock(&sc->mutex);
  1325. ath9k_ps_wakeup(sc);
  1326. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1327. ath9k_ps_restore(sc);
  1328. mutex_unlock(&sc->mutex);
  1329. }
  1330. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1331. {
  1332. struct ath_softc *sc = hw->priv;
  1333. mutex_lock(&sc->mutex);
  1334. ath9k_ps_wakeup(sc);
  1335. ath9k_hw_reset_tsf(sc->sc_ah);
  1336. ath9k_ps_restore(sc);
  1337. mutex_unlock(&sc->mutex);
  1338. }
  1339. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1340. struct ieee80211_vif *vif,
  1341. enum ieee80211_ampdu_mlme_action action,
  1342. struct ieee80211_sta *sta,
  1343. u16 tid, u16 *ssn, u8 buf_size)
  1344. {
  1345. struct ath_softc *sc = hw->priv;
  1346. int ret = 0;
  1347. local_bh_disable();
  1348. switch (action) {
  1349. case IEEE80211_AMPDU_RX_START:
  1350. break;
  1351. case IEEE80211_AMPDU_RX_STOP:
  1352. break;
  1353. case IEEE80211_AMPDU_TX_START:
  1354. ath9k_ps_wakeup(sc);
  1355. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1356. if (!ret)
  1357. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1358. ath9k_ps_restore(sc);
  1359. break;
  1360. case IEEE80211_AMPDU_TX_STOP_CONT:
  1361. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1362. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1363. ath9k_ps_wakeup(sc);
  1364. ath_tx_aggr_stop(sc, sta, tid);
  1365. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1366. ath9k_ps_restore(sc);
  1367. break;
  1368. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1369. ath9k_ps_wakeup(sc);
  1370. ath_tx_aggr_resume(sc, sta, tid);
  1371. ath9k_ps_restore(sc);
  1372. break;
  1373. default:
  1374. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1375. }
  1376. local_bh_enable();
  1377. return ret;
  1378. }
  1379. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1380. struct survey_info *survey)
  1381. {
  1382. struct ath_softc *sc = hw->priv;
  1383. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1384. struct ieee80211_supported_band *sband;
  1385. struct ieee80211_channel *chan;
  1386. unsigned long flags;
  1387. int pos;
  1388. spin_lock_irqsave(&common->cc_lock, flags);
  1389. if (idx == 0)
  1390. ath_update_survey_stats(sc);
  1391. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1392. if (sband && idx >= sband->n_channels) {
  1393. idx -= sband->n_channels;
  1394. sband = NULL;
  1395. }
  1396. if (!sband)
  1397. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1398. if (!sband || idx >= sband->n_channels) {
  1399. spin_unlock_irqrestore(&common->cc_lock, flags);
  1400. return -ENOENT;
  1401. }
  1402. chan = &sband->channels[idx];
  1403. pos = chan->hw_value;
  1404. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1405. survey->channel = chan;
  1406. spin_unlock_irqrestore(&common->cc_lock, flags);
  1407. return 0;
  1408. }
  1409. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1410. {
  1411. struct ath_softc *sc = hw->priv;
  1412. struct ath_hw *ah = sc->sc_ah;
  1413. mutex_lock(&sc->mutex);
  1414. ah->coverage_class = coverage_class;
  1415. ath9k_ps_wakeup(sc);
  1416. ath9k_hw_init_global_settings(ah);
  1417. ath9k_ps_restore(sc);
  1418. mutex_unlock(&sc->mutex);
  1419. }
  1420. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1421. {
  1422. struct ath_softc *sc = hw->priv;
  1423. struct ath_hw *ah = sc->sc_ah;
  1424. struct ath_common *common = ath9k_hw_common(ah);
  1425. int timeout = 200; /* ms */
  1426. int i, j;
  1427. bool drain_txq;
  1428. mutex_lock(&sc->mutex);
  1429. cancel_delayed_work_sync(&sc->tx_complete_work);
  1430. if (ah->ah_flags & AH_UNPLUGGED) {
  1431. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1432. mutex_unlock(&sc->mutex);
  1433. return;
  1434. }
  1435. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1436. ath_dbg(common, ANY, "Device not present\n");
  1437. mutex_unlock(&sc->mutex);
  1438. return;
  1439. }
  1440. for (j = 0; j < timeout; j++) {
  1441. bool npend = false;
  1442. if (j)
  1443. usleep_range(1000, 2000);
  1444. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1445. if (!ATH_TXQ_SETUP(sc, i))
  1446. continue;
  1447. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1448. if (npend)
  1449. break;
  1450. }
  1451. if (!npend)
  1452. break;
  1453. }
  1454. if (drop) {
  1455. ath9k_ps_wakeup(sc);
  1456. spin_lock_bh(&sc->sc_pcu_lock);
  1457. drain_txq = ath_drain_all_txq(sc);
  1458. spin_unlock_bh(&sc->sc_pcu_lock);
  1459. if (!drain_txq)
  1460. ath_reset(sc);
  1461. ath9k_ps_restore(sc);
  1462. ieee80211_wake_queues(hw);
  1463. }
  1464. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1465. mutex_unlock(&sc->mutex);
  1466. }
  1467. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1468. {
  1469. struct ath_softc *sc = hw->priv;
  1470. int i;
  1471. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1472. if (!ATH_TXQ_SETUP(sc, i))
  1473. continue;
  1474. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1475. return true;
  1476. }
  1477. return false;
  1478. }
  1479. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1480. {
  1481. struct ath_softc *sc = hw->priv;
  1482. struct ath_hw *ah = sc->sc_ah;
  1483. struct ieee80211_vif *vif;
  1484. struct ath_vif *avp;
  1485. struct ath_buf *bf;
  1486. struct ath_tx_status ts;
  1487. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1488. int status;
  1489. vif = sc->beacon.bslot[0];
  1490. if (!vif)
  1491. return 0;
  1492. if (!vif->bss_conf.enable_beacon)
  1493. return 0;
  1494. avp = (void *)vif->drv_priv;
  1495. if (!sc->beacon.tx_processed && !edma) {
  1496. tasklet_disable(&sc->bcon_tasklet);
  1497. bf = avp->av_bcbuf;
  1498. if (!bf || !bf->bf_mpdu)
  1499. goto skip;
  1500. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1501. if (status == -EINPROGRESS)
  1502. goto skip;
  1503. sc->beacon.tx_processed = true;
  1504. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1505. skip:
  1506. tasklet_enable(&sc->bcon_tasklet);
  1507. }
  1508. return sc->beacon.tx_last;
  1509. }
  1510. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1511. struct ieee80211_low_level_stats *stats)
  1512. {
  1513. struct ath_softc *sc = hw->priv;
  1514. struct ath_hw *ah = sc->sc_ah;
  1515. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1516. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1517. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1518. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1519. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1520. return 0;
  1521. }
  1522. static u32 fill_chainmask(u32 cap, u32 new)
  1523. {
  1524. u32 filled = 0;
  1525. int i;
  1526. for (i = 0; cap && new; i++, cap >>= 1) {
  1527. if (!(cap & BIT(0)))
  1528. continue;
  1529. if (new & BIT(0))
  1530. filled |= BIT(i);
  1531. new >>= 1;
  1532. }
  1533. return filled;
  1534. }
  1535. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1536. {
  1537. if (AR_SREV_9300_20_OR_LATER(ah))
  1538. return true;
  1539. switch (val & 0x7) {
  1540. case 0x1:
  1541. case 0x3:
  1542. case 0x7:
  1543. return true;
  1544. case 0x2:
  1545. return (ah->caps.rx_chainmask == 1);
  1546. default:
  1547. return false;
  1548. }
  1549. }
  1550. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1551. {
  1552. struct ath_softc *sc = hw->priv;
  1553. struct ath_hw *ah = sc->sc_ah;
  1554. if (ah->caps.rx_chainmask != 1)
  1555. rx_ant |= tx_ant;
  1556. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1557. return -EINVAL;
  1558. sc->ant_rx = rx_ant;
  1559. sc->ant_tx = tx_ant;
  1560. if (ah->caps.rx_chainmask == 1)
  1561. return 0;
  1562. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1563. if (AR_SREV_9100(ah))
  1564. ah->rxchainmask = 0x7;
  1565. else
  1566. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1567. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1568. ath9k_reload_chainmask_settings(sc);
  1569. return 0;
  1570. }
  1571. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1572. {
  1573. struct ath_softc *sc = hw->priv;
  1574. *tx_ant = sc->ant_tx;
  1575. *rx_ant = sc->ant_rx;
  1576. return 0;
  1577. }
  1578. #ifdef CONFIG_PM_SLEEP
  1579. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1580. struct cfg80211_wowlan *wowlan,
  1581. u32 *wow_triggers)
  1582. {
  1583. if (wowlan->disconnect)
  1584. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1585. AH_WOW_BEACON_MISS;
  1586. if (wowlan->magic_pkt)
  1587. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1588. if (wowlan->n_patterns)
  1589. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1590. sc->wow_enabled = *wow_triggers;
  1591. }
  1592. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1593. {
  1594. struct ath_hw *ah = sc->sc_ah;
  1595. struct ath_common *common = ath9k_hw_common(ah);
  1596. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1597. int pattern_count = 0;
  1598. int i, byte_cnt;
  1599. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1600. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1601. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1602. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1603. /*
  1604. * Create Dissassociate / Deauthenticate packet filter
  1605. *
  1606. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1607. * +--------------+----------+---------+--------+--------+----
  1608. * + Frame Control+ Duration + DA + SA + BSSID +
  1609. * +--------------+----------+---------+--------+--------+----
  1610. *
  1611. * The above is the management frame format for disassociate/
  1612. * deauthenticate pattern, from this we need to match the first byte
  1613. * of 'Frame Control' and DA, SA, and BSSID fields
  1614. * (skipping 2nd byte of FC and Duration feild.
  1615. *
  1616. * Disassociate pattern
  1617. * --------------------
  1618. * Frame control = 00 00 1010
  1619. * DA, SA, BSSID = x:x:x:x:x:x
  1620. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1621. * | x:x:x:x:x:x -- 22 bytes
  1622. *
  1623. * Deauthenticate pattern
  1624. * ----------------------
  1625. * Frame control = 00 00 1100
  1626. * DA, SA, BSSID = x:x:x:x:x:x
  1627. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1628. * | x:x:x:x:x:x -- 22 bytes
  1629. */
  1630. /* Create Disassociate Pattern first */
  1631. byte_cnt = 0;
  1632. /* Fill out the mask with all FF's */
  1633. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1634. dis_deauth_mask[i] = 0xff;
  1635. /* copy the first byte of frame control field */
  1636. dis_deauth_pattern[byte_cnt] = 0xa0;
  1637. byte_cnt++;
  1638. /* skip 2nd byte of frame control and Duration field */
  1639. byte_cnt += 3;
  1640. /*
  1641. * need not match the destination mac address, it can be a broadcast
  1642. * mac address or an unicast to this station
  1643. */
  1644. byte_cnt += 6;
  1645. /* copy the source mac address */
  1646. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1647. byte_cnt += 6;
  1648. /* copy the bssid, its same as the source mac address */
  1649. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1650. /* Create Disassociate pattern mask */
  1651. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1652. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1653. /*
  1654. * for AR9280, because of hardware limitation, the
  1655. * first 4 bytes have to be matched for all patterns.
  1656. * the mask for disassociation and de-auth pattern
  1657. * matching need to enable the first 4 bytes.
  1658. * also the duration field needs to be filled.
  1659. */
  1660. dis_deauth_mask[0] = 0xf0;
  1661. /*
  1662. * fill in duration field
  1663. FIXME: what is the exact value ?
  1664. */
  1665. dis_deauth_pattern[2] = 0xff;
  1666. dis_deauth_pattern[3] = 0xff;
  1667. } else {
  1668. dis_deauth_mask[0] = 0xfe;
  1669. }
  1670. dis_deauth_mask[1] = 0x03;
  1671. dis_deauth_mask[2] = 0xc0;
  1672. } else {
  1673. dis_deauth_mask[0] = 0xef;
  1674. dis_deauth_mask[1] = 0x3f;
  1675. dis_deauth_mask[2] = 0x00;
  1676. dis_deauth_mask[3] = 0xfc;
  1677. }
  1678. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1679. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1680. pattern_count, byte_cnt);
  1681. pattern_count++;
  1682. /*
  1683. * for de-authenticate pattern, only the first byte of the frame
  1684. * control field gets changed from 0xA0 to 0xC0
  1685. */
  1686. dis_deauth_pattern[0] = 0xC0;
  1687. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1688. pattern_count, byte_cnt);
  1689. }
  1690. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1691. struct cfg80211_wowlan *wowlan)
  1692. {
  1693. struct ath_hw *ah = sc->sc_ah;
  1694. struct ath9k_wow_pattern *wow_pattern = NULL;
  1695. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1696. int mask_len;
  1697. s8 i = 0;
  1698. if (!wowlan->n_patterns)
  1699. return;
  1700. /*
  1701. * Add the new user configured patterns
  1702. */
  1703. for (i = 0; i < wowlan->n_patterns; i++) {
  1704. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1705. if (!wow_pattern)
  1706. return;
  1707. /*
  1708. * TODO: convert the generic user space pattern to
  1709. * appropriate chip specific/802.11 pattern.
  1710. */
  1711. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1712. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1713. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1714. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1715. patterns[i].pattern_len);
  1716. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1717. wow_pattern->pattern_len = patterns[i].pattern_len;
  1718. /*
  1719. * just need to take care of deauth and disssoc pattern,
  1720. * make sure we don't overwrite them.
  1721. */
  1722. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1723. wow_pattern->mask_bytes,
  1724. i + 2,
  1725. wow_pattern->pattern_len);
  1726. kfree(wow_pattern);
  1727. }
  1728. }
  1729. static int ath9k_suspend(struct ieee80211_hw *hw,
  1730. struct cfg80211_wowlan *wowlan)
  1731. {
  1732. struct ath_softc *sc = hw->priv;
  1733. struct ath_hw *ah = sc->sc_ah;
  1734. struct ath_common *common = ath9k_hw_common(ah);
  1735. u32 wow_triggers_enabled = 0;
  1736. int ret = 0;
  1737. mutex_lock(&sc->mutex);
  1738. ath_cancel_work(sc);
  1739. ath_stop_ani(sc);
  1740. del_timer_sync(&sc->rx_poll_timer);
  1741. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1742. ath_dbg(common, ANY, "Device not present\n");
  1743. ret = -EINVAL;
  1744. goto fail_wow;
  1745. }
  1746. if (WARN_ON(!wowlan)) {
  1747. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1748. ret = -EINVAL;
  1749. goto fail_wow;
  1750. }
  1751. if (!device_can_wakeup(sc->dev)) {
  1752. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1753. ret = 1;
  1754. goto fail_wow;
  1755. }
  1756. /*
  1757. * none of the sta vifs are associated
  1758. * and we are not currently handling multivif
  1759. * cases, for instance we have to seperately
  1760. * configure 'keep alive frame' for each
  1761. * STA.
  1762. */
  1763. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1764. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1765. ret = 1;
  1766. goto fail_wow;
  1767. }
  1768. if (sc->nvifs > 1) {
  1769. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1770. ret = 1;
  1771. goto fail_wow;
  1772. }
  1773. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1774. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1775. wow_triggers_enabled);
  1776. ath9k_ps_wakeup(sc);
  1777. ath9k_stop_btcoex(sc);
  1778. /*
  1779. * Enable wake up on recieving disassoc/deauth
  1780. * frame by default.
  1781. */
  1782. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1783. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1784. ath9k_wow_add_pattern(sc, wowlan);
  1785. spin_lock_bh(&sc->sc_pcu_lock);
  1786. /*
  1787. * To avoid false wake, we enable beacon miss interrupt only
  1788. * when we go to sleep. We save the current interrupt mask
  1789. * so we can restore it after the system wakes up
  1790. */
  1791. sc->wow_intr_before_sleep = ah->imask;
  1792. ah->imask &= ~ATH9K_INT_GLOBAL;
  1793. ath9k_hw_disable_interrupts(ah);
  1794. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1795. ath9k_hw_set_interrupts(ah);
  1796. ath9k_hw_enable_interrupts(ah);
  1797. spin_unlock_bh(&sc->sc_pcu_lock);
  1798. /*
  1799. * we can now sync irq and kill any running tasklets, since we already
  1800. * disabled interrupts and not holding a spin lock
  1801. */
  1802. synchronize_irq(sc->irq);
  1803. tasklet_kill(&sc->intr_tq);
  1804. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1805. ath9k_ps_restore(sc);
  1806. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1807. atomic_inc(&sc->wow_sleep_proc_intr);
  1808. fail_wow:
  1809. mutex_unlock(&sc->mutex);
  1810. return ret;
  1811. }
  1812. static int ath9k_resume(struct ieee80211_hw *hw)
  1813. {
  1814. struct ath_softc *sc = hw->priv;
  1815. struct ath_hw *ah = sc->sc_ah;
  1816. struct ath_common *common = ath9k_hw_common(ah);
  1817. u32 wow_status;
  1818. mutex_lock(&sc->mutex);
  1819. ath9k_ps_wakeup(sc);
  1820. spin_lock_bh(&sc->sc_pcu_lock);
  1821. ath9k_hw_disable_interrupts(ah);
  1822. ah->imask = sc->wow_intr_before_sleep;
  1823. ath9k_hw_set_interrupts(ah);
  1824. ath9k_hw_enable_interrupts(ah);
  1825. spin_unlock_bh(&sc->sc_pcu_lock);
  1826. wow_status = ath9k_hw_wow_wakeup(ah);
  1827. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1828. /*
  1829. * some devices may not pick beacon miss
  1830. * as the reason they woke up so we add
  1831. * that here for that shortcoming.
  1832. */
  1833. wow_status |= AH_WOW_BEACON_MISS;
  1834. atomic_dec(&sc->wow_got_bmiss_intr);
  1835. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1836. }
  1837. atomic_dec(&sc->wow_sleep_proc_intr);
  1838. if (wow_status) {
  1839. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1840. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1841. }
  1842. ath_restart_work(sc);
  1843. ath9k_start_btcoex(sc);
  1844. ath9k_ps_restore(sc);
  1845. mutex_unlock(&sc->mutex);
  1846. return 0;
  1847. }
  1848. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1849. {
  1850. struct ath_softc *sc = hw->priv;
  1851. mutex_lock(&sc->mutex);
  1852. device_init_wakeup(sc->dev, 1);
  1853. device_set_wakeup_enable(sc->dev, enabled);
  1854. mutex_unlock(&sc->mutex);
  1855. }
  1856. #endif
  1857. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1858. {
  1859. struct ath_softc *sc = hw->priv;
  1860. sc->scanning = 1;
  1861. }
  1862. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1863. {
  1864. struct ath_softc *sc = hw->priv;
  1865. sc->scanning = 0;
  1866. }
  1867. struct ieee80211_ops ath9k_ops = {
  1868. .tx = ath9k_tx,
  1869. .start = ath9k_start,
  1870. .stop = ath9k_stop,
  1871. .add_interface = ath9k_add_interface,
  1872. .change_interface = ath9k_change_interface,
  1873. .remove_interface = ath9k_remove_interface,
  1874. .config = ath9k_config,
  1875. .configure_filter = ath9k_configure_filter,
  1876. .sta_add = ath9k_sta_add,
  1877. .sta_remove = ath9k_sta_remove,
  1878. .sta_notify = ath9k_sta_notify,
  1879. .conf_tx = ath9k_conf_tx,
  1880. .bss_info_changed = ath9k_bss_info_changed,
  1881. .set_key = ath9k_set_key,
  1882. .get_tsf = ath9k_get_tsf,
  1883. .set_tsf = ath9k_set_tsf,
  1884. .reset_tsf = ath9k_reset_tsf,
  1885. .ampdu_action = ath9k_ampdu_action,
  1886. .get_survey = ath9k_get_survey,
  1887. .rfkill_poll = ath9k_rfkill_poll_state,
  1888. .set_coverage_class = ath9k_set_coverage_class,
  1889. .flush = ath9k_flush,
  1890. .tx_frames_pending = ath9k_tx_frames_pending,
  1891. .tx_last_beacon = ath9k_tx_last_beacon,
  1892. .get_stats = ath9k_get_stats,
  1893. .set_antenna = ath9k_set_antenna,
  1894. .get_antenna = ath9k_get_antenna,
  1895. #ifdef CONFIG_PM_SLEEP
  1896. .suspend = ath9k_suspend,
  1897. .resume = ath9k_resume,
  1898. .set_wakeup = ath9k_set_wakeup,
  1899. #endif
  1900. #ifdef CONFIG_ATH9K_DEBUGFS
  1901. .get_et_sset_count = ath9k_get_et_sset_count,
  1902. .get_et_stats = ath9k_get_et_stats,
  1903. .get_et_strings = ath9k_get_et_strings,
  1904. #endif
  1905. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  1906. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1907. .sta_remove_debugfs = ath9k_sta_remove_debugfs,
  1908. #endif
  1909. .sw_scan_start = ath9k_sw_scan_start,
  1910. .sw_scan_complete = ath9k_sw_scan_complete,
  1911. };