ar9003_mci.h 11 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef AR9003_MCI_H
  17. #define AR9003_MCI_H
  18. #define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
  19. #define MCI_RECOVERY_DUR_TSF (100 * 1000) /* 100 ms */
  20. /* Default remote BT device MCI COEX version */
  21. #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
  22. #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
  23. /* Local WLAN MCI COEX version */
  24. #define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
  25. #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
  26. enum mci_gpm_coex_query_type {
  27. MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0),
  28. MCI_GPM_COEX_QUERY_BT_TOPOLOGY = BIT(1),
  29. MCI_GPM_COEX_QUERY_BT_DEBUG = BIT(2),
  30. };
  31. enum mci_gpm_coex_halt_bt_gpm {
  32. MCI_GPM_COEX_BT_GPM_UNHALT,
  33. MCI_GPM_COEX_BT_GPM_HALT
  34. };
  35. enum mci_gpm_coex_bt_update_flags_op {
  36. MCI_GPM_COEX_BT_FLAGS_READ,
  37. MCI_GPM_COEX_BT_FLAGS_SET,
  38. MCI_GPM_COEX_BT_FLAGS_CLEAR
  39. };
  40. #define MCI_NUM_BT_CHANNELS 79
  41. #define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
  42. #define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
  43. #define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
  44. #define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
  45. #define MCI_BT_MCI_FLAGS_DEBUG 0x00000020
  46. #define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
  47. #define MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
  48. #define MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
  49. #define MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
  50. #define MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
  51. #define MCI_BT_MCI_FLAGS_AR9462_MODE 0x00001000
  52. #define MCI_BT_MCI_FLAGS_OTHER 0x00010000
  53. #define MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
  54. #define MCI_TOGGLE_BT_MCI_FLAGS (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
  55. MCI_BT_MCI_FLAGS_UPDATE_HDR | \
  56. MCI_BT_MCI_FLAGS_UPDATE_PLD | \
  57. MCI_BT_MCI_FLAGS_MCI_MODE)
  58. #define MCI_2G_FLAGS_CLEAR_MASK 0x00000000
  59. #define MCI_2G_FLAGS_SET_MASK MCI_TOGGLE_BT_MCI_FLAGS
  60. #define MCI_2G_FLAGS MCI_DEFAULT_BT_MCI_FLAGS
  61. #define MCI_5G_FLAGS_CLEAR_MASK MCI_TOGGLE_BT_MCI_FLAGS
  62. #define MCI_5G_FLAGS_SET_MASK 0x00000000
  63. #define MCI_5G_FLAGS (MCI_DEFAULT_BT_MCI_FLAGS & \
  64. ~MCI_TOGGLE_BT_MCI_FLAGS)
  65. /*
  66. * Default value for AR9462 is 0x00002201
  67. */
  68. #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
  69. #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
  70. #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
  71. #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
  72. #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
  73. #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
  74. #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
  75. #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
  76. #define ATH_MCI_CONFIG_AGGR_THRESH_S 8
  77. #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
  78. #define ATH_MCI_CONFIG_CLK_DIV 0x00003000
  79. #define ATH_MCI_CONFIG_CLK_DIV_S 12
  80. #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
  81. #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
  82. #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
  83. #define ATH_MCI_CONFIG_MCI_OBS_MASK (ATH_MCI_CONFIG_MCI_OBS_MCI | \
  84. ATH_MCI_CONFIG_MCI_OBS_TXRX | \
  85. ATH_MCI_CONFIG_MCI_OBS_BT)
  86. #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
  87. enum mci_message_header { /* length of payload */
  88. MCI_LNA_CTRL = 0x10, /* len = 0 */
  89. MCI_CONT_NACK = 0x20, /* len = 0 */
  90. MCI_CONT_INFO = 0x30, /* len = 4 */
  91. MCI_CONT_RST = 0x40, /* len = 0 */
  92. MCI_SCHD_INFO = 0x50, /* len = 16 */
  93. MCI_CPU_INT = 0x60, /* len = 4 */
  94. MCI_SYS_WAKING = 0x70, /* len = 0 */
  95. MCI_GPM = 0x80, /* len = 16 */
  96. MCI_LNA_INFO = 0x90, /* len = 1 */
  97. MCI_LNA_STATE = 0x94,
  98. MCI_LNA_TAKE = 0x98,
  99. MCI_LNA_TRANS = 0x9c,
  100. MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
  101. MCI_REQ_WAKE = 0xc0, /* len = 0 */
  102. MCI_DEBUG_16 = 0xfe, /* len = 2 */
  103. MCI_REMOTE_RESET = 0xff /* len = 16 */
  104. };
  105. enum ath_mci_gpm_coex_profile_type {
  106. MCI_GPM_COEX_PROFILE_UNKNOWN,
  107. MCI_GPM_COEX_PROFILE_RFCOMM,
  108. MCI_GPM_COEX_PROFILE_A2DP,
  109. MCI_GPM_COEX_PROFILE_HID,
  110. MCI_GPM_COEX_PROFILE_BNEP,
  111. MCI_GPM_COEX_PROFILE_VOICE,
  112. MCI_GPM_COEX_PROFILE_A2DPVO,
  113. MCI_GPM_COEX_PROFILE_MAX
  114. };
  115. /* MCI GPM/Coex opcode/type definitions */
  116. enum {
  117. MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
  118. MCI_GPM_COEX_B_GPM_TYPE = 4,
  119. MCI_GPM_COEX_B_GPM_OPCODE = 5,
  120. /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
  121. MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
  122. /* MCI_GPM_COEX_VERSION_QUERY */
  123. /* MCI_GPM_COEX_VERSION_RESPONSE */
  124. MCI_GPM_COEX_B_MAJOR_VERSION = 6,
  125. MCI_GPM_COEX_B_MINOR_VERSION = 7,
  126. /* MCI_GPM_COEX_STATUS_QUERY */
  127. MCI_GPM_COEX_B_BT_BITMAP = 6,
  128. MCI_GPM_COEX_B_WLAN_BITMAP = 7,
  129. /* MCI_GPM_COEX_HALT_BT_GPM */
  130. MCI_GPM_COEX_B_HALT_STATE = 6,
  131. /* MCI_GPM_COEX_WLAN_CHANNELS */
  132. MCI_GPM_COEX_B_CHANNEL_MAP = 6,
  133. /* MCI_GPM_COEX_BT_PROFILE_INFO */
  134. MCI_GPM_COEX_B_PROFILE_TYPE = 6,
  135. MCI_GPM_COEX_B_PROFILE_LINKID = 7,
  136. MCI_GPM_COEX_B_PROFILE_STATE = 8,
  137. MCI_GPM_COEX_B_PROFILE_ROLE = 9,
  138. MCI_GPM_COEX_B_PROFILE_RATE = 10,
  139. MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
  140. MCI_GPM_COEX_H_PROFILE_T = 12,
  141. MCI_GPM_COEX_B_PROFILE_W = 14,
  142. MCI_GPM_COEX_B_PROFILE_A = 15,
  143. /* MCI_GPM_COEX_BT_STATUS_UPDATE */
  144. MCI_GPM_COEX_B_STATUS_TYPE = 6,
  145. MCI_GPM_COEX_B_STATUS_LINKID = 7,
  146. MCI_GPM_COEX_B_STATUS_STATE = 8,
  147. /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
  148. MCI_GPM_COEX_W_BT_FLAGS = 6,
  149. MCI_GPM_COEX_B_BT_FLAGS_OP = 10
  150. };
  151. enum mci_gpm_subtype {
  152. MCI_GPM_BT_CAL_REQ = 0,
  153. MCI_GPM_BT_CAL_GRANT = 1,
  154. MCI_GPM_BT_CAL_DONE = 2,
  155. MCI_GPM_WLAN_CAL_REQ = 3,
  156. MCI_GPM_WLAN_CAL_GRANT = 4,
  157. MCI_GPM_WLAN_CAL_DONE = 5,
  158. MCI_GPM_COEX_AGENT = 0x0c,
  159. MCI_GPM_RSVD_PATTERN = 0xfe,
  160. MCI_GPM_RSVD_PATTERN32 = 0xfefefefe,
  161. MCI_GPM_BT_DEBUG = 0xff
  162. };
  163. enum mci_bt_state {
  164. MCI_BT_SLEEP,
  165. MCI_BT_AWAKE,
  166. MCI_BT_CAL_START,
  167. MCI_BT_CAL
  168. };
  169. /* Type of state query */
  170. enum mci_state_type {
  171. MCI_STATE_ENABLE,
  172. MCI_STATE_SET_BT_AWAKE,
  173. MCI_STATE_LAST_SCHD_MSG_OFFSET,
  174. MCI_STATE_REMOTE_SLEEP,
  175. MCI_STATE_RESET_REQ_WAKE,
  176. MCI_STATE_SEND_WLAN_COEX_VERSION,
  177. MCI_STATE_SEND_VERSION_QUERY,
  178. MCI_STATE_SEND_STATUS_QUERY,
  179. MCI_STATE_RECOVER_RX,
  180. MCI_STATE_NEED_FTP_STOMP,
  181. MCI_STATE_DEBUG,
  182. MCI_STATE_NEED_FLUSH_BT_INFO,
  183. MCI_STATE_MAX
  184. };
  185. enum mci_gpm_coex_opcode {
  186. MCI_GPM_COEX_VERSION_QUERY,
  187. MCI_GPM_COEX_VERSION_RESPONSE,
  188. MCI_GPM_COEX_STATUS_QUERY,
  189. MCI_GPM_COEX_HALT_BT_GPM,
  190. MCI_GPM_COEX_WLAN_CHANNELS,
  191. MCI_GPM_COEX_BT_PROFILE_INFO,
  192. MCI_GPM_COEX_BT_STATUS_UPDATE,
  193. MCI_GPM_COEX_BT_UPDATE_FLAGS,
  194. MCI_GPM_COEX_NOOP,
  195. };
  196. #define MCI_GPM_NOMORE 0
  197. #define MCI_GPM_MORE 1
  198. #define MCI_GPM_INVALID 0xffffffff
  199. #define MCI_GPM_RECYCLE(_p_gpm) do { \
  200. *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
  201. MCI_GPM_RSVD_PATTERN32; \
  202. } while (0)
  203. #define MCI_GPM_TYPE(_p_gpm) \
  204. (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
  205. #define MCI_GPM_OPCODE(_p_gpm) \
  206. (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
  207. #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \
  208. *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
  209. } while (0)
  210. #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \
  211. *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
  212. *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
  213. } while (0)
  214. #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
  215. /*
  216. * Functions that are available to the MCI driver core.
  217. */
  218. bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
  219. u32 *payload, u8 len, bool wait_done,
  220. bool check_bt);
  221. u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type);
  222. int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
  223. u16 len, u32 sched_addr);
  224. void ar9003_mci_cleanup(struct ath_hw *ah);
  225. void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
  226. u32 *rx_msg_intr);
  227. u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, bool first, u32 *more);
  228. void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor);
  229. void ar9003_mci_send_wlan_channels(struct ath_hw *ah);
  230. /*
  231. * These functions are used by ath9k_hw.
  232. */
  233. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  234. void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
  235. void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
  236. void ar9003_mci_init_cal_done(struct ath_hw *ah);
  237. void ar9003_mci_set_full_sleep(struct ath_hw *ah);
  238. void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force);
  239. void ar9003_mci_check_bt(struct ath_hw *ah);
  240. bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
  241. int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  242. struct ath9k_hw_cal_data *caldata);
  243. int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
  244. bool is_full_sleep);
  245. void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
  246. void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah);
  247. void ar9003_mci_set_power_awake(struct ath_hw *ah);
  248. void ar9003_mci_check_gpm_offset(struct ath_hw *ah);
  249. u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode);
  250. #else
  251. static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
  252. {
  253. }
  254. static inline void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
  255. {
  256. }
  257. static inline void ar9003_mci_init_cal_done(struct ath_hw *ah)
  258. {
  259. }
  260. static inline void ar9003_mci_set_full_sleep(struct ath_hw *ah)
  261. {
  262. }
  263. static inline void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
  264. {
  265. }
  266. static inline void ar9003_mci_check_bt(struct ath_hw *ah)
  267. {
  268. }
  269. static inline bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
  270. {
  271. return false;
  272. }
  273. static inline int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  274. struct ath9k_hw_cal_data *caldata)
  275. {
  276. return 0;
  277. }
  278. static inline void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
  279. bool is_full_sleep)
  280. {
  281. }
  282. static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
  283. {
  284. }
  285. static inline void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
  286. {
  287. }
  288. static inline void ar9003_mci_set_power_awake(struct ath_hw *ah)
  289. {
  290. }
  291. static inline void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
  292. {
  293. }
  294. static inline u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode)
  295. {
  296. return -1;
  297. }
  298. #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
  299. #endif