qlcnic_init.c 31 KB

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  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. #include "qlcnic_hw.h"
  9. struct crb_addr_pair {
  10. u32 addr;
  11. u32 data;
  12. };
  13. #define QLCNIC_MAX_CRB_XFORM 60
  14. static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
  15. #define crb_addr_transform(name) \
  16. (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
  17. QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
  18. #define QLCNIC_ADDR_ERROR (0xffffffff)
  19. static int
  20. qlcnic_check_fw_hearbeat(struct qlcnic_adapter *adapter);
  21. static void crb_addr_transform_setup(void)
  22. {
  23. crb_addr_transform(XDMA);
  24. crb_addr_transform(TIMR);
  25. crb_addr_transform(SRE);
  26. crb_addr_transform(SQN3);
  27. crb_addr_transform(SQN2);
  28. crb_addr_transform(SQN1);
  29. crb_addr_transform(SQN0);
  30. crb_addr_transform(SQS3);
  31. crb_addr_transform(SQS2);
  32. crb_addr_transform(SQS1);
  33. crb_addr_transform(SQS0);
  34. crb_addr_transform(RPMX7);
  35. crb_addr_transform(RPMX6);
  36. crb_addr_transform(RPMX5);
  37. crb_addr_transform(RPMX4);
  38. crb_addr_transform(RPMX3);
  39. crb_addr_transform(RPMX2);
  40. crb_addr_transform(RPMX1);
  41. crb_addr_transform(RPMX0);
  42. crb_addr_transform(ROMUSB);
  43. crb_addr_transform(SN);
  44. crb_addr_transform(QMN);
  45. crb_addr_transform(QMS);
  46. crb_addr_transform(PGNI);
  47. crb_addr_transform(PGND);
  48. crb_addr_transform(PGN3);
  49. crb_addr_transform(PGN2);
  50. crb_addr_transform(PGN1);
  51. crb_addr_transform(PGN0);
  52. crb_addr_transform(PGSI);
  53. crb_addr_transform(PGSD);
  54. crb_addr_transform(PGS3);
  55. crb_addr_transform(PGS2);
  56. crb_addr_transform(PGS1);
  57. crb_addr_transform(PGS0);
  58. crb_addr_transform(PS);
  59. crb_addr_transform(PH);
  60. crb_addr_transform(NIU);
  61. crb_addr_transform(I2Q);
  62. crb_addr_transform(EG);
  63. crb_addr_transform(MN);
  64. crb_addr_transform(MS);
  65. crb_addr_transform(CAS2);
  66. crb_addr_transform(CAS1);
  67. crb_addr_transform(CAS0);
  68. crb_addr_transform(CAM);
  69. crb_addr_transform(C2C1);
  70. crb_addr_transform(C2C0);
  71. crb_addr_transform(SMB);
  72. crb_addr_transform(OCM0);
  73. crb_addr_transform(I2C0);
  74. }
  75. void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
  76. {
  77. struct qlcnic_recv_context *recv_ctx;
  78. struct qlcnic_host_rds_ring *rds_ring;
  79. struct qlcnic_rx_buffer *rx_buf;
  80. int i, ring;
  81. recv_ctx = adapter->recv_ctx;
  82. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  83. rds_ring = &recv_ctx->rds_rings[ring];
  84. for (i = 0; i < rds_ring->num_desc; ++i) {
  85. rx_buf = &(rds_ring->rx_buf_arr[i]);
  86. if (rx_buf->skb == NULL)
  87. continue;
  88. pci_unmap_single(adapter->pdev,
  89. rx_buf->dma,
  90. rds_ring->dma_size,
  91. PCI_DMA_FROMDEVICE);
  92. dev_kfree_skb_any(rx_buf->skb);
  93. }
  94. }
  95. }
  96. void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter)
  97. {
  98. struct qlcnic_recv_context *recv_ctx;
  99. struct qlcnic_host_rds_ring *rds_ring;
  100. struct qlcnic_rx_buffer *rx_buf;
  101. int i, ring;
  102. recv_ctx = adapter->recv_ctx;
  103. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  104. rds_ring = &recv_ctx->rds_rings[ring];
  105. INIT_LIST_HEAD(&rds_ring->free_list);
  106. rx_buf = rds_ring->rx_buf_arr;
  107. for (i = 0; i < rds_ring->num_desc; i++) {
  108. list_add_tail(&rx_buf->list,
  109. &rds_ring->free_list);
  110. rx_buf++;
  111. }
  112. }
  113. }
  114. void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
  115. {
  116. struct qlcnic_cmd_buffer *cmd_buf;
  117. struct qlcnic_skb_frag *buffrag;
  118. int i, j;
  119. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  120. cmd_buf = tx_ring->cmd_buf_arr;
  121. for (i = 0; i < tx_ring->num_desc; i++) {
  122. buffrag = cmd_buf->frag_array;
  123. if (buffrag->dma) {
  124. pci_unmap_single(adapter->pdev, buffrag->dma,
  125. buffrag->length, PCI_DMA_TODEVICE);
  126. buffrag->dma = 0ULL;
  127. }
  128. for (j = 0; j < cmd_buf->frag_count; j++) {
  129. buffrag++;
  130. if (buffrag->dma) {
  131. pci_unmap_page(adapter->pdev, buffrag->dma,
  132. buffrag->length,
  133. PCI_DMA_TODEVICE);
  134. buffrag->dma = 0ULL;
  135. }
  136. }
  137. if (cmd_buf->skb) {
  138. dev_kfree_skb_any(cmd_buf->skb);
  139. cmd_buf->skb = NULL;
  140. }
  141. cmd_buf++;
  142. }
  143. }
  144. void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
  145. {
  146. struct qlcnic_recv_context *recv_ctx;
  147. struct qlcnic_host_rds_ring *rds_ring;
  148. int ring;
  149. recv_ctx = adapter->recv_ctx;
  150. if (recv_ctx->rds_rings == NULL)
  151. return;
  152. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  153. rds_ring = &recv_ctx->rds_rings[ring];
  154. vfree(rds_ring->rx_buf_arr);
  155. rds_ring->rx_buf_arr = NULL;
  156. }
  157. kfree(recv_ctx->rds_rings);
  158. }
  159. int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
  160. {
  161. struct qlcnic_recv_context *recv_ctx;
  162. struct qlcnic_host_rds_ring *rds_ring;
  163. struct qlcnic_host_sds_ring *sds_ring;
  164. struct qlcnic_rx_buffer *rx_buf;
  165. int ring, i;
  166. recv_ctx = adapter->recv_ctx;
  167. rds_ring = kcalloc(adapter->max_rds_rings,
  168. sizeof(struct qlcnic_host_rds_ring), GFP_KERNEL);
  169. if (rds_ring == NULL)
  170. goto err_out;
  171. recv_ctx->rds_rings = rds_ring;
  172. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  173. rds_ring = &recv_ctx->rds_rings[ring];
  174. switch (ring) {
  175. case RCV_RING_NORMAL:
  176. rds_ring->num_desc = adapter->num_rxd;
  177. rds_ring->dma_size = QLCNIC_P3P_RX_BUF_MAX_LEN;
  178. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  179. break;
  180. case RCV_RING_JUMBO:
  181. rds_ring->num_desc = adapter->num_jumbo_rxd;
  182. rds_ring->dma_size =
  183. QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN;
  184. if (adapter->ahw->capabilities &
  185. QLCNIC_FW_CAPABILITY_HW_LRO)
  186. rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
  187. rds_ring->skb_size =
  188. rds_ring->dma_size + NET_IP_ALIGN;
  189. break;
  190. }
  191. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  192. if (rds_ring->rx_buf_arr == NULL)
  193. goto err_out;
  194. INIT_LIST_HEAD(&rds_ring->free_list);
  195. /*
  196. * Now go through all of them, set reference handles
  197. * and put them in the queues.
  198. */
  199. rx_buf = rds_ring->rx_buf_arr;
  200. for (i = 0; i < rds_ring->num_desc; i++) {
  201. list_add_tail(&rx_buf->list,
  202. &rds_ring->free_list);
  203. rx_buf->ref_handle = i;
  204. rx_buf++;
  205. }
  206. spin_lock_init(&rds_ring->lock);
  207. }
  208. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  209. sds_ring = &recv_ctx->sds_rings[ring];
  210. sds_ring->irq = adapter->msix_entries[ring].vector;
  211. sds_ring->adapter = adapter;
  212. sds_ring->num_desc = adapter->num_rxd;
  213. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  214. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  215. }
  216. return 0;
  217. err_out:
  218. qlcnic_free_sw_resources(adapter);
  219. return -ENOMEM;
  220. }
  221. /*
  222. * Utility to translate from internal Phantom CRB address
  223. * to external PCI CRB address.
  224. */
  225. static u32 qlcnic_decode_crb_addr(u32 addr)
  226. {
  227. int i;
  228. u32 base_addr, offset, pci_base;
  229. crb_addr_transform_setup();
  230. pci_base = QLCNIC_ADDR_ERROR;
  231. base_addr = addr & 0xfff00000;
  232. offset = addr & 0x000fffff;
  233. for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
  234. if (crb_addr_xform[i] == base_addr) {
  235. pci_base = i << 20;
  236. break;
  237. }
  238. }
  239. if (pci_base == QLCNIC_ADDR_ERROR)
  240. return pci_base;
  241. else
  242. return pci_base + offset;
  243. }
  244. #define QLCNIC_MAX_ROM_WAIT_USEC 100
  245. static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
  246. {
  247. long timeout = 0;
  248. long done = 0;
  249. cond_resched();
  250. while (done == 0) {
  251. done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
  252. done &= 2;
  253. if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
  254. dev_err(&adapter->pdev->dev,
  255. "Timeout reached waiting for rom done");
  256. return -EIO;
  257. }
  258. udelay(1);
  259. }
  260. return 0;
  261. }
  262. static int do_rom_fast_read(struct qlcnic_adapter *adapter,
  263. u32 addr, u32 *valp)
  264. {
  265. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
  266. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  267. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
  268. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  269. if (qlcnic_wait_rom_done(adapter)) {
  270. dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
  271. return -EIO;
  272. }
  273. /* reset abyte_cnt and dummy_byte_cnt */
  274. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
  275. udelay(10);
  276. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  277. *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
  278. return 0;
  279. }
  280. static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  281. u8 *bytes, size_t size)
  282. {
  283. int addridx;
  284. int ret = 0;
  285. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  286. int v;
  287. ret = do_rom_fast_read(adapter, addridx, &v);
  288. if (ret != 0)
  289. break;
  290. *(__le32 *)bytes = cpu_to_le32(v);
  291. bytes += 4;
  292. }
  293. return ret;
  294. }
  295. int
  296. qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  297. u8 *bytes, size_t size)
  298. {
  299. int ret;
  300. ret = qlcnic_rom_lock(adapter);
  301. if (ret < 0)
  302. return ret;
  303. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  304. qlcnic_rom_unlock(adapter);
  305. return ret;
  306. }
  307. int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp)
  308. {
  309. int ret;
  310. if (qlcnic_rom_lock(adapter) != 0)
  311. return -EIO;
  312. ret = do_rom_fast_read(adapter, addr, valp);
  313. qlcnic_rom_unlock(adapter);
  314. return ret;
  315. }
  316. int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
  317. {
  318. int addr, val;
  319. int i, n, init_delay;
  320. struct crb_addr_pair *buf;
  321. unsigned offset;
  322. u32 off;
  323. struct pci_dev *pdev = adapter->pdev;
  324. QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE, 0);
  325. QLC_SHARED_REG_WR32(adapter, QLCNIC_RCVPEG_STATE, 0);
  326. /* Halt all the indiviual PEGs and other blocks */
  327. /* disable all I2Q */
  328. QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x10, 0x0);
  329. QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x14, 0x0);
  330. QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x18, 0x0);
  331. QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x1c, 0x0);
  332. QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x20, 0x0);
  333. QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x24, 0x0);
  334. /* disable all niu interrupts */
  335. QLCWR32(adapter, QLCNIC_CRB_NIU + 0x40, 0xff);
  336. /* disable xge rx/tx */
  337. QLCWR32(adapter, QLCNIC_CRB_NIU + 0x70000, 0x00);
  338. /* disable xg1 rx/tx */
  339. QLCWR32(adapter, QLCNIC_CRB_NIU + 0x80000, 0x00);
  340. /* disable sideband mac */
  341. QLCWR32(adapter, QLCNIC_CRB_NIU + 0x90000, 0x00);
  342. /* disable ap0 mac */
  343. QLCWR32(adapter, QLCNIC_CRB_NIU + 0xa0000, 0x00);
  344. /* disable ap1 mac */
  345. QLCWR32(adapter, QLCNIC_CRB_NIU + 0xb0000, 0x00);
  346. /* halt sre */
  347. val = QLCRD32(adapter, QLCNIC_CRB_SRE + 0x1000);
  348. QLCWR32(adapter, QLCNIC_CRB_SRE + 0x1000, val & (~(0x1)));
  349. /* halt epg */
  350. QLCWR32(adapter, QLCNIC_CRB_EPG + 0x1300, 0x1);
  351. /* halt timers */
  352. QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x0, 0x0);
  353. QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x8, 0x0);
  354. QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x10, 0x0);
  355. QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x18, 0x0);
  356. QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x100, 0x0);
  357. QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x200, 0x0);
  358. /* halt pegs */
  359. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x3c, 1);
  360. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x3c, 1);
  361. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x3c, 1);
  362. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x3c, 1);
  363. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x3c, 1);
  364. msleep(20);
  365. qlcnic_rom_unlock(adapter);
  366. /* big hammer don't reset CAM block on reset */
  367. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  368. /* Init HW CRB block */
  369. if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
  370. qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
  371. dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
  372. return -EIO;
  373. }
  374. offset = n & 0xffffU;
  375. n = (n >> 16) & 0xffffU;
  376. if (n >= 1024) {
  377. dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
  378. return -EIO;
  379. }
  380. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  381. if (buf == NULL)
  382. return -ENOMEM;
  383. for (i = 0; i < n; i++) {
  384. if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  385. qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  386. kfree(buf);
  387. return -EIO;
  388. }
  389. buf[i].addr = addr;
  390. buf[i].data = val;
  391. }
  392. for (i = 0; i < n; i++) {
  393. off = qlcnic_decode_crb_addr(buf[i].addr);
  394. if (off == QLCNIC_ADDR_ERROR) {
  395. dev_err(&pdev->dev, "CRB init value out of range %x\n",
  396. buf[i].addr);
  397. continue;
  398. }
  399. off += QLCNIC_PCI_CRBSPACE;
  400. if (off & 1)
  401. continue;
  402. /* skipping cold reboot MAGIC */
  403. if (off == QLCNIC_CAM_RAM(0x1fc))
  404. continue;
  405. if (off == (QLCNIC_CRB_I2C0 + 0x1c))
  406. continue;
  407. if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
  408. continue;
  409. if (off == (ROMUSB_GLB + 0xa8))
  410. continue;
  411. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  412. continue;
  413. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  414. continue;
  415. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  416. continue;
  417. if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
  418. continue;
  419. /* skip the function enable register */
  420. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
  421. continue;
  422. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
  423. continue;
  424. if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
  425. continue;
  426. init_delay = 1;
  427. /* After writing this register, HW needs time for CRB */
  428. /* to quiet down (else crb_window returns 0xffffffff) */
  429. if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
  430. init_delay = 1000;
  431. QLCWR32(adapter, off, buf[i].data);
  432. msleep(init_delay);
  433. }
  434. kfree(buf);
  435. /* Initialize protocol process engine */
  436. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
  437. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
  438. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
  439. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
  440. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
  441. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
  442. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
  443. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
  444. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
  445. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
  446. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
  447. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0);
  448. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0);
  449. msleep(1);
  450. QLC_SHARED_REG_WR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0);
  451. QLC_SHARED_REG_WR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0);
  452. return 0;
  453. }
  454. static int qlcnic_cmd_peg_ready(struct qlcnic_adapter *adapter)
  455. {
  456. u32 val;
  457. int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
  458. do {
  459. val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CMDPEG_STATE);
  460. switch (val) {
  461. case PHAN_INITIALIZE_COMPLETE:
  462. case PHAN_INITIALIZE_ACK:
  463. return 0;
  464. case PHAN_INITIALIZE_FAILED:
  465. goto out_err;
  466. default:
  467. break;
  468. }
  469. msleep(QLCNIC_CMDPEG_CHECK_DELAY);
  470. } while (--retries);
  471. QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE,
  472. PHAN_INITIALIZE_FAILED);
  473. out_err:
  474. dev_err(&adapter->pdev->dev, "Command Peg initialization not "
  475. "complete, state: 0x%x.\n", val);
  476. return -EIO;
  477. }
  478. static int
  479. qlcnic_receive_peg_ready(struct qlcnic_adapter *adapter)
  480. {
  481. u32 val;
  482. int retries = QLCNIC_RCVPEG_CHECK_RETRY_COUNT;
  483. do {
  484. val = QLC_SHARED_REG_RD32(adapter, QLCNIC_RCVPEG_STATE);
  485. if (val == PHAN_PEG_RCV_INITIALIZED)
  486. return 0;
  487. msleep(QLCNIC_RCVPEG_CHECK_DELAY);
  488. } while (--retries);
  489. if (!retries) {
  490. dev_err(&adapter->pdev->dev, "Receive Peg initialization not "
  491. "complete, state: 0x%x.\n", val);
  492. return -EIO;
  493. }
  494. return 0;
  495. }
  496. int
  497. qlcnic_check_fw_status(struct qlcnic_adapter *adapter)
  498. {
  499. int err;
  500. err = qlcnic_cmd_peg_ready(adapter);
  501. if (err)
  502. return err;
  503. err = qlcnic_receive_peg_ready(adapter);
  504. if (err)
  505. return err;
  506. QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  507. return err;
  508. }
  509. int
  510. qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
  511. int timeo;
  512. u32 val;
  513. val = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO);
  514. val = QLC_DEV_GET_DRV(val, adapter->portnum);
  515. if ((val & 0x3) != QLCNIC_TYPE_NIC) {
  516. dev_err(&adapter->pdev->dev,
  517. "Not an Ethernet NIC func=%u\n", val);
  518. return -EIO;
  519. }
  520. adapter->ahw->physical_port = (val >> 2);
  521. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
  522. timeo = QLCNIC_INIT_TIMEOUT_SECS;
  523. adapter->dev_init_timeo = timeo;
  524. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
  525. timeo = QLCNIC_RESET_TIMEOUT_SECS;
  526. adapter->reset_ack_timeo = timeo;
  527. return 0;
  528. }
  529. static int qlcnic_get_flt_entry(struct qlcnic_adapter *adapter, u8 region,
  530. struct qlcnic_flt_entry *region_entry)
  531. {
  532. struct qlcnic_flt_header flt_hdr;
  533. struct qlcnic_flt_entry *flt_entry;
  534. int i = 0, ret;
  535. u32 entry_size;
  536. memset(region_entry, 0, sizeof(struct qlcnic_flt_entry));
  537. ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION,
  538. (u8 *)&flt_hdr,
  539. sizeof(struct qlcnic_flt_header));
  540. if (ret) {
  541. dev_warn(&adapter->pdev->dev,
  542. "error reading flash layout header\n");
  543. return -EIO;
  544. }
  545. entry_size = flt_hdr.len - sizeof(struct qlcnic_flt_header);
  546. flt_entry = vzalloc(entry_size);
  547. if (flt_entry == NULL)
  548. return -EIO;
  549. ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION +
  550. sizeof(struct qlcnic_flt_header),
  551. (u8 *)flt_entry, entry_size);
  552. if (ret) {
  553. dev_warn(&adapter->pdev->dev,
  554. "error reading flash layout entries\n");
  555. goto err_out;
  556. }
  557. while (i < (entry_size/sizeof(struct qlcnic_flt_entry))) {
  558. if (flt_entry[i].region == region)
  559. break;
  560. i++;
  561. }
  562. if (i >= (entry_size/sizeof(struct qlcnic_flt_entry))) {
  563. dev_warn(&adapter->pdev->dev,
  564. "region=%x not found in %d regions\n", region, i);
  565. ret = -EIO;
  566. goto err_out;
  567. }
  568. memcpy(region_entry, &flt_entry[i], sizeof(struct qlcnic_flt_entry));
  569. err_out:
  570. vfree(flt_entry);
  571. return ret;
  572. }
  573. int
  574. qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
  575. {
  576. struct qlcnic_flt_entry fw_entry;
  577. u32 ver = -1, min_ver;
  578. int ret;
  579. if (adapter->ahw->revision_id == QLCNIC_P3P_C0)
  580. ret = qlcnic_get_flt_entry(adapter, QLCNIC_C0_FW_IMAGE_REGION,
  581. &fw_entry);
  582. else
  583. ret = qlcnic_get_flt_entry(adapter, QLCNIC_B0_FW_IMAGE_REGION,
  584. &fw_entry);
  585. if (!ret)
  586. /* 0-4:-signature, 4-8:-fw version */
  587. qlcnic_rom_fast_read(adapter, fw_entry.start_addr + 4,
  588. (int *)&ver);
  589. else
  590. qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET,
  591. (int *)&ver);
  592. ver = QLCNIC_DECODE_VERSION(ver);
  593. min_ver = QLCNIC_MIN_FW_VERSION;
  594. if (ver < min_ver) {
  595. dev_err(&adapter->pdev->dev,
  596. "firmware version %d.%d.%d unsupported."
  597. "Min supported version %d.%d.%d\n",
  598. _major(ver), _minor(ver), _build(ver),
  599. _major(min_ver), _minor(min_ver), _build(min_ver));
  600. return -EINVAL;
  601. }
  602. return 0;
  603. }
  604. static int
  605. qlcnic_has_mn(struct qlcnic_adapter *adapter)
  606. {
  607. u32 capability;
  608. capability = 0;
  609. capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
  610. if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
  611. return 1;
  612. return 0;
  613. }
  614. static
  615. struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
  616. {
  617. u32 i, entries;
  618. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  619. entries = le32_to_cpu(directory->num_entries);
  620. for (i = 0; i < entries; i++) {
  621. u32 offs = le32_to_cpu(directory->findex) +
  622. i * le32_to_cpu(directory->entry_size);
  623. u32 tab_type = le32_to_cpu(*((__le32 *)&unirom[offs] + 8));
  624. if (tab_type == section)
  625. return (struct uni_table_desc *) &unirom[offs];
  626. }
  627. return NULL;
  628. }
  629. #define FILEHEADER_SIZE (14 * 4)
  630. static int
  631. qlcnic_validate_header(struct qlcnic_adapter *adapter)
  632. {
  633. const u8 *unirom = adapter->fw->data;
  634. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  635. u32 entries, entry_size, tab_size, fw_file_size;
  636. fw_file_size = adapter->fw->size;
  637. if (fw_file_size < FILEHEADER_SIZE)
  638. return -EINVAL;
  639. entries = le32_to_cpu(directory->num_entries);
  640. entry_size = le32_to_cpu(directory->entry_size);
  641. tab_size = le32_to_cpu(directory->findex) + (entries * entry_size);
  642. if (fw_file_size < tab_size)
  643. return -EINVAL;
  644. return 0;
  645. }
  646. static int
  647. qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
  648. {
  649. struct uni_table_desc *tab_desc;
  650. struct uni_data_desc *descr;
  651. u32 offs, tab_size, data_size, idx;
  652. const u8 *unirom = adapter->fw->data;
  653. __le32 temp;
  654. temp = *((__le32 *)&unirom[adapter->file_prd_off] +
  655. QLCNIC_UNI_BOOTLD_IDX_OFF);
  656. idx = le32_to_cpu(temp);
  657. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
  658. if (!tab_desc)
  659. return -EINVAL;
  660. tab_size = le32_to_cpu(tab_desc->findex) +
  661. le32_to_cpu(tab_desc->entry_size) * (idx + 1);
  662. if (adapter->fw->size < tab_size)
  663. return -EINVAL;
  664. offs = le32_to_cpu(tab_desc->findex) +
  665. le32_to_cpu(tab_desc->entry_size) * idx;
  666. descr = (struct uni_data_desc *)&unirom[offs];
  667. data_size = le32_to_cpu(descr->findex) + le32_to_cpu(descr->size);
  668. if (adapter->fw->size < data_size)
  669. return -EINVAL;
  670. return 0;
  671. }
  672. static int
  673. qlcnic_validate_fw(struct qlcnic_adapter *adapter)
  674. {
  675. struct uni_table_desc *tab_desc;
  676. struct uni_data_desc *descr;
  677. const u8 *unirom = adapter->fw->data;
  678. u32 offs, tab_size, data_size, idx;
  679. __le32 temp;
  680. temp = *((__le32 *)&unirom[adapter->file_prd_off] +
  681. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  682. idx = le32_to_cpu(temp);
  683. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
  684. if (!tab_desc)
  685. return -EINVAL;
  686. tab_size = le32_to_cpu(tab_desc->findex) +
  687. le32_to_cpu(tab_desc->entry_size) * (idx + 1);
  688. if (adapter->fw->size < tab_size)
  689. return -EINVAL;
  690. offs = le32_to_cpu(tab_desc->findex) +
  691. le32_to_cpu(tab_desc->entry_size) * idx;
  692. descr = (struct uni_data_desc *)&unirom[offs];
  693. data_size = le32_to_cpu(descr->findex) + le32_to_cpu(descr->size);
  694. if (adapter->fw->size < data_size)
  695. return -EINVAL;
  696. return 0;
  697. }
  698. static int
  699. qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
  700. {
  701. struct uni_table_desc *ptab_descr;
  702. const u8 *unirom = adapter->fw->data;
  703. int mn_present = qlcnic_has_mn(adapter);
  704. u32 entries, entry_size, tab_size, i;
  705. __le32 temp;
  706. ptab_descr = qlcnic_get_table_desc(unirom,
  707. QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
  708. if (!ptab_descr)
  709. return -EINVAL;
  710. entries = le32_to_cpu(ptab_descr->num_entries);
  711. entry_size = le32_to_cpu(ptab_descr->entry_size);
  712. tab_size = le32_to_cpu(ptab_descr->findex) + (entries * entry_size);
  713. if (adapter->fw->size < tab_size)
  714. return -EINVAL;
  715. nomn:
  716. for (i = 0; i < entries; i++) {
  717. u32 flags, file_chiprev, offs;
  718. u8 chiprev = adapter->ahw->revision_id;
  719. u32 flagbit;
  720. offs = le32_to_cpu(ptab_descr->findex) +
  721. i * le32_to_cpu(ptab_descr->entry_size);
  722. temp = *((__le32 *)&unirom[offs] + QLCNIC_UNI_FLAGS_OFF);
  723. flags = le32_to_cpu(temp);
  724. temp = *((__le32 *)&unirom[offs] + QLCNIC_UNI_CHIP_REV_OFF);
  725. file_chiprev = le32_to_cpu(temp);
  726. flagbit = mn_present ? 1 : 2;
  727. if ((chiprev == file_chiprev) &&
  728. ((1ULL << flagbit) & flags)) {
  729. adapter->file_prd_off = offs;
  730. return 0;
  731. }
  732. }
  733. if (mn_present) {
  734. mn_present = 0;
  735. goto nomn;
  736. }
  737. return -EINVAL;
  738. }
  739. static int
  740. qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
  741. {
  742. if (qlcnic_validate_header(adapter)) {
  743. dev_err(&adapter->pdev->dev,
  744. "unified image: header validation failed\n");
  745. return -EINVAL;
  746. }
  747. if (qlcnic_validate_product_offs(adapter)) {
  748. dev_err(&adapter->pdev->dev,
  749. "unified image: product validation failed\n");
  750. return -EINVAL;
  751. }
  752. if (qlcnic_validate_bootld(adapter)) {
  753. dev_err(&adapter->pdev->dev,
  754. "unified image: bootld validation failed\n");
  755. return -EINVAL;
  756. }
  757. if (qlcnic_validate_fw(adapter)) {
  758. dev_err(&adapter->pdev->dev,
  759. "unified image: firmware validation failed\n");
  760. return -EINVAL;
  761. }
  762. return 0;
  763. }
  764. static
  765. struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
  766. u32 section, u32 idx_offset)
  767. {
  768. const u8 *unirom = adapter->fw->data;
  769. struct uni_table_desc *tab_desc;
  770. u32 offs, idx;
  771. __le32 temp;
  772. temp = *((__le32 *)&unirom[adapter->file_prd_off] + idx_offset);
  773. idx = le32_to_cpu(temp);
  774. tab_desc = qlcnic_get_table_desc(unirom, section);
  775. if (tab_desc == NULL)
  776. return NULL;
  777. offs = le32_to_cpu(tab_desc->findex) +
  778. le32_to_cpu(tab_desc->entry_size) * idx;
  779. return (struct uni_data_desc *)&unirom[offs];
  780. }
  781. static u8 *
  782. qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
  783. {
  784. u32 offs = QLCNIC_BOOTLD_START;
  785. struct uni_data_desc *data_desc;
  786. data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_BOOTLD,
  787. QLCNIC_UNI_BOOTLD_IDX_OFF);
  788. if (adapter->ahw->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  789. offs = le32_to_cpu(data_desc->findex);
  790. return (u8 *)&adapter->fw->data[offs];
  791. }
  792. static u8 *
  793. qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
  794. {
  795. u32 offs = QLCNIC_IMAGE_START;
  796. struct uni_data_desc *data_desc;
  797. data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  798. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  799. if (adapter->ahw->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  800. offs = le32_to_cpu(data_desc->findex);
  801. return (u8 *)&adapter->fw->data[offs];
  802. }
  803. static u32 qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
  804. {
  805. struct uni_data_desc *data_desc;
  806. const u8 *unirom = adapter->fw->data;
  807. data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  808. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  809. if (adapter->ahw->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  810. return le32_to_cpu(data_desc->size);
  811. else
  812. return le32_to_cpu(*(__le32 *)&unirom[QLCNIC_FW_SIZE_OFFSET]);
  813. }
  814. static u32 qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
  815. {
  816. struct uni_data_desc *fw_data_desc;
  817. const struct firmware *fw = adapter->fw;
  818. u32 major, minor, sub;
  819. __le32 version_offset;
  820. const u8 *ver_str;
  821. int i, ret;
  822. if (adapter->ahw->fw_type != QLCNIC_UNIFIED_ROMIMAGE) {
  823. version_offset = *(__le32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET];
  824. return le32_to_cpu(version_offset);
  825. }
  826. fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  827. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  828. ver_str = fw->data + le32_to_cpu(fw_data_desc->findex) +
  829. le32_to_cpu(fw_data_desc->size) - 17;
  830. for (i = 0; i < 12; i++) {
  831. if (!strncmp(&ver_str[i], "REV=", 4)) {
  832. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  833. &major, &minor, &sub);
  834. if (ret != 3)
  835. return 0;
  836. else
  837. return major + (minor << 8) + (sub << 16);
  838. }
  839. }
  840. return 0;
  841. }
  842. static u32 qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
  843. {
  844. const struct firmware *fw = adapter->fw;
  845. u32 bios_ver, prd_off = adapter->file_prd_off;
  846. u8 *version_offset;
  847. __le32 temp;
  848. if (adapter->ahw->fw_type != QLCNIC_UNIFIED_ROMIMAGE) {
  849. version_offset = (u8 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET];
  850. return le32_to_cpu(*(__le32 *)version_offset);
  851. }
  852. temp = *((__le32 *)(&fw->data[prd_off]) + QLCNIC_UNI_BIOS_VERSION_OFF);
  853. bios_ver = le32_to_cpu(temp);
  854. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
  855. }
  856. static void qlcnic_rom_lock_recovery(struct qlcnic_adapter *adapter)
  857. {
  858. if (qlcnic_pcie_sem_lock(adapter, 2, QLCNIC_ROM_LOCK_ID))
  859. dev_info(&adapter->pdev->dev, "Resetting rom_lock\n");
  860. qlcnic_pcie_sem_unlock(adapter, 2);
  861. }
  862. static int
  863. qlcnic_check_fw_hearbeat(struct qlcnic_adapter *adapter)
  864. {
  865. u32 heartbeat, ret = -EIO;
  866. int retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
  867. adapter->heartbeat = QLC_SHARED_REG_RD32(adapter,
  868. QLCNIC_PEG_ALIVE_COUNTER);
  869. do {
  870. msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
  871. heartbeat = QLC_SHARED_REG_RD32(adapter,
  872. QLCNIC_PEG_ALIVE_COUNTER);
  873. if (heartbeat != adapter->heartbeat) {
  874. ret = QLCNIC_RCODE_SUCCESS;
  875. break;
  876. }
  877. } while (--retries);
  878. return ret;
  879. }
  880. int
  881. qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
  882. {
  883. if ((adapter->flags & QLCNIC_FW_HANG) ||
  884. qlcnic_check_fw_hearbeat(adapter)) {
  885. qlcnic_rom_lock_recovery(adapter);
  886. return 1;
  887. }
  888. if (adapter->need_fw_reset)
  889. return 1;
  890. if (adapter->fw)
  891. return 1;
  892. return 0;
  893. }
  894. static const char *fw_name[] = {
  895. QLCNIC_UNIFIED_ROMIMAGE_NAME,
  896. QLCNIC_FLASH_ROMIMAGE_NAME,
  897. };
  898. int
  899. qlcnic_load_firmware(struct qlcnic_adapter *adapter)
  900. {
  901. __le64 *ptr64;
  902. u32 i, flashaddr, size;
  903. const struct firmware *fw = adapter->fw;
  904. struct pci_dev *pdev = adapter->pdev;
  905. dev_info(&pdev->dev, "loading firmware from %s\n",
  906. fw_name[adapter->ahw->fw_type]);
  907. if (fw) {
  908. u64 data;
  909. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  910. ptr64 = (__le64 *)qlcnic_get_bootld_offs(adapter);
  911. flashaddr = QLCNIC_BOOTLD_START;
  912. for (i = 0; i < size; i++) {
  913. data = le64_to_cpu(ptr64[i]);
  914. if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
  915. return -EIO;
  916. flashaddr += 8;
  917. }
  918. size = qlcnic_get_fw_size(adapter) / 8;
  919. ptr64 = (__le64 *)qlcnic_get_fw_offs(adapter);
  920. flashaddr = QLCNIC_IMAGE_START;
  921. for (i = 0; i < size; i++) {
  922. data = le64_to_cpu(ptr64[i]);
  923. if (qlcnic_pci_mem_write_2M(adapter,
  924. flashaddr, data))
  925. return -EIO;
  926. flashaddr += 8;
  927. }
  928. size = qlcnic_get_fw_size(adapter) % 8;
  929. if (size) {
  930. data = le64_to_cpu(ptr64[i]);
  931. if (qlcnic_pci_mem_write_2M(adapter,
  932. flashaddr, data))
  933. return -EIO;
  934. }
  935. } else {
  936. u64 data;
  937. u32 hi, lo;
  938. int ret;
  939. struct qlcnic_flt_entry bootld_entry;
  940. ret = qlcnic_get_flt_entry(adapter, QLCNIC_BOOTLD_REGION,
  941. &bootld_entry);
  942. if (!ret) {
  943. size = bootld_entry.size / 8;
  944. flashaddr = bootld_entry.start_addr;
  945. } else {
  946. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  947. flashaddr = QLCNIC_BOOTLD_START;
  948. dev_info(&pdev->dev,
  949. "using legacy method to get flash fw region");
  950. }
  951. for (i = 0; i < size; i++) {
  952. if (qlcnic_rom_fast_read(adapter,
  953. flashaddr, (int *)&lo) != 0)
  954. return -EIO;
  955. if (qlcnic_rom_fast_read(adapter,
  956. flashaddr + 4, (int *)&hi) != 0)
  957. return -EIO;
  958. data = (((u64)hi << 32) | lo);
  959. if (qlcnic_pci_mem_write_2M(adapter,
  960. flashaddr, data))
  961. return -EIO;
  962. flashaddr += 8;
  963. }
  964. }
  965. msleep(1);
  966. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
  967. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
  968. return 0;
  969. }
  970. static int
  971. qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
  972. {
  973. u32 val;
  974. u32 ver, bios, min_size;
  975. struct pci_dev *pdev = adapter->pdev;
  976. const struct firmware *fw = adapter->fw;
  977. u8 fw_type = adapter->ahw->fw_type;
  978. if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
  979. if (qlcnic_validate_unified_romimage(adapter))
  980. return -EINVAL;
  981. min_size = QLCNIC_UNI_FW_MIN_SIZE;
  982. } else {
  983. val = le32_to_cpu(*(__le32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
  984. if (val != QLCNIC_BDINFO_MAGIC)
  985. return -EINVAL;
  986. min_size = QLCNIC_FW_MIN_SIZE;
  987. }
  988. if (fw->size < min_size)
  989. return -EINVAL;
  990. val = qlcnic_get_fw_version(adapter);
  991. ver = QLCNIC_DECODE_VERSION(val);
  992. if (ver < QLCNIC_MIN_FW_VERSION) {
  993. dev_err(&pdev->dev,
  994. "%s: firmware version %d.%d.%d unsupported\n",
  995. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  996. return -EINVAL;
  997. }
  998. val = qlcnic_get_bios_version(adapter);
  999. qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
  1000. if (val != bios) {
  1001. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  1002. fw_name[fw_type]);
  1003. return -EINVAL;
  1004. }
  1005. QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, QLCNIC_BDINFO_MAGIC);
  1006. return 0;
  1007. }
  1008. static void
  1009. qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
  1010. {
  1011. u8 fw_type;
  1012. switch (adapter->ahw->fw_type) {
  1013. case QLCNIC_UNKNOWN_ROMIMAGE:
  1014. fw_type = QLCNIC_UNIFIED_ROMIMAGE;
  1015. break;
  1016. case QLCNIC_UNIFIED_ROMIMAGE:
  1017. default:
  1018. fw_type = QLCNIC_FLASH_ROMIMAGE;
  1019. break;
  1020. }
  1021. adapter->ahw->fw_type = fw_type;
  1022. }
  1023. void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
  1024. {
  1025. struct pci_dev *pdev = adapter->pdev;
  1026. int rc;
  1027. adapter->ahw->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
  1028. next:
  1029. qlcnic_get_next_fwtype(adapter);
  1030. if (adapter->ahw->fw_type == QLCNIC_FLASH_ROMIMAGE) {
  1031. adapter->fw = NULL;
  1032. } else {
  1033. rc = request_firmware(&adapter->fw,
  1034. fw_name[adapter->ahw->fw_type],
  1035. &pdev->dev);
  1036. if (rc != 0)
  1037. goto next;
  1038. rc = qlcnic_validate_firmware(adapter);
  1039. if (rc != 0) {
  1040. release_firmware(adapter->fw);
  1041. msleep(1);
  1042. goto next;
  1043. }
  1044. }
  1045. }
  1046. void
  1047. qlcnic_release_firmware(struct qlcnic_adapter *adapter)
  1048. {
  1049. release_firmware(adapter->fw);
  1050. adapter->fw = NULL;
  1051. }