netxen_nic_init.c 46 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include <linux/if_vlan.h>
  29. #include "netxen_nic.h"
  30. #include "netxen_nic_hw.h"
  31. struct crb_addr_pair {
  32. u32 addr;
  33. u32 data;
  34. };
  35. #define NETXEN_MAX_CRB_XFORM 60
  36. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  37. #define NETXEN_ADDR_ERROR (0xffffffff)
  38. #define crb_addr_transform(name) \
  39. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  40. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  41. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  42. static void
  43. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  44. struct nx_host_rds_ring *rds_ring);
  45. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  46. static void crb_addr_transform_setup(void)
  47. {
  48. crb_addr_transform(XDMA);
  49. crb_addr_transform(TIMR);
  50. crb_addr_transform(SRE);
  51. crb_addr_transform(SQN3);
  52. crb_addr_transform(SQN2);
  53. crb_addr_transform(SQN1);
  54. crb_addr_transform(SQN0);
  55. crb_addr_transform(SQS3);
  56. crb_addr_transform(SQS2);
  57. crb_addr_transform(SQS1);
  58. crb_addr_transform(SQS0);
  59. crb_addr_transform(RPMX7);
  60. crb_addr_transform(RPMX6);
  61. crb_addr_transform(RPMX5);
  62. crb_addr_transform(RPMX4);
  63. crb_addr_transform(RPMX3);
  64. crb_addr_transform(RPMX2);
  65. crb_addr_transform(RPMX1);
  66. crb_addr_transform(RPMX0);
  67. crb_addr_transform(ROMUSB);
  68. crb_addr_transform(SN);
  69. crb_addr_transform(QMN);
  70. crb_addr_transform(QMS);
  71. crb_addr_transform(PGNI);
  72. crb_addr_transform(PGND);
  73. crb_addr_transform(PGN3);
  74. crb_addr_transform(PGN2);
  75. crb_addr_transform(PGN1);
  76. crb_addr_transform(PGN0);
  77. crb_addr_transform(PGSI);
  78. crb_addr_transform(PGSD);
  79. crb_addr_transform(PGS3);
  80. crb_addr_transform(PGS2);
  81. crb_addr_transform(PGS1);
  82. crb_addr_transform(PGS0);
  83. crb_addr_transform(PS);
  84. crb_addr_transform(PH);
  85. crb_addr_transform(NIU);
  86. crb_addr_transform(I2Q);
  87. crb_addr_transform(EG);
  88. crb_addr_transform(MN);
  89. crb_addr_transform(MS);
  90. crb_addr_transform(CAS2);
  91. crb_addr_transform(CAS1);
  92. crb_addr_transform(CAS0);
  93. crb_addr_transform(CAM);
  94. crb_addr_transform(C2C1);
  95. crb_addr_transform(C2C0);
  96. crb_addr_transform(SMB);
  97. crb_addr_transform(OCM0);
  98. crb_addr_transform(I2C0);
  99. }
  100. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  101. {
  102. struct netxen_recv_context *recv_ctx;
  103. struct nx_host_rds_ring *rds_ring;
  104. struct netxen_rx_buffer *rx_buf;
  105. int i, ring;
  106. recv_ctx = &adapter->recv_ctx;
  107. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  108. rds_ring = &recv_ctx->rds_rings[ring];
  109. for (i = 0; i < rds_ring->num_desc; ++i) {
  110. rx_buf = &(rds_ring->rx_buf_arr[i]);
  111. if (rx_buf->state == NETXEN_BUFFER_FREE)
  112. continue;
  113. pci_unmap_single(adapter->pdev,
  114. rx_buf->dma,
  115. rds_ring->dma_size,
  116. PCI_DMA_FROMDEVICE);
  117. if (rx_buf->skb != NULL)
  118. dev_kfree_skb_any(rx_buf->skb);
  119. }
  120. }
  121. }
  122. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  123. {
  124. struct netxen_cmd_buffer *cmd_buf;
  125. struct netxen_skb_frag *buffrag;
  126. int i, j;
  127. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  128. cmd_buf = tx_ring->cmd_buf_arr;
  129. for (i = 0; i < tx_ring->num_desc; i++) {
  130. buffrag = cmd_buf->frag_array;
  131. if (buffrag->dma) {
  132. pci_unmap_single(adapter->pdev, buffrag->dma,
  133. buffrag->length, PCI_DMA_TODEVICE);
  134. buffrag->dma = 0ULL;
  135. }
  136. for (j = 1; j < cmd_buf->frag_count; j++) {
  137. buffrag++;
  138. if (buffrag->dma) {
  139. pci_unmap_page(adapter->pdev, buffrag->dma,
  140. buffrag->length,
  141. PCI_DMA_TODEVICE);
  142. buffrag->dma = 0ULL;
  143. }
  144. }
  145. if (cmd_buf->skb) {
  146. dev_kfree_skb_any(cmd_buf->skb);
  147. cmd_buf->skb = NULL;
  148. }
  149. cmd_buf++;
  150. }
  151. }
  152. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  153. {
  154. struct netxen_recv_context *recv_ctx;
  155. struct nx_host_rds_ring *rds_ring;
  156. struct nx_host_tx_ring *tx_ring;
  157. int ring;
  158. recv_ctx = &adapter->recv_ctx;
  159. if (recv_ctx->rds_rings == NULL)
  160. goto skip_rds;
  161. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  162. rds_ring = &recv_ctx->rds_rings[ring];
  163. vfree(rds_ring->rx_buf_arr);
  164. rds_ring->rx_buf_arr = NULL;
  165. }
  166. kfree(recv_ctx->rds_rings);
  167. skip_rds:
  168. if (adapter->tx_ring == NULL)
  169. return;
  170. tx_ring = adapter->tx_ring;
  171. vfree(tx_ring->cmd_buf_arr);
  172. kfree(tx_ring);
  173. adapter->tx_ring = NULL;
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. tx_ring = kzalloc(sizeof(struct nx_host_tx_ring), GFP_KERNEL);
  186. if (tx_ring == NULL)
  187. return -ENOMEM;
  188. adapter->tx_ring = tx_ring;
  189. tx_ring->num_desc = adapter->num_txd;
  190. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  191. cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
  192. if (cmd_buf_arr == NULL)
  193. goto err_out;
  194. tx_ring->cmd_buf_arr = cmd_buf_arr;
  195. recv_ctx = &adapter->recv_ctx;
  196. rds_ring = kcalloc(adapter->max_rds_rings,
  197. sizeof(struct nx_host_rds_ring), GFP_KERNEL);
  198. if (rds_ring == NULL)
  199. goto err_out;
  200. recv_ctx->rds_rings = rds_ring;
  201. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  202. rds_ring = &recv_ctx->rds_rings[ring];
  203. switch (ring) {
  204. case RCV_RING_NORMAL:
  205. rds_ring->num_desc = adapter->num_rxd;
  206. if (adapter->ahw.cut_through) {
  207. rds_ring->dma_size =
  208. NX_CT_DEFAULT_RX_BUF_LEN;
  209. rds_ring->skb_size =
  210. NX_CT_DEFAULT_RX_BUF_LEN;
  211. } else {
  212. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  213. rds_ring->dma_size =
  214. NX_P3_RX_BUF_MAX_LEN;
  215. else
  216. rds_ring->dma_size =
  217. NX_P2_RX_BUF_MAX_LEN;
  218. rds_ring->skb_size =
  219. rds_ring->dma_size + NET_IP_ALIGN;
  220. }
  221. break;
  222. case RCV_RING_JUMBO:
  223. rds_ring->num_desc = adapter->num_jumbo_rxd;
  224. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  225. rds_ring->dma_size =
  226. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  227. else
  228. rds_ring->dma_size =
  229. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  230. if (adapter->capabilities & NX_CAP0_HW_LRO)
  231. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  232. rds_ring->skb_size =
  233. rds_ring->dma_size + NET_IP_ALIGN;
  234. break;
  235. case RCV_RING_LRO:
  236. rds_ring->num_desc = adapter->num_lro_rxd;
  237. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  238. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  239. break;
  240. }
  241. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  242. if (rds_ring->rx_buf_arr == NULL)
  243. /* free whatever was already allocated */
  244. goto err_out;
  245. INIT_LIST_HEAD(&rds_ring->free_list);
  246. /*
  247. * Now go through all of them, set reference handles
  248. * and put them in the queues.
  249. */
  250. rx_buf = rds_ring->rx_buf_arr;
  251. for (i = 0; i < rds_ring->num_desc; i++) {
  252. list_add_tail(&rx_buf->list,
  253. &rds_ring->free_list);
  254. rx_buf->ref_handle = i;
  255. rx_buf->state = NETXEN_BUFFER_FREE;
  256. rx_buf++;
  257. }
  258. spin_lock_init(&rds_ring->lock);
  259. }
  260. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  261. sds_ring = &recv_ctx->sds_rings[ring];
  262. sds_ring->irq = adapter->msix_entries[ring].vector;
  263. sds_ring->adapter = adapter;
  264. sds_ring->num_desc = adapter->num_rxd;
  265. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  266. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  267. }
  268. return 0;
  269. err_out:
  270. netxen_free_sw_resources(adapter);
  271. return -ENOMEM;
  272. }
  273. /*
  274. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  275. * address to external PCI CRB address.
  276. */
  277. static u32 netxen_decode_crb_addr(u32 addr)
  278. {
  279. int i;
  280. u32 base_addr, offset, pci_base;
  281. crb_addr_transform_setup();
  282. pci_base = NETXEN_ADDR_ERROR;
  283. base_addr = addr & 0xfff00000;
  284. offset = addr & 0x000fffff;
  285. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  286. if (crb_addr_xform[i] == base_addr) {
  287. pci_base = i << 20;
  288. break;
  289. }
  290. }
  291. if (pci_base == NETXEN_ADDR_ERROR)
  292. return pci_base;
  293. else
  294. return pci_base + offset;
  295. }
  296. #define NETXEN_MAX_ROM_WAIT_USEC 100
  297. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  298. {
  299. long timeout = 0;
  300. long done = 0;
  301. cond_resched();
  302. while (done == 0) {
  303. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  304. done &= 2;
  305. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  306. dev_err(&adapter->pdev->dev,
  307. "Timeout reached waiting for rom done");
  308. return -EIO;
  309. }
  310. udelay(1);
  311. }
  312. return 0;
  313. }
  314. static int do_rom_fast_read(struct netxen_adapter *adapter,
  315. int addr, int *valp)
  316. {
  317. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  318. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  319. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  320. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  321. if (netxen_wait_rom_done(adapter)) {
  322. printk("Error waiting for rom done\n");
  323. return -EIO;
  324. }
  325. /* reset abyte_cnt and dummy_byte_cnt */
  326. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  327. udelay(10);
  328. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  329. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  330. return 0;
  331. }
  332. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  333. u8 *bytes, size_t size)
  334. {
  335. int addridx;
  336. int ret = 0;
  337. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  338. int v;
  339. ret = do_rom_fast_read(adapter, addridx, &v);
  340. if (ret != 0)
  341. break;
  342. *(__le32 *)bytes = cpu_to_le32(v);
  343. bytes += 4;
  344. }
  345. return ret;
  346. }
  347. int
  348. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  349. u8 *bytes, size_t size)
  350. {
  351. int ret;
  352. ret = netxen_rom_lock(adapter);
  353. if (ret < 0)
  354. return ret;
  355. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  356. netxen_rom_unlock(adapter);
  357. return ret;
  358. }
  359. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  360. {
  361. int ret;
  362. if (netxen_rom_lock(adapter) != 0)
  363. return -EIO;
  364. ret = do_rom_fast_read(adapter, addr, valp);
  365. netxen_rom_unlock(adapter);
  366. return ret;
  367. }
  368. #define NETXEN_BOARDTYPE 0x4008
  369. #define NETXEN_BOARDNUM 0x400c
  370. #define NETXEN_CHIPNUM 0x4010
  371. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  372. {
  373. int addr, val;
  374. int i, n, init_delay = 0;
  375. struct crb_addr_pair *buf;
  376. unsigned offset;
  377. u32 off;
  378. /* resetall */
  379. netxen_rom_lock(adapter);
  380. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  381. netxen_rom_unlock(adapter);
  382. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  383. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  384. (n != 0xcafecafe) ||
  385. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  386. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  387. "n: %08x\n", netxen_nic_driver_name, n);
  388. return -EIO;
  389. }
  390. offset = n & 0xffffU;
  391. n = (n >> 16) & 0xffffU;
  392. } else {
  393. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  394. !(n & 0x80000000)) {
  395. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  396. "n: %08x\n", netxen_nic_driver_name, n);
  397. return -EIO;
  398. }
  399. offset = 1;
  400. n &= ~0x80000000;
  401. }
  402. if (n >= 1024) {
  403. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  404. " initialized.\n", __func__, n);
  405. return -EIO;
  406. }
  407. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  408. if (buf == NULL)
  409. return -ENOMEM;
  410. for (i = 0; i < n; i++) {
  411. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  412. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  413. kfree(buf);
  414. return -EIO;
  415. }
  416. buf[i].addr = addr;
  417. buf[i].data = val;
  418. }
  419. for (i = 0; i < n; i++) {
  420. off = netxen_decode_crb_addr(buf[i].addr);
  421. if (off == NETXEN_ADDR_ERROR) {
  422. printk(KERN_ERR"CRB init value out of range %x\n",
  423. buf[i].addr);
  424. continue;
  425. }
  426. off += NETXEN_PCI_CRBSPACE;
  427. if (off & 1)
  428. continue;
  429. /* skipping cold reboot MAGIC */
  430. if (off == NETXEN_CAM_RAM(0x1fc))
  431. continue;
  432. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  433. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  434. continue;
  435. /* do not reset PCI */
  436. if (off == (ROMUSB_GLB + 0xbc))
  437. continue;
  438. if (off == (ROMUSB_GLB + 0xa8))
  439. continue;
  440. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  441. continue;
  442. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  443. continue;
  444. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  445. continue;
  446. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  447. continue;
  448. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  449. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  450. buf[i].data = 0x1020;
  451. /* skip the function enable register */
  452. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  453. continue;
  454. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  455. continue;
  456. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  457. continue;
  458. }
  459. init_delay = 1;
  460. /* After writing this register, HW needs time for CRB */
  461. /* to quiet down (else crb_window returns 0xffffffff) */
  462. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  463. init_delay = 1000;
  464. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  465. /* hold xdma in reset also */
  466. buf[i].data = NETXEN_NIC_XDMA_RESET;
  467. buf[i].data = 0x8000ff;
  468. }
  469. }
  470. NXWR32(adapter, off, buf[i].data);
  471. msleep(init_delay);
  472. }
  473. kfree(buf);
  474. /* disable_peg_cache_all */
  475. /* unreset_net_cache */
  476. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  477. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  478. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  479. }
  480. /* p2dn replyCount */
  481. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  482. /* disable_peg_cache 0 */
  483. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  484. /* disable_peg_cache 1 */
  485. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  486. /* peg_clr_all */
  487. /* peg_clr 0 */
  488. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  489. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  490. /* peg_clr 1 */
  491. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  492. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  493. /* peg_clr 2 */
  494. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  495. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  496. /* peg_clr 3 */
  497. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  498. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  499. return 0;
  500. }
  501. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  502. {
  503. uint32_t i;
  504. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  505. __le32 entries = cpu_to_le32(directory->num_entries);
  506. for (i = 0; i < entries; i++) {
  507. __le32 offs = cpu_to_le32(directory->findex) +
  508. (i * cpu_to_le32(directory->entry_size));
  509. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  510. if (tab_type == section)
  511. return (struct uni_table_desc *) &unirom[offs];
  512. }
  513. return NULL;
  514. }
  515. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  516. static int
  517. netxen_nic_validate_header(struct netxen_adapter *adapter)
  518. {
  519. const u8 *unirom = adapter->fw->data;
  520. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  521. u32 fw_file_size = adapter->fw->size;
  522. u32 tab_size;
  523. __le32 entries;
  524. __le32 entry_size;
  525. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  526. return -EINVAL;
  527. entries = cpu_to_le32(directory->num_entries);
  528. entry_size = cpu_to_le32(directory->entry_size);
  529. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  530. if (fw_file_size < tab_size)
  531. return -EINVAL;
  532. return 0;
  533. }
  534. static int
  535. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  536. {
  537. struct uni_table_desc *tab_desc;
  538. struct uni_data_desc *descr;
  539. const u8 *unirom = adapter->fw->data;
  540. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  541. NX_UNI_BOOTLD_IDX_OFF));
  542. u32 offs;
  543. u32 tab_size;
  544. u32 data_size;
  545. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  546. if (!tab_desc)
  547. return -EINVAL;
  548. tab_size = cpu_to_le32(tab_desc->findex) +
  549. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  550. if (adapter->fw->size < tab_size)
  551. return -EINVAL;
  552. offs = cpu_to_le32(tab_desc->findex) +
  553. (cpu_to_le32(tab_desc->entry_size) * (idx));
  554. descr = (struct uni_data_desc *)&unirom[offs];
  555. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  556. if (adapter->fw->size < data_size)
  557. return -EINVAL;
  558. return 0;
  559. }
  560. static int
  561. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  562. {
  563. struct uni_table_desc *tab_desc;
  564. struct uni_data_desc *descr;
  565. const u8 *unirom = adapter->fw->data;
  566. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  567. NX_UNI_FIRMWARE_IDX_OFF));
  568. u32 offs;
  569. u32 tab_size;
  570. u32 data_size;
  571. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  572. if (!tab_desc)
  573. return -EINVAL;
  574. tab_size = cpu_to_le32(tab_desc->findex) +
  575. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  576. if (adapter->fw->size < tab_size)
  577. return -EINVAL;
  578. offs = cpu_to_le32(tab_desc->findex) +
  579. (cpu_to_le32(tab_desc->entry_size) * (idx));
  580. descr = (struct uni_data_desc *)&unirom[offs];
  581. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  582. if (adapter->fw->size < data_size)
  583. return -EINVAL;
  584. return 0;
  585. }
  586. static int
  587. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  588. {
  589. struct uni_table_desc *ptab_descr;
  590. const u8 *unirom = adapter->fw->data;
  591. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  592. 1 : netxen_p3_has_mn(adapter);
  593. __le32 entries;
  594. __le32 entry_size;
  595. u32 tab_size;
  596. u32 i;
  597. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  598. if (ptab_descr == NULL)
  599. return -EINVAL;
  600. entries = cpu_to_le32(ptab_descr->num_entries);
  601. entry_size = cpu_to_le32(ptab_descr->entry_size);
  602. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  603. if (adapter->fw->size < tab_size)
  604. return -EINVAL;
  605. nomn:
  606. for (i = 0; i < entries; i++) {
  607. __le32 flags, file_chiprev, offs;
  608. u8 chiprev = adapter->ahw.revision_id;
  609. uint32_t flagbit;
  610. offs = cpu_to_le32(ptab_descr->findex) +
  611. (i * cpu_to_le32(ptab_descr->entry_size));
  612. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  613. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  614. NX_UNI_CHIP_REV_OFF));
  615. flagbit = mn_present ? 1 : 2;
  616. if ((chiprev == file_chiprev) &&
  617. ((1ULL << flagbit) & flags)) {
  618. adapter->file_prd_off = offs;
  619. return 0;
  620. }
  621. }
  622. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  623. mn_present = 0;
  624. goto nomn;
  625. }
  626. return -EINVAL;
  627. }
  628. static int
  629. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  630. {
  631. if (netxen_nic_validate_header(adapter)) {
  632. dev_err(&adapter->pdev->dev,
  633. "unified image: header validation failed\n");
  634. return -EINVAL;
  635. }
  636. if (netxen_nic_validate_product_offs(adapter)) {
  637. dev_err(&adapter->pdev->dev,
  638. "unified image: product validation failed\n");
  639. return -EINVAL;
  640. }
  641. if (netxen_nic_validate_bootld(adapter)) {
  642. dev_err(&adapter->pdev->dev,
  643. "unified image: bootld validation failed\n");
  644. return -EINVAL;
  645. }
  646. if (netxen_nic_validate_fw(adapter)) {
  647. dev_err(&adapter->pdev->dev,
  648. "unified image: firmware validation failed\n");
  649. return -EINVAL;
  650. }
  651. return 0;
  652. }
  653. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  654. u32 section, u32 idx_offset)
  655. {
  656. const u8 *unirom = adapter->fw->data;
  657. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  658. idx_offset));
  659. struct uni_table_desc *tab_desc;
  660. __le32 offs;
  661. tab_desc = nx_get_table_desc(unirom, section);
  662. if (tab_desc == NULL)
  663. return NULL;
  664. offs = cpu_to_le32(tab_desc->findex) +
  665. (cpu_to_le32(tab_desc->entry_size) * idx);
  666. return (struct uni_data_desc *)&unirom[offs];
  667. }
  668. static u8 *
  669. nx_get_bootld_offs(struct netxen_adapter *adapter)
  670. {
  671. u32 offs = NETXEN_BOOTLD_START;
  672. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  673. offs = cpu_to_le32((nx_get_data_desc(adapter,
  674. NX_UNI_DIR_SECT_BOOTLD,
  675. NX_UNI_BOOTLD_IDX_OFF))->findex);
  676. return (u8 *)&adapter->fw->data[offs];
  677. }
  678. static u8 *
  679. nx_get_fw_offs(struct netxen_adapter *adapter)
  680. {
  681. u32 offs = NETXEN_IMAGE_START;
  682. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  683. offs = cpu_to_le32((nx_get_data_desc(adapter,
  684. NX_UNI_DIR_SECT_FW,
  685. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  686. return (u8 *)&adapter->fw->data[offs];
  687. }
  688. static __le32
  689. nx_get_fw_size(struct netxen_adapter *adapter)
  690. {
  691. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  692. return cpu_to_le32((nx_get_data_desc(adapter,
  693. NX_UNI_DIR_SECT_FW,
  694. NX_UNI_FIRMWARE_IDX_OFF))->size);
  695. else
  696. return cpu_to_le32(
  697. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  698. }
  699. static __le32
  700. nx_get_fw_version(struct netxen_adapter *adapter)
  701. {
  702. struct uni_data_desc *fw_data_desc;
  703. const struct firmware *fw = adapter->fw;
  704. __le32 major, minor, sub;
  705. const u8 *ver_str;
  706. int i, ret = 0;
  707. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  708. fw_data_desc = nx_get_data_desc(adapter,
  709. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  710. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  711. cpu_to_le32(fw_data_desc->size) - 17;
  712. for (i = 0; i < 12; i++) {
  713. if (!strncmp(&ver_str[i], "REV=", 4)) {
  714. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  715. &major, &minor, &sub);
  716. break;
  717. }
  718. }
  719. if (ret != 3)
  720. return 0;
  721. return major + (minor << 8) + (sub << 16);
  722. } else
  723. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  724. }
  725. static __le32
  726. nx_get_bios_version(struct netxen_adapter *adapter)
  727. {
  728. const struct firmware *fw = adapter->fw;
  729. __le32 bios_ver, prd_off = adapter->file_prd_off;
  730. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  731. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  732. + NX_UNI_BIOS_VERSION_OFF));
  733. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  734. (bios_ver >> 24);
  735. } else
  736. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  737. }
  738. int
  739. netxen_need_fw_reset(struct netxen_adapter *adapter)
  740. {
  741. u32 count, old_count;
  742. u32 val, version, major, minor, build;
  743. int i, timeout;
  744. u8 fw_type;
  745. /* NX2031 firmware doesn't support heartbit */
  746. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  747. return 1;
  748. if (adapter->need_fw_reset)
  749. return 1;
  750. /* last attempt had failed */
  751. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  752. return 1;
  753. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  754. for (i = 0; i < 10; i++) {
  755. timeout = msleep_interruptible(200);
  756. if (timeout) {
  757. NXWR32(adapter, CRB_CMDPEG_STATE,
  758. PHAN_INITIALIZE_FAILED);
  759. return -EINTR;
  760. }
  761. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  762. if (count != old_count)
  763. break;
  764. }
  765. /* firmware is dead */
  766. if (count == old_count)
  767. return 1;
  768. /* check if we have got newer or different file firmware */
  769. if (adapter->fw) {
  770. val = nx_get_fw_version(adapter);
  771. version = NETXEN_DECODE_VERSION(val);
  772. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  773. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  774. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  775. if (version > NETXEN_VERSION_CODE(major, minor, build))
  776. return 1;
  777. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  778. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  779. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  780. fw_type = (val & 0x4) ?
  781. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  782. if (adapter->fw_type != fw_type)
  783. return 1;
  784. }
  785. }
  786. return 0;
  787. }
  788. #define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
  789. int
  790. netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
  791. {
  792. u32 flash_fw_ver, min_fw_ver;
  793. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  794. return 0;
  795. if (netxen_rom_fast_read(adapter,
  796. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  797. dev_err(&adapter->pdev->dev, "Unable to read flash fw"
  798. "version\n");
  799. return -EIO;
  800. }
  801. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  802. min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
  803. if (flash_fw_ver >= min_fw_ver)
  804. return 0;
  805. dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
  806. "[4.0.505]. Please update firmware on flash\n",
  807. _major(flash_fw_ver), _minor(flash_fw_ver),
  808. _build(flash_fw_ver));
  809. return -EINVAL;
  810. }
  811. static char *fw_name[] = {
  812. NX_P2_MN_ROMIMAGE_NAME,
  813. NX_P3_CT_ROMIMAGE_NAME,
  814. NX_P3_MN_ROMIMAGE_NAME,
  815. NX_UNIFIED_ROMIMAGE_NAME,
  816. NX_FLASH_ROMIMAGE_NAME,
  817. };
  818. int
  819. netxen_load_firmware(struct netxen_adapter *adapter)
  820. {
  821. u64 *ptr64;
  822. u32 i, flashaddr, size;
  823. const struct firmware *fw = adapter->fw;
  824. struct pci_dev *pdev = adapter->pdev;
  825. dev_info(&pdev->dev, "loading firmware from %s\n",
  826. fw_name[adapter->fw_type]);
  827. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  828. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  829. if (fw) {
  830. __le64 data;
  831. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  832. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  833. flashaddr = NETXEN_BOOTLD_START;
  834. for (i = 0; i < size; i++) {
  835. data = cpu_to_le64(ptr64[i]);
  836. if (adapter->pci_mem_write(adapter, flashaddr, data))
  837. return -EIO;
  838. flashaddr += 8;
  839. }
  840. size = (__force u32)nx_get_fw_size(adapter) / 8;
  841. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  842. flashaddr = NETXEN_IMAGE_START;
  843. for (i = 0; i < size; i++) {
  844. data = cpu_to_le64(ptr64[i]);
  845. if (adapter->pci_mem_write(adapter,
  846. flashaddr, data))
  847. return -EIO;
  848. flashaddr += 8;
  849. }
  850. size = (__force u32)nx_get_fw_size(adapter) % 8;
  851. if (size) {
  852. data = cpu_to_le64(ptr64[i]);
  853. if (adapter->pci_mem_write(adapter,
  854. flashaddr, data))
  855. return -EIO;
  856. }
  857. } else {
  858. u64 data;
  859. u32 hi, lo;
  860. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  861. flashaddr = NETXEN_BOOTLD_START;
  862. for (i = 0; i < size; i++) {
  863. if (netxen_rom_fast_read(adapter,
  864. flashaddr, (int *)&lo) != 0)
  865. return -EIO;
  866. if (netxen_rom_fast_read(adapter,
  867. flashaddr + 4, (int *)&hi) != 0)
  868. return -EIO;
  869. /* hi, lo are already in host endian byteorder */
  870. data = (((u64)hi << 32) | lo);
  871. if (adapter->pci_mem_write(adapter,
  872. flashaddr, data))
  873. return -EIO;
  874. flashaddr += 8;
  875. }
  876. }
  877. msleep(1);
  878. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  879. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  880. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  881. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  882. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  883. else {
  884. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  885. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  886. }
  887. return 0;
  888. }
  889. static int
  890. netxen_validate_firmware(struct netxen_adapter *adapter)
  891. {
  892. __le32 val;
  893. __le32 flash_fw_ver;
  894. u32 file_fw_ver, min_ver, bios;
  895. struct pci_dev *pdev = adapter->pdev;
  896. const struct firmware *fw = adapter->fw;
  897. u8 fw_type = adapter->fw_type;
  898. u32 crbinit_fix_fw;
  899. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  900. if (netxen_nic_validate_unified_romimage(adapter))
  901. return -EINVAL;
  902. } else {
  903. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  904. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  905. return -EINVAL;
  906. if (fw->size < NX_FW_MIN_SIZE)
  907. return -EINVAL;
  908. }
  909. val = nx_get_fw_version(adapter);
  910. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  911. min_ver = NETXEN_MIN_P3_FW_SUPP;
  912. else
  913. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  914. file_fw_ver = NETXEN_DECODE_VERSION(val);
  915. if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
  916. (file_fw_ver < min_ver)) {
  917. dev_err(&pdev->dev,
  918. "%s: firmware version %d.%d.%d unsupported\n",
  919. fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
  920. _build(file_fw_ver));
  921. return -EINVAL;
  922. }
  923. val = nx_get_bios_version(adapter);
  924. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  925. if ((__force u32)val != bios) {
  926. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  927. fw_name[fw_type]);
  928. return -EINVAL;
  929. }
  930. if (netxen_rom_fast_read(adapter,
  931. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  932. dev_err(&pdev->dev, "Unable to read flash fw version\n");
  933. return -EIO;
  934. }
  935. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  936. /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
  937. crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
  938. if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
  939. NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  940. dev_err(&pdev->dev, "Incompatibility detected between driver "
  941. "and firmware version on flash. This configuration "
  942. "is not recommended. Please update the firmware on "
  943. "flash immediately\n");
  944. return -EINVAL;
  945. }
  946. /* check if flashed firmware is newer only for no-mn and P2 case*/
  947. if (!netxen_p3_has_mn(adapter) ||
  948. NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  949. if (flash_fw_ver > file_fw_ver) {
  950. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  951. fw_name[fw_type]);
  952. return -EINVAL;
  953. }
  954. }
  955. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  956. return 0;
  957. }
  958. static void
  959. nx_get_next_fwtype(struct netxen_adapter *adapter)
  960. {
  961. u8 fw_type;
  962. switch (adapter->fw_type) {
  963. case NX_UNKNOWN_ROMIMAGE:
  964. fw_type = NX_UNIFIED_ROMIMAGE;
  965. break;
  966. case NX_UNIFIED_ROMIMAGE:
  967. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  968. fw_type = NX_FLASH_ROMIMAGE;
  969. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  970. fw_type = NX_P2_MN_ROMIMAGE;
  971. else if (netxen_p3_has_mn(adapter))
  972. fw_type = NX_P3_MN_ROMIMAGE;
  973. else
  974. fw_type = NX_P3_CT_ROMIMAGE;
  975. break;
  976. case NX_P3_MN_ROMIMAGE:
  977. fw_type = NX_P3_CT_ROMIMAGE;
  978. break;
  979. case NX_P2_MN_ROMIMAGE:
  980. case NX_P3_CT_ROMIMAGE:
  981. default:
  982. fw_type = NX_FLASH_ROMIMAGE;
  983. break;
  984. }
  985. adapter->fw_type = fw_type;
  986. }
  987. static int
  988. netxen_p3_has_mn(struct netxen_adapter *adapter)
  989. {
  990. u32 capability, flashed_ver;
  991. capability = 0;
  992. /* NX2031 always had MN */
  993. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  994. return 1;
  995. netxen_rom_fast_read(adapter,
  996. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  997. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  998. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  999. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  1000. if (capability & NX_PEG_TUNE_MN_PRESENT)
  1001. return 1;
  1002. }
  1003. return 0;
  1004. }
  1005. void netxen_request_firmware(struct netxen_adapter *adapter)
  1006. {
  1007. struct pci_dev *pdev = adapter->pdev;
  1008. int rc = 0;
  1009. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  1010. next:
  1011. nx_get_next_fwtype(adapter);
  1012. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  1013. adapter->fw = NULL;
  1014. } else {
  1015. rc = request_firmware(&adapter->fw,
  1016. fw_name[adapter->fw_type], &pdev->dev);
  1017. if (rc != 0)
  1018. goto next;
  1019. rc = netxen_validate_firmware(adapter);
  1020. if (rc != 0) {
  1021. release_firmware(adapter->fw);
  1022. msleep(1);
  1023. goto next;
  1024. }
  1025. }
  1026. }
  1027. void
  1028. netxen_release_firmware(struct netxen_adapter *adapter)
  1029. {
  1030. release_firmware(adapter->fw);
  1031. adapter->fw = NULL;
  1032. }
  1033. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1034. {
  1035. u64 addr;
  1036. u32 hi, lo;
  1037. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1038. return 0;
  1039. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1040. NETXEN_HOST_DUMMY_DMA_SIZE,
  1041. &adapter->dummy_dma.phys_addr);
  1042. if (adapter->dummy_dma.addr == NULL) {
  1043. dev_err(&adapter->pdev->dev,
  1044. "ERROR: Could not allocate dummy DMA memory\n");
  1045. return -ENOMEM;
  1046. }
  1047. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1048. hi = (addr >> 32) & 0xffffffff;
  1049. lo = addr & 0xffffffff;
  1050. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1051. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1052. return 0;
  1053. }
  1054. /*
  1055. * NetXen DMA watchdog control:
  1056. *
  1057. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1058. * Bit 1 : disable_request => 1 req disable dma watchdog
  1059. * Bit 2 : enable_request => 1 req enable dma watchdog
  1060. * Bit 3-31 : unused
  1061. */
  1062. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1063. {
  1064. int i = 100;
  1065. u32 ctrl;
  1066. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1067. return;
  1068. if (!adapter->dummy_dma.addr)
  1069. return;
  1070. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1071. if ((ctrl & 0x1) != 0) {
  1072. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1073. while ((ctrl & 0x1) != 0) {
  1074. msleep(50);
  1075. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1076. if (--i == 0)
  1077. break;
  1078. }
  1079. }
  1080. if (i) {
  1081. pci_free_consistent(adapter->pdev,
  1082. NETXEN_HOST_DUMMY_DMA_SIZE,
  1083. adapter->dummy_dma.addr,
  1084. adapter->dummy_dma.phys_addr);
  1085. adapter->dummy_dma.addr = NULL;
  1086. } else
  1087. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1088. }
  1089. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1090. {
  1091. u32 val = 0;
  1092. int retries = 60;
  1093. if (pegtune_val)
  1094. return 0;
  1095. do {
  1096. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1097. switch (val) {
  1098. case PHAN_INITIALIZE_COMPLETE:
  1099. case PHAN_INITIALIZE_ACK:
  1100. return 0;
  1101. case PHAN_INITIALIZE_FAILED:
  1102. goto out_err;
  1103. default:
  1104. break;
  1105. }
  1106. msleep(500);
  1107. } while (--retries);
  1108. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1109. out_err:
  1110. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1111. return -EIO;
  1112. }
  1113. static int
  1114. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1115. {
  1116. u32 val = 0;
  1117. int retries = 2000;
  1118. do {
  1119. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1120. if (val == PHAN_PEG_RCV_INITIALIZED)
  1121. return 0;
  1122. msleep(10);
  1123. } while (--retries);
  1124. if (!retries) {
  1125. printk(KERN_ERR "Receive Peg initialization not "
  1126. "complete, state: 0x%x.\n", val);
  1127. return -EIO;
  1128. }
  1129. return 0;
  1130. }
  1131. int netxen_init_firmware(struct netxen_adapter *adapter)
  1132. {
  1133. int err;
  1134. err = netxen_receive_peg_ready(adapter);
  1135. if (err)
  1136. return err;
  1137. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1138. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1139. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1140. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1141. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1142. return err;
  1143. }
  1144. static void
  1145. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1146. {
  1147. u32 cable_OUI;
  1148. u16 cable_len;
  1149. u16 link_speed;
  1150. u8 link_status, module, duplex, autoneg;
  1151. struct net_device *netdev = adapter->netdev;
  1152. adapter->has_link_events = 1;
  1153. cable_OUI = msg->body[1] & 0xffffffff;
  1154. cable_len = (msg->body[1] >> 32) & 0xffff;
  1155. link_speed = (msg->body[1] >> 48) & 0xffff;
  1156. link_status = msg->body[2] & 0xff;
  1157. duplex = (msg->body[2] >> 16) & 0xff;
  1158. autoneg = (msg->body[2] >> 24) & 0xff;
  1159. module = (msg->body[2] >> 8) & 0xff;
  1160. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1161. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1162. netdev->name, cable_OUI, cable_len);
  1163. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1164. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1165. netdev->name, cable_len);
  1166. }
  1167. /* update link parameters */
  1168. if (duplex == LINKEVENT_FULL_DUPLEX)
  1169. adapter->link_duplex = DUPLEX_FULL;
  1170. else
  1171. adapter->link_duplex = DUPLEX_HALF;
  1172. adapter->module_type = module;
  1173. adapter->link_autoneg = autoneg;
  1174. adapter->link_speed = link_speed;
  1175. netxen_advert_link_change(adapter, link_status);
  1176. }
  1177. static void
  1178. netxen_handle_fw_message(int desc_cnt, int index,
  1179. struct nx_host_sds_ring *sds_ring)
  1180. {
  1181. nx_fw_msg_t msg;
  1182. struct status_desc *desc;
  1183. int i = 0, opcode;
  1184. while (desc_cnt > 0 && i < 8) {
  1185. desc = &sds_ring->desc_head[index];
  1186. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1187. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1188. index = get_next_index(index, sds_ring->num_desc);
  1189. desc_cnt--;
  1190. }
  1191. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1192. switch (opcode) {
  1193. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1194. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1195. break;
  1196. default:
  1197. break;
  1198. }
  1199. }
  1200. static int
  1201. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1202. struct nx_host_rds_ring *rds_ring,
  1203. struct netxen_rx_buffer *buffer)
  1204. {
  1205. struct sk_buff *skb;
  1206. dma_addr_t dma;
  1207. struct pci_dev *pdev = adapter->pdev;
  1208. buffer->skb = netdev_alloc_skb(adapter->netdev, rds_ring->skb_size);
  1209. if (!buffer->skb)
  1210. return 1;
  1211. skb = buffer->skb;
  1212. if (!adapter->ahw.cut_through)
  1213. skb_reserve(skb, 2);
  1214. dma = pci_map_single(pdev, skb->data,
  1215. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1216. if (pci_dma_mapping_error(pdev, dma)) {
  1217. dev_kfree_skb_any(skb);
  1218. buffer->skb = NULL;
  1219. return 1;
  1220. }
  1221. buffer->skb = skb;
  1222. buffer->dma = dma;
  1223. buffer->state = NETXEN_BUFFER_BUSY;
  1224. return 0;
  1225. }
  1226. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1227. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1228. {
  1229. struct netxen_rx_buffer *buffer;
  1230. struct sk_buff *skb;
  1231. buffer = &rds_ring->rx_buf_arr[index];
  1232. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1233. PCI_DMA_FROMDEVICE);
  1234. skb = buffer->skb;
  1235. if (!skb)
  1236. goto no_skb;
  1237. if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
  1238. && cksum == STATUS_CKSUM_OK)) {
  1239. adapter->stats.csummed++;
  1240. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1241. } else
  1242. skb->ip_summed = CHECKSUM_NONE;
  1243. buffer->skb = NULL;
  1244. no_skb:
  1245. buffer->state = NETXEN_BUFFER_FREE;
  1246. return skb;
  1247. }
  1248. static struct netxen_rx_buffer *
  1249. netxen_process_rcv(struct netxen_adapter *adapter,
  1250. struct nx_host_sds_ring *sds_ring,
  1251. int ring, u64 sts_data0)
  1252. {
  1253. struct net_device *netdev = adapter->netdev;
  1254. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1255. struct netxen_rx_buffer *buffer;
  1256. struct sk_buff *skb;
  1257. struct nx_host_rds_ring *rds_ring;
  1258. int index, length, cksum, pkt_offset;
  1259. if (unlikely(ring >= adapter->max_rds_rings))
  1260. return NULL;
  1261. rds_ring = &recv_ctx->rds_rings[ring];
  1262. index = netxen_get_sts_refhandle(sts_data0);
  1263. if (unlikely(index >= rds_ring->num_desc))
  1264. return NULL;
  1265. buffer = &rds_ring->rx_buf_arr[index];
  1266. length = netxen_get_sts_totallength(sts_data0);
  1267. cksum = netxen_get_sts_status(sts_data0);
  1268. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1269. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1270. if (!skb)
  1271. return buffer;
  1272. if (length > rds_ring->skb_size)
  1273. skb_put(skb, rds_ring->skb_size);
  1274. else
  1275. skb_put(skb, length);
  1276. if (pkt_offset)
  1277. skb_pull(skb, pkt_offset);
  1278. skb->protocol = eth_type_trans(skb, netdev);
  1279. napi_gro_receive(&sds_ring->napi, skb);
  1280. adapter->stats.rx_pkts++;
  1281. adapter->stats.rxbytes += length;
  1282. return buffer;
  1283. }
  1284. #define TCP_HDR_SIZE 20
  1285. #define TCP_TS_OPTION_SIZE 12
  1286. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1287. static struct netxen_rx_buffer *
  1288. netxen_process_lro(struct netxen_adapter *adapter,
  1289. struct nx_host_sds_ring *sds_ring,
  1290. int ring, u64 sts_data0, u64 sts_data1)
  1291. {
  1292. struct net_device *netdev = adapter->netdev;
  1293. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1294. struct netxen_rx_buffer *buffer;
  1295. struct sk_buff *skb;
  1296. struct nx_host_rds_ring *rds_ring;
  1297. struct iphdr *iph;
  1298. struct tcphdr *th;
  1299. bool push, timestamp;
  1300. int l2_hdr_offset, l4_hdr_offset;
  1301. int index;
  1302. u16 lro_length, length, data_offset;
  1303. u32 seq_number;
  1304. u8 vhdr_len = 0;
  1305. if (unlikely(ring > adapter->max_rds_rings))
  1306. return NULL;
  1307. rds_ring = &recv_ctx->rds_rings[ring];
  1308. index = netxen_get_lro_sts_refhandle(sts_data0);
  1309. if (unlikely(index > rds_ring->num_desc))
  1310. return NULL;
  1311. buffer = &rds_ring->rx_buf_arr[index];
  1312. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1313. lro_length = netxen_get_lro_sts_length(sts_data0);
  1314. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1315. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1316. push = netxen_get_lro_sts_push_flag(sts_data0);
  1317. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1318. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1319. if (!skb)
  1320. return buffer;
  1321. if (timestamp)
  1322. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1323. else
  1324. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1325. skb_put(skb, lro_length + data_offset);
  1326. skb_pull(skb, l2_hdr_offset);
  1327. skb->protocol = eth_type_trans(skb, netdev);
  1328. if (skb->protocol == htons(ETH_P_8021Q))
  1329. vhdr_len = VLAN_HLEN;
  1330. iph = (struct iphdr *)(skb->data + vhdr_len);
  1331. th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
  1332. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1333. iph->tot_len = htons(length);
  1334. iph->check = 0;
  1335. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1336. th->psh = push;
  1337. th->seq = htonl(seq_number);
  1338. length = skb->len;
  1339. if (adapter->flags & NETXEN_FW_MSS_CAP)
  1340. skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1);
  1341. netif_receive_skb(skb);
  1342. adapter->stats.lro_pkts++;
  1343. adapter->stats.rxbytes += length;
  1344. return buffer;
  1345. }
  1346. #define netxen_merge_rx_buffers(list, head) \
  1347. do { list_splice_tail_init(list, head); } while (0);
  1348. int
  1349. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1350. {
  1351. struct netxen_adapter *adapter = sds_ring->adapter;
  1352. struct list_head *cur;
  1353. struct status_desc *desc;
  1354. struct netxen_rx_buffer *rxbuf;
  1355. u32 consumer = sds_ring->consumer;
  1356. int count = 0;
  1357. u64 sts_data0, sts_data1;
  1358. int opcode, ring = 0, desc_cnt;
  1359. while (count < max) {
  1360. desc = &sds_ring->desc_head[consumer];
  1361. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1362. if (!(sts_data0 & STATUS_OWNER_HOST))
  1363. break;
  1364. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1365. opcode = netxen_get_sts_opcode(sts_data0);
  1366. switch (opcode) {
  1367. case NETXEN_NIC_RXPKT_DESC:
  1368. case NETXEN_OLD_RXPKT_DESC:
  1369. case NETXEN_NIC_SYN_OFFLOAD:
  1370. ring = netxen_get_sts_type(sts_data0);
  1371. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1372. ring, sts_data0);
  1373. break;
  1374. case NETXEN_NIC_LRO_DESC:
  1375. ring = netxen_get_lro_sts_type(sts_data0);
  1376. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1377. rxbuf = netxen_process_lro(adapter, sds_ring,
  1378. ring, sts_data0, sts_data1);
  1379. break;
  1380. case NETXEN_NIC_RESPONSE_DESC:
  1381. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1382. default:
  1383. goto skip;
  1384. }
  1385. WARN_ON(desc_cnt > 1);
  1386. if (rxbuf)
  1387. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1388. skip:
  1389. for (; desc_cnt > 0; desc_cnt--) {
  1390. desc = &sds_ring->desc_head[consumer];
  1391. desc->status_desc_data[0] =
  1392. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1393. consumer = get_next_index(consumer, sds_ring->num_desc);
  1394. }
  1395. count++;
  1396. }
  1397. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1398. struct nx_host_rds_ring *rds_ring =
  1399. &adapter->recv_ctx.rds_rings[ring];
  1400. if (!list_empty(&sds_ring->free_list[ring])) {
  1401. list_for_each(cur, &sds_ring->free_list[ring]) {
  1402. rxbuf = list_entry(cur,
  1403. struct netxen_rx_buffer, list);
  1404. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1405. }
  1406. spin_lock(&rds_ring->lock);
  1407. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1408. &rds_ring->free_list);
  1409. spin_unlock(&rds_ring->lock);
  1410. }
  1411. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1412. }
  1413. if (count) {
  1414. sds_ring->consumer = consumer;
  1415. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1416. }
  1417. return count;
  1418. }
  1419. /* Process Command status ring */
  1420. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1421. {
  1422. u32 sw_consumer, hw_consumer;
  1423. int count = 0, i;
  1424. struct netxen_cmd_buffer *buffer;
  1425. struct pci_dev *pdev = adapter->pdev;
  1426. struct net_device *netdev = adapter->netdev;
  1427. struct netxen_skb_frag *frag;
  1428. int done = 0;
  1429. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1430. if (!spin_trylock(&adapter->tx_clean_lock))
  1431. return 1;
  1432. sw_consumer = tx_ring->sw_consumer;
  1433. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1434. while (sw_consumer != hw_consumer) {
  1435. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1436. if (buffer->skb) {
  1437. frag = &buffer->frag_array[0];
  1438. pci_unmap_single(pdev, frag->dma, frag->length,
  1439. PCI_DMA_TODEVICE);
  1440. frag->dma = 0ULL;
  1441. for (i = 1; i < buffer->frag_count; i++) {
  1442. frag++; /* Get the next frag */
  1443. pci_unmap_page(pdev, frag->dma, frag->length,
  1444. PCI_DMA_TODEVICE);
  1445. frag->dma = 0ULL;
  1446. }
  1447. adapter->stats.xmitfinished++;
  1448. dev_kfree_skb_any(buffer->skb);
  1449. buffer->skb = NULL;
  1450. }
  1451. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1452. if (++count >= MAX_STATUS_HANDLE)
  1453. break;
  1454. }
  1455. if (count && netif_running(netdev)) {
  1456. tx_ring->sw_consumer = sw_consumer;
  1457. smp_mb();
  1458. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
  1459. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1460. netif_wake_queue(netdev);
  1461. adapter->tx_timeo_cnt = 0;
  1462. }
  1463. /*
  1464. * If everything is freed up to consumer then check if the ring is full
  1465. * If the ring is full then check if more needs to be freed and
  1466. * schedule the call back again.
  1467. *
  1468. * This happens when there are 2 CPUs. One could be freeing and the
  1469. * other filling it. If the ring is full when we get out of here and
  1470. * the card has already interrupted the host then the host can miss the
  1471. * interrupt.
  1472. *
  1473. * There is still a possible race condition and the host could miss an
  1474. * interrupt. The card has to take care of this.
  1475. */
  1476. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1477. done = (sw_consumer == hw_consumer);
  1478. spin_unlock(&adapter->tx_clean_lock);
  1479. return done;
  1480. }
  1481. void
  1482. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1483. struct nx_host_rds_ring *rds_ring)
  1484. {
  1485. struct rcv_desc *pdesc;
  1486. struct netxen_rx_buffer *buffer;
  1487. int producer, count = 0;
  1488. netxen_ctx_msg msg = 0;
  1489. struct list_head *head;
  1490. producer = rds_ring->producer;
  1491. head = &rds_ring->free_list;
  1492. while (!list_empty(head)) {
  1493. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1494. if (!buffer->skb) {
  1495. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1496. break;
  1497. }
  1498. count++;
  1499. list_del(&buffer->list);
  1500. /* make a rcv descriptor */
  1501. pdesc = &rds_ring->desc_head[producer];
  1502. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1503. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1504. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1505. producer = get_next_index(producer, rds_ring->num_desc);
  1506. }
  1507. if (count) {
  1508. rds_ring->producer = producer;
  1509. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1510. (producer-1) & (rds_ring->num_desc-1));
  1511. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1512. /*
  1513. * Write a doorbell msg to tell phanmon of change in
  1514. * receive ring producer
  1515. * Only for firmware version < 4.0.0
  1516. */
  1517. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1518. netxen_set_msg_privid(msg);
  1519. netxen_set_msg_count(msg,
  1520. ((producer - 1) &
  1521. (rds_ring->num_desc - 1)));
  1522. netxen_set_msg_ctxid(msg, adapter->portnum);
  1523. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1524. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1525. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1526. }
  1527. }
  1528. }
  1529. static void
  1530. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1531. struct nx_host_rds_ring *rds_ring)
  1532. {
  1533. struct rcv_desc *pdesc;
  1534. struct netxen_rx_buffer *buffer;
  1535. int producer, count = 0;
  1536. struct list_head *head;
  1537. if (!spin_trylock(&rds_ring->lock))
  1538. return;
  1539. producer = rds_ring->producer;
  1540. head = &rds_ring->free_list;
  1541. while (!list_empty(head)) {
  1542. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1543. if (!buffer->skb) {
  1544. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1545. break;
  1546. }
  1547. count++;
  1548. list_del(&buffer->list);
  1549. /* make a rcv descriptor */
  1550. pdesc = &rds_ring->desc_head[producer];
  1551. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1552. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1553. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1554. producer = get_next_index(producer, rds_ring->num_desc);
  1555. }
  1556. if (count) {
  1557. rds_ring->producer = producer;
  1558. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1559. (producer - 1) & (rds_ring->num_desc - 1));
  1560. }
  1561. spin_unlock(&rds_ring->lock);
  1562. }
  1563. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1564. {
  1565. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1566. }