resource_tracker.c 87 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844
  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. struct rb_node node;
  56. u64 res_id;
  57. int owner;
  58. int state;
  59. int from_state;
  60. int to_state;
  61. int removing;
  62. };
  63. enum {
  64. RES_ANY_BUSY = 1
  65. };
  66. struct res_gid {
  67. struct list_head list;
  68. u8 gid[16];
  69. enum mlx4_protocol prot;
  70. enum mlx4_steer_type steer;
  71. };
  72. enum res_qp_states {
  73. RES_QP_BUSY = RES_ANY_BUSY,
  74. /* QP number was allocated */
  75. RES_QP_RESERVED,
  76. /* ICM memory for QP context was mapped */
  77. RES_QP_MAPPED,
  78. /* QP is in hw ownership */
  79. RES_QP_HW
  80. };
  81. struct res_qp {
  82. struct res_common com;
  83. struct res_mtt *mtt;
  84. struct res_cq *rcq;
  85. struct res_cq *scq;
  86. struct res_srq *srq;
  87. struct list_head mcg_list;
  88. spinlock_t mcg_spl;
  89. int local_qpn;
  90. atomic_t ref_count;
  91. };
  92. enum res_mtt_states {
  93. RES_MTT_BUSY = RES_ANY_BUSY,
  94. RES_MTT_ALLOCATED,
  95. };
  96. static inline const char *mtt_states_str(enum res_mtt_states state)
  97. {
  98. switch (state) {
  99. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  100. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  101. default: return "Unknown";
  102. }
  103. }
  104. struct res_mtt {
  105. struct res_common com;
  106. int order;
  107. atomic_t ref_count;
  108. };
  109. enum res_mpt_states {
  110. RES_MPT_BUSY = RES_ANY_BUSY,
  111. RES_MPT_RESERVED,
  112. RES_MPT_MAPPED,
  113. RES_MPT_HW,
  114. };
  115. struct res_mpt {
  116. struct res_common com;
  117. struct res_mtt *mtt;
  118. int key;
  119. };
  120. enum res_eq_states {
  121. RES_EQ_BUSY = RES_ANY_BUSY,
  122. RES_EQ_RESERVED,
  123. RES_EQ_HW,
  124. };
  125. struct res_eq {
  126. struct res_common com;
  127. struct res_mtt *mtt;
  128. };
  129. enum res_cq_states {
  130. RES_CQ_BUSY = RES_ANY_BUSY,
  131. RES_CQ_ALLOCATED,
  132. RES_CQ_HW,
  133. };
  134. struct res_cq {
  135. struct res_common com;
  136. struct res_mtt *mtt;
  137. atomic_t ref_count;
  138. };
  139. enum res_srq_states {
  140. RES_SRQ_BUSY = RES_ANY_BUSY,
  141. RES_SRQ_ALLOCATED,
  142. RES_SRQ_HW,
  143. };
  144. struct res_srq {
  145. struct res_common com;
  146. struct res_mtt *mtt;
  147. struct res_cq *cq;
  148. atomic_t ref_count;
  149. };
  150. enum res_counter_states {
  151. RES_COUNTER_BUSY = RES_ANY_BUSY,
  152. RES_COUNTER_ALLOCATED,
  153. };
  154. struct res_counter {
  155. struct res_common com;
  156. int port;
  157. };
  158. enum res_xrcdn_states {
  159. RES_XRCD_BUSY = RES_ANY_BUSY,
  160. RES_XRCD_ALLOCATED,
  161. };
  162. struct res_xrcdn {
  163. struct res_common com;
  164. int port;
  165. };
  166. enum res_fs_rule_states {
  167. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  168. RES_FS_RULE_ALLOCATED,
  169. };
  170. struct res_fs_rule {
  171. struct res_common com;
  172. int qpn;
  173. };
  174. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  175. {
  176. struct rb_node *node = root->rb_node;
  177. while (node) {
  178. struct res_common *res = container_of(node, struct res_common,
  179. node);
  180. if (res_id < res->res_id)
  181. node = node->rb_left;
  182. else if (res_id > res->res_id)
  183. node = node->rb_right;
  184. else
  185. return res;
  186. }
  187. return NULL;
  188. }
  189. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  190. {
  191. struct rb_node **new = &(root->rb_node), *parent = NULL;
  192. /* Figure out where to put new node */
  193. while (*new) {
  194. struct res_common *this = container_of(*new, struct res_common,
  195. node);
  196. parent = *new;
  197. if (res->res_id < this->res_id)
  198. new = &((*new)->rb_left);
  199. else if (res->res_id > this->res_id)
  200. new = &((*new)->rb_right);
  201. else
  202. return -EEXIST;
  203. }
  204. /* Add new node and rebalance tree. */
  205. rb_link_node(&res->node, parent, new);
  206. rb_insert_color(&res->node, root);
  207. return 0;
  208. }
  209. enum qp_transition {
  210. QP_TRANS_INIT2RTR,
  211. QP_TRANS_RTR2RTS,
  212. QP_TRANS_RTS2RTS,
  213. QP_TRANS_SQERR2RTS,
  214. QP_TRANS_SQD2SQD,
  215. QP_TRANS_SQD2RTS
  216. };
  217. /* For Debug uses */
  218. static const char *ResourceType(enum mlx4_resource rt)
  219. {
  220. switch (rt) {
  221. case RES_QP: return "RES_QP";
  222. case RES_CQ: return "RES_CQ";
  223. case RES_SRQ: return "RES_SRQ";
  224. case RES_MPT: return "RES_MPT";
  225. case RES_MTT: return "RES_MTT";
  226. case RES_MAC: return "RES_MAC";
  227. case RES_EQ: return "RES_EQ";
  228. case RES_COUNTER: return "RES_COUNTER";
  229. case RES_FS_RULE: return "RES_FS_RULE";
  230. case RES_XRCD: return "RES_XRCD";
  231. default: return "Unknown resource type !!!";
  232. };
  233. }
  234. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  235. {
  236. struct mlx4_priv *priv = mlx4_priv(dev);
  237. int i;
  238. int t;
  239. priv->mfunc.master.res_tracker.slave_list =
  240. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  241. GFP_KERNEL);
  242. if (!priv->mfunc.master.res_tracker.slave_list)
  243. return -ENOMEM;
  244. for (i = 0 ; i < dev->num_slaves; i++) {
  245. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  246. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  247. slave_list[i].res_list[t]);
  248. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  249. }
  250. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  251. dev->num_slaves);
  252. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  253. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  254. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  255. return 0 ;
  256. }
  257. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  258. enum mlx4_res_tracker_free_type type)
  259. {
  260. struct mlx4_priv *priv = mlx4_priv(dev);
  261. int i;
  262. if (priv->mfunc.master.res_tracker.slave_list) {
  263. if (type != RES_TR_FREE_STRUCTS_ONLY)
  264. for (i = 0 ; i < dev->num_slaves; i++)
  265. if (type == RES_TR_FREE_ALL ||
  266. dev->caps.function != i)
  267. mlx4_delete_all_resources_for_slave(dev, i);
  268. if (type != RES_TR_FREE_SLAVES_ONLY) {
  269. kfree(priv->mfunc.master.res_tracker.slave_list);
  270. priv->mfunc.master.res_tracker.slave_list = NULL;
  271. }
  272. }
  273. }
  274. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  275. struct mlx4_cmd_mailbox *inbox)
  276. {
  277. u8 sched = *(u8 *)(inbox->buf + 64);
  278. u8 orig_index = *(u8 *)(inbox->buf + 35);
  279. u8 new_index;
  280. struct mlx4_priv *priv = mlx4_priv(dev);
  281. int port;
  282. port = (sched >> 6 & 1) + 1;
  283. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  284. *(u8 *)(inbox->buf + 35) = new_index;
  285. }
  286. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  287. u8 slave)
  288. {
  289. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  290. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  291. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  292. if (MLX4_QP_ST_UD == ts)
  293. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  294. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  295. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  296. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  297. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  298. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  299. }
  300. }
  301. static int mpt_mask(struct mlx4_dev *dev)
  302. {
  303. return dev->caps.num_mpts - 1;
  304. }
  305. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  306. enum mlx4_resource type)
  307. {
  308. struct mlx4_priv *priv = mlx4_priv(dev);
  309. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  310. res_id);
  311. }
  312. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  313. enum mlx4_resource type,
  314. void *res)
  315. {
  316. struct res_common *r;
  317. int err = 0;
  318. spin_lock_irq(mlx4_tlock(dev));
  319. r = find_res(dev, res_id, type);
  320. if (!r) {
  321. err = -ENONET;
  322. goto exit;
  323. }
  324. if (r->state == RES_ANY_BUSY) {
  325. err = -EBUSY;
  326. goto exit;
  327. }
  328. if (r->owner != slave) {
  329. err = -EPERM;
  330. goto exit;
  331. }
  332. r->from_state = r->state;
  333. r->state = RES_ANY_BUSY;
  334. if (res)
  335. *((struct res_common **)res) = r;
  336. exit:
  337. spin_unlock_irq(mlx4_tlock(dev));
  338. return err;
  339. }
  340. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  341. enum mlx4_resource type,
  342. u64 res_id, int *slave)
  343. {
  344. struct res_common *r;
  345. int err = -ENOENT;
  346. int id = res_id;
  347. if (type == RES_QP)
  348. id &= 0x7fffff;
  349. spin_lock(mlx4_tlock(dev));
  350. r = find_res(dev, id, type);
  351. if (r) {
  352. *slave = r->owner;
  353. err = 0;
  354. }
  355. spin_unlock(mlx4_tlock(dev));
  356. return err;
  357. }
  358. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  359. enum mlx4_resource type)
  360. {
  361. struct res_common *r;
  362. spin_lock_irq(mlx4_tlock(dev));
  363. r = find_res(dev, res_id, type);
  364. if (r)
  365. r->state = r->from_state;
  366. spin_unlock_irq(mlx4_tlock(dev));
  367. }
  368. static struct res_common *alloc_qp_tr(int id)
  369. {
  370. struct res_qp *ret;
  371. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  372. if (!ret)
  373. return NULL;
  374. ret->com.res_id = id;
  375. ret->com.state = RES_QP_RESERVED;
  376. ret->local_qpn = id;
  377. INIT_LIST_HEAD(&ret->mcg_list);
  378. spin_lock_init(&ret->mcg_spl);
  379. atomic_set(&ret->ref_count, 0);
  380. return &ret->com;
  381. }
  382. static struct res_common *alloc_mtt_tr(int id, int order)
  383. {
  384. struct res_mtt *ret;
  385. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  386. if (!ret)
  387. return NULL;
  388. ret->com.res_id = id;
  389. ret->order = order;
  390. ret->com.state = RES_MTT_ALLOCATED;
  391. atomic_set(&ret->ref_count, 0);
  392. return &ret->com;
  393. }
  394. static struct res_common *alloc_mpt_tr(int id, int key)
  395. {
  396. struct res_mpt *ret;
  397. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  398. if (!ret)
  399. return NULL;
  400. ret->com.res_id = id;
  401. ret->com.state = RES_MPT_RESERVED;
  402. ret->key = key;
  403. return &ret->com;
  404. }
  405. static struct res_common *alloc_eq_tr(int id)
  406. {
  407. struct res_eq *ret;
  408. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  409. if (!ret)
  410. return NULL;
  411. ret->com.res_id = id;
  412. ret->com.state = RES_EQ_RESERVED;
  413. return &ret->com;
  414. }
  415. static struct res_common *alloc_cq_tr(int id)
  416. {
  417. struct res_cq *ret;
  418. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  419. if (!ret)
  420. return NULL;
  421. ret->com.res_id = id;
  422. ret->com.state = RES_CQ_ALLOCATED;
  423. atomic_set(&ret->ref_count, 0);
  424. return &ret->com;
  425. }
  426. static struct res_common *alloc_srq_tr(int id)
  427. {
  428. struct res_srq *ret;
  429. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  430. if (!ret)
  431. return NULL;
  432. ret->com.res_id = id;
  433. ret->com.state = RES_SRQ_ALLOCATED;
  434. atomic_set(&ret->ref_count, 0);
  435. return &ret->com;
  436. }
  437. static struct res_common *alloc_counter_tr(int id)
  438. {
  439. struct res_counter *ret;
  440. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  441. if (!ret)
  442. return NULL;
  443. ret->com.res_id = id;
  444. ret->com.state = RES_COUNTER_ALLOCATED;
  445. return &ret->com;
  446. }
  447. static struct res_common *alloc_xrcdn_tr(int id)
  448. {
  449. struct res_xrcdn *ret;
  450. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  451. if (!ret)
  452. return NULL;
  453. ret->com.res_id = id;
  454. ret->com.state = RES_XRCD_ALLOCATED;
  455. return &ret->com;
  456. }
  457. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  458. {
  459. struct res_fs_rule *ret;
  460. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  461. if (!ret)
  462. return NULL;
  463. ret->com.res_id = id;
  464. ret->com.state = RES_FS_RULE_ALLOCATED;
  465. ret->qpn = qpn;
  466. return &ret->com;
  467. }
  468. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  469. int extra)
  470. {
  471. struct res_common *ret;
  472. switch (type) {
  473. case RES_QP:
  474. ret = alloc_qp_tr(id);
  475. break;
  476. case RES_MPT:
  477. ret = alloc_mpt_tr(id, extra);
  478. break;
  479. case RES_MTT:
  480. ret = alloc_mtt_tr(id, extra);
  481. break;
  482. case RES_EQ:
  483. ret = alloc_eq_tr(id);
  484. break;
  485. case RES_CQ:
  486. ret = alloc_cq_tr(id);
  487. break;
  488. case RES_SRQ:
  489. ret = alloc_srq_tr(id);
  490. break;
  491. case RES_MAC:
  492. printk(KERN_ERR "implementation missing\n");
  493. return NULL;
  494. case RES_COUNTER:
  495. ret = alloc_counter_tr(id);
  496. break;
  497. case RES_XRCD:
  498. ret = alloc_xrcdn_tr(id);
  499. break;
  500. case RES_FS_RULE:
  501. ret = alloc_fs_rule_tr(id, extra);
  502. break;
  503. default:
  504. return NULL;
  505. }
  506. if (ret)
  507. ret->owner = slave;
  508. return ret;
  509. }
  510. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  511. enum mlx4_resource type, int extra)
  512. {
  513. int i;
  514. int err;
  515. struct mlx4_priv *priv = mlx4_priv(dev);
  516. struct res_common **res_arr;
  517. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  518. struct rb_root *root = &tracker->res_tree[type];
  519. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  520. if (!res_arr)
  521. return -ENOMEM;
  522. for (i = 0; i < count; ++i) {
  523. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  524. if (!res_arr[i]) {
  525. for (--i; i >= 0; --i)
  526. kfree(res_arr[i]);
  527. kfree(res_arr);
  528. return -ENOMEM;
  529. }
  530. }
  531. spin_lock_irq(mlx4_tlock(dev));
  532. for (i = 0; i < count; ++i) {
  533. if (find_res(dev, base + i, type)) {
  534. err = -EEXIST;
  535. goto undo;
  536. }
  537. err = res_tracker_insert(root, res_arr[i]);
  538. if (err)
  539. goto undo;
  540. list_add_tail(&res_arr[i]->list,
  541. &tracker->slave_list[slave].res_list[type]);
  542. }
  543. spin_unlock_irq(mlx4_tlock(dev));
  544. kfree(res_arr);
  545. return 0;
  546. undo:
  547. for (--i; i >= base; --i)
  548. rb_erase(&res_arr[i]->node, root);
  549. spin_unlock_irq(mlx4_tlock(dev));
  550. for (i = 0; i < count; ++i)
  551. kfree(res_arr[i]);
  552. kfree(res_arr);
  553. return err;
  554. }
  555. static int remove_qp_ok(struct res_qp *res)
  556. {
  557. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  558. !list_empty(&res->mcg_list)) {
  559. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  560. res->com.state, atomic_read(&res->ref_count));
  561. return -EBUSY;
  562. } else if (res->com.state != RES_QP_RESERVED) {
  563. return -EPERM;
  564. }
  565. return 0;
  566. }
  567. static int remove_mtt_ok(struct res_mtt *res, int order)
  568. {
  569. if (res->com.state == RES_MTT_BUSY ||
  570. atomic_read(&res->ref_count)) {
  571. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  572. __func__, __LINE__,
  573. mtt_states_str(res->com.state),
  574. atomic_read(&res->ref_count));
  575. return -EBUSY;
  576. } else if (res->com.state != RES_MTT_ALLOCATED)
  577. return -EPERM;
  578. else if (res->order != order)
  579. return -EINVAL;
  580. return 0;
  581. }
  582. static int remove_mpt_ok(struct res_mpt *res)
  583. {
  584. if (res->com.state == RES_MPT_BUSY)
  585. return -EBUSY;
  586. else if (res->com.state != RES_MPT_RESERVED)
  587. return -EPERM;
  588. return 0;
  589. }
  590. static int remove_eq_ok(struct res_eq *res)
  591. {
  592. if (res->com.state == RES_MPT_BUSY)
  593. return -EBUSY;
  594. else if (res->com.state != RES_MPT_RESERVED)
  595. return -EPERM;
  596. return 0;
  597. }
  598. static int remove_counter_ok(struct res_counter *res)
  599. {
  600. if (res->com.state == RES_COUNTER_BUSY)
  601. return -EBUSY;
  602. else if (res->com.state != RES_COUNTER_ALLOCATED)
  603. return -EPERM;
  604. return 0;
  605. }
  606. static int remove_xrcdn_ok(struct res_xrcdn *res)
  607. {
  608. if (res->com.state == RES_XRCD_BUSY)
  609. return -EBUSY;
  610. else if (res->com.state != RES_XRCD_ALLOCATED)
  611. return -EPERM;
  612. return 0;
  613. }
  614. static int remove_fs_rule_ok(struct res_fs_rule *res)
  615. {
  616. if (res->com.state == RES_FS_RULE_BUSY)
  617. return -EBUSY;
  618. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  619. return -EPERM;
  620. return 0;
  621. }
  622. static int remove_cq_ok(struct res_cq *res)
  623. {
  624. if (res->com.state == RES_CQ_BUSY)
  625. return -EBUSY;
  626. else if (res->com.state != RES_CQ_ALLOCATED)
  627. return -EPERM;
  628. return 0;
  629. }
  630. static int remove_srq_ok(struct res_srq *res)
  631. {
  632. if (res->com.state == RES_SRQ_BUSY)
  633. return -EBUSY;
  634. else if (res->com.state != RES_SRQ_ALLOCATED)
  635. return -EPERM;
  636. return 0;
  637. }
  638. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  639. {
  640. switch (type) {
  641. case RES_QP:
  642. return remove_qp_ok((struct res_qp *)res);
  643. case RES_CQ:
  644. return remove_cq_ok((struct res_cq *)res);
  645. case RES_SRQ:
  646. return remove_srq_ok((struct res_srq *)res);
  647. case RES_MPT:
  648. return remove_mpt_ok((struct res_mpt *)res);
  649. case RES_MTT:
  650. return remove_mtt_ok((struct res_mtt *)res, extra);
  651. case RES_MAC:
  652. return -ENOSYS;
  653. case RES_EQ:
  654. return remove_eq_ok((struct res_eq *)res);
  655. case RES_COUNTER:
  656. return remove_counter_ok((struct res_counter *)res);
  657. case RES_XRCD:
  658. return remove_xrcdn_ok((struct res_xrcdn *)res);
  659. case RES_FS_RULE:
  660. return remove_fs_rule_ok((struct res_fs_rule *)res);
  661. default:
  662. return -EINVAL;
  663. }
  664. }
  665. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  666. enum mlx4_resource type, int extra)
  667. {
  668. u64 i;
  669. int err;
  670. struct mlx4_priv *priv = mlx4_priv(dev);
  671. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  672. struct res_common *r;
  673. spin_lock_irq(mlx4_tlock(dev));
  674. for (i = base; i < base + count; ++i) {
  675. r = res_tracker_lookup(&tracker->res_tree[type], i);
  676. if (!r) {
  677. err = -ENOENT;
  678. goto out;
  679. }
  680. if (r->owner != slave) {
  681. err = -EPERM;
  682. goto out;
  683. }
  684. err = remove_ok(r, type, extra);
  685. if (err)
  686. goto out;
  687. }
  688. for (i = base; i < base + count; ++i) {
  689. r = res_tracker_lookup(&tracker->res_tree[type], i);
  690. rb_erase(&r->node, &tracker->res_tree[type]);
  691. list_del(&r->list);
  692. kfree(r);
  693. }
  694. err = 0;
  695. out:
  696. spin_unlock_irq(mlx4_tlock(dev));
  697. return err;
  698. }
  699. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  700. enum res_qp_states state, struct res_qp **qp,
  701. int alloc)
  702. {
  703. struct mlx4_priv *priv = mlx4_priv(dev);
  704. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  705. struct res_qp *r;
  706. int err = 0;
  707. spin_lock_irq(mlx4_tlock(dev));
  708. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  709. if (!r)
  710. err = -ENOENT;
  711. else if (r->com.owner != slave)
  712. err = -EPERM;
  713. else {
  714. switch (state) {
  715. case RES_QP_BUSY:
  716. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  717. __func__, r->com.res_id);
  718. err = -EBUSY;
  719. break;
  720. case RES_QP_RESERVED:
  721. if (r->com.state == RES_QP_MAPPED && !alloc)
  722. break;
  723. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  724. err = -EINVAL;
  725. break;
  726. case RES_QP_MAPPED:
  727. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  728. r->com.state == RES_QP_HW)
  729. break;
  730. else {
  731. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  732. r->com.res_id);
  733. err = -EINVAL;
  734. }
  735. break;
  736. case RES_QP_HW:
  737. if (r->com.state != RES_QP_MAPPED)
  738. err = -EINVAL;
  739. break;
  740. default:
  741. err = -EINVAL;
  742. }
  743. if (!err) {
  744. r->com.from_state = r->com.state;
  745. r->com.to_state = state;
  746. r->com.state = RES_QP_BUSY;
  747. if (qp)
  748. *qp = r;
  749. }
  750. }
  751. spin_unlock_irq(mlx4_tlock(dev));
  752. return err;
  753. }
  754. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  755. enum res_mpt_states state, struct res_mpt **mpt)
  756. {
  757. struct mlx4_priv *priv = mlx4_priv(dev);
  758. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  759. struct res_mpt *r;
  760. int err = 0;
  761. spin_lock_irq(mlx4_tlock(dev));
  762. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  763. if (!r)
  764. err = -ENOENT;
  765. else if (r->com.owner != slave)
  766. err = -EPERM;
  767. else {
  768. switch (state) {
  769. case RES_MPT_BUSY:
  770. err = -EINVAL;
  771. break;
  772. case RES_MPT_RESERVED:
  773. if (r->com.state != RES_MPT_MAPPED)
  774. err = -EINVAL;
  775. break;
  776. case RES_MPT_MAPPED:
  777. if (r->com.state != RES_MPT_RESERVED &&
  778. r->com.state != RES_MPT_HW)
  779. err = -EINVAL;
  780. break;
  781. case RES_MPT_HW:
  782. if (r->com.state != RES_MPT_MAPPED)
  783. err = -EINVAL;
  784. break;
  785. default:
  786. err = -EINVAL;
  787. }
  788. if (!err) {
  789. r->com.from_state = r->com.state;
  790. r->com.to_state = state;
  791. r->com.state = RES_MPT_BUSY;
  792. if (mpt)
  793. *mpt = r;
  794. }
  795. }
  796. spin_unlock_irq(mlx4_tlock(dev));
  797. return err;
  798. }
  799. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  800. enum res_eq_states state, struct res_eq **eq)
  801. {
  802. struct mlx4_priv *priv = mlx4_priv(dev);
  803. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  804. struct res_eq *r;
  805. int err = 0;
  806. spin_lock_irq(mlx4_tlock(dev));
  807. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  808. if (!r)
  809. err = -ENOENT;
  810. else if (r->com.owner != slave)
  811. err = -EPERM;
  812. else {
  813. switch (state) {
  814. case RES_EQ_BUSY:
  815. err = -EINVAL;
  816. break;
  817. case RES_EQ_RESERVED:
  818. if (r->com.state != RES_EQ_HW)
  819. err = -EINVAL;
  820. break;
  821. case RES_EQ_HW:
  822. if (r->com.state != RES_EQ_RESERVED)
  823. err = -EINVAL;
  824. break;
  825. default:
  826. err = -EINVAL;
  827. }
  828. if (!err) {
  829. r->com.from_state = r->com.state;
  830. r->com.to_state = state;
  831. r->com.state = RES_EQ_BUSY;
  832. if (eq)
  833. *eq = r;
  834. }
  835. }
  836. spin_unlock_irq(mlx4_tlock(dev));
  837. return err;
  838. }
  839. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  840. enum res_cq_states state, struct res_cq **cq)
  841. {
  842. struct mlx4_priv *priv = mlx4_priv(dev);
  843. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  844. struct res_cq *r;
  845. int err;
  846. spin_lock_irq(mlx4_tlock(dev));
  847. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  848. if (!r)
  849. err = -ENOENT;
  850. else if (r->com.owner != slave)
  851. err = -EPERM;
  852. else {
  853. switch (state) {
  854. case RES_CQ_BUSY:
  855. err = -EBUSY;
  856. break;
  857. case RES_CQ_ALLOCATED:
  858. if (r->com.state != RES_CQ_HW)
  859. err = -EINVAL;
  860. else if (atomic_read(&r->ref_count))
  861. err = -EBUSY;
  862. else
  863. err = 0;
  864. break;
  865. case RES_CQ_HW:
  866. if (r->com.state != RES_CQ_ALLOCATED)
  867. err = -EINVAL;
  868. else
  869. err = 0;
  870. break;
  871. default:
  872. err = -EINVAL;
  873. }
  874. if (!err) {
  875. r->com.from_state = r->com.state;
  876. r->com.to_state = state;
  877. r->com.state = RES_CQ_BUSY;
  878. if (cq)
  879. *cq = r;
  880. }
  881. }
  882. spin_unlock_irq(mlx4_tlock(dev));
  883. return err;
  884. }
  885. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  886. enum res_cq_states state, struct res_srq **srq)
  887. {
  888. struct mlx4_priv *priv = mlx4_priv(dev);
  889. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  890. struct res_srq *r;
  891. int err = 0;
  892. spin_lock_irq(mlx4_tlock(dev));
  893. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  894. if (!r)
  895. err = -ENOENT;
  896. else if (r->com.owner != slave)
  897. err = -EPERM;
  898. else {
  899. switch (state) {
  900. case RES_SRQ_BUSY:
  901. err = -EINVAL;
  902. break;
  903. case RES_SRQ_ALLOCATED:
  904. if (r->com.state != RES_SRQ_HW)
  905. err = -EINVAL;
  906. else if (atomic_read(&r->ref_count))
  907. err = -EBUSY;
  908. break;
  909. case RES_SRQ_HW:
  910. if (r->com.state != RES_SRQ_ALLOCATED)
  911. err = -EINVAL;
  912. break;
  913. default:
  914. err = -EINVAL;
  915. }
  916. if (!err) {
  917. r->com.from_state = r->com.state;
  918. r->com.to_state = state;
  919. r->com.state = RES_SRQ_BUSY;
  920. if (srq)
  921. *srq = r;
  922. }
  923. }
  924. spin_unlock_irq(mlx4_tlock(dev));
  925. return err;
  926. }
  927. static void res_abort_move(struct mlx4_dev *dev, int slave,
  928. enum mlx4_resource type, int id)
  929. {
  930. struct mlx4_priv *priv = mlx4_priv(dev);
  931. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  932. struct res_common *r;
  933. spin_lock_irq(mlx4_tlock(dev));
  934. r = res_tracker_lookup(&tracker->res_tree[type], id);
  935. if (r && (r->owner == slave))
  936. r->state = r->from_state;
  937. spin_unlock_irq(mlx4_tlock(dev));
  938. }
  939. static void res_end_move(struct mlx4_dev *dev, int slave,
  940. enum mlx4_resource type, int id)
  941. {
  942. struct mlx4_priv *priv = mlx4_priv(dev);
  943. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  944. struct res_common *r;
  945. spin_lock_irq(mlx4_tlock(dev));
  946. r = res_tracker_lookup(&tracker->res_tree[type], id);
  947. if (r && (r->owner == slave))
  948. r->state = r->to_state;
  949. spin_unlock_irq(mlx4_tlock(dev));
  950. }
  951. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  952. {
  953. return mlx4_is_qp_reserved(dev, qpn) &&
  954. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  955. }
  956. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  957. {
  958. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  959. }
  960. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  961. u64 in_param, u64 *out_param)
  962. {
  963. int err;
  964. int count;
  965. int align;
  966. int base;
  967. int qpn;
  968. switch (op) {
  969. case RES_OP_RESERVE:
  970. count = get_param_l(&in_param);
  971. align = get_param_h(&in_param);
  972. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  973. if (err)
  974. return err;
  975. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  976. if (err) {
  977. __mlx4_qp_release_range(dev, base, count);
  978. return err;
  979. }
  980. set_param_l(out_param, base);
  981. break;
  982. case RES_OP_MAP_ICM:
  983. qpn = get_param_l(&in_param) & 0x7fffff;
  984. if (valid_reserved(dev, slave, qpn)) {
  985. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  986. if (err)
  987. return err;
  988. }
  989. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  990. NULL, 1);
  991. if (err)
  992. return err;
  993. if (!fw_reserved(dev, qpn)) {
  994. err = __mlx4_qp_alloc_icm(dev, qpn);
  995. if (err) {
  996. res_abort_move(dev, slave, RES_QP, qpn);
  997. return err;
  998. }
  999. }
  1000. res_end_move(dev, slave, RES_QP, qpn);
  1001. break;
  1002. default:
  1003. err = -EINVAL;
  1004. break;
  1005. }
  1006. return err;
  1007. }
  1008. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1009. u64 in_param, u64 *out_param)
  1010. {
  1011. int err = -EINVAL;
  1012. int base;
  1013. int order;
  1014. if (op != RES_OP_RESERVE_AND_MAP)
  1015. return err;
  1016. order = get_param_l(&in_param);
  1017. base = __mlx4_alloc_mtt_range(dev, order);
  1018. if (base == -1)
  1019. return -ENOMEM;
  1020. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1021. if (err)
  1022. __mlx4_free_mtt_range(dev, base, order);
  1023. else
  1024. set_param_l(out_param, base);
  1025. return err;
  1026. }
  1027. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1028. u64 in_param, u64 *out_param)
  1029. {
  1030. int err = -EINVAL;
  1031. int index;
  1032. int id;
  1033. struct res_mpt *mpt;
  1034. switch (op) {
  1035. case RES_OP_RESERVE:
  1036. index = __mlx4_mpt_reserve(dev);
  1037. if (index == -1)
  1038. break;
  1039. id = index & mpt_mask(dev);
  1040. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1041. if (err) {
  1042. __mlx4_mpt_release(dev, index);
  1043. break;
  1044. }
  1045. set_param_l(out_param, index);
  1046. break;
  1047. case RES_OP_MAP_ICM:
  1048. index = get_param_l(&in_param);
  1049. id = index & mpt_mask(dev);
  1050. err = mr_res_start_move_to(dev, slave, id,
  1051. RES_MPT_MAPPED, &mpt);
  1052. if (err)
  1053. return err;
  1054. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1055. if (err) {
  1056. res_abort_move(dev, slave, RES_MPT, id);
  1057. return err;
  1058. }
  1059. res_end_move(dev, slave, RES_MPT, id);
  1060. break;
  1061. }
  1062. return err;
  1063. }
  1064. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1065. u64 in_param, u64 *out_param)
  1066. {
  1067. int cqn;
  1068. int err;
  1069. switch (op) {
  1070. case RES_OP_RESERVE_AND_MAP:
  1071. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1072. if (err)
  1073. break;
  1074. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1075. if (err) {
  1076. __mlx4_cq_free_icm(dev, cqn);
  1077. break;
  1078. }
  1079. set_param_l(out_param, cqn);
  1080. break;
  1081. default:
  1082. err = -EINVAL;
  1083. }
  1084. return err;
  1085. }
  1086. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1087. u64 in_param, u64 *out_param)
  1088. {
  1089. int srqn;
  1090. int err;
  1091. switch (op) {
  1092. case RES_OP_RESERVE_AND_MAP:
  1093. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1094. if (err)
  1095. break;
  1096. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1097. if (err) {
  1098. __mlx4_srq_free_icm(dev, srqn);
  1099. break;
  1100. }
  1101. set_param_l(out_param, srqn);
  1102. break;
  1103. default:
  1104. err = -EINVAL;
  1105. }
  1106. return err;
  1107. }
  1108. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1109. {
  1110. struct mlx4_priv *priv = mlx4_priv(dev);
  1111. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1112. struct mac_res *res;
  1113. res = kzalloc(sizeof *res, GFP_KERNEL);
  1114. if (!res)
  1115. return -ENOMEM;
  1116. res->mac = mac;
  1117. res->port = (u8) port;
  1118. list_add_tail(&res->list,
  1119. &tracker->slave_list[slave].res_list[RES_MAC]);
  1120. return 0;
  1121. }
  1122. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1123. int port)
  1124. {
  1125. struct mlx4_priv *priv = mlx4_priv(dev);
  1126. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1127. struct list_head *mac_list =
  1128. &tracker->slave_list[slave].res_list[RES_MAC];
  1129. struct mac_res *res, *tmp;
  1130. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1131. if (res->mac == mac && res->port == (u8) port) {
  1132. list_del(&res->list);
  1133. kfree(res);
  1134. break;
  1135. }
  1136. }
  1137. }
  1138. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1139. {
  1140. struct mlx4_priv *priv = mlx4_priv(dev);
  1141. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1142. struct list_head *mac_list =
  1143. &tracker->slave_list[slave].res_list[RES_MAC];
  1144. struct mac_res *res, *tmp;
  1145. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1146. list_del(&res->list);
  1147. __mlx4_unregister_mac(dev, res->port, res->mac);
  1148. kfree(res);
  1149. }
  1150. }
  1151. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1152. u64 in_param, u64 *out_param)
  1153. {
  1154. int err = -EINVAL;
  1155. int port;
  1156. u64 mac;
  1157. if (op != RES_OP_RESERVE_AND_MAP)
  1158. return err;
  1159. port = get_param_l(out_param);
  1160. mac = in_param;
  1161. err = __mlx4_register_mac(dev, port, mac);
  1162. if (err >= 0) {
  1163. set_param_l(out_param, err);
  1164. err = 0;
  1165. }
  1166. if (!err) {
  1167. err = mac_add_to_slave(dev, slave, mac, port);
  1168. if (err)
  1169. __mlx4_unregister_mac(dev, port, mac);
  1170. }
  1171. return err;
  1172. }
  1173. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1174. u64 in_param, u64 *out_param)
  1175. {
  1176. return 0;
  1177. }
  1178. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1179. u64 in_param, u64 *out_param)
  1180. {
  1181. u32 index;
  1182. int err;
  1183. if (op != RES_OP_RESERVE)
  1184. return -EINVAL;
  1185. err = __mlx4_counter_alloc(dev, &index);
  1186. if (err)
  1187. return err;
  1188. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1189. if (err)
  1190. __mlx4_counter_free(dev, index);
  1191. else
  1192. set_param_l(out_param, index);
  1193. return err;
  1194. }
  1195. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1196. u64 in_param, u64 *out_param)
  1197. {
  1198. u32 xrcdn;
  1199. int err;
  1200. if (op != RES_OP_RESERVE)
  1201. return -EINVAL;
  1202. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1203. if (err)
  1204. return err;
  1205. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1206. if (err)
  1207. __mlx4_xrcd_free(dev, xrcdn);
  1208. else
  1209. set_param_l(out_param, xrcdn);
  1210. return err;
  1211. }
  1212. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1213. struct mlx4_vhcr *vhcr,
  1214. struct mlx4_cmd_mailbox *inbox,
  1215. struct mlx4_cmd_mailbox *outbox,
  1216. struct mlx4_cmd_info *cmd)
  1217. {
  1218. int err;
  1219. int alop = vhcr->op_modifier;
  1220. switch (vhcr->in_modifier) {
  1221. case RES_QP:
  1222. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1223. vhcr->in_param, &vhcr->out_param);
  1224. break;
  1225. case RES_MTT:
  1226. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1227. vhcr->in_param, &vhcr->out_param);
  1228. break;
  1229. case RES_MPT:
  1230. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1231. vhcr->in_param, &vhcr->out_param);
  1232. break;
  1233. case RES_CQ:
  1234. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1235. vhcr->in_param, &vhcr->out_param);
  1236. break;
  1237. case RES_SRQ:
  1238. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1239. vhcr->in_param, &vhcr->out_param);
  1240. break;
  1241. case RES_MAC:
  1242. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1243. vhcr->in_param, &vhcr->out_param);
  1244. break;
  1245. case RES_VLAN:
  1246. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1247. vhcr->in_param, &vhcr->out_param);
  1248. break;
  1249. case RES_COUNTER:
  1250. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1251. vhcr->in_param, &vhcr->out_param);
  1252. break;
  1253. case RES_XRCD:
  1254. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1255. vhcr->in_param, &vhcr->out_param);
  1256. break;
  1257. default:
  1258. err = -EINVAL;
  1259. break;
  1260. }
  1261. return err;
  1262. }
  1263. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1264. u64 in_param)
  1265. {
  1266. int err;
  1267. int count;
  1268. int base;
  1269. int qpn;
  1270. switch (op) {
  1271. case RES_OP_RESERVE:
  1272. base = get_param_l(&in_param) & 0x7fffff;
  1273. count = get_param_h(&in_param);
  1274. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1275. if (err)
  1276. break;
  1277. __mlx4_qp_release_range(dev, base, count);
  1278. break;
  1279. case RES_OP_MAP_ICM:
  1280. qpn = get_param_l(&in_param) & 0x7fffff;
  1281. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1282. NULL, 0);
  1283. if (err)
  1284. return err;
  1285. if (!fw_reserved(dev, qpn))
  1286. __mlx4_qp_free_icm(dev, qpn);
  1287. res_end_move(dev, slave, RES_QP, qpn);
  1288. if (valid_reserved(dev, slave, qpn))
  1289. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1290. break;
  1291. default:
  1292. err = -EINVAL;
  1293. break;
  1294. }
  1295. return err;
  1296. }
  1297. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1298. u64 in_param, u64 *out_param)
  1299. {
  1300. int err = -EINVAL;
  1301. int base;
  1302. int order;
  1303. if (op != RES_OP_RESERVE_AND_MAP)
  1304. return err;
  1305. base = get_param_l(&in_param);
  1306. order = get_param_h(&in_param);
  1307. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1308. if (!err)
  1309. __mlx4_free_mtt_range(dev, base, order);
  1310. return err;
  1311. }
  1312. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1313. u64 in_param)
  1314. {
  1315. int err = -EINVAL;
  1316. int index;
  1317. int id;
  1318. struct res_mpt *mpt;
  1319. switch (op) {
  1320. case RES_OP_RESERVE:
  1321. index = get_param_l(&in_param);
  1322. id = index & mpt_mask(dev);
  1323. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1324. if (err)
  1325. break;
  1326. index = mpt->key;
  1327. put_res(dev, slave, id, RES_MPT);
  1328. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1329. if (err)
  1330. break;
  1331. __mlx4_mpt_release(dev, index);
  1332. break;
  1333. case RES_OP_MAP_ICM:
  1334. index = get_param_l(&in_param);
  1335. id = index & mpt_mask(dev);
  1336. err = mr_res_start_move_to(dev, slave, id,
  1337. RES_MPT_RESERVED, &mpt);
  1338. if (err)
  1339. return err;
  1340. __mlx4_mpt_free_icm(dev, mpt->key);
  1341. res_end_move(dev, slave, RES_MPT, id);
  1342. return err;
  1343. break;
  1344. default:
  1345. err = -EINVAL;
  1346. break;
  1347. }
  1348. return err;
  1349. }
  1350. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1351. u64 in_param, u64 *out_param)
  1352. {
  1353. int cqn;
  1354. int err;
  1355. switch (op) {
  1356. case RES_OP_RESERVE_AND_MAP:
  1357. cqn = get_param_l(&in_param);
  1358. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1359. if (err)
  1360. break;
  1361. __mlx4_cq_free_icm(dev, cqn);
  1362. break;
  1363. default:
  1364. err = -EINVAL;
  1365. break;
  1366. }
  1367. return err;
  1368. }
  1369. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1370. u64 in_param, u64 *out_param)
  1371. {
  1372. int srqn;
  1373. int err;
  1374. switch (op) {
  1375. case RES_OP_RESERVE_AND_MAP:
  1376. srqn = get_param_l(&in_param);
  1377. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1378. if (err)
  1379. break;
  1380. __mlx4_srq_free_icm(dev, srqn);
  1381. break;
  1382. default:
  1383. err = -EINVAL;
  1384. break;
  1385. }
  1386. return err;
  1387. }
  1388. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1389. u64 in_param, u64 *out_param)
  1390. {
  1391. int port;
  1392. int err = 0;
  1393. switch (op) {
  1394. case RES_OP_RESERVE_AND_MAP:
  1395. port = get_param_l(out_param);
  1396. mac_del_from_slave(dev, slave, in_param, port);
  1397. __mlx4_unregister_mac(dev, port, in_param);
  1398. break;
  1399. default:
  1400. err = -EINVAL;
  1401. break;
  1402. }
  1403. return err;
  1404. }
  1405. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1406. u64 in_param, u64 *out_param)
  1407. {
  1408. return 0;
  1409. }
  1410. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1411. u64 in_param, u64 *out_param)
  1412. {
  1413. int index;
  1414. int err;
  1415. if (op != RES_OP_RESERVE)
  1416. return -EINVAL;
  1417. index = get_param_l(&in_param);
  1418. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1419. if (err)
  1420. return err;
  1421. __mlx4_counter_free(dev, index);
  1422. return err;
  1423. }
  1424. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1425. u64 in_param, u64 *out_param)
  1426. {
  1427. int xrcdn;
  1428. int err;
  1429. if (op != RES_OP_RESERVE)
  1430. return -EINVAL;
  1431. xrcdn = get_param_l(&in_param);
  1432. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1433. if (err)
  1434. return err;
  1435. __mlx4_xrcd_free(dev, xrcdn);
  1436. return err;
  1437. }
  1438. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1439. struct mlx4_vhcr *vhcr,
  1440. struct mlx4_cmd_mailbox *inbox,
  1441. struct mlx4_cmd_mailbox *outbox,
  1442. struct mlx4_cmd_info *cmd)
  1443. {
  1444. int err = -EINVAL;
  1445. int alop = vhcr->op_modifier;
  1446. switch (vhcr->in_modifier) {
  1447. case RES_QP:
  1448. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1449. vhcr->in_param);
  1450. break;
  1451. case RES_MTT:
  1452. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1453. vhcr->in_param, &vhcr->out_param);
  1454. break;
  1455. case RES_MPT:
  1456. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1457. vhcr->in_param);
  1458. break;
  1459. case RES_CQ:
  1460. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1461. vhcr->in_param, &vhcr->out_param);
  1462. break;
  1463. case RES_SRQ:
  1464. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1465. vhcr->in_param, &vhcr->out_param);
  1466. break;
  1467. case RES_MAC:
  1468. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1469. vhcr->in_param, &vhcr->out_param);
  1470. break;
  1471. case RES_VLAN:
  1472. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1473. vhcr->in_param, &vhcr->out_param);
  1474. break;
  1475. case RES_COUNTER:
  1476. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1477. vhcr->in_param, &vhcr->out_param);
  1478. break;
  1479. case RES_XRCD:
  1480. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1481. vhcr->in_param, &vhcr->out_param);
  1482. default:
  1483. break;
  1484. }
  1485. return err;
  1486. }
  1487. /* ugly but other choices are uglier */
  1488. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1489. {
  1490. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1491. }
  1492. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1493. {
  1494. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1495. }
  1496. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1497. {
  1498. return be32_to_cpu(mpt->mtt_sz);
  1499. }
  1500. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  1501. {
  1502. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  1503. }
  1504. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  1505. {
  1506. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  1507. }
  1508. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  1509. {
  1510. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  1511. }
  1512. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  1513. {
  1514. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  1515. }
  1516. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1517. {
  1518. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1519. }
  1520. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1521. {
  1522. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1523. }
  1524. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1525. {
  1526. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1527. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1528. int log_sq_sride = qpc->sq_size_stride & 7;
  1529. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1530. int log_rq_stride = qpc->rq_size_stride & 7;
  1531. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1532. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1533. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1534. int sq_size;
  1535. int rq_size;
  1536. int total_pages;
  1537. int total_mem;
  1538. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1539. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1540. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1541. total_mem = sq_size + rq_size;
  1542. total_pages =
  1543. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1544. page_shift);
  1545. return total_pages;
  1546. }
  1547. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1548. int size, struct res_mtt *mtt)
  1549. {
  1550. int res_start = mtt->com.res_id;
  1551. int res_size = (1 << mtt->order);
  1552. if (start < res_start || start + size > res_start + res_size)
  1553. return -EPERM;
  1554. return 0;
  1555. }
  1556. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1557. struct mlx4_vhcr *vhcr,
  1558. struct mlx4_cmd_mailbox *inbox,
  1559. struct mlx4_cmd_mailbox *outbox,
  1560. struct mlx4_cmd_info *cmd)
  1561. {
  1562. int err;
  1563. int index = vhcr->in_modifier;
  1564. struct res_mtt *mtt;
  1565. struct res_mpt *mpt;
  1566. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1567. int phys;
  1568. int id;
  1569. u32 pd;
  1570. int pd_slave;
  1571. id = index & mpt_mask(dev);
  1572. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1573. if (err)
  1574. return err;
  1575. /* Disable memory windows for VFs. */
  1576. if (!mr_is_region(inbox->buf)) {
  1577. err = -EPERM;
  1578. goto ex_abort;
  1579. }
  1580. /* Make sure that the PD bits related to the slave id are zeros. */
  1581. pd = mr_get_pd(inbox->buf);
  1582. pd_slave = (pd >> 17) & 0x7f;
  1583. if (pd_slave != 0 && pd_slave != slave) {
  1584. err = -EPERM;
  1585. goto ex_abort;
  1586. }
  1587. if (mr_is_fmr(inbox->buf)) {
  1588. /* FMR and Bind Enable are forbidden in slave devices. */
  1589. if (mr_is_bind_enabled(inbox->buf)) {
  1590. err = -EPERM;
  1591. goto ex_abort;
  1592. }
  1593. /* FMR and Memory Windows are also forbidden. */
  1594. if (!mr_is_region(inbox->buf)) {
  1595. err = -EPERM;
  1596. goto ex_abort;
  1597. }
  1598. }
  1599. phys = mr_phys_mpt(inbox->buf);
  1600. if (!phys) {
  1601. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1602. if (err)
  1603. goto ex_abort;
  1604. err = check_mtt_range(dev, slave, mtt_base,
  1605. mr_get_mtt_size(inbox->buf), mtt);
  1606. if (err)
  1607. goto ex_put;
  1608. mpt->mtt = mtt;
  1609. }
  1610. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1611. if (err)
  1612. goto ex_put;
  1613. if (!phys) {
  1614. atomic_inc(&mtt->ref_count);
  1615. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1616. }
  1617. res_end_move(dev, slave, RES_MPT, id);
  1618. return 0;
  1619. ex_put:
  1620. if (!phys)
  1621. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1622. ex_abort:
  1623. res_abort_move(dev, slave, RES_MPT, id);
  1624. return err;
  1625. }
  1626. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1627. struct mlx4_vhcr *vhcr,
  1628. struct mlx4_cmd_mailbox *inbox,
  1629. struct mlx4_cmd_mailbox *outbox,
  1630. struct mlx4_cmd_info *cmd)
  1631. {
  1632. int err;
  1633. int index = vhcr->in_modifier;
  1634. struct res_mpt *mpt;
  1635. int id;
  1636. id = index & mpt_mask(dev);
  1637. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1638. if (err)
  1639. return err;
  1640. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1641. if (err)
  1642. goto ex_abort;
  1643. if (mpt->mtt)
  1644. atomic_dec(&mpt->mtt->ref_count);
  1645. res_end_move(dev, slave, RES_MPT, id);
  1646. return 0;
  1647. ex_abort:
  1648. res_abort_move(dev, slave, RES_MPT, id);
  1649. return err;
  1650. }
  1651. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1652. struct mlx4_vhcr *vhcr,
  1653. struct mlx4_cmd_mailbox *inbox,
  1654. struct mlx4_cmd_mailbox *outbox,
  1655. struct mlx4_cmd_info *cmd)
  1656. {
  1657. int err;
  1658. int index = vhcr->in_modifier;
  1659. struct res_mpt *mpt;
  1660. int id;
  1661. id = index & mpt_mask(dev);
  1662. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1663. if (err)
  1664. return err;
  1665. if (mpt->com.from_state != RES_MPT_HW) {
  1666. err = -EBUSY;
  1667. goto out;
  1668. }
  1669. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1670. out:
  1671. put_res(dev, slave, id, RES_MPT);
  1672. return err;
  1673. }
  1674. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1675. {
  1676. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1677. }
  1678. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1679. {
  1680. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1681. }
  1682. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1683. {
  1684. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1685. }
  1686. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  1687. struct mlx4_qp_context *context)
  1688. {
  1689. u32 qpn = vhcr->in_modifier & 0xffffff;
  1690. u32 qkey = 0;
  1691. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  1692. return;
  1693. /* adjust qkey in qp context */
  1694. context->qkey = cpu_to_be32(qkey);
  1695. }
  1696. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1697. struct mlx4_vhcr *vhcr,
  1698. struct mlx4_cmd_mailbox *inbox,
  1699. struct mlx4_cmd_mailbox *outbox,
  1700. struct mlx4_cmd_info *cmd)
  1701. {
  1702. int err;
  1703. int qpn = vhcr->in_modifier & 0x7fffff;
  1704. struct res_mtt *mtt;
  1705. struct res_qp *qp;
  1706. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1707. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1708. int mtt_size = qp_get_mtt_size(qpc);
  1709. struct res_cq *rcq;
  1710. struct res_cq *scq;
  1711. int rcqn = qp_get_rcqn(qpc);
  1712. int scqn = qp_get_scqn(qpc);
  1713. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1714. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1715. struct res_srq *srq;
  1716. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1717. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1718. if (err)
  1719. return err;
  1720. qp->local_qpn = local_qpn;
  1721. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1722. if (err)
  1723. goto ex_abort;
  1724. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1725. if (err)
  1726. goto ex_put_mtt;
  1727. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1728. if (err)
  1729. goto ex_put_mtt;
  1730. if (scqn != rcqn) {
  1731. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1732. if (err)
  1733. goto ex_put_rcq;
  1734. } else
  1735. scq = rcq;
  1736. if (use_srq) {
  1737. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1738. if (err)
  1739. goto ex_put_scq;
  1740. }
  1741. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  1742. update_pkey_index(dev, slave, inbox);
  1743. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1744. if (err)
  1745. goto ex_put_srq;
  1746. atomic_inc(&mtt->ref_count);
  1747. qp->mtt = mtt;
  1748. atomic_inc(&rcq->ref_count);
  1749. qp->rcq = rcq;
  1750. atomic_inc(&scq->ref_count);
  1751. qp->scq = scq;
  1752. if (scqn != rcqn)
  1753. put_res(dev, slave, scqn, RES_CQ);
  1754. if (use_srq) {
  1755. atomic_inc(&srq->ref_count);
  1756. put_res(dev, slave, srqn, RES_SRQ);
  1757. qp->srq = srq;
  1758. }
  1759. put_res(dev, slave, rcqn, RES_CQ);
  1760. put_res(dev, slave, mtt_base, RES_MTT);
  1761. res_end_move(dev, slave, RES_QP, qpn);
  1762. return 0;
  1763. ex_put_srq:
  1764. if (use_srq)
  1765. put_res(dev, slave, srqn, RES_SRQ);
  1766. ex_put_scq:
  1767. if (scqn != rcqn)
  1768. put_res(dev, slave, scqn, RES_CQ);
  1769. ex_put_rcq:
  1770. put_res(dev, slave, rcqn, RES_CQ);
  1771. ex_put_mtt:
  1772. put_res(dev, slave, mtt_base, RES_MTT);
  1773. ex_abort:
  1774. res_abort_move(dev, slave, RES_QP, qpn);
  1775. return err;
  1776. }
  1777. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1778. {
  1779. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1780. }
  1781. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1782. {
  1783. int log_eq_size = eqc->log_eq_size & 0x1f;
  1784. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1785. if (log_eq_size + 5 < page_shift)
  1786. return 1;
  1787. return 1 << (log_eq_size + 5 - page_shift);
  1788. }
  1789. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1790. {
  1791. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1792. }
  1793. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1794. {
  1795. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1796. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1797. if (log_cq_size + 5 < page_shift)
  1798. return 1;
  1799. return 1 << (log_cq_size + 5 - page_shift);
  1800. }
  1801. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1802. struct mlx4_vhcr *vhcr,
  1803. struct mlx4_cmd_mailbox *inbox,
  1804. struct mlx4_cmd_mailbox *outbox,
  1805. struct mlx4_cmd_info *cmd)
  1806. {
  1807. int err;
  1808. int eqn = vhcr->in_modifier;
  1809. int res_id = (slave << 8) | eqn;
  1810. struct mlx4_eq_context *eqc = inbox->buf;
  1811. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1812. int mtt_size = eq_get_mtt_size(eqc);
  1813. struct res_eq *eq;
  1814. struct res_mtt *mtt;
  1815. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1816. if (err)
  1817. return err;
  1818. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1819. if (err)
  1820. goto out_add;
  1821. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1822. if (err)
  1823. goto out_move;
  1824. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1825. if (err)
  1826. goto out_put;
  1827. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1828. if (err)
  1829. goto out_put;
  1830. atomic_inc(&mtt->ref_count);
  1831. eq->mtt = mtt;
  1832. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1833. res_end_move(dev, slave, RES_EQ, res_id);
  1834. return 0;
  1835. out_put:
  1836. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1837. out_move:
  1838. res_abort_move(dev, slave, RES_EQ, res_id);
  1839. out_add:
  1840. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1841. return err;
  1842. }
  1843. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1844. int len, struct res_mtt **res)
  1845. {
  1846. struct mlx4_priv *priv = mlx4_priv(dev);
  1847. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1848. struct res_mtt *mtt;
  1849. int err = -EINVAL;
  1850. spin_lock_irq(mlx4_tlock(dev));
  1851. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1852. com.list) {
  1853. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1854. *res = mtt;
  1855. mtt->com.from_state = mtt->com.state;
  1856. mtt->com.state = RES_MTT_BUSY;
  1857. err = 0;
  1858. break;
  1859. }
  1860. }
  1861. spin_unlock_irq(mlx4_tlock(dev));
  1862. return err;
  1863. }
  1864. static int verify_qp_parameters(struct mlx4_dev *dev,
  1865. struct mlx4_cmd_mailbox *inbox,
  1866. enum qp_transition transition, u8 slave)
  1867. {
  1868. u32 qp_type;
  1869. struct mlx4_qp_context *qp_ctx;
  1870. enum mlx4_qp_optpar optpar;
  1871. qp_ctx = inbox->buf + 8;
  1872. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  1873. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  1874. switch (qp_type) {
  1875. case MLX4_QP_ST_RC:
  1876. case MLX4_QP_ST_UC:
  1877. switch (transition) {
  1878. case QP_TRANS_INIT2RTR:
  1879. case QP_TRANS_RTR2RTS:
  1880. case QP_TRANS_RTS2RTS:
  1881. case QP_TRANS_SQD2SQD:
  1882. case QP_TRANS_SQD2RTS:
  1883. if (slave != mlx4_master_func_num(dev))
  1884. /* slaves have only gid index 0 */
  1885. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  1886. if (qp_ctx->pri_path.mgid_index)
  1887. return -EINVAL;
  1888. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  1889. if (qp_ctx->alt_path.mgid_index)
  1890. return -EINVAL;
  1891. break;
  1892. default:
  1893. break;
  1894. }
  1895. break;
  1896. default:
  1897. break;
  1898. }
  1899. return 0;
  1900. }
  1901. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1902. struct mlx4_vhcr *vhcr,
  1903. struct mlx4_cmd_mailbox *inbox,
  1904. struct mlx4_cmd_mailbox *outbox,
  1905. struct mlx4_cmd_info *cmd)
  1906. {
  1907. struct mlx4_mtt mtt;
  1908. __be64 *page_list = inbox->buf;
  1909. u64 *pg_list = (u64 *)page_list;
  1910. int i;
  1911. struct res_mtt *rmtt = NULL;
  1912. int start = be64_to_cpu(page_list[0]);
  1913. int npages = vhcr->in_modifier;
  1914. int err;
  1915. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1916. if (err)
  1917. return err;
  1918. /* Call the SW implementation of write_mtt:
  1919. * - Prepare a dummy mtt struct
  1920. * - Translate inbox contents to simple addresses in host endianess */
  1921. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1922. we don't really use it */
  1923. mtt.order = 0;
  1924. mtt.page_shift = 0;
  1925. for (i = 0; i < npages; ++i)
  1926. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1927. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1928. ((u64 *)page_list + 2));
  1929. if (rmtt)
  1930. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1931. return err;
  1932. }
  1933. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1934. struct mlx4_vhcr *vhcr,
  1935. struct mlx4_cmd_mailbox *inbox,
  1936. struct mlx4_cmd_mailbox *outbox,
  1937. struct mlx4_cmd_info *cmd)
  1938. {
  1939. int eqn = vhcr->in_modifier;
  1940. int res_id = eqn | (slave << 8);
  1941. struct res_eq *eq;
  1942. int err;
  1943. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1944. if (err)
  1945. return err;
  1946. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1947. if (err)
  1948. goto ex_abort;
  1949. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1950. if (err)
  1951. goto ex_put;
  1952. atomic_dec(&eq->mtt->ref_count);
  1953. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1954. res_end_move(dev, slave, RES_EQ, res_id);
  1955. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1956. return 0;
  1957. ex_put:
  1958. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1959. ex_abort:
  1960. res_abort_move(dev, slave, RES_EQ, res_id);
  1961. return err;
  1962. }
  1963. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1964. {
  1965. struct mlx4_priv *priv = mlx4_priv(dev);
  1966. struct mlx4_slave_event_eq_info *event_eq;
  1967. struct mlx4_cmd_mailbox *mailbox;
  1968. u32 in_modifier = 0;
  1969. int err;
  1970. int res_id;
  1971. struct res_eq *req;
  1972. if (!priv->mfunc.master.slave_state)
  1973. return -EINVAL;
  1974. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1975. /* Create the event only if the slave is registered */
  1976. if (event_eq->eqn < 0)
  1977. return 0;
  1978. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1979. res_id = (slave << 8) | event_eq->eqn;
  1980. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1981. if (err)
  1982. goto unlock;
  1983. if (req->com.from_state != RES_EQ_HW) {
  1984. err = -EINVAL;
  1985. goto put;
  1986. }
  1987. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1988. if (IS_ERR(mailbox)) {
  1989. err = PTR_ERR(mailbox);
  1990. goto put;
  1991. }
  1992. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1993. ++event_eq->token;
  1994. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1995. }
  1996. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1997. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1998. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1999. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2000. MLX4_CMD_NATIVE);
  2001. put_res(dev, slave, res_id, RES_EQ);
  2002. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2003. mlx4_free_cmd_mailbox(dev, mailbox);
  2004. return err;
  2005. put:
  2006. put_res(dev, slave, res_id, RES_EQ);
  2007. unlock:
  2008. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2009. return err;
  2010. }
  2011. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2012. struct mlx4_vhcr *vhcr,
  2013. struct mlx4_cmd_mailbox *inbox,
  2014. struct mlx4_cmd_mailbox *outbox,
  2015. struct mlx4_cmd_info *cmd)
  2016. {
  2017. int eqn = vhcr->in_modifier;
  2018. int res_id = eqn | (slave << 8);
  2019. struct res_eq *eq;
  2020. int err;
  2021. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2022. if (err)
  2023. return err;
  2024. if (eq->com.from_state != RES_EQ_HW) {
  2025. err = -EINVAL;
  2026. goto ex_put;
  2027. }
  2028. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2029. ex_put:
  2030. put_res(dev, slave, res_id, RES_EQ);
  2031. return err;
  2032. }
  2033. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2034. struct mlx4_vhcr *vhcr,
  2035. struct mlx4_cmd_mailbox *inbox,
  2036. struct mlx4_cmd_mailbox *outbox,
  2037. struct mlx4_cmd_info *cmd)
  2038. {
  2039. int err;
  2040. int cqn = vhcr->in_modifier;
  2041. struct mlx4_cq_context *cqc = inbox->buf;
  2042. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2043. struct res_cq *cq;
  2044. struct res_mtt *mtt;
  2045. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2046. if (err)
  2047. return err;
  2048. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2049. if (err)
  2050. goto out_move;
  2051. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2052. if (err)
  2053. goto out_put;
  2054. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2055. if (err)
  2056. goto out_put;
  2057. atomic_inc(&mtt->ref_count);
  2058. cq->mtt = mtt;
  2059. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2060. res_end_move(dev, slave, RES_CQ, cqn);
  2061. return 0;
  2062. out_put:
  2063. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2064. out_move:
  2065. res_abort_move(dev, slave, RES_CQ, cqn);
  2066. return err;
  2067. }
  2068. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2069. struct mlx4_vhcr *vhcr,
  2070. struct mlx4_cmd_mailbox *inbox,
  2071. struct mlx4_cmd_mailbox *outbox,
  2072. struct mlx4_cmd_info *cmd)
  2073. {
  2074. int err;
  2075. int cqn = vhcr->in_modifier;
  2076. struct res_cq *cq;
  2077. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2078. if (err)
  2079. return err;
  2080. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2081. if (err)
  2082. goto out_move;
  2083. atomic_dec(&cq->mtt->ref_count);
  2084. res_end_move(dev, slave, RES_CQ, cqn);
  2085. return 0;
  2086. out_move:
  2087. res_abort_move(dev, slave, RES_CQ, cqn);
  2088. return err;
  2089. }
  2090. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2091. struct mlx4_vhcr *vhcr,
  2092. struct mlx4_cmd_mailbox *inbox,
  2093. struct mlx4_cmd_mailbox *outbox,
  2094. struct mlx4_cmd_info *cmd)
  2095. {
  2096. int cqn = vhcr->in_modifier;
  2097. struct res_cq *cq;
  2098. int err;
  2099. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2100. if (err)
  2101. return err;
  2102. if (cq->com.from_state != RES_CQ_HW)
  2103. goto ex_put;
  2104. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2105. ex_put:
  2106. put_res(dev, slave, cqn, RES_CQ);
  2107. return err;
  2108. }
  2109. static int handle_resize(struct mlx4_dev *dev, int slave,
  2110. struct mlx4_vhcr *vhcr,
  2111. struct mlx4_cmd_mailbox *inbox,
  2112. struct mlx4_cmd_mailbox *outbox,
  2113. struct mlx4_cmd_info *cmd,
  2114. struct res_cq *cq)
  2115. {
  2116. int err;
  2117. struct res_mtt *orig_mtt;
  2118. struct res_mtt *mtt;
  2119. struct mlx4_cq_context *cqc = inbox->buf;
  2120. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2121. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2122. if (err)
  2123. return err;
  2124. if (orig_mtt != cq->mtt) {
  2125. err = -EINVAL;
  2126. goto ex_put;
  2127. }
  2128. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2129. if (err)
  2130. goto ex_put;
  2131. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2132. if (err)
  2133. goto ex_put1;
  2134. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2135. if (err)
  2136. goto ex_put1;
  2137. atomic_dec(&orig_mtt->ref_count);
  2138. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2139. atomic_inc(&mtt->ref_count);
  2140. cq->mtt = mtt;
  2141. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2142. return 0;
  2143. ex_put1:
  2144. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2145. ex_put:
  2146. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2147. return err;
  2148. }
  2149. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2150. struct mlx4_vhcr *vhcr,
  2151. struct mlx4_cmd_mailbox *inbox,
  2152. struct mlx4_cmd_mailbox *outbox,
  2153. struct mlx4_cmd_info *cmd)
  2154. {
  2155. int cqn = vhcr->in_modifier;
  2156. struct res_cq *cq;
  2157. int err;
  2158. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2159. if (err)
  2160. return err;
  2161. if (cq->com.from_state != RES_CQ_HW)
  2162. goto ex_put;
  2163. if (vhcr->op_modifier == 0) {
  2164. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2165. goto ex_put;
  2166. }
  2167. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2168. ex_put:
  2169. put_res(dev, slave, cqn, RES_CQ);
  2170. return err;
  2171. }
  2172. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2173. {
  2174. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2175. int log_rq_stride = srqc->logstride & 7;
  2176. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2177. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2178. return 1;
  2179. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2180. }
  2181. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2182. struct mlx4_vhcr *vhcr,
  2183. struct mlx4_cmd_mailbox *inbox,
  2184. struct mlx4_cmd_mailbox *outbox,
  2185. struct mlx4_cmd_info *cmd)
  2186. {
  2187. int err;
  2188. int srqn = vhcr->in_modifier;
  2189. struct res_mtt *mtt;
  2190. struct res_srq *srq;
  2191. struct mlx4_srq_context *srqc = inbox->buf;
  2192. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2193. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2194. return -EINVAL;
  2195. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2196. if (err)
  2197. return err;
  2198. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2199. if (err)
  2200. goto ex_abort;
  2201. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2202. mtt);
  2203. if (err)
  2204. goto ex_put_mtt;
  2205. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2206. if (err)
  2207. goto ex_put_mtt;
  2208. atomic_inc(&mtt->ref_count);
  2209. srq->mtt = mtt;
  2210. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2211. res_end_move(dev, slave, RES_SRQ, srqn);
  2212. return 0;
  2213. ex_put_mtt:
  2214. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2215. ex_abort:
  2216. res_abort_move(dev, slave, RES_SRQ, srqn);
  2217. return err;
  2218. }
  2219. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2220. struct mlx4_vhcr *vhcr,
  2221. struct mlx4_cmd_mailbox *inbox,
  2222. struct mlx4_cmd_mailbox *outbox,
  2223. struct mlx4_cmd_info *cmd)
  2224. {
  2225. int err;
  2226. int srqn = vhcr->in_modifier;
  2227. struct res_srq *srq;
  2228. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2229. if (err)
  2230. return err;
  2231. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2232. if (err)
  2233. goto ex_abort;
  2234. atomic_dec(&srq->mtt->ref_count);
  2235. if (srq->cq)
  2236. atomic_dec(&srq->cq->ref_count);
  2237. res_end_move(dev, slave, RES_SRQ, srqn);
  2238. return 0;
  2239. ex_abort:
  2240. res_abort_move(dev, slave, RES_SRQ, srqn);
  2241. return err;
  2242. }
  2243. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2244. struct mlx4_vhcr *vhcr,
  2245. struct mlx4_cmd_mailbox *inbox,
  2246. struct mlx4_cmd_mailbox *outbox,
  2247. struct mlx4_cmd_info *cmd)
  2248. {
  2249. int err;
  2250. int srqn = vhcr->in_modifier;
  2251. struct res_srq *srq;
  2252. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2253. if (err)
  2254. return err;
  2255. if (srq->com.from_state != RES_SRQ_HW) {
  2256. err = -EBUSY;
  2257. goto out;
  2258. }
  2259. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2260. out:
  2261. put_res(dev, slave, srqn, RES_SRQ);
  2262. return err;
  2263. }
  2264. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2265. struct mlx4_vhcr *vhcr,
  2266. struct mlx4_cmd_mailbox *inbox,
  2267. struct mlx4_cmd_mailbox *outbox,
  2268. struct mlx4_cmd_info *cmd)
  2269. {
  2270. int err;
  2271. int srqn = vhcr->in_modifier;
  2272. struct res_srq *srq;
  2273. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2274. if (err)
  2275. return err;
  2276. if (srq->com.from_state != RES_SRQ_HW) {
  2277. err = -EBUSY;
  2278. goto out;
  2279. }
  2280. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2281. out:
  2282. put_res(dev, slave, srqn, RES_SRQ);
  2283. return err;
  2284. }
  2285. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2286. struct mlx4_vhcr *vhcr,
  2287. struct mlx4_cmd_mailbox *inbox,
  2288. struct mlx4_cmd_mailbox *outbox,
  2289. struct mlx4_cmd_info *cmd)
  2290. {
  2291. int err;
  2292. int qpn = vhcr->in_modifier & 0x7fffff;
  2293. struct res_qp *qp;
  2294. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2295. if (err)
  2296. return err;
  2297. if (qp->com.from_state != RES_QP_HW) {
  2298. err = -EBUSY;
  2299. goto out;
  2300. }
  2301. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2302. out:
  2303. put_res(dev, slave, qpn, RES_QP);
  2304. return err;
  2305. }
  2306. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2307. struct mlx4_vhcr *vhcr,
  2308. struct mlx4_cmd_mailbox *inbox,
  2309. struct mlx4_cmd_mailbox *outbox,
  2310. struct mlx4_cmd_info *cmd)
  2311. {
  2312. struct mlx4_qp_context *context = inbox->buf + 8;
  2313. adjust_proxy_tun_qkey(dev, vhcr, context);
  2314. update_pkey_index(dev, slave, inbox);
  2315. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2316. }
  2317. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2318. struct mlx4_vhcr *vhcr,
  2319. struct mlx4_cmd_mailbox *inbox,
  2320. struct mlx4_cmd_mailbox *outbox,
  2321. struct mlx4_cmd_info *cmd)
  2322. {
  2323. int err;
  2324. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2325. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2326. if (err)
  2327. return err;
  2328. update_pkey_index(dev, slave, inbox);
  2329. update_gid(dev, inbox, (u8)slave);
  2330. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2331. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2332. }
  2333. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2334. struct mlx4_vhcr *vhcr,
  2335. struct mlx4_cmd_mailbox *inbox,
  2336. struct mlx4_cmd_mailbox *outbox,
  2337. struct mlx4_cmd_info *cmd)
  2338. {
  2339. int err;
  2340. struct mlx4_qp_context *context = inbox->buf + 8;
  2341. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2342. if (err)
  2343. return err;
  2344. update_pkey_index(dev, slave, inbox);
  2345. update_gid(dev, inbox, (u8)slave);
  2346. adjust_proxy_tun_qkey(dev, vhcr, context);
  2347. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2348. }
  2349. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2350. struct mlx4_vhcr *vhcr,
  2351. struct mlx4_cmd_mailbox *inbox,
  2352. struct mlx4_cmd_mailbox *outbox,
  2353. struct mlx4_cmd_info *cmd)
  2354. {
  2355. int err;
  2356. struct mlx4_qp_context *context = inbox->buf + 8;
  2357. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2358. if (err)
  2359. return err;
  2360. update_pkey_index(dev, slave, inbox);
  2361. update_gid(dev, inbox, (u8)slave);
  2362. adjust_proxy_tun_qkey(dev, vhcr, context);
  2363. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2364. }
  2365. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2366. struct mlx4_vhcr *vhcr,
  2367. struct mlx4_cmd_mailbox *inbox,
  2368. struct mlx4_cmd_mailbox *outbox,
  2369. struct mlx4_cmd_info *cmd)
  2370. {
  2371. struct mlx4_qp_context *context = inbox->buf + 8;
  2372. adjust_proxy_tun_qkey(dev, vhcr, context);
  2373. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2374. }
  2375. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2376. struct mlx4_vhcr *vhcr,
  2377. struct mlx4_cmd_mailbox *inbox,
  2378. struct mlx4_cmd_mailbox *outbox,
  2379. struct mlx4_cmd_info *cmd)
  2380. {
  2381. int err;
  2382. struct mlx4_qp_context *context = inbox->buf + 8;
  2383. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2384. if (err)
  2385. return err;
  2386. adjust_proxy_tun_qkey(dev, vhcr, context);
  2387. update_gid(dev, inbox, (u8)slave);
  2388. update_pkey_index(dev, slave, inbox);
  2389. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2390. }
  2391. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2392. struct mlx4_vhcr *vhcr,
  2393. struct mlx4_cmd_mailbox *inbox,
  2394. struct mlx4_cmd_mailbox *outbox,
  2395. struct mlx4_cmd_info *cmd)
  2396. {
  2397. int err;
  2398. struct mlx4_qp_context *context = inbox->buf + 8;
  2399. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2400. if (err)
  2401. return err;
  2402. adjust_proxy_tun_qkey(dev, vhcr, context);
  2403. update_gid(dev, inbox, (u8)slave);
  2404. update_pkey_index(dev, slave, inbox);
  2405. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2406. }
  2407. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2408. struct mlx4_vhcr *vhcr,
  2409. struct mlx4_cmd_mailbox *inbox,
  2410. struct mlx4_cmd_mailbox *outbox,
  2411. struct mlx4_cmd_info *cmd)
  2412. {
  2413. int err;
  2414. int qpn = vhcr->in_modifier & 0x7fffff;
  2415. struct res_qp *qp;
  2416. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2417. if (err)
  2418. return err;
  2419. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2420. if (err)
  2421. goto ex_abort;
  2422. atomic_dec(&qp->mtt->ref_count);
  2423. atomic_dec(&qp->rcq->ref_count);
  2424. atomic_dec(&qp->scq->ref_count);
  2425. if (qp->srq)
  2426. atomic_dec(&qp->srq->ref_count);
  2427. res_end_move(dev, slave, RES_QP, qpn);
  2428. return 0;
  2429. ex_abort:
  2430. res_abort_move(dev, slave, RES_QP, qpn);
  2431. return err;
  2432. }
  2433. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2434. struct res_qp *rqp, u8 *gid)
  2435. {
  2436. struct res_gid *res;
  2437. list_for_each_entry(res, &rqp->mcg_list, list) {
  2438. if (!memcmp(res->gid, gid, 16))
  2439. return res;
  2440. }
  2441. return NULL;
  2442. }
  2443. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2444. u8 *gid, enum mlx4_protocol prot,
  2445. enum mlx4_steer_type steer)
  2446. {
  2447. struct res_gid *res;
  2448. int err;
  2449. res = kzalloc(sizeof *res, GFP_KERNEL);
  2450. if (!res)
  2451. return -ENOMEM;
  2452. spin_lock_irq(&rqp->mcg_spl);
  2453. if (find_gid(dev, slave, rqp, gid)) {
  2454. kfree(res);
  2455. err = -EEXIST;
  2456. } else {
  2457. memcpy(res->gid, gid, 16);
  2458. res->prot = prot;
  2459. res->steer = steer;
  2460. list_add_tail(&res->list, &rqp->mcg_list);
  2461. err = 0;
  2462. }
  2463. spin_unlock_irq(&rqp->mcg_spl);
  2464. return err;
  2465. }
  2466. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2467. u8 *gid, enum mlx4_protocol prot,
  2468. enum mlx4_steer_type steer)
  2469. {
  2470. struct res_gid *res;
  2471. int err;
  2472. spin_lock_irq(&rqp->mcg_spl);
  2473. res = find_gid(dev, slave, rqp, gid);
  2474. if (!res || res->prot != prot || res->steer != steer)
  2475. err = -EINVAL;
  2476. else {
  2477. list_del(&res->list);
  2478. kfree(res);
  2479. err = 0;
  2480. }
  2481. spin_unlock_irq(&rqp->mcg_spl);
  2482. return err;
  2483. }
  2484. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2485. struct mlx4_vhcr *vhcr,
  2486. struct mlx4_cmd_mailbox *inbox,
  2487. struct mlx4_cmd_mailbox *outbox,
  2488. struct mlx4_cmd_info *cmd)
  2489. {
  2490. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2491. u8 *gid = inbox->buf;
  2492. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2493. int err;
  2494. int qpn;
  2495. struct res_qp *rqp;
  2496. int attach = vhcr->op_modifier;
  2497. int block_loopback = vhcr->in_modifier >> 31;
  2498. u8 steer_type_mask = 2;
  2499. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2500. if (dev->caps.steering_mode != MLX4_STEERING_MODE_B0)
  2501. return -EINVAL;
  2502. qpn = vhcr->in_modifier & 0xffffff;
  2503. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2504. if (err)
  2505. return err;
  2506. qp.qpn = qpn;
  2507. if (attach) {
  2508. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2509. if (err)
  2510. goto ex_put;
  2511. err = mlx4_qp_attach_common(dev, &qp, gid,
  2512. block_loopback, prot, type);
  2513. if (err)
  2514. goto ex_rem;
  2515. } else {
  2516. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2517. if (err)
  2518. goto ex_put;
  2519. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2520. }
  2521. put_res(dev, slave, qpn, RES_QP);
  2522. return 0;
  2523. ex_rem:
  2524. /* ignore error return below, already in error */
  2525. (void) rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2526. ex_put:
  2527. put_res(dev, slave, qpn, RES_QP);
  2528. return err;
  2529. }
  2530. /*
  2531. * MAC validation for Flow Steering rules.
  2532. * VF can attach rules only with a mac address which is assigned to it.
  2533. */
  2534. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  2535. struct list_head *rlist)
  2536. {
  2537. struct mac_res *res, *tmp;
  2538. __be64 be_mac;
  2539. /* make sure it isn't multicast or broadcast mac*/
  2540. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  2541. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  2542. list_for_each_entry_safe(res, tmp, rlist, list) {
  2543. be_mac = cpu_to_be64(res->mac << 16);
  2544. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  2545. return 0;
  2546. }
  2547. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  2548. eth_header->eth.dst_mac, slave);
  2549. return -EINVAL;
  2550. }
  2551. return 0;
  2552. }
  2553. /*
  2554. * In case of missing eth header, append eth header with a MAC address
  2555. * assigned to the VF.
  2556. */
  2557. static int add_eth_header(struct mlx4_dev *dev, int slave,
  2558. struct mlx4_cmd_mailbox *inbox,
  2559. struct list_head *rlist, int header_id)
  2560. {
  2561. struct mac_res *res, *tmp;
  2562. u8 port;
  2563. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2564. struct mlx4_net_trans_rule_hw_eth *eth_header;
  2565. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  2566. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  2567. __be64 be_mac = 0;
  2568. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  2569. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2570. port = ctrl->port;
  2571. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  2572. /* Clear a space in the inbox for eth header */
  2573. switch (header_id) {
  2574. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2575. ip_header =
  2576. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  2577. memmove(ip_header, eth_header,
  2578. sizeof(*ip_header) + sizeof(*l4_header));
  2579. break;
  2580. case MLX4_NET_TRANS_RULE_ID_TCP:
  2581. case MLX4_NET_TRANS_RULE_ID_UDP:
  2582. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  2583. (eth_header + 1);
  2584. memmove(l4_header, eth_header, sizeof(*l4_header));
  2585. break;
  2586. default:
  2587. return -EINVAL;
  2588. }
  2589. list_for_each_entry_safe(res, tmp, rlist, list) {
  2590. if (port == res->port) {
  2591. be_mac = cpu_to_be64(res->mac << 16);
  2592. break;
  2593. }
  2594. }
  2595. if (!be_mac) {
  2596. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  2597. port);
  2598. return -EINVAL;
  2599. }
  2600. memset(eth_header, 0, sizeof(*eth_header));
  2601. eth_header->size = sizeof(*eth_header) >> 2;
  2602. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  2603. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  2604. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  2605. return 0;
  2606. }
  2607. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2608. struct mlx4_vhcr *vhcr,
  2609. struct mlx4_cmd_mailbox *inbox,
  2610. struct mlx4_cmd_mailbox *outbox,
  2611. struct mlx4_cmd_info *cmd)
  2612. {
  2613. struct mlx4_priv *priv = mlx4_priv(dev);
  2614. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2615. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  2616. int err;
  2617. int qpn;
  2618. struct res_qp *rqp;
  2619. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2620. struct _rule_hw *rule_header;
  2621. int header_id;
  2622. if (dev->caps.steering_mode !=
  2623. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2624. return -EOPNOTSUPP;
  2625. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2626. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  2627. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2628. if (err) {
  2629. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  2630. return err;
  2631. }
  2632. rule_header = (struct _rule_hw *)(ctrl + 1);
  2633. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  2634. switch (header_id) {
  2635. case MLX4_NET_TRANS_RULE_ID_ETH:
  2636. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  2637. err = -EINVAL;
  2638. goto err_put;
  2639. }
  2640. break;
  2641. case MLX4_NET_TRANS_RULE_ID_IB:
  2642. break;
  2643. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2644. case MLX4_NET_TRANS_RULE_ID_TCP:
  2645. case MLX4_NET_TRANS_RULE_ID_UDP:
  2646. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  2647. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  2648. err = -EINVAL;
  2649. goto err_put;
  2650. }
  2651. vhcr->in_modifier +=
  2652. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  2653. break;
  2654. default:
  2655. pr_err("Corrupted mailbox.\n");
  2656. err = -EINVAL;
  2657. goto err_put;
  2658. }
  2659. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2660. vhcr->in_modifier, 0,
  2661. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2662. MLX4_CMD_NATIVE);
  2663. if (err)
  2664. goto err_put;
  2665. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  2666. if (err) {
  2667. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  2668. /* detach rule*/
  2669. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  2670. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2671. MLX4_CMD_NATIVE);
  2672. goto err_put;
  2673. }
  2674. atomic_inc(&rqp->ref_count);
  2675. err_put:
  2676. put_res(dev, slave, qpn, RES_QP);
  2677. return err;
  2678. }
  2679. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2680. struct mlx4_vhcr *vhcr,
  2681. struct mlx4_cmd_mailbox *inbox,
  2682. struct mlx4_cmd_mailbox *outbox,
  2683. struct mlx4_cmd_info *cmd)
  2684. {
  2685. int err;
  2686. struct res_qp *rqp;
  2687. struct res_fs_rule *rrule;
  2688. if (dev->caps.steering_mode !=
  2689. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2690. return -EOPNOTSUPP;
  2691. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  2692. if (err)
  2693. return err;
  2694. /* Release the rule form busy state before removal */
  2695. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  2696. err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
  2697. if (err)
  2698. return err;
  2699. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  2700. if (err) {
  2701. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  2702. goto out;
  2703. }
  2704. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2705. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2706. MLX4_CMD_NATIVE);
  2707. if (!err)
  2708. atomic_dec(&rqp->ref_count);
  2709. out:
  2710. put_res(dev, slave, rrule->qpn, RES_QP);
  2711. return err;
  2712. }
  2713. enum {
  2714. BUSY_MAX_RETRIES = 10
  2715. };
  2716. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2717. struct mlx4_vhcr *vhcr,
  2718. struct mlx4_cmd_mailbox *inbox,
  2719. struct mlx4_cmd_mailbox *outbox,
  2720. struct mlx4_cmd_info *cmd)
  2721. {
  2722. int err;
  2723. int index = vhcr->in_modifier & 0xffff;
  2724. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2725. if (err)
  2726. return err;
  2727. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2728. put_res(dev, slave, index, RES_COUNTER);
  2729. return err;
  2730. }
  2731. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2732. {
  2733. struct res_gid *rgid;
  2734. struct res_gid *tmp;
  2735. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2736. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2737. qp.qpn = rqp->local_qpn;
  2738. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2739. rgid->steer);
  2740. list_del(&rgid->list);
  2741. kfree(rgid);
  2742. }
  2743. }
  2744. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2745. enum mlx4_resource type, int print)
  2746. {
  2747. struct mlx4_priv *priv = mlx4_priv(dev);
  2748. struct mlx4_resource_tracker *tracker =
  2749. &priv->mfunc.master.res_tracker;
  2750. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2751. struct res_common *r;
  2752. struct res_common *tmp;
  2753. int busy;
  2754. busy = 0;
  2755. spin_lock_irq(mlx4_tlock(dev));
  2756. list_for_each_entry_safe(r, tmp, rlist, list) {
  2757. if (r->owner == slave) {
  2758. if (!r->removing) {
  2759. if (r->state == RES_ANY_BUSY) {
  2760. if (print)
  2761. mlx4_dbg(dev,
  2762. "%s id 0x%llx is busy\n",
  2763. ResourceType(type),
  2764. r->res_id);
  2765. ++busy;
  2766. } else {
  2767. r->from_state = r->state;
  2768. r->state = RES_ANY_BUSY;
  2769. r->removing = 1;
  2770. }
  2771. }
  2772. }
  2773. }
  2774. spin_unlock_irq(mlx4_tlock(dev));
  2775. return busy;
  2776. }
  2777. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2778. enum mlx4_resource type)
  2779. {
  2780. unsigned long begin;
  2781. int busy;
  2782. begin = jiffies;
  2783. do {
  2784. busy = _move_all_busy(dev, slave, type, 0);
  2785. if (time_after(jiffies, begin + 5 * HZ))
  2786. break;
  2787. if (busy)
  2788. cond_resched();
  2789. } while (busy);
  2790. if (busy)
  2791. busy = _move_all_busy(dev, slave, type, 1);
  2792. return busy;
  2793. }
  2794. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2795. {
  2796. struct mlx4_priv *priv = mlx4_priv(dev);
  2797. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2798. struct list_head *qp_list =
  2799. &tracker->slave_list[slave].res_list[RES_QP];
  2800. struct res_qp *qp;
  2801. struct res_qp *tmp;
  2802. int state;
  2803. u64 in_param;
  2804. int qpn;
  2805. int err;
  2806. err = move_all_busy(dev, slave, RES_QP);
  2807. if (err)
  2808. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2809. "for slave %d\n", slave);
  2810. spin_lock_irq(mlx4_tlock(dev));
  2811. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2812. spin_unlock_irq(mlx4_tlock(dev));
  2813. if (qp->com.owner == slave) {
  2814. qpn = qp->com.res_id;
  2815. detach_qp(dev, slave, qp);
  2816. state = qp->com.from_state;
  2817. while (state != 0) {
  2818. switch (state) {
  2819. case RES_QP_RESERVED:
  2820. spin_lock_irq(mlx4_tlock(dev));
  2821. rb_erase(&qp->com.node,
  2822. &tracker->res_tree[RES_QP]);
  2823. list_del(&qp->com.list);
  2824. spin_unlock_irq(mlx4_tlock(dev));
  2825. kfree(qp);
  2826. state = 0;
  2827. break;
  2828. case RES_QP_MAPPED:
  2829. if (!valid_reserved(dev, slave, qpn))
  2830. __mlx4_qp_free_icm(dev, qpn);
  2831. state = RES_QP_RESERVED;
  2832. break;
  2833. case RES_QP_HW:
  2834. in_param = slave;
  2835. err = mlx4_cmd(dev, in_param,
  2836. qp->local_qpn, 2,
  2837. MLX4_CMD_2RST_QP,
  2838. MLX4_CMD_TIME_CLASS_A,
  2839. MLX4_CMD_NATIVE);
  2840. if (err)
  2841. mlx4_dbg(dev, "rem_slave_qps: failed"
  2842. " to move slave %d qpn %d to"
  2843. " reset\n", slave,
  2844. qp->local_qpn);
  2845. atomic_dec(&qp->rcq->ref_count);
  2846. atomic_dec(&qp->scq->ref_count);
  2847. atomic_dec(&qp->mtt->ref_count);
  2848. if (qp->srq)
  2849. atomic_dec(&qp->srq->ref_count);
  2850. state = RES_QP_MAPPED;
  2851. break;
  2852. default:
  2853. state = 0;
  2854. }
  2855. }
  2856. }
  2857. spin_lock_irq(mlx4_tlock(dev));
  2858. }
  2859. spin_unlock_irq(mlx4_tlock(dev));
  2860. }
  2861. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2862. {
  2863. struct mlx4_priv *priv = mlx4_priv(dev);
  2864. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2865. struct list_head *srq_list =
  2866. &tracker->slave_list[slave].res_list[RES_SRQ];
  2867. struct res_srq *srq;
  2868. struct res_srq *tmp;
  2869. int state;
  2870. u64 in_param;
  2871. LIST_HEAD(tlist);
  2872. int srqn;
  2873. int err;
  2874. err = move_all_busy(dev, slave, RES_SRQ);
  2875. if (err)
  2876. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2877. "busy for slave %d\n", slave);
  2878. spin_lock_irq(mlx4_tlock(dev));
  2879. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2880. spin_unlock_irq(mlx4_tlock(dev));
  2881. if (srq->com.owner == slave) {
  2882. srqn = srq->com.res_id;
  2883. state = srq->com.from_state;
  2884. while (state != 0) {
  2885. switch (state) {
  2886. case RES_SRQ_ALLOCATED:
  2887. __mlx4_srq_free_icm(dev, srqn);
  2888. spin_lock_irq(mlx4_tlock(dev));
  2889. rb_erase(&srq->com.node,
  2890. &tracker->res_tree[RES_SRQ]);
  2891. list_del(&srq->com.list);
  2892. spin_unlock_irq(mlx4_tlock(dev));
  2893. kfree(srq);
  2894. state = 0;
  2895. break;
  2896. case RES_SRQ_HW:
  2897. in_param = slave;
  2898. err = mlx4_cmd(dev, in_param, srqn, 1,
  2899. MLX4_CMD_HW2SW_SRQ,
  2900. MLX4_CMD_TIME_CLASS_A,
  2901. MLX4_CMD_NATIVE);
  2902. if (err)
  2903. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2904. " to move slave %d srq %d to"
  2905. " SW ownership\n",
  2906. slave, srqn);
  2907. atomic_dec(&srq->mtt->ref_count);
  2908. if (srq->cq)
  2909. atomic_dec(&srq->cq->ref_count);
  2910. state = RES_SRQ_ALLOCATED;
  2911. break;
  2912. default:
  2913. state = 0;
  2914. }
  2915. }
  2916. }
  2917. spin_lock_irq(mlx4_tlock(dev));
  2918. }
  2919. spin_unlock_irq(mlx4_tlock(dev));
  2920. }
  2921. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2922. {
  2923. struct mlx4_priv *priv = mlx4_priv(dev);
  2924. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2925. struct list_head *cq_list =
  2926. &tracker->slave_list[slave].res_list[RES_CQ];
  2927. struct res_cq *cq;
  2928. struct res_cq *tmp;
  2929. int state;
  2930. u64 in_param;
  2931. LIST_HEAD(tlist);
  2932. int cqn;
  2933. int err;
  2934. err = move_all_busy(dev, slave, RES_CQ);
  2935. if (err)
  2936. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2937. "busy for slave %d\n", slave);
  2938. spin_lock_irq(mlx4_tlock(dev));
  2939. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2940. spin_unlock_irq(mlx4_tlock(dev));
  2941. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2942. cqn = cq->com.res_id;
  2943. state = cq->com.from_state;
  2944. while (state != 0) {
  2945. switch (state) {
  2946. case RES_CQ_ALLOCATED:
  2947. __mlx4_cq_free_icm(dev, cqn);
  2948. spin_lock_irq(mlx4_tlock(dev));
  2949. rb_erase(&cq->com.node,
  2950. &tracker->res_tree[RES_CQ]);
  2951. list_del(&cq->com.list);
  2952. spin_unlock_irq(mlx4_tlock(dev));
  2953. kfree(cq);
  2954. state = 0;
  2955. break;
  2956. case RES_CQ_HW:
  2957. in_param = slave;
  2958. err = mlx4_cmd(dev, in_param, cqn, 1,
  2959. MLX4_CMD_HW2SW_CQ,
  2960. MLX4_CMD_TIME_CLASS_A,
  2961. MLX4_CMD_NATIVE);
  2962. if (err)
  2963. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2964. " to move slave %d cq %d to"
  2965. " SW ownership\n",
  2966. slave, cqn);
  2967. atomic_dec(&cq->mtt->ref_count);
  2968. state = RES_CQ_ALLOCATED;
  2969. break;
  2970. default:
  2971. state = 0;
  2972. }
  2973. }
  2974. }
  2975. spin_lock_irq(mlx4_tlock(dev));
  2976. }
  2977. spin_unlock_irq(mlx4_tlock(dev));
  2978. }
  2979. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2980. {
  2981. struct mlx4_priv *priv = mlx4_priv(dev);
  2982. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2983. struct list_head *mpt_list =
  2984. &tracker->slave_list[slave].res_list[RES_MPT];
  2985. struct res_mpt *mpt;
  2986. struct res_mpt *tmp;
  2987. int state;
  2988. u64 in_param;
  2989. LIST_HEAD(tlist);
  2990. int mptn;
  2991. int err;
  2992. err = move_all_busy(dev, slave, RES_MPT);
  2993. if (err)
  2994. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2995. "busy for slave %d\n", slave);
  2996. spin_lock_irq(mlx4_tlock(dev));
  2997. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2998. spin_unlock_irq(mlx4_tlock(dev));
  2999. if (mpt->com.owner == slave) {
  3000. mptn = mpt->com.res_id;
  3001. state = mpt->com.from_state;
  3002. while (state != 0) {
  3003. switch (state) {
  3004. case RES_MPT_RESERVED:
  3005. __mlx4_mpt_release(dev, mpt->key);
  3006. spin_lock_irq(mlx4_tlock(dev));
  3007. rb_erase(&mpt->com.node,
  3008. &tracker->res_tree[RES_MPT]);
  3009. list_del(&mpt->com.list);
  3010. spin_unlock_irq(mlx4_tlock(dev));
  3011. kfree(mpt);
  3012. state = 0;
  3013. break;
  3014. case RES_MPT_MAPPED:
  3015. __mlx4_mpt_free_icm(dev, mpt->key);
  3016. state = RES_MPT_RESERVED;
  3017. break;
  3018. case RES_MPT_HW:
  3019. in_param = slave;
  3020. err = mlx4_cmd(dev, in_param, mptn, 0,
  3021. MLX4_CMD_HW2SW_MPT,
  3022. MLX4_CMD_TIME_CLASS_A,
  3023. MLX4_CMD_NATIVE);
  3024. if (err)
  3025. mlx4_dbg(dev, "rem_slave_mrs: failed"
  3026. " to move slave %d mpt %d to"
  3027. " SW ownership\n",
  3028. slave, mptn);
  3029. if (mpt->mtt)
  3030. atomic_dec(&mpt->mtt->ref_count);
  3031. state = RES_MPT_MAPPED;
  3032. break;
  3033. default:
  3034. state = 0;
  3035. }
  3036. }
  3037. }
  3038. spin_lock_irq(mlx4_tlock(dev));
  3039. }
  3040. spin_unlock_irq(mlx4_tlock(dev));
  3041. }
  3042. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  3043. {
  3044. struct mlx4_priv *priv = mlx4_priv(dev);
  3045. struct mlx4_resource_tracker *tracker =
  3046. &priv->mfunc.master.res_tracker;
  3047. struct list_head *mtt_list =
  3048. &tracker->slave_list[slave].res_list[RES_MTT];
  3049. struct res_mtt *mtt;
  3050. struct res_mtt *tmp;
  3051. int state;
  3052. LIST_HEAD(tlist);
  3053. int base;
  3054. int err;
  3055. err = move_all_busy(dev, slave, RES_MTT);
  3056. if (err)
  3057. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  3058. "busy for slave %d\n", slave);
  3059. spin_lock_irq(mlx4_tlock(dev));
  3060. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  3061. spin_unlock_irq(mlx4_tlock(dev));
  3062. if (mtt->com.owner == slave) {
  3063. base = mtt->com.res_id;
  3064. state = mtt->com.from_state;
  3065. while (state != 0) {
  3066. switch (state) {
  3067. case RES_MTT_ALLOCATED:
  3068. __mlx4_free_mtt_range(dev, base,
  3069. mtt->order);
  3070. spin_lock_irq(mlx4_tlock(dev));
  3071. rb_erase(&mtt->com.node,
  3072. &tracker->res_tree[RES_MTT]);
  3073. list_del(&mtt->com.list);
  3074. spin_unlock_irq(mlx4_tlock(dev));
  3075. kfree(mtt);
  3076. state = 0;
  3077. break;
  3078. default:
  3079. state = 0;
  3080. }
  3081. }
  3082. }
  3083. spin_lock_irq(mlx4_tlock(dev));
  3084. }
  3085. spin_unlock_irq(mlx4_tlock(dev));
  3086. }
  3087. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3088. {
  3089. struct mlx4_priv *priv = mlx4_priv(dev);
  3090. struct mlx4_resource_tracker *tracker =
  3091. &priv->mfunc.master.res_tracker;
  3092. struct list_head *fs_rule_list =
  3093. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3094. struct res_fs_rule *fs_rule;
  3095. struct res_fs_rule *tmp;
  3096. int state;
  3097. u64 base;
  3098. int err;
  3099. err = move_all_busy(dev, slave, RES_FS_RULE);
  3100. if (err)
  3101. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3102. slave);
  3103. spin_lock_irq(mlx4_tlock(dev));
  3104. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3105. spin_unlock_irq(mlx4_tlock(dev));
  3106. if (fs_rule->com.owner == slave) {
  3107. base = fs_rule->com.res_id;
  3108. state = fs_rule->com.from_state;
  3109. while (state != 0) {
  3110. switch (state) {
  3111. case RES_FS_RULE_ALLOCATED:
  3112. /* detach rule */
  3113. err = mlx4_cmd(dev, base, 0, 0,
  3114. MLX4_QP_FLOW_STEERING_DETACH,
  3115. MLX4_CMD_TIME_CLASS_A,
  3116. MLX4_CMD_NATIVE);
  3117. spin_lock_irq(mlx4_tlock(dev));
  3118. rb_erase(&fs_rule->com.node,
  3119. &tracker->res_tree[RES_FS_RULE]);
  3120. list_del(&fs_rule->com.list);
  3121. spin_unlock_irq(mlx4_tlock(dev));
  3122. kfree(fs_rule);
  3123. state = 0;
  3124. break;
  3125. default:
  3126. state = 0;
  3127. }
  3128. }
  3129. }
  3130. spin_lock_irq(mlx4_tlock(dev));
  3131. }
  3132. spin_unlock_irq(mlx4_tlock(dev));
  3133. }
  3134. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3135. {
  3136. struct mlx4_priv *priv = mlx4_priv(dev);
  3137. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3138. struct list_head *eq_list =
  3139. &tracker->slave_list[slave].res_list[RES_EQ];
  3140. struct res_eq *eq;
  3141. struct res_eq *tmp;
  3142. int err;
  3143. int state;
  3144. LIST_HEAD(tlist);
  3145. int eqn;
  3146. struct mlx4_cmd_mailbox *mailbox;
  3147. err = move_all_busy(dev, slave, RES_EQ);
  3148. if (err)
  3149. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3150. "busy for slave %d\n", slave);
  3151. spin_lock_irq(mlx4_tlock(dev));
  3152. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3153. spin_unlock_irq(mlx4_tlock(dev));
  3154. if (eq->com.owner == slave) {
  3155. eqn = eq->com.res_id;
  3156. state = eq->com.from_state;
  3157. while (state != 0) {
  3158. switch (state) {
  3159. case RES_EQ_RESERVED:
  3160. spin_lock_irq(mlx4_tlock(dev));
  3161. rb_erase(&eq->com.node,
  3162. &tracker->res_tree[RES_EQ]);
  3163. list_del(&eq->com.list);
  3164. spin_unlock_irq(mlx4_tlock(dev));
  3165. kfree(eq);
  3166. state = 0;
  3167. break;
  3168. case RES_EQ_HW:
  3169. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3170. if (IS_ERR(mailbox)) {
  3171. cond_resched();
  3172. continue;
  3173. }
  3174. err = mlx4_cmd_box(dev, slave, 0,
  3175. eqn & 0xff, 0,
  3176. MLX4_CMD_HW2SW_EQ,
  3177. MLX4_CMD_TIME_CLASS_A,
  3178. MLX4_CMD_NATIVE);
  3179. if (err)
  3180. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3181. " to move slave %d eqs %d to"
  3182. " SW ownership\n", slave, eqn);
  3183. mlx4_free_cmd_mailbox(dev, mailbox);
  3184. atomic_dec(&eq->mtt->ref_count);
  3185. state = RES_EQ_RESERVED;
  3186. break;
  3187. default:
  3188. state = 0;
  3189. }
  3190. }
  3191. }
  3192. spin_lock_irq(mlx4_tlock(dev));
  3193. }
  3194. spin_unlock_irq(mlx4_tlock(dev));
  3195. }
  3196. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3197. {
  3198. struct mlx4_priv *priv = mlx4_priv(dev);
  3199. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3200. struct list_head *counter_list =
  3201. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3202. struct res_counter *counter;
  3203. struct res_counter *tmp;
  3204. int err;
  3205. int index;
  3206. err = move_all_busy(dev, slave, RES_COUNTER);
  3207. if (err)
  3208. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3209. "busy for slave %d\n", slave);
  3210. spin_lock_irq(mlx4_tlock(dev));
  3211. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3212. if (counter->com.owner == slave) {
  3213. index = counter->com.res_id;
  3214. rb_erase(&counter->com.node,
  3215. &tracker->res_tree[RES_COUNTER]);
  3216. list_del(&counter->com.list);
  3217. kfree(counter);
  3218. __mlx4_counter_free(dev, index);
  3219. }
  3220. }
  3221. spin_unlock_irq(mlx4_tlock(dev));
  3222. }
  3223. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3224. {
  3225. struct mlx4_priv *priv = mlx4_priv(dev);
  3226. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3227. struct list_head *xrcdn_list =
  3228. &tracker->slave_list[slave].res_list[RES_XRCD];
  3229. struct res_xrcdn *xrcd;
  3230. struct res_xrcdn *tmp;
  3231. int err;
  3232. int xrcdn;
  3233. err = move_all_busy(dev, slave, RES_XRCD);
  3234. if (err)
  3235. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3236. "busy for slave %d\n", slave);
  3237. spin_lock_irq(mlx4_tlock(dev));
  3238. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3239. if (xrcd->com.owner == slave) {
  3240. xrcdn = xrcd->com.res_id;
  3241. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3242. list_del(&xrcd->com.list);
  3243. kfree(xrcd);
  3244. __mlx4_xrcd_free(dev, xrcdn);
  3245. }
  3246. }
  3247. spin_unlock_irq(mlx4_tlock(dev));
  3248. }
  3249. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3250. {
  3251. struct mlx4_priv *priv = mlx4_priv(dev);
  3252. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3253. /*VLAN*/
  3254. rem_slave_macs(dev, slave);
  3255. rem_slave_fs_rule(dev, slave);
  3256. rem_slave_qps(dev, slave);
  3257. rem_slave_srqs(dev, slave);
  3258. rem_slave_cqs(dev, slave);
  3259. rem_slave_mrs(dev, slave);
  3260. rem_slave_eqs(dev, slave);
  3261. rem_slave_mtts(dev, slave);
  3262. rem_slave_counters(dev, slave);
  3263. rem_slave_xrcdns(dev, slave);
  3264. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3265. }