atl1c_main.c 77 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.1-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. /*
  26. * atl1c_pci_tbl - PCI Device ID Table
  27. *
  28. * Wildcard entries (PCI_ANY_ID) should come last
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
  35. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  39. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  40. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  41. /* required last entry */
  42. { 0 }
  43. };
  44. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  45. MODULE_AUTHOR("Jie Yang");
  46. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  47. MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
  48. MODULE_LICENSE("GPL");
  49. MODULE_VERSION(ATL1C_DRV_VERSION);
  50. static int atl1c_stop_mac(struct atl1c_hw *hw);
  51. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  52. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  53. static void atl1c_start_mac(struct atl1c_adapter *adapter);
  54. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  55. int *work_done, int work_to_do);
  56. static int atl1c_up(struct atl1c_adapter *adapter);
  57. static void atl1c_down(struct atl1c_adapter *adapter);
  58. static int atl1c_reset_mac(struct atl1c_hw *hw);
  59. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  60. static int atl1c_configure(struct atl1c_adapter *adapter);
  61. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  62. static const u16 atl1c_pay_load_size[] = {
  63. 128, 256, 512, 1024, 2048, 4096,
  64. };
  65. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  66. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  67. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  68. {
  69. u32 mst_data, data;
  70. /* pclk sel could switch to 25M */
  71. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  72. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  73. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  74. /* WoL/PCIE related settings */
  75. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  76. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  77. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  78. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  79. } else { /* new dev set bit5 of MASTER */
  80. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  81. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  82. mst_data | MASTER_CTRL_WAKEN_25M);
  83. }
  84. /* aspm/PCIE setting only for l2cb 1.0 */
  85. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  86. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  87. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  88. L2CB1_PCIE_PHYMISC2_CDR_BW);
  89. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  90. L2CB1_PCIE_PHYMISC2_L0S_TH);
  91. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  92. /* extend L1 sync timer */
  93. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  94. data |= LINK_CTRL_EXT_SYNC;
  95. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  96. }
  97. /* l2cb 1.x & l1d 1.x */
  98. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  99. AT_READ_REG(hw, REG_PM_CTRL, &data);
  100. data |= PM_CTRL_L0S_BUFSRX_EN;
  101. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  102. /* clear vendor msg */
  103. AT_READ_REG(hw, REG_DMA_DBG, &data);
  104. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  105. }
  106. }
  107. /* FIXME: no need any more ? */
  108. /*
  109. * atl1c_init_pcie - init PCIE module
  110. */
  111. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  112. {
  113. u32 data;
  114. u32 pci_cmd;
  115. struct pci_dev *pdev = hw->adapter->pdev;
  116. int pos;
  117. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  118. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  119. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  120. PCI_COMMAND_IO);
  121. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  122. /*
  123. * Clear any PowerSaveing Settings
  124. */
  125. pci_enable_wake(pdev, PCI_D3hot, 0);
  126. pci_enable_wake(pdev, PCI_D3cold, 0);
  127. /* wol sts read-clear */
  128. AT_READ_REG(hw, REG_WOL_CTRL, &data);
  129. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  130. /*
  131. * Mask some pcie error bits
  132. */
  133. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  134. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  135. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  136. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  137. /* clear error status */
  138. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
  139. PCI_EXP_DEVSTA_NFED |
  140. PCI_EXP_DEVSTA_FED |
  141. PCI_EXP_DEVSTA_CED |
  142. PCI_EXP_DEVSTA_URD);
  143. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  144. data &= ~LTSSM_ID_EN_WRO;
  145. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  146. atl1c_pcie_patch(hw);
  147. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  148. atl1c_disable_l0s_l1(hw);
  149. msleep(5);
  150. }
  151. /**
  152. * atl1c_irq_enable - Enable default interrupt generation settings
  153. * @adapter: board private structure
  154. */
  155. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  156. {
  157. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  158. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  159. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  160. AT_WRITE_FLUSH(&adapter->hw);
  161. }
  162. }
  163. /**
  164. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  165. * @adapter: board private structure
  166. */
  167. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  168. {
  169. atomic_inc(&adapter->irq_sem);
  170. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  171. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  172. AT_WRITE_FLUSH(&adapter->hw);
  173. synchronize_irq(adapter->pdev->irq);
  174. }
  175. /**
  176. * atl1c_irq_reset - reset interrupt confiure on the NIC
  177. * @adapter: board private structure
  178. */
  179. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  180. {
  181. atomic_set(&adapter->irq_sem, 1);
  182. atl1c_irq_enable(adapter);
  183. }
  184. /*
  185. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  186. * of the idle status register until the device is actually idle
  187. */
  188. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  189. {
  190. int timeout;
  191. u32 data;
  192. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  193. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  194. if ((data & modu_ctrl) == 0)
  195. return 0;
  196. msleep(1);
  197. }
  198. return data;
  199. }
  200. /**
  201. * atl1c_phy_config - Timer Call-back
  202. * @data: pointer to netdev cast into an unsigned long
  203. */
  204. static void atl1c_phy_config(unsigned long data)
  205. {
  206. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  207. struct atl1c_hw *hw = &adapter->hw;
  208. unsigned long flags;
  209. spin_lock_irqsave(&adapter->mdio_lock, flags);
  210. atl1c_restart_autoneg(hw);
  211. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  212. }
  213. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  214. {
  215. WARN_ON(in_interrupt());
  216. atl1c_down(adapter);
  217. atl1c_up(adapter);
  218. clear_bit(__AT_RESETTING, &adapter->flags);
  219. }
  220. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  221. {
  222. struct atl1c_hw *hw = &adapter->hw;
  223. struct net_device *netdev = adapter->netdev;
  224. struct pci_dev *pdev = adapter->pdev;
  225. int err;
  226. unsigned long flags;
  227. u16 speed, duplex, phy_data;
  228. spin_lock_irqsave(&adapter->mdio_lock, flags);
  229. /* MII_BMSR must read twise */
  230. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  231. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  232. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  233. if ((phy_data & BMSR_LSTATUS) == 0) {
  234. /* link down */
  235. netif_carrier_off(netdev);
  236. hw->hibernate = true;
  237. if (atl1c_reset_mac(hw) != 0)
  238. if (netif_msg_hw(adapter))
  239. dev_warn(&pdev->dev, "reset mac failed\n");
  240. atl1c_set_aspm(hw, SPEED_0);
  241. atl1c_post_phy_linkchg(hw, SPEED_0);
  242. atl1c_reset_dma_ring(adapter);
  243. atl1c_configure(adapter);
  244. } else {
  245. /* Link Up */
  246. hw->hibernate = false;
  247. spin_lock_irqsave(&adapter->mdio_lock, flags);
  248. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  249. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  250. if (unlikely(err))
  251. return;
  252. /* link result is our setting */
  253. if (adapter->link_speed != speed ||
  254. adapter->link_duplex != duplex) {
  255. adapter->link_speed = speed;
  256. adapter->link_duplex = duplex;
  257. atl1c_set_aspm(hw, speed);
  258. atl1c_post_phy_linkchg(hw, speed);
  259. atl1c_start_mac(adapter);
  260. if (netif_msg_link(adapter))
  261. dev_info(&pdev->dev,
  262. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  263. atl1c_driver_name, netdev->name,
  264. adapter->link_speed,
  265. adapter->link_duplex == FULL_DUPLEX ?
  266. "Full Duplex" : "Half Duplex");
  267. }
  268. if (!netif_carrier_ok(netdev))
  269. netif_carrier_on(netdev);
  270. }
  271. }
  272. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  273. {
  274. struct net_device *netdev = adapter->netdev;
  275. struct pci_dev *pdev = adapter->pdev;
  276. u16 phy_data;
  277. u16 link_up;
  278. spin_lock(&adapter->mdio_lock);
  279. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  280. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  281. spin_unlock(&adapter->mdio_lock);
  282. link_up = phy_data & BMSR_LSTATUS;
  283. /* notify upper layer link down ASAP */
  284. if (!link_up) {
  285. if (netif_carrier_ok(netdev)) {
  286. /* old link state: Up */
  287. netif_carrier_off(netdev);
  288. if (netif_msg_link(adapter))
  289. dev_info(&pdev->dev,
  290. "%s: %s NIC Link is Down\n",
  291. atl1c_driver_name, netdev->name);
  292. adapter->link_speed = SPEED_0;
  293. }
  294. }
  295. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  296. schedule_work(&adapter->common_task);
  297. }
  298. static void atl1c_common_task(struct work_struct *work)
  299. {
  300. struct atl1c_adapter *adapter;
  301. struct net_device *netdev;
  302. adapter = container_of(work, struct atl1c_adapter, common_task);
  303. netdev = adapter->netdev;
  304. if (test_bit(__AT_DOWN, &adapter->flags))
  305. return;
  306. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  307. netif_device_detach(netdev);
  308. atl1c_down(adapter);
  309. atl1c_up(adapter);
  310. netif_device_attach(netdev);
  311. }
  312. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  313. &adapter->work_event)) {
  314. atl1c_irq_disable(adapter);
  315. atl1c_check_link_status(adapter);
  316. atl1c_irq_enable(adapter);
  317. }
  318. }
  319. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  320. {
  321. del_timer_sync(&adapter->phy_config_timer);
  322. }
  323. /**
  324. * atl1c_tx_timeout - Respond to a Tx Hang
  325. * @netdev: network interface device structure
  326. */
  327. static void atl1c_tx_timeout(struct net_device *netdev)
  328. {
  329. struct atl1c_adapter *adapter = netdev_priv(netdev);
  330. /* Do the reset outside of interrupt context */
  331. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  332. schedule_work(&adapter->common_task);
  333. }
  334. /**
  335. * atl1c_set_multi - Multicast and Promiscuous mode set
  336. * @netdev: network interface device structure
  337. *
  338. * The set_multi entry point is called whenever the multicast address
  339. * list or the network interface flags are updated. This routine is
  340. * responsible for configuring the hardware for proper multicast,
  341. * promiscuous mode, and all-multi behavior.
  342. */
  343. static void atl1c_set_multi(struct net_device *netdev)
  344. {
  345. struct atl1c_adapter *adapter = netdev_priv(netdev);
  346. struct atl1c_hw *hw = &adapter->hw;
  347. struct netdev_hw_addr *ha;
  348. u32 mac_ctrl_data;
  349. u32 hash_value;
  350. /* Check for Promiscuous and All Multicast modes */
  351. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  352. if (netdev->flags & IFF_PROMISC) {
  353. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  354. } else if (netdev->flags & IFF_ALLMULTI) {
  355. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  356. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  357. } else {
  358. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  359. }
  360. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  361. /* clear the old settings from the multicast hash table */
  362. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  363. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  364. /* comoute mc addresses' hash value ,and put it into hash table */
  365. netdev_for_each_mc_addr(ha, netdev) {
  366. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  367. atl1c_hash_set(hw, hash_value);
  368. }
  369. }
  370. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  371. {
  372. if (features & NETIF_F_HW_VLAN_RX) {
  373. /* enable VLAN tag insert/strip */
  374. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  375. } else {
  376. /* disable VLAN tag insert/strip */
  377. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  378. }
  379. }
  380. static void atl1c_vlan_mode(struct net_device *netdev,
  381. netdev_features_t features)
  382. {
  383. struct atl1c_adapter *adapter = netdev_priv(netdev);
  384. struct pci_dev *pdev = adapter->pdev;
  385. u32 mac_ctrl_data = 0;
  386. if (netif_msg_pktdata(adapter))
  387. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  388. atl1c_irq_disable(adapter);
  389. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  390. __atl1c_vlan_mode(features, &mac_ctrl_data);
  391. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  392. atl1c_irq_enable(adapter);
  393. }
  394. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  395. {
  396. struct pci_dev *pdev = adapter->pdev;
  397. if (netif_msg_pktdata(adapter))
  398. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  399. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  400. }
  401. /**
  402. * atl1c_set_mac - Change the Ethernet Address of the NIC
  403. * @netdev: network interface device structure
  404. * @p: pointer to an address structure
  405. *
  406. * Returns 0 on success, negative on failure
  407. */
  408. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  409. {
  410. struct atl1c_adapter *adapter = netdev_priv(netdev);
  411. struct sockaddr *addr = p;
  412. if (!is_valid_ether_addr(addr->sa_data))
  413. return -EADDRNOTAVAIL;
  414. if (netif_running(netdev))
  415. return -EBUSY;
  416. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  417. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  418. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  419. return 0;
  420. }
  421. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  422. struct net_device *dev)
  423. {
  424. int mtu = dev->mtu;
  425. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  426. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  427. }
  428. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  429. netdev_features_t features)
  430. {
  431. /*
  432. * Since there is no support for separate rx/tx vlan accel
  433. * enable/disable make sure tx flag is always in same state as rx.
  434. */
  435. if (features & NETIF_F_HW_VLAN_RX)
  436. features |= NETIF_F_HW_VLAN_TX;
  437. else
  438. features &= ~NETIF_F_HW_VLAN_TX;
  439. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  440. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  441. return features;
  442. }
  443. static int atl1c_set_features(struct net_device *netdev,
  444. netdev_features_t features)
  445. {
  446. netdev_features_t changed = netdev->features ^ features;
  447. if (changed & NETIF_F_HW_VLAN_RX)
  448. atl1c_vlan_mode(netdev, features);
  449. return 0;
  450. }
  451. /**
  452. * atl1c_change_mtu - Change the Maximum Transfer Unit
  453. * @netdev: network interface device structure
  454. * @new_mtu: new value for maximum frame size
  455. *
  456. * Returns 0 on success, negative on failure
  457. */
  458. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  459. {
  460. struct atl1c_adapter *adapter = netdev_priv(netdev);
  461. struct atl1c_hw *hw = &adapter->hw;
  462. int old_mtu = netdev->mtu;
  463. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  464. /* Fast Ethernet controller doesn't support jumbo packet */
  465. if (((hw->nic_type == athr_l2c ||
  466. hw->nic_type == athr_l2c_b ||
  467. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  468. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  469. max_frame > MAX_JUMBO_FRAME_SIZE) {
  470. if (netif_msg_link(adapter))
  471. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  472. return -EINVAL;
  473. }
  474. /* set MTU */
  475. if (old_mtu != new_mtu && netif_running(netdev)) {
  476. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  477. msleep(1);
  478. netdev->mtu = new_mtu;
  479. adapter->hw.max_frame_size = new_mtu;
  480. atl1c_set_rxbufsize(adapter, netdev);
  481. atl1c_down(adapter);
  482. netdev_update_features(netdev);
  483. atl1c_up(adapter);
  484. clear_bit(__AT_RESETTING, &adapter->flags);
  485. }
  486. return 0;
  487. }
  488. /*
  489. * caller should hold mdio_lock
  490. */
  491. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  492. {
  493. struct atl1c_adapter *adapter = netdev_priv(netdev);
  494. u16 result;
  495. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  496. return result;
  497. }
  498. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  499. int reg_num, int val)
  500. {
  501. struct atl1c_adapter *adapter = netdev_priv(netdev);
  502. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  503. }
  504. static int atl1c_mii_ioctl(struct net_device *netdev,
  505. struct ifreq *ifr, int cmd)
  506. {
  507. struct atl1c_adapter *adapter = netdev_priv(netdev);
  508. struct pci_dev *pdev = adapter->pdev;
  509. struct mii_ioctl_data *data = if_mii(ifr);
  510. unsigned long flags;
  511. int retval = 0;
  512. if (!netif_running(netdev))
  513. return -EINVAL;
  514. spin_lock_irqsave(&adapter->mdio_lock, flags);
  515. switch (cmd) {
  516. case SIOCGMIIPHY:
  517. data->phy_id = 0;
  518. break;
  519. case SIOCGMIIREG:
  520. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  521. &data->val_out)) {
  522. retval = -EIO;
  523. goto out;
  524. }
  525. break;
  526. case SIOCSMIIREG:
  527. if (data->reg_num & ~(0x1F)) {
  528. retval = -EFAULT;
  529. goto out;
  530. }
  531. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  532. data->reg_num, data->val_in);
  533. if (atl1c_write_phy_reg(&adapter->hw,
  534. data->reg_num, data->val_in)) {
  535. retval = -EIO;
  536. goto out;
  537. }
  538. break;
  539. default:
  540. retval = -EOPNOTSUPP;
  541. break;
  542. }
  543. out:
  544. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  545. return retval;
  546. }
  547. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  548. {
  549. switch (cmd) {
  550. case SIOCGMIIPHY:
  551. case SIOCGMIIREG:
  552. case SIOCSMIIREG:
  553. return atl1c_mii_ioctl(netdev, ifr, cmd);
  554. default:
  555. return -EOPNOTSUPP;
  556. }
  557. }
  558. /**
  559. * atl1c_alloc_queues - Allocate memory for all rings
  560. * @adapter: board private structure to initialize
  561. *
  562. */
  563. static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
  564. {
  565. return 0;
  566. }
  567. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  568. {
  569. switch (hw->device_id) {
  570. case PCI_DEVICE_ID_ATTANSIC_L2C:
  571. hw->nic_type = athr_l2c;
  572. break;
  573. case PCI_DEVICE_ID_ATTANSIC_L1C:
  574. hw->nic_type = athr_l1c;
  575. break;
  576. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  577. hw->nic_type = athr_l2c_b;
  578. break;
  579. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  580. hw->nic_type = athr_l2c_b2;
  581. break;
  582. case PCI_DEVICE_ID_ATHEROS_L1D:
  583. hw->nic_type = athr_l1d;
  584. break;
  585. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  586. hw->nic_type = athr_l1d_2;
  587. break;
  588. default:
  589. break;
  590. }
  591. }
  592. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  593. {
  594. u32 link_ctrl_data;
  595. atl1c_set_mac_type(hw);
  596. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  597. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  598. ATL1C_TXQ_MODE_ENHANCE;
  599. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  600. ATL1C_ASPM_L1_SUPPORT;
  601. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  602. if (hw->nic_type == athr_l1c ||
  603. hw->nic_type == athr_l1d ||
  604. hw->nic_type == athr_l1d_2)
  605. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  606. return 0;
  607. }
  608. struct atl1c_platform_patch {
  609. u16 pci_did;
  610. u8 pci_revid;
  611. u16 subsystem_vid;
  612. u16 subsystem_did;
  613. u32 patch_flag;
  614. #define ATL1C_LINK_PATCH 0x1
  615. };
  616. static const struct atl1c_platform_patch plats[] = {
  617. {0x2060, 0xC1, 0x1019, 0x8152, 0x1},
  618. {0x2060, 0xC1, 0x1019, 0x2060, 0x1},
  619. {0x2060, 0xC1, 0x1019, 0xE000, 0x1},
  620. {0x2062, 0xC0, 0x1019, 0x8152, 0x1},
  621. {0x2062, 0xC0, 0x1019, 0x2062, 0x1},
  622. {0x2062, 0xC0, 0x1458, 0xE000, 0x1},
  623. {0x2062, 0xC1, 0x1019, 0x8152, 0x1},
  624. {0x2062, 0xC1, 0x1019, 0x2062, 0x1},
  625. {0x2062, 0xC1, 0x1458, 0xE000, 0x1},
  626. {0x2062, 0xC1, 0x1565, 0x2802, 0x1},
  627. {0x2062, 0xC1, 0x1565, 0x2801, 0x1},
  628. {0x1073, 0xC0, 0x1019, 0x8151, 0x1},
  629. {0x1073, 0xC0, 0x1019, 0x1073, 0x1},
  630. {0x1073, 0xC0, 0x1458, 0xE000, 0x1},
  631. {0x1083, 0xC0, 0x1458, 0xE000, 0x1},
  632. {0x1083, 0xC0, 0x1019, 0x8151, 0x1},
  633. {0x1083, 0xC0, 0x1019, 0x1083, 0x1},
  634. {0x1083, 0xC0, 0x1462, 0x7680, 0x1},
  635. {0x1083, 0xC0, 0x1565, 0x2803, 0x1},
  636. {0},
  637. };
  638. static void atl1c_patch_assign(struct atl1c_hw *hw)
  639. {
  640. struct pci_dev *pdev = hw->adapter->pdev;
  641. u32 misc_ctrl;
  642. int i = 0;
  643. hw->msi_lnkpatch = false;
  644. while (plats[i].pci_did != 0) {
  645. if (plats[i].pci_did == hw->device_id &&
  646. plats[i].pci_revid == hw->revision_id &&
  647. plats[i].subsystem_vid == hw->subsystem_vendor_id &&
  648. plats[i].subsystem_did == hw->subsystem_id) {
  649. if (plats[i].patch_flag & ATL1C_LINK_PATCH)
  650. hw->msi_lnkpatch = true;
  651. }
  652. i++;
  653. }
  654. if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
  655. hw->revision_id == L2CB_V21) {
  656. /* config acess mode */
  657. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  658. REG_PCIE_DEV_MISC_CTRL);
  659. pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
  660. misc_ctrl &= ~0x100;
  661. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  662. REG_PCIE_DEV_MISC_CTRL);
  663. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
  664. }
  665. }
  666. /**
  667. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  668. * @adapter: board private structure to initialize
  669. *
  670. * atl1c_sw_init initializes the Adapter private data structure.
  671. * Fields are initialized based on PCI device information and
  672. * OS network device settings (MTU size).
  673. */
  674. static int atl1c_sw_init(struct atl1c_adapter *adapter)
  675. {
  676. struct atl1c_hw *hw = &adapter->hw;
  677. struct pci_dev *pdev = adapter->pdev;
  678. u32 revision;
  679. adapter->wol = 0;
  680. device_set_wakeup_enable(&pdev->dev, false);
  681. adapter->link_speed = SPEED_0;
  682. adapter->link_duplex = FULL_DUPLEX;
  683. adapter->tpd_ring[0].count = 1024;
  684. adapter->rfd_ring.count = 512;
  685. hw->vendor_id = pdev->vendor;
  686. hw->device_id = pdev->device;
  687. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  688. hw->subsystem_id = pdev->subsystem_device;
  689. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
  690. hw->revision_id = revision & 0xFF;
  691. /* before link up, we assume hibernate is true */
  692. hw->hibernate = true;
  693. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  694. if (atl1c_setup_mac_funcs(hw) != 0) {
  695. dev_err(&pdev->dev, "set mac function pointers failed\n");
  696. return -1;
  697. }
  698. atl1c_patch_assign(hw);
  699. hw->intr_mask = IMR_NORMAL_MASK;
  700. hw->phy_configured = false;
  701. hw->preamble_len = 7;
  702. hw->max_frame_size = adapter->netdev->mtu;
  703. hw->autoneg_advertised = ADVERTISED_Autoneg;
  704. hw->indirect_tab = 0xE4E4E4E4;
  705. hw->base_cpu = 0;
  706. hw->ict = 50000; /* 100ms */
  707. hw->smb_timer = 200000; /* 400ms */
  708. hw->rx_imt = 200;
  709. hw->tx_imt = 1000;
  710. hw->tpd_burst = 5;
  711. hw->rfd_burst = 8;
  712. hw->dma_order = atl1c_dma_ord_out;
  713. hw->dmar_block = atl1c_dma_req_1024;
  714. if (atl1c_alloc_queues(adapter)) {
  715. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  716. return -ENOMEM;
  717. }
  718. /* TODO */
  719. atl1c_set_rxbufsize(adapter, adapter->netdev);
  720. atomic_set(&adapter->irq_sem, 1);
  721. spin_lock_init(&adapter->mdio_lock);
  722. spin_lock_init(&adapter->tx_lock);
  723. set_bit(__AT_DOWN, &adapter->flags);
  724. return 0;
  725. }
  726. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  727. struct atl1c_buffer *buffer_info, int in_irq)
  728. {
  729. u16 pci_driection;
  730. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  731. return;
  732. if (buffer_info->dma) {
  733. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  734. pci_driection = PCI_DMA_FROMDEVICE;
  735. else
  736. pci_driection = PCI_DMA_TODEVICE;
  737. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  738. pci_unmap_single(pdev, buffer_info->dma,
  739. buffer_info->length, pci_driection);
  740. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  741. pci_unmap_page(pdev, buffer_info->dma,
  742. buffer_info->length, pci_driection);
  743. }
  744. if (buffer_info->skb) {
  745. if (in_irq)
  746. dev_kfree_skb_irq(buffer_info->skb);
  747. else
  748. dev_kfree_skb(buffer_info->skb);
  749. }
  750. buffer_info->dma = 0;
  751. buffer_info->skb = NULL;
  752. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  753. }
  754. /**
  755. * atl1c_clean_tx_ring - Free Tx-skb
  756. * @adapter: board private structure
  757. */
  758. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  759. enum atl1c_trans_queue type)
  760. {
  761. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  762. struct atl1c_buffer *buffer_info;
  763. struct pci_dev *pdev = adapter->pdev;
  764. u16 index, ring_count;
  765. ring_count = tpd_ring->count;
  766. for (index = 0; index < ring_count; index++) {
  767. buffer_info = &tpd_ring->buffer_info[index];
  768. atl1c_clean_buffer(pdev, buffer_info, 0);
  769. }
  770. /* Zero out Tx-buffers */
  771. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  772. ring_count);
  773. atomic_set(&tpd_ring->next_to_clean, 0);
  774. tpd_ring->next_to_use = 0;
  775. }
  776. /**
  777. * atl1c_clean_rx_ring - Free rx-reservation skbs
  778. * @adapter: board private structure
  779. */
  780. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  781. {
  782. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  783. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  784. struct atl1c_buffer *buffer_info;
  785. struct pci_dev *pdev = adapter->pdev;
  786. int j;
  787. for (j = 0; j < rfd_ring->count; j++) {
  788. buffer_info = &rfd_ring->buffer_info[j];
  789. atl1c_clean_buffer(pdev, buffer_info, 0);
  790. }
  791. /* zero out the descriptor ring */
  792. memset(rfd_ring->desc, 0, rfd_ring->size);
  793. rfd_ring->next_to_clean = 0;
  794. rfd_ring->next_to_use = 0;
  795. rrd_ring->next_to_use = 0;
  796. rrd_ring->next_to_clean = 0;
  797. }
  798. /*
  799. * Read / Write Ptr Initialize:
  800. */
  801. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  802. {
  803. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  804. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  805. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  806. struct atl1c_buffer *buffer_info;
  807. int i, j;
  808. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  809. tpd_ring[i].next_to_use = 0;
  810. atomic_set(&tpd_ring[i].next_to_clean, 0);
  811. buffer_info = tpd_ring[i].buffer_info;
  812. for (j = 0; j < tpd_ring->count; j++)
  813. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  814. ATL1C_BUFFER_FREE);
  815. }
  816. rfd_ring->next_to_use = 0;
  817. rfd_ring->next_to_clean = 0;
  818. rrd_ring->next_to_use = 0;
  819. rrd_ring->next_to_clean = 0;
  820. for (j = 0; j < rfd_ring->count; j++) {
  821. buffer_info = &rfd_ring->buffer_info[j];
  822. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  823. }
  824. }
  825. /**
  826. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  827. * @adapter: board private structure
  828. *
  829. * Free all transmit software resources
  830. */
  831. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  832. {
  833. struct pci_dev *pdev = adapter->pdev;
  834. pci_free_consistent(pdev, adapter->ring_header.size,
  835. adapter->ring_header.desc,
  836. adapter->ring_header.dma);
  837. adapter->ring_header.desc = NULL;
  838. /* Note: just free tdp_ring.buffer_info,
  839. * it contain rfd_ring.buffer_info, do not double free */
  840. if (adapter->tpd_ring[0].buffer_info) {
  841. kfree(adapter->tpd_ring[0].buffer_info);
  842. adapter->tpd_ring[0].buffer_info = NULL;
  843. }
  844. }
  845. /**
  846. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  847. * @adapter: board private structure
  848. *
  849. * Return 0 on success, negative on failure
  850. */
  851. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  852. {
  853. struct pci_dev *pdev = adapter->pdev;
  854. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  855. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  856. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  857. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  858. int size;
  859. int i;
  860. int count = 0;
  861. int rx_desc_count = 0;
  862. u32 offset = 0;
  863. rrd_ring->count = rfd_ring->count;
  864. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  865. tpd_ring[i].count = tpd_ring[0].count;
  866. /* 2 tpd queue, one high priority queue,
  867. * another normal priority queue */
  868. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  869. rfd_ring->count);
  870. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  871. if (unlikely(!tpd_ring->buffer_info))
  872. goto err_nomem;
  873. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  874. tpd_ring[i].buffer_info =
  875. (tpd_ring->buffer_info + count);
  876. count += tpd_ring[i].count;
  877. }
  878. rfd_ring->buffer_info =
  879. (tpd_ring->buffer_info + count);
  880. count += rfd_ring->count;
  881. rx_desc_count += rfd_ring->count;
  882. /*
  883. * real ring DMA buffer
  884. * each ring/block may need up to 8 bytes for alignment, hence the
  885. * additional bytes tacked onto the end.
  886. */
  887. ring_header->size = size =
  888. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  889. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  890. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  891. 8 * 4;
  892. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  893. &ring_header->dma);
  894. if (unlikely(!ring_header->desc)) {
  895. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  896. goto err_nomem;
  897. }
  898. memset(ring_header->desc, 0, ring_header->size);
  899. /* init TPD ring */
  900. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  901. offset = tpd_ring[0].dma - ring_header->dma;
  902. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  903. tpd_ring[i].dma = ring_header->dma + offset;
  904. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  905. tpd_ring[i].size =
  906. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  907. offset += roundup(tpd_ring[i].size, 8);
  908. }
  909. /* init RFD ring */
  910. rfd_ring->dma = ring_header->dma + offset;
  911. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  912. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  913. offset += roundup(rfd_ring->size, 8);
  914. /* init RRD ring */
  915. rrd_ring->dma = ring_header->dma + offset;
  916. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  917. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  918. rrd_ring->count;
  919. offset += roundup(rrd_ring->size, 8);
  920. return 0;
  921. err_nomem:
  922. kfree(tpd_ring->buffer_info);
  923. return -ENOMEM;
  924. }
  925. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  926. {
  927. struct atl1c_hw *hw = &adapter->hw;
  928. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  929. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  930. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  931. adapter->tpd_ring;
  932. /* TPD */
  933. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  934. (u32)((tpd_ring[atl1c_trans_normal].dma &
  935. AT_DMA_HI_ADDR_MASK) >> 32));
  936. /* just enable normal priority TX queue */
  937. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  938. (u32)(tpd_ring[atl1c_trans_normal].dma &
  939. AT_DMA_LO_ADDR_MASK));
  940. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  941. (u32)(tpd_ring[atl1c_trans_high].dma &
  942. AT_DMA_LO_ADDR_MASK));
  943. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  944. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  945. /* RFD */
  946. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  947. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  948. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  949. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  950. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  951. rfd_ring->count & RFD_RING_SIZE_MASK);
  952. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  953. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  954. /* RRD */
  955. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  956. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  957. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  958. (rrd_ring->count & RRD_RING_SIZE_MASK));
  959. if (hw->nic_type == athr_l2c_b) {
  960. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  961. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  962. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  963. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  964. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  965. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  966. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  967. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  968. }
  969. /* Load all of base address above */
  970. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  971. }
  972. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  973. {
  974. struct atl1c_hw *hw = &adapter->hw;
  975. int max_pay_load;
  976. u16 tx_offload_thresh;
  977. u32 txq_ctrl_data;
  978. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  979. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  980. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  981. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  982. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  983. /*
  984. * if BIOS had changed the dam-read-max-length to an invalid value,
  985. * restore it to default value
  986. */
  987. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  988. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  989. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  990. }
  991. txq_ctrl_data =
  992. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  993. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  994. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  995. }
  996. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  997. {
  998. struct atl1c_hw *hw = &adapter->hw;
  999. u32 rxq_ctrl_data;
  1000. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  1001. RXQ_RFD_BURST_NUM_SHIFT;
  1002. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  1003. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  1004. /* aspm for gigabit */
  1005. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  1006. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  1007. ASPM_THRUPUT_LIMIT_100M);
  1008. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  1009. }
  1010. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  1011. {
  1012. struct atl1c_hw *hw = &adapter->hw;
  1013. u32 dma_ctrl_data;
  1014. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  1015. DMA_CTRL_RREQ_PRI_DATA |
  1016. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  1017. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  1018. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  1019. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  1020. }
  1021. /*
  1022. * Stop the mac, transmit and receive units
  1023. * hw - Struct containing variables accessed by shared code
  1024. * return : 0 or idle status (if error)
  1025. */
  1026. static int atl1c_stop_mac(struct atl1c_hw *hw)
  1027. {
  1028. u32 data;
  1029. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1030. data &= ~RXQ_CTRL_EN;
  1031. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1032. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1033. data &= ~TXQ_CTRL_EN;
  1034. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1035. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  1036. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  1037. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1038. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1039. return (int)atl1c_wait_until_idle(hw,
  1040. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1041. }
  1042. static void atl1c_start_mac(struct atl1c_adapter *adapter)
  1043. {
  1044. struct atl1c_hw *hw = &adapter->hw;
  1045. u32 mac, txq, rxq;
  1046. hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
  1047. hw->mac_speed = adapter->link_speed == SPEED_1000 ?
  1048. atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
  1049. AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
  1050. AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
  1051. AT_READ_REG(hw, REG_MAC_CTRL, &mac);
  1052. txq |= TXQ_CTRL_EN;
  1053. rxq |= RXQ_CTRL_EN;
  1054. mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
  1055. MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
  1056. MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
  1057. MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
  1058. MAC_CTRL_HASH_ALG_CRC32;
  1059. if (hw->mac_duplex)
  1060. mac |= MAC_CTRL_DUPLX;
  1061. else
  1062. mac &= ~MAC_CTRL_DUPLX;
  1063. mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
  1064. mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
  1065. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
  1066. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
  1067. AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
  1068. }
  1069. /*
  1070. * Reset the transmit and receive units; mask and clear all interrupts.
  1071. * hw - Struct containing variables accessed by shared code
  1072. * return : 0 or idle status (if error)
  1073. */
  1074. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1075. {
  1076. struct atl1c_adapter *adapter = hw->adapter;
  1077. struct pci_dev *pdev = adapter->pdev;
  1078. u32 ctrl_data = 0;
  1079. atl1c_stop_mac(hw);
  1080. /*
  1081. * Issue Soft Reset to the MAC. This will reset the chip's
  1082. * transmit, receive, DMA. It will not effect
  1083. * the current PCI configuration. The global reset bit is self-
  1084. * clearing, and should clear within a microsecond.
  1085. */
  1086. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1087. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1088. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1089. AT_WRITE_FLUSH(hw);
  1090. msleep(10);
  1091. /* Wait at least 10ms for All module to be Idle */
  1092. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1093. dev_err(&pdev->dev,
  1094. "MAC state machine can't be idle since"
  1095. " disabled for 10ms second\n");
  1096. return -1;
  1097. }
  1098. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1099. /* driver control speed/duplex */
  1100. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1101. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1102. /* clk switch setting */
  1103. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1104. switch (hw->nic_type) {
  1105. case athr_l2c_b:
  1106. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1107. SERDES_MAC_CLK_SLOWDOWN);
  1108. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1109. break;
  1110. case athr_l2c_b2:
  1111. case athr_l1d_2:
  1112. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1113. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1114. break;
  1115. default:
  1116. break;
  1117. }
  1118. return 0;
  1119. }
  1120. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1121. {
  1122. u16 ctrl_flags = hw->ctrl_flags;
  1123. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1124. atl1c_set_aspm(hw, SPEED_0);
  1125. hw->ctrl_flags = ctrl_flags;
  1126. }
  1127. /*
  1128. * Set ASPM state.
  1129. * Enable/disable L0s/L1 depend on link state.
  1130. */
  1131. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1132. {
  1133. u32 pm_ctrl_data;
  1134. u32 link_l1_timer;
  1135. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1136. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1137. PM_CTRL_ASPM_L0S_EN |
  1138. PM_CTRL_MAC_ASPM_CHK);
  1139. /* L1 timer */
  1140. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1141. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1142. link_l1_timer =
  1143. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1144. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1145. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1146. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1147. } else {
  1148. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1149. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1150. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1151. link_l1_timer = 1;
  1152. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1153. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1154. }
  1155. /* L0S/L1 enable */
  1156. if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
  1157. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1158. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1159. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1160. /* l2cb & l1d & l2cb2 & l1d2 */
  1161. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1162. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1163. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1164. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1165. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1166. PM_CTRL_SERDES_PD_EX_L1 |
  1167. PM_CTRL_CLK_SWH_L1;
  1168. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1169. PM_CTRL_SERDES_PLL_L1_EN |
  1170. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1171. PM_CTRL_SA_DLY_EN |
  1172. PM_CTRL_HOTRST);
  1173. /* disable l0s if link down or l2cb */
  1174. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1175. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1176. } else { /* l1c */
  1177. pm_ctrl_data =
  1178. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1179. if (link_speed != SPEED_0) {
  1180. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1181. PM_CTRL_SERDES_PLL_L1_EN |
  1182. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1183. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1184. PM_CTRL_CLK_SWH_L1 |
  1185. PM_CTRL_ASPM_L0S_EN |
  1186. PM_CTRL_ASPM_L1_EN);
  1187. } else { /* link down */
  1188. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1189. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1190. PM_CTRL_SERDES_PLL_L1_EN |
  1191. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1192. PM_CTRL_ASPM_L0S_EN);
  1193. }
  1194. }
  1195. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1196. return;
  1197. }
  1198. /**
  1199. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1200. * @adapter: board private structure
  1201. *
  1202. * Configure the Tx /Rx unit of the MAC after a reset.
  1203. */
  1204. static int atl1c_configure_mac(struct atl1c_adapter *adapter)
  1205. {
  1206. struct atl1c_hw *hw = &adapter->hw;
  1207. u32 master_ctrl_data = 0;
  1208. u32 intr_modrt_data;
  1209. u32 data;
  1210. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1211. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1212. MASTER_CTRL_RX_ITIMER_EN |
  1213. MASTER_CTRL_INT_RDCLR);
  1214. /* clear interrupt status */
  1215. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1216. /* Clear any WOL status */
  1217. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1218. /* set Interrupt Clear Timer
  1219. * HW will enable self to assert interrupt event to system after
  1220. * waiting x-time for software to notify it accept interrupt.
  1221. */
  1222. data = CLK_GATING_EN_ALL;
  1223. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1224. if (hw->nic_type == athr_l2c_b)
  1225. data &= ~CLK_GATING_RXMAC_EN;
  1226. } else
  1227. data = 0;
  1228. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1229. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1230. hw->ict & INT_RETRIG_TIMER_MASK);
  1231. atl1c_configure_des_ring(adapter);
  1232. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1233. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1234. IRQ_MODRT_TX_TIMER_SHIFT;
  1235. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1236. IRQ_MODRT_RX_TIMER_SHIFT;
  1237. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1238. master_ctrl_data |=
  1239. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1240. }
  1241. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1242. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1243. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1244. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1245. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1246. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1247. /* set MTU */
  1248. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1249. VLAN_HLEN + ETH_FCS_LEN);
  1250. atl1c_configure_tx(adapter);
  1251. atl1c_configure_rx(adapter);
  1252. atl1c_configure_dma(adapter);
  1253. return 0;
  1254. }
  1255. static int atl1c_configure(struct atl1c_adapter *adapter)
  1256. {
  1257. struct net_device *netdev = adapter->netdev;
  1258. int num;
  1259. atl1c_init_ring_ptrs(adapter);
  1260. atl1c_set_multi(netdev);
  1261. atl1c_restore_vlan(adapter);
  1262. num = atl1c_alloc_rx_buffer(adapter);
  1263. if (unlikely(num == 0))
  1264. return -ENOMEM;
  1265. if (atl1c_configure_mac(adapter))
  1266. return -EIO;
  1267. return 0;
  1268. }
  1269. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1270. {
  1271. u16 hw_reg_addr = 0;
  1272. unsigned long *stats_item = NULL;
  1273. u32 data;
  1274. /* update rx status */
  1275. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1276. stats_item = &adapter->hw_stats.rx_ok;
  1277. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1278. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1279. *stats_item += data;
  1280. stats_item++;
  1281. hw_reg_addr += 4;
  1282. }
  1283. /* update tx status */
  1284. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1285. stats_item = &adapter->hw_stats.tx_ok;
  1286. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1287. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1288. *stats_item += data;
  1289. stats_item++;
  1290. hw_reg_addr += 4;
  1291. }
  1292. }
  1293. /**
  1294. * atl1c_get_stats - Get System Network Statistics
  1295. * @netdev: network interface device structure
  1296. *
  1297. * Returns the address of the device statistics structure.
  1298. * The statistics are actually updated from the timer callback.
  1299. */
  1300. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1301. {
  1302. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1303. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1304. struct net_device_stats *net_stats = &netdev->stats;
  1305. atl1c_update_hw_stats(adapter);
  1306. net_stats->rx_packets = hw_stats->rx_ok;
  1307. net_stats->tx_packets = hw_stats->tx_ok;
  1308. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1309. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1310. net_stats->multicast = hw_stats->rx_mcast;
  1311. net_stats->collisions = hw_stats->tx_1_col +
  1312. hw_stats->tx_2_col * 2 +
  1313. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1314. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1315. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1316. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1317. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1318. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1319. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1320. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1321. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1322. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1323. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1324. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1325. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1326. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1327. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1328. return net_stats;
  1329. }
  1330. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1331. {
  1332. u16 phy_data;
  1333. spin_lock(&adapter->mdio_lock);
  1334. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1335. spin_unlock(&adapter->mdio_lock);
  1336. }
  1337. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1338. enum atl1c_trans_queue type)
  1339. {
  1340. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1341. struct atl1c_buffer *buffer_info;
  1342. struct pci_dev *pdev = adapter->pdev;
  1343. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1344. u16 hw_next_to_clean;
  1345. u16 reg;
  1346. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1347. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1348. while (next_to_clean != hw_next_to_clean) {
  1349. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1350. atl1c_clean_buffer(pdev, buffer_info, 1);
  1351. if (++next_to_clean == tpd_ring->count)
  1352. next_to_clean = 0;
  1353. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1354. }
  1355. if (netif_queue_stopped(adapter->netdev) &&
  1356. netif_carrier_ok(adapter->netdev)) {
  1357. netif_wake_queue(adapter->netdev);
  1358. }
  1359. return true;
  1360. }
  1361. /**
  1362. * atl1c_intr - Interrupt Handler
  1363. * @irq: interrupt number
  1364. * @data: pointer to a network interface device structure
  1365. */
  1366. static irqreturn_t atl1c_intr(int irq, void *data)
  1367. {
  1368. struct net_device *netdev = data;
  1369. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1370. struct pci_dev *pdev = adapter->pdev;
  1371. struct atl1c_hw *hw = &adapter->hw;
  1372. int max_ints = AT_MAX_INT_WORK;
  1373. int handled = IRQ_NONE;
  1374. u32 status;
  1375. u32 reg_data;
  1376. do {
  1377. AT_READ_REG(hw, REG_ISR, &reg_data);
  1378. status = reg_data & hw->intr_mask;
  1379. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1380. if (max_ints != AT_MAX_INT_WORK)
  1381. handled = IRQ_HANDLED;
  1382. break;
  1383. }
  1384. /* link event */
  1385. if (status & ISR_GPHY)
  1386. atl1c_clear_phy_int(adapter);
  1387. /* Ack ISR */
  1388. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1389. if (status & ISR_RX_PKT) {
  1390. if (likely(napi_schedule_prep(&adapter->napi))) {
  1391. hw->intr_mask &= ~ISR_RX_PKT;
  1392. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1393. __napi_schedule(&adapter->napi);
  1394. }
  1395. }
  1396. if (status & ISR_TX_PKT)
  1397. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1398. handled = IRQ_HANDLED;
  1399. /* check if PCIE PHY Link down */
  1400. if (status & ISR_ERROR) {
  1401. if (netif_msg_hw(adapter))
  1402. dev_err(&pdev->dev,
  1403. "atl1c hardware error (status = 0x%x)\n",
  1404. status & ISR_ERROR);
  1405. /* reset MAC */
  1406. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1407. schedule_work(&adapter->common_task);
  1408. return IRQ_HANDLED;
  1409. }
  1410. if (status & ISR_OVER)
  1411. if (netif_msg_intr(adapter))
  1412. dev_warn(&pdev->dev,
  1413. "TX/RX overflow (status = 0x%x)\n",
  1414. status & ISR_OVER);
  1415. /* link event */
  1416. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1417. netdev->stats.tx_carrier_errors++;
  1418. atl1c_link_chg_event(adapter);
  1419. break;
  1420. }
  1421. } while (--max_ints > 0);
  1422. /* re-enable Interrupt*/
  1423. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1424. return handled;
  1425. }
  1426. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1427. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1428. {
  1429. /*
  1430. * The pid field in RRS in not correct sometimes, so we
  1431. * cannot figure out if the packet is fragmented or not,
  1432. * so we tell the KERNEL CHECKSUM_NONE
  1433. */
  1434. skb_checksum_none_assert(skb);
  1435. }
  1436. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1437. {
  1438. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1439. struct pci_dev *pdev = adapter->pdev;
  1440. struct atl1c_buffer *buffer_info, *next_info;
  1441. struct sk_buff *skb;
  1442. void *vir_addr = NULL;
  1443. u16 num_alloc = 0;
  1444. u16 rfd_next_to_use, next_next;
  1445. struct atl1c_rx_free_desc *rfd_desc;
  1446. dma_addr_t mapping;
  1447. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1448. if (++next_next == rfd_ring->count)
  1449. next_next = 0;
  1450. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1451. next_info = &rfd_ring->buffer_info[next_next];
  1452. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1453. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1454. skb = netdev_alloc_skb(adapter->netdev, adapter->rx_buffer_len);
  1455. if (unlikely(!skb)) {
  1456. if (netif_msg_rx_err(adapter))
  1457. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1458. break;
  1459. }
  1460. /*
  1461. * Make buffer alignment 2 beyond a 16 byte boundary
  1462. * this will result in a 16 byte aligned IP header after
  1463. * the 14 byte MAC header is removed
  1464. */
  1465. vir_addr = skb->data;
  1466. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1467. buffer_info->skb = skb;
  1468. buffer_info->length = adapter->rx_buffer_len;
  1469. mapping = pci_map_single(pdev, vir_addr,
  1470. buffer_info->length,
  1471. PCI_DMA_FROMDEVICE);
  1472. if (unlikely(pci_dma_mapping_error(pdev, mapping))) {
  1473. dev_kfree_skb(skb);
  1474. buffer_info->skb = NULL;
  1475. buffer_info->length = 0;
  1476. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  1477. netif_warn(adapter, rx_err, adapter->netdev, "RX pci_map_single failed");
  1478. break;
  1479. }
  1480. buffer_info->dma = mapping;
  1481. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1482. ATL1C_PCIMAP_FROMDEVICE);
  1483. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1484. rfd_next_to_use = next_next;
  1485. if (++next_next == rfd_ring->count)
  1486. next_next = 0;
  1487. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1488. next_info = &rfd_ring->buffer_info[next_next];
  1489. num_alloc++;
  1490. }
  1491. if (num_alloc) {
  1492. /* TODO: update mailbox here */
  1493. wmb();
  1494. rfd_ring->next_to_use = rfd_next_to_use;
  1495. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1496. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1497. }
  1498. return num_alloc;
  1499. }
  1500. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1501. struct atl1c_recv_ret_status *rrs, u16 num)
  1502. {
  1503. u16 i;
  1504. /* the relationship between rrd and rfd is one map one */
  1505. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1506. rrd_ring->next_to_clean)) {
  1507. rrs->word3 &= ~RRS_RXD_UPDATED;
  1508. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1509. rrd_ring->next_to_clean = 0;
  1510. }
  1511. }
  1512. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1513. struct atl1c_recv_ret_status *rrs, u16 num)
  1514. {
  1515. u16 i;
  1516. u16 rfd_index;
  1517. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1518. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1519. RRS_RX_RFD_INDEX_MASK;
  1520. for (i = 0; i < num; i++) {
  1521. buffer_info[rfd_index].skb = NULL;
  1522. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1523. ATL1C_BUFFER_FREE);
  1524. if (++rfd_index == rfd_ring->count)
  1525. rfd_index = 0;
  1526. }
  1527. rfd_ring->next_to_clean = rfd_index;
  1528. }
  1529. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1530. int *work_done, int work_to_do)
  1531. {
  1532. u16 rfd_num, rfd_index;
  1533. u16 count = 0;
  1534. u16 length;
  1535. struct pci_dev *pdev = adapter->pdev;
  1536. struct net_device *netdev = adapter->netdev;
  1537. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1538. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1539. struct sk_buff *skb;
  1540. struct atl1c_recv_ret_status *rrs;
  1541. struct atl1c_buffer *buffer_info;
  1542. while (1) {
  1543. if (*work_done >= work_to_do)
  1544. break;
  1545. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1546. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1547. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1548. RRS_RX_RFD_CNT_MASK;
  1549. if (unlikely(rfd_num != 1))
  1550. /* TODO support mul rfd*/
  1551. if (netif_msg_rx_err(adapter))
  1552. dev_warn(&pdev->dev,
  1553. "Multi rfd not support yet!\n");
  1554. goto rrs_checked;
  1555. } else {
  1556. break;
  1557. }
  1558. rrs_checked:
  1559. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1560. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1561. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1562. if (netif_msg_rx_err(adapter))
  1563. dev_warn(&pdev->dev,
  1564. "wrong packet! rrs word3 is %x\n",
  1565. rrs->word3);
  1566. continue;
  1567. }
  1568. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1569. RRS_PKT_SIZE_MASK);
  1570. /* Good Receive */
  1571. if (likely(rfd_num == 1)) {
  1572. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1573. RRS_RX_RFD_INDEX_MASK;
  1574. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1575. pci_unmap_single(pdev, buffer_info->dma,
  1576. buffer_info->length, PCI_DMA_FROMDEVICE);
  1577. skb = buffer_info->skb;
  1578. } else {
  1579. /* TODO */
  1580. if (netif_msg_rx_err(adapter))
  1581. dev_warn(&pdev->dev,
  1582. "Multi rfd not support yet!\n");
  1583. break;
  1584. }
  1585. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1586. skb_put(skb, length - ETH_FCS_LEN);
  1587. skb->protocol = eth_type_trans(skb, netdev);
  1588. atl1c_rx_checksum(adapter, skb, rrs);
  1589. if (rrs->word3 & RRS_VLAN_INS) {
  1590. u16 vlan;
  1591. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1592. vlan = le16_to_cpu(vlan);
  1593. __vlan_hwaccel_put_tag(skb, vlan);
  1594. }
  1595. netif_receive_skb(skb);
  1596. (*work_done)++;
  1597. count++;
  1598. }
  1599. if (count)
  1600. atl1c_alloc_rx_buffer(adapter);
  1601. }
  1602. /**
  1603. * atl1c_clean - NAPI Rx polling callback
  1604. */
  1605. static int atl1c_clean(struct napi_struct *napi, int budget)
  1606. {
  1607. struct atl1c_adapter *adapter =
  1608. container_of(napi, struct atl1c_adapter, napi);
  1609. int work_done = 0;
  1610. /* Keep link state information with original netdev */
  1611. if (!netif_carrier_ok(adapter->netdev))
  1612. goto quit_polling;
  1613. /* just enable one RXQ */
  1614. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1615. if (work_done < budget) {
  1616. quit_polling:
  1617. napi_complete(napi);
  1618. adapter->hw.intr_mask |= ISR_RX_PKT;
  1619. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1620. }
  1621. return work_done;
  1622. }
  1623. #ifdef CONFIG_NET_POLL_CONTROLLER
  1624. /*
  1625. * Polling 'interrupt' - used by things like netconsole to send skbs
  1626. * without having to re-enable interrupts. It's not called while
  1627. * the interrupt routine is executing.
  1628. */
  1629. static void atl1c_netpoll(struct net_device *netdev)
  1630. {
  1631. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1632. disable_irq(adapter->pdev->irq);
  1633. atl1c_intr(adapter->pdev->irq, netdev);
  1634. enable_irq(adapter->pdev->irq);
  1635. }
  1636. #endif
  1637. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1638. {
  1639. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1640. u16 next_to_use = 0;
  1641. u16 next_to_clean = 0;
  1642. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1643. next_to_use = tpd_ring->next_to_use;
  1644. return (u16)(next_to_clean > next_to_use) ?
  1645. (next_to_clean - next_to_use - 1) :
  1646. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1647. }
  1648. /*
  1649. * get next usable tpd
  1650. * Note: should call atl1c_tdp_avail to make sure
  1651. * there is enough tpd to use
  1652. */
  1653. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1654. enum atl1c_trans_queue type)
  1655. {
  1656. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1657. struct atl1c_tpd_desc *tpd_desc;
  1658. u16 next_to_use = 0;
  1659. next_to_use = tpd_ring->next_to_use;
  1660. if (++tpd_ring->next_to_use == tpd_ring->count)
  1661. tpd_ring->next_to_use = 0;
  1662. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1663. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1664. return tpd_desc;
  1665. }
  1666. static struct atl1c_buffer *
  1667. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1668. {
  1669. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1670. return &tpd_ring->buffer_info[tpd -
  1671. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1672. }
  1673. /* Calculate the transmit packet descript needed*/
  1674. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1675. {
  1676. u16 tpd_req;
  1677. u16 proto_hdr_len = 0;
  1678. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1679. if (skb_is_gso(skb)) {
  1680. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1681. if (proto_hdr_len < skb_headlen(skb))
  1682. tpd_req++;
  1683. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1684. tpd_req++;
  1685. }
  1686. return tpd_req;
  1687. }
  1688. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1689. struct sk_buff *skb,
  1690. struct atl1c_tpd_desc **tpd,
  1691. enum atl1c_trans_queue type)
  1692. {
  1693. struct pci_dev *pdev = adapter->pdev;
  1694. u8 hdr_len;
  1695. u32 real_len;
  1696. unsigned short offload_type;
  1697. int err;
  1698. if (skb_is_gso(skb)) {
  1699. if (skb_header_cloned(skb)) {
  1700. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1701. if (unlikely(err))
  1702. return -1;
  1703. }
  1704. offload_type = skb_shinfo(skb)->gso_type;
  1705. if (offload_type & SKB_GSO_TCPV4) {
  1706. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1707. + ntohs(ip_hdr(skb)->tot_len));
  1708. if (real_len < skb->len)
  1709. pskb_trim(skb, real_len);
  1710. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1711. if (unlikely(skb->len == hdr_len)) {
  1712. /* only xsum need */
  1713. if (netif_msg_tx_queued(adapter))
  1714. dev_warn(&pdev->dev,
  1715. "IPV4 tso with zero data??\n");
  1716. goto check_sum;
  1717. } else {
  1718. ip_hdr(skb)->check = 0;
  1719. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1720. ip_hdr(skb)->saddr,
  1721. ip_hdr(skb)->daddr,
  1722. 0, IPPROTO_TCP, 0);
  1723. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1724. }
  1725. }
  1726. if (offload_type & SKB_GSO_TCPV6) {
  1727. struct atl1c_tpd_ext_desc *etpd =
  1728. *(struct atl1c_tpd_ext_desc **)(tpd);
  1729. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1730. *tpd = atl1c_get_tpd(adapter, type);
  1731. ipv6_hdr(skb)->payload_len = 0;
  1732. /* check payload == 0 byte ? */
  1733. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1734. if (unlikely(skb->len == hdr_len)) {
  1735. /* only xsum need */
  1736. if (netif_msg_tx_queued(adapter))
  1737. dev_warn(&pdev->dev,
  1738. "IPV6 tso with zero data??\n");
  1739. goto check_sum;
  1740. } else
  1741. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1742. &ipv6_hdr(skb)->saddr,
  1743. &ipv6_hdr(skb)->daddr,
  1744. 0, IPPROTO_TCP, 0);
  1745. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1746. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1747. etpd->pkt_len = cpu_to_le32(skb->len);
  1748. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1749. }
  1750. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1751. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1752. TPD_TCPHDR_OFFSET_SHIFT;
  1753. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1754. TPD_MSS_SHIFT;
  1755. return 0;
  1756. }
  1757. check_sum:
  1758. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1759. u8 css, cso;
  1760. cso = skb_checksum_start_offset(skb);
  1761. if (unlikely(cso & 0x1)) {
  1762. if (netif_msg_tx_err(adapter))
  1763. dev_err(&adapter->pdev->dev,
  1764. "payload offset should not an event number\n");
  1765. return -1;
  1766. } else {
  1767. css = cso + skb->csum_offset;
  1768. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1769. TPD_PLOADOFFSET_SHIFT;
  1770. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1771. TPD_CCSUM_OFFSET_SHIFT;
  1772. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1773. }
  1774. }
  1775. return 0;
  1776. }
  1777. static void atl1c_tx_rollback(struct atl1c_adapter *adpt,
  1778. struct atl1c_tpd_desc *first_tpd,
  1779. enum atl1c_trans_queue type)
  1780. {
  1781. struct atl1c_tpd_ring *tpd_ring = &adpt->tpd_ring[type];
  1782. struct atl1c_buffer *buffer_info;
  1783. struct atl1c_tpd_desc *tpd;
  1784. u16 first_index, index;
  1785. first_index = first_tpd - (struct atl1c_tpd_desc *)tpd_ring->desc;
  1786. index = first_index;
  1787. while (index != tpd_ring->next_to_use) {
  1788. tpd = ATL1C_TPD_DESC(tpd_ring, index);
  1789. buffer_info = &tpd_ring->buffer_info[index];
  1790. atl1c_clean_buffer(adpt->pdev, buffer_info, 0);
  1791. memset(tpd, 0, sizeof(struct atl1c_tpd_desc));
  1792. if (++index == tpd_ring->count)
  1793. index = 0;
  1794. }
  1795. tpd_ring->next_to_use = first_index;
  1796. }
  1797. static int atl1c_tx_map(struct atl1c_adapter *adapter,
  1798. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1799. enum atl1c_trans_queue type)
  1800. {
  1801. struct atl1c_tpd_desc *use_tpd = NULL;
  1802. struct atl1c_buffer *buffer_info = NULL;
  1803. u16 buf_len = skb_headlen(skb);
  1804. u16 map_len = 0;
  1805. u16 mapped_len = 0;
  1806. u16 hdr_len = 0;
  1807. u16 nr_frags;
  1808. u16 f;
  1809. int tso;
  1810. nr_frags = skb_shinfo(skb)->nr_frags;
  1811. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1812. if (tso) {
  1813. /* TSO */
  1814. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1815. use_tpd = tpd;
  1816. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1817. buffer_info->length = map_len;
  1818. buffer_info->dma = pci_map_single(adapter->pdev,
  1819. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1820. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1821. buffer_info->dma)))
  1822. goto err_dma;
  1823. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1824. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1825. ATL1C_PCIMAP_TODEVICE);
  1826. mapped_len += map_len;
  1827. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1828. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1829. }
  1830. if (mapped_len < buf_len) {
  1831. /* mapped_len == 0, means we should use the first tpd,
  1832. which is given by caller */
  1833. if (mapped_len == 0)
  1834. use_tpd = tpd;
  1835. else {
  1836. use_tpd = atl1c_get_tpd(adapter, type);
  1837. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1838. }
  1839. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1840. buffer_info->length = buf_len - mapped_len;
  1841. buffer_info->dma =
  1842. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1843. buffer_info->length, PCI_DMA_TODEVICE);
  1844. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1845. buffer_info->dma)))
  1846. goto err_dma;
  1847. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1848. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1849. ATL1C_PCIMAP_TODEVICE);
  1850. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1851. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1852. }
  1853. for (f = 0; f < nr_frags; f++) {
  1854. struct skb_frag_struct *frag;
  1855. frag = &skb_shinfo(skb)->frags[f];
  1856. use_tpd = atl1c_get_tpd(adapter, type);
  1857. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1858. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1859. buffer_info->length = skb_frag_size(frag);
  1860. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1861. frag, 0,
  1862. buffer_info->length,
  1863. DMA_TO_DEVICE);
  1864. if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma))
  1865. goto err_dma;
  1866. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1867. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1868. ATL1C_PCIMAP_TODEVICE);
  1869. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1870. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1871. }
  1872. /* The last tpd */
  1873. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1874. /* The last buffer info contain the skb address,
  1875. so it will be free after unmap */
  1876. buffer_info->skb = skb;
  1877. return 0;
  1878. err_dma:
  1879. buffer_info->dma = 0;
  1880. buffer_info->length = 0;
  1881. return -1;
  1882. }
  1883. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1884. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1885. {
  1886. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1887. u16 reg;
  1888. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1889. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1890. }
  1891. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1892. struct net_device *netdev)
  1893. {
  1894. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1895. unsigned long flags;
  1896. u16 tpd_req = 1;
  1897. struct atl1c_tpd_desc *tpd;
  1898. enum atl1c_trans_queue type = atl1c_trans_normal;
  1899. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1900. dev_kfree_skb_any(skb);
  1901. return NETDEV_TX_OK;
  1902. }
  1903. tpd_req = atl1c_cal_tpd_req(skb);
  1904. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1905. if (netif_msg_pktdata(adapter))
  1906. dev_info(&adapter->pdev->dev, "tx locked\n");
  1907. return NETDEV_TX_LOCKED;
  1908. }
  1909. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1910. /* no enough descriptor, just stop queue */
  1911. netif_stop_queue(netdev);
  1912. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1913. return NETDEV_TX_BUSY;
  1914. }
  1915. tpd = atl1c_get_tpd(adapter, type);
  1916. /* do TSO and check sum */
  1917. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1918. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1919. dev_kfree_skb_any(skb);
  1920. return NETDEV_TX_OK;
  1921. }
  1922. if (unlikely(vlan_tx_tag_present(skb))) {
  1923. u16 vlan = vlan_tx_tag_get(skb);
  1924. __le16 tag;
  1925. vlan = cpu_to_le16(vlan);
  1926. AT_VLAN_TO_TAG(vlan, tag);
  1927. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1928. tpd->vlan_tag = tag;
  1929. }
  1930. if (skb_network_offset(skb) != ETH_HLEN)
  1931. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1932. if (atl1c_tx_map(adapter, skb, tpd, type) < 0) {
  1933. netif_info(adapter, tx_done, adapter->netdev,
  1934. "tx-skb droppted due to dma error\n");
  1935. /* roll back tpd/buffer */
  1936. atl1c_tx_rollback(adapter, tpd, type);
  1937. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1938. dev_kfree_skb(skb);
  1939. } else {
  1940. atl1c_tx_queue(adapter, skb, tpd, type);
  1941. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1942. }
  1943. return NETDEV_TX_OK;
  1944. }
  1945. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1946. {
  1947. struct net_device *netdev = adapter->netdev;
  1948. free_irq(adapter->pdev->irq, netdev);
  1949. if (adapter->have_msi)
  1950. pci_disable_msi(adapter->pdev);
  1951. }
  1952. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1953. {
  1954. struct pci_dev *pdev = adapter->pdev;
  1955. struct net_device *netdev = adapter->netdev;
  1956. int flags = 0;
  1957. int err = 0;
  1958. adapter->have_msi = true;
  1959. err = pci_enable_msi(adapter->pdev);
  1960. if (err) {
  1961. if (netif_msg_ifup(adapter))
  1962. dev_err(&pdev->dev,
  1963. "Unable to allocate MSI interrupt Error: %d\n",
  1964. err);
  1965. adapter->have_msi = false;
  1966. }
  1967. if (!adapter->have_msi)
  1968. flags |= IRQF_SHARED;
  1969. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  1970. netdev->name, netdev);
  1971. if (err) {
  1972. if (netif_msg_ifup(adapter))
  1973. dev_err(&pdev->dev,
  1974. "Unable to allocate interrupt Error: %d\n",
  1975. err);
  1976. if (adapter->have_msi)
  1977. pci_disable_msi(adapter->pdev);
  1978. return err;
  1979. }
  1980. if (netif_msg_ifup(adapter))
  1981. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1982. return err;
  1983. }
  1984. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
  1985. {
  1986. /* release tx-pending skbs and reset tx/rx ring index */
  1987. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1988. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1989. atl1c_clean_rx_ring(adapter);
  1990. }
  1991. static int atl1c_up(struct atl1c_adapter *adapter)
  1992. {
  1993. struct net_device *netdev = adapter->netdev;
  1994. int err;
  1995. netif_carrier_off(netdev);
  1996. err = atl1c_configure(adapter);
  1997. if (unlikely(err))
  1998. goto err_up;
  1999. err = atl1c_request_irq(adapter);
  2000. if (unlikely(err))
  2001. goto err_up;
  2002. atl1c_check_link_status(adapter);
  2003. clear_bit(__AT_DOWN, &adapter->flags);
  2004. napi_enable(&adapter->napi);
  2005. atl1c_irq_enable(adapter);
  2006. netif_start_queue(netdev);
  2007. return err;
  2008. err_up:
  2009. atl1c_clean_rx_ring(adapter);
  2010. return err;
  2011. }
  2012. static void atl1c_down(struct atl1c_adapter *adapter)
  2013. {
  2014. struct net_device *netdev = adapter->netdev;
  2015. atl1c_del_timer(adapter);
  2016. adapter->work_event = 0; /* clear all event */
  2017. /* signal that we're down so the interrupt handler does not
  2018. * reschedule our watchdog timer */
  2019. set_bit(__AT_DOWN, &adapter->flags);
  2020. netif_carrier_off(netdev);
  2021. napi_disable(&adapter->napi);
  2022. atl1c_irq_disable(adapter);
  2023. atl1c_free_irq(adapter);
  2024. /* disable ASPM if device inactive */
  2025. atl1c_disable_l0s_l1(&adapter->hw);
  2026. /* reset MAC to disable all RX/TX */
  2027. atl1c_reset_mac(&adapter->hw);
  2028. msleep(1);
  2029. adapter->link_speed = SPEED_0;
  2030. adapter->link_duplex = -1;
  2031. atl1c_reset_dma_ring(adapter);
  2032. }
  2033. /**
  2034. * atl1c_open - Called when a network interface is made active
  2035. * @netdev: network interface device structure
  2036. *
  2037. * Returns 0 on success, negative value on failure
  2038. *
  2039. * The open entry point is called when a network interface is made
  2040. * active by the system (IFF_UP). At this point all resources needed
  2041. * for transmit and receive operations are allocated, the interrupt
  2042. * handler is registered with the OS, the watchdog timer is started,
  2043. * and the stack is notified that the interface is ready.
  2044. */
  2045. static int atl1c_open(struct net_device *netdev)
  2046. {
  2047. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2048. int err;
  2049. /* disallow open during test */
  2050. if (test_bit(__AT_TESTING, &adapter->flags))
  2051. return -EBUSY;
  2052. /* allocate rx/tx dma buffer & descriptors */
  2053. err = atl1c_setup_ring_resources(adapter);
  2054. if (unlikely(err))
  2055. return err;
  2056. err = atl1c_up(adapter);
  2057. if (unlikely(err))
  2058. goto err_up;
  2059. return 0;
  2060. err_up:
  2061. atl1c_free_irq(adapter);
  2062. atl1c_free_ring_resources(adapter);
  2063. atl1c_reset_mac(&adapter->hw);
  2064. return err;
  2065. }
  2066. /**
  2067. * atl1c_close - Disables a network interface
  2068. * @netdev: network interface device structure
  2069. *
  2070. * Returns 0, this is not allowed to fail
  2071. *
  2072. * The close entry point is called when an interface is de-activated
  2073. * by the OS. The hardware is still under the drivers control, but
  2074. * needs to be disabled. A global MAC reset is issued to stop the
  2075. * hardware, and all transmit and receive resources are freed.
  2076. */
  2077. static int atl1c_close(struct net_device *netdev)
  2078. {
  2079. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2080. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2081. set_bit(__AT_DOWN, &adapter->flags);
  2082. cancel_work_sync(&adapter->common_task);
  2083. atl1c_down(adapter);
  2084. atl1c_free_ring_resources(adapter);
  2085. return 0;
  2086. }
  2087. static int atl1c_suspend(struct device *dev)
  2088. {
  2089. struct pci_dev *pdev = to_pci_dev(dev);
  2090. struct net_device *netdev = pci_get_drvdata(pdev);
  2091. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2092. struct atl1c_hw *hw = &adapter->hw;
  2093. u32 wufc = adapter->wol;
  2094. atl1c_disable_l0s_l1(hw);
  2095. if (netif_running(netdev)) {
  2096. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2097. atl1c_down(adapter);
  2098. }
  2099. netif_device_detach(netdev);
  2100. if (wufc)
  2101. if (atl1c_phy_to_ps_link(hw) != 0)
  2102. dev_dbg(&pdev->dev, "phy power saving failed");
  2103. atl1c_power_saving(hw, wufc);
  2104. return 0;
  2105. }
  2106. #ifdef CONFIG_PM_SLEEP
  2107. static int atl1c_resume(struct device *dev)
  2108. {
  2109. struct pci_dev *pdev = to_pci_dev(dev);
  2110. struct net_device *netdev = pci_get_drvdata(pdev);
  2111. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2112. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2113. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2114. atl1c_phy_reset(&adapter->hw);
  2115. atl1c_reset_mac(&adapter->hw);
  2116. atl1c_phy_init(&adapter->hw);
  2117. #if 0
  2118. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2119. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2120. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2121. #endif
  2122. netif_device_attach(netdev);
  2123. if (netif_running(netdev))
  2124. atl1c_up(adapter);
  2125. return 0;
  2126. }
  2127. #endif
  2128. static void atl1c_shutdown(struct pci_dev *pdev)
  2129. {
  2130. struct net_device *netdev = pci_get_drvdata(pdev);
  2131. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2132. atl1c_suspend(&pdev->dev);
  2133. pci_wake_from_d3(pdev, adapter->wol);
  2134. pci_set_power_state(pdev, PCI_D3hot);
  2135. }
  2136. static const struct net_device_ops atl1c_netdev_ops = {
  2137. .ndo_open = atl1c_open,
  2138. .ndo_stop = atl1c_close,
  2139. .ndo_validate_addr = eth_validate_addr,
  2140. .ndo_start_xmit = atl1c_xmit_frame,
  2141. .ndo_set_mac_address = atl1c_set_mac_addr,
  2142. .ndo_set_rx_mode = atl1c_set_multi,
  2143. .ndo_change_mtu = atl1c_change_mtu,
  2144. .ndo_fix_features = atl1c_fix_features,
  2145. .ndo_set_features = atl1c_set_features,
  2146. .ndo_do_ioctl = atl1c_ioctl,
  2147. .ndo_tx_timeout = atl1c_tx_timeout,
  2148. .ndo_get_stats = atl1c_get_stats,
  2149. #ifdef CONFIG_NET_POLL_CONTROLLER
  2150. .ndo_poll_controller = atl1c_netpoll,
  2151. #endif
  2152. };
  2153. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2154. {
  2155. SET_NETDEV_DEV(netdev, &pdev->dev);
  2156. pci_set_drvdata(pdev, netdev);
  2157. netdev->netdev_ops = &atl1c_netdev_ops;
  2158. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2159. atl1c_set_ethtool_ops(netdev);
  2160. /* TODO: add when ready */
  2161. netdev->hw_features = NETIF_F_SG |
  2162. NETIF_F_HW_CSUM |
  2163. NETIF_F_HW_VLAN_RX |
  2164. NETIF_F_TSO |
  2165. NETIF_F_TSO6;
  2166. netdev->features = netdev->hw_features |
  2167. NETIF_F_HW_VLAN_TX;
  2168. return 0;
  2169. }
  2170. /**
  2171. * atl1c_probe - Device Initialization Routine
  2172. * @pdev: PCI device information struct
  2173. * @ent: entry in atl1c_pci_tbl
  2174. *
  2175. * Returns 0 on success, negative on failure
  2176. *
  2177. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2178. * The OS initialization, configuring of the adapter private structure,
  2179. * and a hardware reset occur.
  2180. */
  2181. static int atl1c_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2182. {
  2183. struct net_device *netdev;
  2184. struct atl1c_adapter *adapter;
  2185. static int cards_found;
  2186. int err = 0;
  2187. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2188. err = pci_enable_device_mem(pdev);
  2189. if (err) {
  2190. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2191. return err;
  2192. }
  2193. /*
  2194. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2195. * shared register for the high 32 bits, so only a single, aligned,
  2196. * 4 GB physical address range can be used at a time.
  2197. *
  2198. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2199. * worth. It is far easier to limit to 32-bit DMA than update
  2200. * various kernel subsystems to support the mechanics required by a
  2201. * fixed-high-32-bit system.
  2202. */
  2203. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2204. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2205. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2206. goto err_dma;
  2207. }
  2208. err = pci_request_regions(pdev, atl1c_driver_name);
  2209. if (err) {
  2210. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2211. goto err_pci_reg;
  2212. }
  2213. pci_set_master(pdev);
  2214. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2215. if (netdev == NULL) {
  2216. err = -ENOMEM;
  2217. goto err_alloc_etherdev;
  2218. }
  2219. err = atl1c_init_netdev(netdev, pdev);
  2220. if (err) {
  2221. dev_err(&pdev->dev, "init netdevice failed\n");
  2222. goto err_init_netdev;
  2223. }
  2224. adapter = netdev_priv(netdev);
  2225. adapter->bd_number = cards_found;
  2226. adapter->netdev = netdev;
  2227. adapter->pdev = pdev;
  2228. adapter->hw.adapter = adapter;
  2229. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2230. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2231. if (!adapter->hw.hw_addr) {
  2232. err = -EIO;
  2233. dev_err(&pdev->dev, "cannot map device registers\n");
  2234. goto err_ioremap;
  2235. }
  2236. /* init mii data */
  2237. adapter->mii.dev = netdev;
  2238. adapter->mii.mdio_read = atl1c_mdio_read;
  2239. adapter->mii.mdio_write = atl1c_mdio_write;
  2240. adapter->mii.phy_id_mask = 0x1f;
  2241. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2242. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2243. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2244. (unsigned long)adapter);
  2245. /* setup the private structure */
  2246. err = atl1c_sw_init(adapter);
  2247. if (err) {
  2248. dev_err(&pdev->dev, "net device private data init failed\n");
  2249. goto err_sw_init;
  2250. }
  2251. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2252. /* Init GPHY as early as possible due to power saving issue */
  2253. atl1c_phy_reset(&adapter->hw);
  2254. err = atl1c_reset_mac(&adapter->hw);
  2255. if (err) {
  2256. err = -EIO;
  2257. goto err_reset;
  2258. }
  2259. /* reset the controller to
  2260. * put the device in a known good starting state */
  2261. err = atl1c_phy_init(&adapter->hw);
  2262. if (err) {
  2263. err = -EIO;
  2264. goto err_reset;
  2265. }
  2266. if (atl1c_read_mac_addr(&adapter->hw)) {
  2267. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2268. netdev->addr_assign_type = NET_ADDR_RANDOM;
  2269. }
  2270. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2271. if (netif_msg_probe(adapter))
  2272. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2273. adapter->hw.mac_addr);
  2274. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  2275. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2276. adapter->work_event = 0;
  2277. err = register_netdev(netdev);
  2278. if (err) {
  2279. dev_err(&pdev->dev, "register netdevice failed\n");
  2280. goto err_register;
  2281. }
  2282. if (netif_msg_probe(adapter))
  2283. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2284. cards_found++;
  2285. return 0;
  2286. err_reset:
  2287. err_register:
  2288. err_sw_init:
  2289. iounmap(adapter->hw.hw_addr);
  2290. err_init_netdev:
  2291. err_ioremap:
  2292. free_netdev(netdev);
  2293. err_alloc_etherdev:
  2294. pci_release_regions(pdev);
  2295. err_pci_reg:
  2296. err_dma:
  2297. pci_disable_device(pdev);
  2298. return err;
  2299. }
  2300. /**
  2301. * atl1c_remove - Device Removal Routine
  2302. * @pdev: PCI device information struct
  2303. *
  2304. * atl1c_remove is called by the PCI subsystem to alert the driver
  2305. * that it should release a PCI device. The could be caused by a
  2306. * Hot-Plug event, or because the driver is going to be removed from
  2307. * memory.
  2308. */
  2309. static void atl1c_remove(struct pci_dev *pdev)
  2310. {
  2311. struct net_device *netdev = pci_get_drvdata(pdev);
  2312. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2313. unregister_netdev(netdev);
  2314. /* restore permanent address */
  2315. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
  2316. atl1c_phy_disable(&adapter->hw);
  2317. iounmap(adapter->hw.hw_addr);
  2318. pci_release_regions(pdev);
  2319. pci_disable_device(pdev);
  2320. free_netdev(netdev);
  2321. }
  2322. /**
  2323. * atl1c_io_error_detected - called when PCI error is detected
  2324. * @pdev: Pointer to PCI device
  2325. * @state: The current pci connection state
  2326. *
  2327. * This function is called after a PCI bus error affecting
  2328. * this device has been detected.
  2329. */
  2330. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2331. pci_channel_state_t state)
  2332. {
  2333. struct net_device *netdev = pci_get_drvdata(pdev);
  2334. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2335. netif_device_detach(netdev);
  2336. if (state == pci_channel_io_perm_failure)
  2337. return PCI_ERS_RESULT_DISCONNECT;
  2338. if (netif_running(netdev))
  2339. atl1c_down(adapter);
  2340. pci_disable_device(pdev);
  2341. /* Request a slot slot reset. */
  2342. return PCI_ERS_RESULT_NEED_RESET;
  2343. }
  2344. /**
  2345. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2346. * @pdev: Pointer to PCI device
  2347. *
  2348. * Restart the card from scratch, as if from a cold-boot. Implementation
  2349. * resembles the first-half of the e1000_resume routine.
  2350. */
  2351. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2352. {
  2353. struct net_device *netdev = pci_get_drvdata(pdev);
  2354. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2355. if (pci_enable_device(pdev)) {
  2356. if (netif_msg_hw(adapter))
  2357. dev_err(&pdev->dev,
  2358. "Cannot re-enable PCI device after reset\n");
  2359. return PCI_ERS_RESULT_DISCONNECT;
  2360. }
  2361. pci_set_master(pdev);
  2362. pci_enable_wake(pdev, PCI_D3hot, 0);
  2363. pci_enable_wake(pdev, PCI_D3cold, 0);
  2364. atl1c_reset_mac(&adapter->hw);
  2365. return PCI_ERS_RESULT_RECOVERED;
  2366. }
  2367. /**
  2368. * atl1c_io_resume - called when traffic can start flowing again.
  2369. * @pdev: Pointer to PCI device
  2370. *
  2371. * This callback is called when the error recovery driver tells us that
  2372. * its OK to resume normal operation. Implementation resembles the
  2373. * second-half of the atl1c_resume routine.
  2374. */
  2375. static void atl1c_io_resume(struct pci_dev *pdev)
  2376. {
  2377. struct net_device *netdev = pci_get_drvdata(pdev);
  2378. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2379. if (netif_running(netdev)) {
  2380. if (atl1c_up(adapter)) {
  2381. if (netif_msg_hw(adapter))
  2382. dev_err(&pdev->dev,
  2383. "Cannot bring device back up after reset\n");
  2384. return;
  2385. }
  2386. }
  2387. netif_device_attach(netdev);
  2388. }
  2389. static const struct pci_error_handlers atl1c_err_handler = {
  2390. .error_detected = atl1c_io_error_detected,
  2391. .slot_reset = atl1c_io_slot_reset,
  2392. .resume = atl1c_io_resume,
  2393. };
  2394. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2395. static struct pci_driver atl1c_driver = {
  2396. .name = atl1c_driver_name,
  2397. .id_table = atl1c_pci_tbl,
  2398. .probe = atl1c_probe,
  2399. .remove = atl1c_remove,
  2400. .shutdown = atl1c_shutdown,
  2401. .err_handler = &atl1c_err_handler,
  2402. .driver.pm = &atl1c_pm_ops,
  2403. };
  2404. /**
  2405. * atl1c_init_module - Driver Registration Routine
  2406. *
  2407. * atl1c_init_module is the first routine called when the driver is
  2408. * loaded. All it does is register with the PCI subsystem.
  2409. */
  2410. static int __init atl1c_init_module(void)
  2411. {
  2412. return pci_register_driver(&atl1c_driver);
  2413. }
  2414. /**
  2415. * atl1c_exit_module - Driver Exit Cleanup Routine
  2416. *
  2417. * atl1c_exit_module is called just before the driver is removed
  2418. * from memory.
  2419. */
  2420. static void __exit atl1c_exit_module(void)
  2421. {
  2422. pci_unregister_driver(&atl1c_driver);
  2423. }
  2424. module_init(atl1c_init_module);
  2425. module_exit(atl1c_exit_module);