caif_shmcore.c 18 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson AB 2010
  3. * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com
  4. * Authors: Amarnath Revanna / amarnath.bangalore.revanna@stericsson.com,
  5. * Daniel Martensson / daniel.martensson@stericsson.com
  6. * License terms: GNU General Public License (GPL) version 2
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
  9. #include <linux/spinlock.h>
  10. #include <linux/sched.h>
  11. #include <linux/list.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/if_arp.h>
  14. #include <linux/io.h>
  15. #include <net/caif/caif_device.h>
  16. #include <net/caif/caif_shm.h>
  17. #define NR_TX_BUF 6
  18. #define NR_RX_BUF 6
  19. #define TX_BUF_SZ 0x2000
  20. #define RX_BUF_SZ 0x2000
  21. #define CAIF_NEEDED_HEADROOM 32
  22. #define CAIF_FLOW_ON 1
  23. #define CAIF_FLOW_OFF 0
  24. #define LOW_WATERMARK 3
  25. #define HIGH_WATERMARK 4
  26. /* Maximum number of CAIF buffers per shared memory buffer. */
  27. #define SHM_MAX_FRMS_PER_BUF 10
  28. /*
  29. * Size in bytes of the descriptor area
  30. * (With end of descriptor signalling)
  31. */
  32. #define SHM_CAIF_DESC_SIZE ((SHM_MAX_FRMS_PER_BUF + 1) * \
  33. sizeof(struct shm_pck_desc))
  34. /*
  35. * Offset to the first CAIF frame within a shared memory buffer.
  36. * Aligned on 32 bytes.
  37. */
  38. #define SHM_CAIF_FRM_OFS (SHM_CAIF_DESC_SIZE + (SHM_CAIF_DESC_SIZE % 32))
  39. /* Number of bytes for CAIF shared memory header. */
  40. #define SHM_HDR_LEN 1
  41. /* Number of padding bytes for the complete CAIF frame. */
  42. #define SHM_FRM_PAD_LEN 4
  43. #define CAIF_MAX_MTU 4096
  44. #define SHM_SET_FULL(x) (((x+1) & 0x0F) << 0)
  45. #define SHM_GET_FULL(x) (((x >> 0) & 0x0F) - 1)
  46. #define SHM_SET_EMPTY(x) (((x+1) & 0x0F) << 4)
  47. #define SHM_GET_EMPTY(x) (((x >> 4) & 0x0F) - 1)
  48. #define SHM_FULL_MASK (0x0F << 0)
  49. #define SHM_EMPTY_MASK (0x0F << 4)
  50. struct shm_pck_desc {
  51. /*
  52. * Offset from start of shared memory area to start of
  53. * shared memory CAIF frame.
  54. */
  55. u32 frm_ofs;
  56. u32 frm_len;
  57. };
  58. struct buf_list {
  59. unsigned char *desc_vptr;
  60. u32 phy_addr;
  61. u32 index;
  62. u32 len;
  63. u32 frames;
  64. u32 frm_ofs;
  65. struct list_head list;
  66. };
  67. struct shm_caif_frm {
  68. /* Number of bytes of padding before the CAIF frame. */
  69. u8 hdr_ofs;
  70. };
  71. struct shmdrv_layer {
  72. /* caif_dev_common must always be first in the structure*/
  73. struct caif_dev_common cfdev;
  74. u32 shm_tx_addr;
  75. u32 shm_rx_addr;
  76. u32 shm_base_addr;
  77. u32 tx_empty_available;
  78. spinlock_t lock;
  79. struct list_head tx_empty_list;
  80. struct list_head tx_pend_list;
  81. struct list_head tx_full_list;
  82. struct list_head rx_empty_list;
  83. struct list_head rx_pend_list;
  84. struct list_head rx_full_list;
  85. struct workqueue_struct *pshm_tx_workqueue;
  86. struct workqueue_struct *pshm_rx_workqueue;
  87. struct work_struct shm_tx_work;
  88. struct work_struct shm_rx_work;
  89. struct sk_buff_head sk_qhead;
  90. struct shmdev_layer *pshm_dev;
  91. };
  92. static int shm_netdev_open(struct net_device *shm_netdev)
  93. {
  94. netif_wake_queue(shm_netdev);
  95. return 0;
  96. }
  97. static int shm_netdev_close(struct net_device *shm_netdev)
  98. {
  99. netif_stop_queue(shm_netdev);
  100. return 0;
  101. }
  102. int caif_shmdrv_rx_cb(u32 mbx_msg, void *priv)
  103. {
  104. struct buf_list *pbuf;
  105. struct shmdrv_layer *pshm_drv;
  106. struct list_head *pos;
  107. u32 avail_emptybuff = 0;
  108. unsigned long flags = 0;
  109. pshm_drv = priv;
  110. /* Check for received buffers. */
  111. if (mbx_msg & SHM_FULL_MASK) {
  112. int idx;
  113. spin_lock_irqsave(&pshm_drv->lock, flags);
  114. /* Check whether we have any outstanding buffers. */
  115. if (list_empty(&pshm_drv->rx_empty_list)) {
  116. /* Release spin lock. */
  117. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  118. /* We print even in IRQ context... */
  119. pr_warn("No empty Rx buffers to fill: "
  120. "mbx_msg:%x\n", mbx_msg);
  121. /* Bail out. */
  122. goto err_sync;
  123. }
  124. pbuf =
  125. list_entry(pshm_drv->rx_empty_list.next,
  126. struct buf_list, list);
  127. idx = pbuf->index;
  128. /* Check buffer synchronization. */
  129. if (idx != SHM_GET_FULL(mbx_msg)) {
  130. /* We print even in IRQ context... */
  131. pr_warn(
  132. "phyif_shm_mbx_msg_cb: RX full out of sync:"
  133. " idx:%d, msg:%x SHM_GET_FULL(mbx_msg):%x\n",
  134. idx, mbx_msg, SHM_GET_FULL(mbx_msg));
  135. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  136. /* Bail out. */
  137. goto err_sync;
  138. }
  139. list_del_init(&pbuf->list);
  140. list_add_tail(&pbuf->list, &pshm_drv->rx_full_list);
  141. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  142. /* Schedule RX work queue. */
  143. if (!work_pending(&pshm_drv->shm_rx_work))
  144. queue_work(pshm_drv->pshm_rx_workqueue,
  145. &pshm_drv->shm_rx_work);
  146. }
  147. /* Check for emptied buffers. */
  148. if (mbx_msg & SHM_EMPTY_MASK) {
  149. int idx;
  150. spin_lock_irqsave(&pshm_drv->lock, flags);
  151. /* Check whether we have any outstanding buffers. */
  152. if (list_empty(&pshm_drv->tx_full_list)) {
  153. /* We print even in IRQ context... */
  154. pr_warn("No TX to empty: msg:%x\n", mbx_msg);
  155. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  156. /* Bail out. */
  157. goto err_sync;
  158. }
  159. pbuf =
  160. list_entry(pshm_drv->tx_full_list.next,
  161. struct buf_list, list);
  162. idx = pbuf->index;
  163. /* Check buffer synchronization. */
  164. if (idx != SHM_GET_EMPTY(mbx_msg)) {
  165. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  166. /* We print even in IRQ context... */
  167. pr_warn("TX empty "
  168. "out of sync:idx:%d, msg:%x\n", idx, mbx_msg);
  169. /* Bail out. */
  170. goto err_sync;
  171. }
  172. list_del_init(&pbuf->list);
  173. /* Reset buffer parameters. */
  174. pbuf->frames = 0;
  175. pbuf->frm_ofs = SHM_CAIF_FRM_OFS;
  176. list_add_tail(&pbuf->list, &pshm_drv->tx_empty_list);
  177. /* Check the available no. of buffers in the empty list */
  178. list_for_each(pos, &pshm_drv->tx_empty_list)
  179. avail_emptybuff++;
  180. /* Check whether we have to wake up the transmitter. */
  181. if ((avail_emptybuff > HIGH_WATERMARK) &&
  182. (!pshm_drv->tx_empty_available)) {
  183. pshm_drv->tx_empty_available = 1;
  184. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  185. pshm_drv->cfdev.flowctrl
  186. (pshm_drv->pshm_dev->pshm_netdev,
  187. CAIF_FLOW_ON);
  188. /* Schedule the work queue. if required */
  189. if (!work_pending(&pshm_drv->shm_tx_work))
  190. queue_work(pshm_drv->pshm_tx_workqueue,
  191. &pshm_drv->shm_tx_work);
  192. } else
  193. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  194. }
  195. return 0;
  196. err_sync:
  197. return -EIO;
  198. }
  199. static void shm_rx_work_func(struct work_struct *rx_work)
  200. {
  201. struct shmdrv_layer *pshm_drv;
  202. struct buf_list *pbuf;
  203. unsigned long flags = 0;
  204. struct sk_buff *skb;
  205. char *p;
  206. int ret;
  207. pshm_drv = container_of(rx_work, struct shmdrv_layer, shm_rx_work);
  208. while (1) {
  209. struct shm_pck_desc *pck_desc;
  210. spin_lock_irqsave(&pshm_drv->lock, flags);
  211. /* Check for received buffers. */
  212. if (list_empty(&pshm_drv->rx_full_list)) {
  213. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  214. break;
  215. }
  216. pbuf =
  217. list_entry(pshm_drv->rx_full_list.next, struct buf_list,
  218. list);
  219. list_del_init(&pbuf->list);
  220. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  221. /* Retrieve pointer to start of the packet descriptor area. */
  222. pck_desc = (struct shm_pck_desc *) pbuf->desc_vptr;
  223. /*
  224. * Check whether descriptor contains a CAIF shared memory
  225. * frame.
  226. */
  227. while (pck_desc->frm_ofs) {
  228. unsigned int frm_buf_ofs;
  229. unsigned int frm_pck_ofs;
  230. unsigned int frm_pck_len;
  231. /*
  232. * Check whether offset is within buffer limits
  233. * (lower).
  234. */
  235. if (pck_desc->frm_ofs <
  236. (pbuf->phy_addr - pshm_drv->shm_base_addr))
  237. break;
  238. /*
  239. * Check whether offset is within buffer limits
  240. * (higher).
  241. */
  242. if (pck_desc->frm_ofs >
  243. ((pbuf->phy_addr - pshm_drv->shm_base_addr) +
  244. pbuf->len))
  245. break;
  246. /* Calculate offset from start of buffer. */
  247. frm_buf_ofs =
  248. pck_desc->frm_ofs - (pbuf->phy_addr -
  249. pshm_drv->shm_base_addr);
  250. /*
  251. * Calculate offset and length of CAIF packet while
  252. * taking care of the shared memory header.
  253. */
  254. frm_pck_ofs =
  255. frm_buf_ofs + SHM_HDR_LEN +
  256. (*(pbuf->desc_vptr + frm_buf_ofs));
  257. frm_pck_len =
  258. (pck_desc->frm_len - SHM_HDR_LEN -
  259. (*(pbuf->desc_vptr + frm_buf_ofs)));
  260. /* Check whether CAIF packet is within buffer limits */
  261. if ((frm_pck_ofs + pck_desc->frm_len) > pbuf->len)
  262. break;
  263. /* Get a suitable CAIF packet and copy in data. */
  264. skb = netdev_alloc_skb(pshm_drv->pshm_dev->pshm_netdev,
  265. frm_pck_len + 1);
  266. if (skb == NULL) {
  267. pr_info("OOM: Try next frame in descriptor\n");
  268. break;
  269. }
  270. p = skb_put(skb, frm_pck_len);
  271. memcpy(p, pbuf->desc_vptr + frm_pck_ofs, frm_pck_len);
  272. skb->protocol = htons(ETH_P_CAIF);
  273. skb_reset_mac_header(skb);
  274. skb->dev = pshm_drv->pshm_dev->pshm_netdev;
  275. /* Push received packet up the stack. */
  276. ret = netif_rx_ni(skb);
  277. if (!ret) {
  278. pshm_drv->pshm_dev->pshm_netdev->stats.
  279. rx_packets++;
  280. pshm_drv->pshm_dev->pshm_netdev->stats.
  281. rx_bytes += pck_desc->frm_len;
  282. } else
  283. ++pshm_drv->pshm_dev->pshm_netdev->stats.
  284. rx_dropped;
  285. /* Move to next packet descriptor. */
  286. pck_desc++;
  287. }
  288. spin_lock_irqsave(&pshm_drv->lock, flags);
  289. list_add_tail(&pbuf->list, &pshm_drv->rx_pend_list);
  290. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  291. }
  292. /* Schedule the work queue. if required */
  293. if (!work_pending(&pshm_drv->shm_tx_work))
  294. queue_work(pshm_drv->pshm_tx_workqueue, &pshm_drv->shm_tx_work);
  295. }
  296. static void shm_tx_work_func(struct work_struct *tx_work)
  297. {
  298. u32 mbox_msg;
  299. unsigned int frmlen, avail_emptybuff, append = 0;
  300. unsigned long flags = 0;
  301. struct buf_list *pbuf = NULL;
  302. struct shmdrv_layer *pshm_drv;
  303. struct shm_caif_frm *frm;
  304. struct sk_buff *skb;
  305. struct shm_pck_desc *pck_desc;
  306. struct list_head *pos;
  307. pshm_drv = container_of(tx_work, struct shmdrv_layer, shm_tx_work);
  308. do {
  309. /* Initialize mailbox message. */
  310. mbox_msg = 0x00;
  311. avail_emptybuff = 0;
  312. spin_lock_irqsave(&pshm_drv->lock, flags);
  313. /* Check for pending receive buffers. */
  314. if (!list_empty(&pshm_drv->rx_pend_list)) {
  315. pbuf = list_entry(pshm_drv->rx_pend_list.next,
  316. struct buf_list, list);
  317. list_del_init(&pbuf->list);
  318. list_add_tail(&pbuf->list, &pshm_drv->rx_empty_list);
  319. /*
  320. * Value index is never changed,
  321. * so read access should be safe.
  322. */
  323. mbox_msg |= SHM_SET_EMPTY(pbuf->index);
  324. }
  325. skb = skb_peek(&pshm_drv->sk_qhead);
  326. if (skb == NULL)
  327. goto send_msg;
  328. /* Check the available no. of buffers in the empty list */
  329. list_for_each(pos, &pshm_drv->tx_empty_list)
  330. avail_emptybuff++;
  331. if ((avail_emptybuff < LOW_WATERMARK) &&
  332. pshm_drv->tx_empty_available) {
  333. /* Update blocking condition. */
  334. pshm_drv->tx_empty_available = 0;
  335. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  336. pshm_drv->cfdev.flowctrl
  337. (pshm_drv->pshm_dev->pshm_netdev,
  338. CAIF_FLOW_OFF);
  339. spin_lock_irqsave(&pshm_drv->lock, flags);
  340. }
  341. /*
  342. * We simply return back to the caller if we do not have space
  343. * either in Tx pending list or Tx empty list. In this case,
  344. * we hold the received skb in the skb list, waiting to
  345. * be transmitted once Tx buffers become available
  346. */
  347. if (list_empty(&pshm_drv->tx_empty_list))
  348. goto send_msg;
  349. /* Get the first free Tx buffer. */
  350. pbuf = list_entry(pshm_drv->tx_empty_list.next,
  351. struct buf_list, list);
  352. do {
  353. if (append) {
  354. skb = skb_peek(&pshm_drv->sk_qhead);
  355. if (skb == NULL)
  356. break;
  357. }
  358. frm = (struct shm_caif_frm *)
  359. (pbuf->desc_vptr + pbuf->frm_ofs);
  360. frm->hdr_ofs = 0;
  361. frmlen = 0;
  362. frmlen += SHM_HDR_LEN + frm->hdr_ofs + skb->len;
  363. /* Add tail padding if needed. */
  364. if (frmlen % SHM_FRM_PAD_LEN)
  365. frmlen += SHM_FRM_PAD_LEN -
  366. (frmlen % SHM_FRM_PAD_LEN);
  367. /*
  368. * Verify that packet, header and additional padding
  369. * can fit within the buffer frame area.
  370. */
  371. if (frmlen >= (pbuf->len - pbuf->frm_ofs))
  372. break;
  373. if (!append) {
  374. list_del_init(&pbuf->list);
  375. append = 1;
  376. }
  377. skb = skb_dequeue(&pshm_drv->sk_qhead);
  378. if (skb == NULL)
  379. break;
  380. /* Copy in CAIF frame. */
  381. skb_copy_bits(skb, 0, pbuf->desc_vptr +
  382. pbuf->frm_ofs + SHM_HDR_LEN +
  383. frm->hdr_ofs, skb->len);
  384. pshm_drv->pshm_dev->pshm_netdev->stats.tx_packets++;
  385. pshm_drv->pshm_dev->pshm_netdev->stats.tx_bytes +=
  386. frmlen;
  387. dev_kfree_skb_irq(skb);
  388. /* Fill in the shared memory packet descriptor area. */
  389. pck_desc = (struct shm_pck_desc *) (pbuf->desc_vptr);
  390. /* Forward to current frame. */
  391. pck_desc += pbuf->frames;
  392. pck_desc->frm_ofs = (pbuf->phy_addr -
  393. pshm_drv->shm_base_addr) +
  394. pbuf->frm_ofs;
  395. pck_desc->frm_len = frmlen;
  396. /* Terminate packet descriptor area. */
  397. pck_desc++;
  398. pck_desc->frm_ofs = 0;
  399. /* Update buffer parameters. */
  400. pbuf->frames++;
  401. pbuf->frm_ofs += frmlen + (frmlen % 32);
  402. } while (pbuf->frames < SHM_MAX_FRMS_PER_BUF);
  403. /* Assign buffer as full. */
  404. list_add_tail(&pbuf->list, &pshm_drv->tx_full_list);
  405. append = 0;
  406. mbox_msg |= SHM_SET_FULL(pbuf->index);
  407. send_msg:
  408. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  409. if (mbox_msg)
  410. pshm_drv->pshm_dev->pshmdev_mbxsend
  411. (pshm_drv->pshm_dev->shm_id, mbox_msg);
  412. } while (mbox_msg);
  413. }
  414. static int shm_netdev_tx(struct sk_buff *skb, struct net_device *shm_netdev)
  415. {
  416. struct shmdrv_layer *pshm_drv;
  417. pshm_drv = netdev_priv(shm_netdev);
  418. skb_queue_tail(&pshm_drv->sk_qhead, skb);
  419. /* Schedule Tx work queue. for deferred processing of skbs*/
  420. if (!work_pending(&pshm_drv->shm_tx_work))
  421. queue_work(pshm_drv->pshm_tx_workqueue, &pshm_drv->shm_tx_work);
  422. return 0;
  423. }
  424. static const struct net_device_ops netdev_ops = {
  425. .ndo_open = shm_netdev_open,
  426. .ndo_stop = shm_netdev_close,
  427. .ndo_start_xmit = shm_netdev_tx,
  428. };
  429. static void shm_netdev_setup(struct net_device *pshm_netdev)
  430. {
  431. struct shmdrv_layer *pshm_drv;
  432. pshm_netdev->netdev_ops = &netdev_ops;
  433. pshm_netdev->mtu = CAIF_MAX_MTU;
  434. pshm_netdev->type = ARPHRD_CAIF;
  435. pshm_netdev->hard_header_len = CAIF_NEEDED_HEADROOM;
  436. pshm_netdev->tx_queue_len = 0;
  437. pshm_netdev->destructor = free_netdev;
  438. pshm_drv = netdev_priv(pshm_netdev);
  439. /* Initialize structures in a clean state. */
  440. memset(pshm_drv, 0, sizeof(struct shmdrv_layer));
  441. pshm_drv->cfdev.link_select = CAIF_LINK_LOW_LATENCY;
  442. }
  443. int caif_shmcore_probe(struct shmdev_layer *pshm_dev)
  444. {
  445. int result, j;
  446. struct shmdrv_layer *pshm_drv = NULL;
  447. pshm_dev->pshm_netdev = alloc_netdev(sizeof(struct shmdrv_layer),
  448. "cfshm%d", shm_netdev_setup);
  449. if (!pshm_dev->pshm_netdev)
  450. return -ENOMEM;
  451. pshm_drv = netdev_priv(pshm_dev->pshm_netdev);
  452. pshm_drv->pshm_dev = pshm_dev;
  453. /*
  454. * Initialization starts with the verification of the
  455. * availability of MBX driver by calling its setup function.
  456. * MBX driver must be available by this time for proper
  457. * functioning of SHM driver.
  458. */
  459. if ((pshm_dev->pshmdev_mbxsetup
  460. (caif_shmdrv_rx_cb, pshm_dev, pshm_drv)) != 0) {
  461. pr_warn("Could not config. SHM Mailbox,"
  462. " Bailing out.....\n");
  463. free_netdev(pshm_dev->pshm_netdev);
  464. return -ENODEV;
  465. }
  466. skb_queue_head_init(&pshm_drv->sk_qhead);
  467. pr_info("SHM DEVICE[%d] PROBED BY DRIVER, NEW SHM DRIVER"
  468. " INSTANCE AT pshm_drv =0x%p\n",
  469. pshm_drv->pshm_dev->shm_id, pshm_drv);
  470. if (pshm_dev->shm_total_sz <
  471. (NR_TX_BUF * TX_BUF_SZ + NR_RX_BUF * RX_BUF_SZ)) {
  472. pr_warn("ERROR, Amount of available"
  473. " Phys. SHM cannot accommodate current SHM "
  474. "driver configuration, Bailing out ...\n");
  475. free_netdev(pshm_dev->pshm_netdev);
  476. return -ENOMEM;
  477. }
  478. pshm_drv->shm_base_addr = pshm_dev->shm_base_addr;
  479. pshm_drv->shm_tx_addr = pshm_drv->shm_base_addr;
  480. if (pshm_dev->shm_loopback)
  481. pshm_drv->shm_rx_addr = pshm_drv->shm_tx_addr;
  482. else
  483. pshm_drv->shm_rx_addr = pshm_dev->shm_base_addr +
  484. (NR_TX_BUF * TX_BUF_SZ);
  485. spin_lock_init(&pshm_drv->lock);
  486. INIT_LIST_HEAD(&pshm_drv->tx_empty_list);
  487. INIT_LIST_HEAD(&pshm_drv->tx_pend_list);
  488. INIT_LIST_HEAD(&pshm_drv->tx_full_list);
  489. INIT_LIST_HEAD(&pshm_drv->rx_empty_list);
  490. INIT_LIST_HEAD(&pshm_drv->rx_pend_list);
  491. INIT_LIST_HEAD(&pshm_drv->rx_full_list);
  492. INIT_WORK(&pshm_drv->shm_tx_work, shm_tx_work_func);
  493. INIT_WORK(&pshm_drv->shm_rx_work, shm_rx_work_func);
  494. pshm_drv->pshm_tx_workqueue =
  495. create_singlethread_workqueue("shm_tx_work");
  496. pshm_drv->pshm_rx_workqueue =
  497. create_singlethread_workqueue("shm_rx_work");
  498. for (j = 0; j < NR_TX_BUF; j++) {
  499. struct buf_list *tx_buf =
  500. kmalloc(sizeof(struct buf_list), GFP_KERNEL);
  501. if (tx_buf == NULL) {
  502. free_netdev(pshm_dev->pshm_netdev);
  503. return -ENOMEM;
  504. }
  505. tx_buf->index = j;
  506. tx_buf->phy_addr = pshm_drv->shm_tx_addr + (TX_BUF_SZ * j);
  507. tx_buf->len = TX_BUF_SZ;
  508. tx_buf->frames = 0;
  509. tx_buf->frm_ofs = SHM_CAIF_FRM_OFS;
  510. if (pshm_dev->shm_loopback)
  511. tx_buf->desc_vptr = (unsigned char *)tx_buf->phy_addr;
  512. else
  513. /*
  514. * FIXME: the result of ioremap is not a pointer - arnd
  515. */
  516. tx_buf->desc_vptr =
  517. ioremap(tx_buf->phy_addr, TX_BUF_SZ);
  518. list_add_tail(&tx_buf->list, &pshm_drv->tx_empty_list);
  519. }
  520. for (j = 0; j < NR_RX_BUF; j++) {
  521. struct buf_list *rx_buf =
  522. kmalloc(sizeof(struct buf_list), GFP_KERNEL);
  523. if (rx_buf == NULL) {
  524. free_netdev(pshm_dev->pshm_netdev);
  525. return -ENOMEM;
  526. }
  527. rx_buf->index = j;
  528. rx_buf->phy_addr = pshm_drv->shm_rx_addr + (RX_BUF_SZ * j);
  529. rx_buf->len = RX_BUF_SZ;
  530. if (pshm_dev->shm_loopback)
  531. rx_buf->desc_vptr = (unsigned char *)rx_buf->phy_addr;
  532. else
  533. rx_buf->desc_vptr =
  534. ioremap(rx_buf->phy_addr, RX_BUF_SZ);
  535. list_add_tail(&rx_buf->list, &pshm_drv->rx_empty_list);
  536. }
  537. pshm_drv->tx_empty_available = 1;
  538. result = register_netdev(pshm_dev->pshm_netdev);
  539. if (result)
  540. pr_warn("ERROR[%d], SHM could not, "
  541. "register with NW FRMWK Bailing out ...\n", result);
  542. return result;
  543. }
  544. void caif_shmcore_remove(struct net_device *pshm_netdev)
  545. {
  546. struct buf_list *pbuf;
  547. struct shmdrv_layer *pshm_drv = NULL;
  548. pshm_drv = netdev_priv(pshm_netdev);
  549. while (!(list_empty(&pshm_drv->tx_pend_list))) {
  550. pbuf =
  551. list_entry(pshm_drv->tx_pend_list.next,
  552. struct buf_list, list);
  553. list_del(&pbuf->list);
  554. kfree(pbuf);
  555. }
  556. while (!(list_empty(&pshm_drv->tx_full_list))) {
  557. pbuf =
  558. list_entry(pshm_drv->tx_full_list.next,
  559. struct buf_list, list);
  560. list_del(&pbuf->list);
  561. kfree(pbuf);
  562. }
  563. while (!(list_empty(&pshm_drv->tx_empty_list))) {
  564. pbuf =
  565. list_entry(pshm_drv->tx_empty_list.next,
  566. struct buf_list, list);
  567. list_del(&pbuf->list);
  568. kfree(pbuf);
  569. }
  570. while (!(list_empty(&pshm_drv->rx_full_list))) {
  571. pbuf =
  572. list_entry(pshm_drv->tx_full_list.next,
  573. struct buf_list, list);
  574. list_del(&pbuf->list);
  575. kfree(pbuf);
  576. }
  577. while (!(list_empty(&pshm_drv->rx_pend_list))) {
  578. pbuf =
  579. list_entry(pshm_drv->tx_pend_list.next,
  580. struct buf_list, list);
  581. list_del(&pbuf->list);
  582. kfree(pbuf);
  583. }
  584. while (!(list_empty(&pshm_drv->rx_empty_list))) {
  585. pbuf =
  586. list_entry(pshm_drv->rx_empty_list.next,
  587. struct buf_list, list);
  588. list_del(&pbuf->list);
  589. kfree(pbuf);
  590. }
  591. /* Destroy work queues. */
  592. destroy_workqueue(pshm_drv->pshm_tx_workqueue);
  593. destroy_workqueue(pshm_drv->pshm_rx_workqueue);
  594. unregister_netdev(pshm_netdev);
  595. }