grufile.c 15 KB

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  1. /*
  2. * SN Platform GRU Driver
  3. *
  4. * FILE OPERATIONS & DRIVER INITIALIZATION
  5. *
  6. * This file supports the user system call for file open, close, mmap, etc.
  7. * This also incudes the driver initialization code.
  8. *
  9. * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/module.h>
  26. #include <linux/kernel.h>
  27. #include <linux/errno.h>
  28. #include <linux/slab.h>
  29. #include <linux/mm.h>
  30. #include <linux/io.h>
  31. #include <linux/spinlock.h>
  32. #include <linux/device.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/proc_fs.h>
  36. #include <linux/uaccess.h>
  37. #ifdef CONFIG_X86_64
  38. #include <asm/uv/uv_irq.h>
  39. #endif
  40. #include <asm/uv/uv.h>
  41. #include "gru.h"
  42. #include "grulib.h"
  43. #include "grutables.h"
  44. #include <asm/uv/uv_hub.h>
  45. #include <asm/uv/uv_mmrs.h>
  46. struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
  47. unsigned long gru_start_paddr __read_mostly;
  48. void *gru_start_vaddr __read_mostly;
  49. unsigned long gru_end_paddr __read_mostly;
  50. unsigned int gru_max_gids __read_mostly;
  51. struct gru_stats_s gru_stats;
  52. /* Guaranteed user available resources on each node */
  53. static int max_user_cbrs, max_user_dsr_bytes;
  54. static struct miscdevice gru_miscdev;
  55. /*
  56. * gru_vma_close
  57. *
  58. * Called when unmapping a device mapping. Frees all gru resources
  59. * and tables belonging to the vma.
  60. */
  61. static void gru_vma_close(struct vm_area_struct *vma)
  62. {
  63. struct gru_vma_data *vdata;
  64. struct gru_thread_state *gts;
  65. struct list_head *entry, *next;
  66. if (!vma->vm_private_data)
  67. return;
  68. vdata = vma->vm_private_data;
  69. vma->vm_private_data = NULL;
  70. gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
  71. vdata);
  72. list_for_each_safe(entry, next, &vdata->vd_head) {
  73. gts =
  74. list_entry(entry, struct gru_thread_state, ts_next);
  75. list_del(&gts->ts_next);
  76. mutex_lock(&gts->ts_ctxlock);
  77. if (gts->ts_gru)
  78. gru_unload_context(gts, 0);
  79. mutex_unlock(&gts->ts_ctxlock);
  80. gts_drop(gts);
  81. }
  82. kfree(vdata);
  83. STAT(vdata_free);
  84. }
  85. /*
  86. * gru_file_mmap
  87. *
  88. * Called when mmapping the device. Initializes the vma with a fault handler
  89. * and private data structure necessary to allocate, track, and free the
  90. * underlying pages.
  91. */
  92. static int gru_file_mmap(struct file *file, struct vm_area_struct *vma)
  93. {
  94. if ((vma->vm_flags & (VM_SHARED | VM_WRITE)) != (VM_SHARED | VM_WRITE))
  95. return -EPERM;
  96. if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) ||
  97. vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
  98. return -EINVAL;
  99. vma->vm_flags |= VM_IO | VM_PFNMAP | VM_LOCKED |
  100. VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP;
  101. vma->vm_page_prot = PAGE_SHARED;
  102. vma->vm_ops = &gru_vm_ops;
  103. vma->vm_private_data = gru_alloc_vma_data(vma, 0);
  104. if (!vma->vm_private_data)
  105. return -ENOMEM;
  106. gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
  107. file, vma->vm_start, vma, vma->vm_private_data);
  108. return 0;
  109. }
  110. /*
  111. * Create a new GRU context
  112. */
  113. static int gru_create_new_context(unsigned long arg)
  114. {
  115. struct gru_create_context_req req;
  116. struct vm_area_struct *vma;
  117. struct gru_vma_data *vdata;
  118. int ret = -EINVAL;
  119. if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
  120. return -EFAULT;
  121. if (req.data_segment_bytes > max_user_dsr_bytes)
  122. return -EINVAL;
  123. if (req.control_blocks > max_user_cbrs || !req.maximum_thread_count)
  124. return -EINVAL;
  125. if (!(req.options & GRU_OPT_MISS_MASK))
  126. req.options |= GRU_OPT_MISS_FMM_INTR;
  127. down_write(&current->mm->mmap_sem);
  128. vma = gru_find_vma(req.gseg);
  129. if (vma) {
  130. vdata = vma->vm_private_data;
  131. vdata->vd_user_options = req.options;
  132. vdata->vd_dsr_au_count =
  133. GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
  134. vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
  135. vdata->vd_tlb_preload_count = req.tlb_preload_count;
  136. ret = 0;
  137. }
  138. up_write(&current->mm->mmap_sem);
  139. return ret;
  140. }
  141. /*
  142. * Get GRU configuration info (temp - for emulator testing)
  143. */
  144. static long gru_get_config_info(unsigned long arg)
  145. {
  146. struct gru_config_info info;
  147. int nodesperblade;
  148. if (num_online_nodes() > 1 &&
  149. (uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
  150. nodesperblade = 2;
  151. else
  152. nodesperblade = 1;
  153. info.cpus = num_online_cpus();
  154. info.nodes = num_online_nodes();
  155. info.blades = info.nodes / nodesperblade;
  156. info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;
  157. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  158. return -EFAULT;
  159. return 0;
  160. }
  161. /*
  162. * gru_file_unlocked_ioctl
  163. *
  164. * Called to update file attributes via IOCTL calls.
  165. */
  166. static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
  167. unsigned long arg)
  168. {
  169. int err = -EBADRQC;
  170. gru_dbg(grudev, "file %p, req 0x%x, 0x%lx\n", file, req, arg);
  171. switch (req) {
  172. case GRU_CREATE_CONTEXT:
  173. err = gru_create_new_context(arg);
  174. break;
  175. case GRU_SET_CONTEXT_OPTION:
  176. err = gru_set_context_option(arg);
  177. break;
  178. case GRU_USER_GET_EXCEPTION_DETAIL:
  179. err = gru_get_exception_detail(arg);
  180. break;
  181. case GRU_USER_UNLOAD_CONTEXT:
  182. err = gru_user_unload_context(arg);
  183. break;
  184. case GRU_USER_FLUSH_TLB:
  185. err = gru_user_flush_tlb(arg);
  186. break;
  187. case GRU_USER_CALL_OS:
  188. err = gru_handle_user_call_os(arg);
  189. break;
  190. case GRU_GET_GSEG_STATISTICS:
  191. err = gru_get_gseg_statistics(arg);
  192. break;
  193. case GRU_KTEST:
  194. err = gru_ktest(arg);
  195. break;
  196. case GRU_GET_CONFIG_INFO:
  197. err = gru_get_config_info(arg);
  198. break;
  199. case GRU_DUMP_CHIPLET_STATE:
  200. err = gru_dump_chiplet_request(arg);
  201. break;
  202. }
  203. return err;
  204. }
  205. /*
  206. * Called at init time to build tables for all GRUs that are present in the
  207. * system.
  208. */
  209. static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
  210. void *vaddr, int blade_id, int chiplet_id)
  211. {
  212. spin_lock_init(&gru->gs_lock);
  213. spin_lock_init(&gru->gs_asid_lock);
  214. gru->gs_gru_base_paddr = paddr;
  215. gru->gs_gru_base_vaddr = vaddr;
  216. gru->gs_gid = blade_id * GRU_CHIPLETS_PER_BLADE + chiplet_id;
  217. gru->gs_blade = gru_base[blade_id];
  218. gru->gs_blade_id = blade_id;
  219. gru->gs_chiplet_id = chiplet_id;
  220. gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
  221. gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
  222. gru->gs_asid_limit = MAX_ASID;
  223. gru_tgh_flush_init(gru);
  224. if (gru->gs_gid >= gru_max_gids)
  225. gru_max_gids = gru->gs_gid + 1;
  226. gru_dbg(grudev, "bid %d, gid %d, vaddr %p (0x%lx)\n",
  227. blade_id, gru->gs_gid, gru->gs_gru_base_vaddr,
  228. gru->gs_gru_base_paddr);
  229. }
  230. static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
  231. {
  232. int pnode, nid, bid, chip;
  233. int cbrs, dsrbytes, n;
  234. int order = get_order(sizeof(struct gru_blade_state));
  235. struct page *page;
  236. struct gru_state *gru;
  237. unsigned long paddr;
  238. void *vaddr;
  239. max_user_cbrs = GRU_NUM_CB;
  240. max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
  241. for_each_possible_blade(bid) {
  242. pnode = uv_blade_to_pnode(bid);
  243. nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
  244. page = alloc_pages_node(nid, GFP_KERNEL, order);
  245. if (!page)
  246. goto fail;
  247. gru_base[bid] = page_address(page);
  248. memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
  249. gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
  250. spin_lock_init(&gru_base[bid]->bs_lock);
  251. init_rwsem(&gru_base[bid]->bs_kgts_sema);
  252. dsrbytes = 0;
  253. cbrs = 0;
  254. for (gru = gru_base[bid]->bs_grus, chip = 0;
  255. chip < GRU_CHIPLETS_PER_BLADE;
  256. chip++, gru++) {
  257. paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
  258. vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
  259. gru_init_chiplet(gru, paddr, vaddr, bid, chip);
  260. n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
  261. cbrs = max(cbrs, n);
  262. n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
  263. dsrbytes = max(dsrbytes, n);
  264. }
  265. max_user_cbrs = min(max_user_cbrs, cbrs);
  266. max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
  267. }
  268. return 0;
  269. fail:
  270. for (bid--; bid >= 0; bid--)
  271. free_pages((unsigned long)gru_base[bid], order);
  272. return -ENOMEM;
  273. }
  274. static void gru_free_tables(void)
  275. {
  276. int bid;
  277. int order = get_order(sizeof(struct gru_state) *
  278. GRU_CHIPLETS_PER_BLADE);
  279. for (bid = 0; bid < GRU_MAX_BLADES; bid++)
  280. free_pages((unsigned long)gru_base[bid], order);
  281. }
  282. static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
  283. {
  284. unsigned long mmr = 0;
  285. int core;
  286. /*
  287. * We target the cores of a blade and not the hyperthreads themselves.
  288. * There is a max of 8 cores per socket and 2 sockets per blade,
  289. * making for a max total of 16 cores (i.e., 16 CPUs without
  290. * hyperthreading and 32 CPUs with hyperthreading).
  291. */
  292. core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
  293. if (core >= GRU_NUM_TFM || uv_cpu_ht_number(cpu))
  294. return 0;
  295. if (chiplet == 0) {
  296. mmr = UVH_GR0_TLB_INT0_CONFIG +
  297. core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
  298. } else if (chiplet == 1) {
  299. mmr = UVH_GR1_TLB_INT0_CONFIG +
  300. core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
  301. } else {
  302. BUG();
  303. }
  304. *corep = core;
  305. return mmr;
  306. }
  307. #ifdef CONFIG_IA64
  308. static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
  309. static void gru_noop(struct irq_data *d)
  310. {
  311. }
  312. static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
  313. [0 ... GRU_CHIPLETS_PER_BLADE - 1] {
  314. .irq_mask = gru_noop,
  315. .irq_unmask = gru_noop,
  316. .irq_ack = gru_noop
  317. }
  318. };
  319. static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
  320. irq_handler_t irq_handler, int cpu, int blade)
  321. {
  322. unsigned long mmr;
  323. int irq = IRQ_GRU + chiplet;
  324. int ret, core;
  325. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  326. if (mmr == 0)
  327. return 0;
  328. if (gru_irq_count[chiplet] == 0) {
  329. gru_chip[chiplet].name = irq_name;
  330. ret = irq_set_chip(irq, &gru_chip[chiplet]);
  331. if (ret) {
  332. printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
  333. GRU_DRIVER_ID_STR, -ret);
  334. return ret;
  335. }
  336. ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
  337. if (ret) {
  338. printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
  339. GRU_DRIVER_ID_STR, -ret);
  340. return ret;
  341. }
  342. }
  343. gru_irq_count[chiplet]++;
  344. return 0;
  345. }
  346. static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
  347. {
  348. unsigned long mmr;
  349. int core, irq = IRQ_GRU + chiplet;
  350. if (gru_irq_count[chiplet] == 0)
  351. return;
  352. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  353. if (mmr == 0)
  354. return;
  355. if (--gru_irq_count[chiplet] == 0)
  356. free_irq(irq, NULL);
  357. }
  358. #elif defined CONFIG_X86_64
  359. static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
  360. irq_handler_t irq_handler, int cpu, int blade)
  361. {
  362. unsigned long mmr;
  363. int irq, core;
  364. int ret;
  365. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  366. if (mmr == 0)
  367. return 0;
  368. irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
  369. if (irq < 0) {
  370. printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
  371. GRU_DRIVER_ID_STR, -irq);
  372. return irq;
  373. }
  374. ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
  375. if (ret) {
  376. uv_teardown_irq(irq);
  377. printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
  378. GRU_DRIVER_ID_STR, -ret);
  379. return ret;
  380. }
  381. gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
  382. return 0;
  383. }
  384. static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
  385. {
  386. int irq, core;
  387. unsigned long mmr;
  388. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  389. if (mmr) {
  390. irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
  391. if (irq) {
  392. free_irq(irq, NULL);
  393. uv_teardown_irq(irq);
  394. }
  395. }
  396. }
  397. #endif
  398. static void gru_teardown_tlb_irqs(void)
  399. {
  400. int blade;
  401. int cpu;
  402. for_each_online_cpu(cpu) {
  403. blade = uv_cpu_to_blade_id(cpu);
  404. gru_chiplet_teardown_tlb_irq(0, cpu, blade);
  405. gru_chiplet_teardown_tlb_irq(1, cpu, blade);
  406. }
  407. for_each_possible_blade(blade) {
  408. if (uv_blade_nr_possible_cpus(blade))
  409. continue;
  410. gru_chiplet_teardown_tlb_irq(0, 0, blade);
  411. gru_chiplet_teardown_tlb_irq(1, 0, blade);
  412. }
  413. }
  414. static int gru_setup_tlb_irqs(void)
  415. {
  416. int blade;
  417. int cpu;
  418. int ret;
  419. for_each_online_cpu(cpu) {
  420. blade = uv_cpu_to_blade_id(cpu);
  421. ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
  422. if (ret != 0)
  423. goto exit1;
  424. ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
  425. if (ret != 0)
  426. goto exit1;
  427. }
  428. for_each_possible_blade(blade) {
  429. if (uv_blade_nr_possible_cpus(blade))
  430. continue;
  431. ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
  432. if (ret != 0)
  433. goto exit1;
  434. ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
  435. if (ret != 0)
  436. goto exit1;
  437. }
  438. return 0;
  439. exit1:
  440. gru_teardown_tlb_irqs();
  441. return ret;
  442. }
  443. /*
  444. * gru_init
  445. *
  446. * Called at boot or module load time to initialize the GRUs.
  447. */
  448. static int __init gru_init(void)
  449. {
  450. int ret;
  451. if (!is_uv_system() || (is_uvx_hub() && !is_uv2_hub()))
  452. return 0;
  453. #if defined CONFIG_IA64
  454. gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
  455. #else
  456. gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR) &
  457. 0x7fffffffffffUL;
  458. #endif
  459. gru_start_vaddr = __va(gru_start_paddr);
  460. gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
  461. printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
  462. gru_start_paddr, gru_end_paddr);
  463. ret = misc_register(&gru_miscdev);
  464. if (ret) {
  465. printk(KERN_ERR "%s: misc_register failed\n",
  466. GRU_DRIVER_ID_STR);
  467. goto exit0;
  468. }
  469. ret = gru_proc_init();
  470. if (ret) {
  471. printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
  472. goto exit1;
  473. }
  474. ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
  475. if (ret) {
  476. printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
  477. goto exit2;
  478. }
  479. ret = gru_setup_tlb_irqs();
  480. if (ret != 0)
  481. goto exit3;
  482. gru_kservices_init();
  483. printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
  484. GRU_DRIVER_VERSION_STR);
  485. return 0;
  486. exit3:
  487. gru_free_tables();
  488. exit2:
  489. gru_proc_exit();
  490. exit1:
  491. misc_deregister(&gru_miscdev);
  492. exit0:
  493. return ret;
  494. }
  495. static void __exit gru_exit(void)
  496. {
  497. if (!is_uv_system())
  498. return;
  499. gru_teardown_tlb_irqs();
  500. gru_kservices_exit();
  501. gru_free_tables();
  502. misc_deregister(&gru_miscdev);
  503. gru_proc_exit();
  504. }
  505. static const struct file_operations gru_fops = {
  506. .owner = THIS_MODULE,
  507. .unlocked_ioctl = gru_file_unlocked_ioctl,
  508. .mmap = gru_file_mmap,
  509. .llseek = noop_llseek,
  510. };
  511. static struct miscdevice gru_miscdev = {
  512. .minor = MISC_DYNAMIC_MINOR,
  513. .name = "gru",
  514. .fops = &gru_fops,
  515. };
  516. const struct vm_operations_struct gru_vm_ops = {
  517. .close = gru_vma_close,
  518. .fault = gru_fault,
  519. };
  520. #ifndef MODULE
  521. fs_initcall(gru_init);
  522. #else
  523. module_init(gru_init);
  524. #endif
  525. module_exit(gru_exit);
  526. module_param(gru_options, ulong, 0644);
  527. MODULE_PARM_DESC(gru_options, "Various debug options");
  528. MODULE_AUTHOR("Silicon Graphics, Inc.");
  529. MODULE_LICENSE("GPL");
  530. MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
  531. MODULE_VERSION(GRU_DRIVER_VERSION_STR);