ir-rx51.c 12 KB

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  1. /*
  2. * Copyright (C) 2008 Nokia Corporation
  3. *
  4. * Based on lirc_serial.c
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/uaccess.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/sched.h>
  26. #include <linux/wait.h>
  27. #include <plat/dmtimer.h>
  28. #include <plat/clock.h>
  29. #include <media/lirc.h>
  30. #include <media/lirc_dev.h>
  31. #include <media/ir-rx51.h>
  32. #define LIRC_RX51_DRIVER_FEATURES (LIRC_CAN_SET_SEND_DUTY_CYCLE | \
  33. LIRC_CAN_SET_SEND_CARRIER | \
  34. LIRC_CAN_SEND_PULSE)
  35. #define DRIVER_NAME "lirc_rx51"
  36. #define WBUF_LEN 256
  37. #define TIMER_MAX_VALUE 0xffffffff
  38. struct lirc_rx51 {
  39. struct omap_dm_timer *pwm_timer;
  40. struct omap_dm_timer *pulse_timer;
  41. struct device *dev;
  42. struct lirc_rx51_platform_data *pdata;
  43. wait_queue_head_t wqueue;
  44. unsigned long fclk_khz;
  45. unsigned int freq; /* carrier frequency */
  46. unsigned int duty_cycle; /* carrier duty cycle */
  47. unsigned int irq_num;
  48. unsigned int match;
  49. int wbuf[WBUF_LEN];
  50. int wbuf_index;
  51. unsigned long device_is_open;
  52. int pwm_timer_num;
  53. };
  54. static void lirc_rx51_on(struct lirc_rx51 *lirc_rx51)
  55. {
  56. omap_dm_timer_set_pwm(lirc_rx51->pwm_timer, 0, 1,
  57. OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
  58. }
  59. static void lirc_rx51_off(struct lirc_rx51 *lirc_rx51)
  60. {
  61. omap_dm_timer_set_pwm(lirc_rx51->pwm_timer, 0, 1,
  62. OMAP_TIMER_TRIGGER_NONE);
  63. }
  64. static int init_timing_params(struct lirc_rx51 *lirc_rx51)
  65. {
  66. u32 load, match;
  67. load = -(lirc_rx51->fclk_khz * 1000 / lirc_rx51->freq);
  68. match = -(lirc_rx51->duty_cycle * -load / 100);
  69. omap_dm_timer_set_load(lirc_rx51->pwm_timer, 1, load);
  70. omap_dm_timer_set_match(lirc_rx51->pwm_timer, 1, match);
  71. omap_dm_timer_write_counter(lirc_rx51->pwm_timer, TIMER_MAX_VALUE - 2);
  72. omap_dm_timer_start(lirc_rx51->pwm_timer);
  73. omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
  74. omap_dm_timer_start(lirc_rx51->pulse_timer);
  75. lirc_rx51->match = 0;
  76. return 0;
  77. }
  78. #define tics_after(a, b) ((long)(b) - (long)(a) < 0)
  79. static int pulse_timer_set_timeout(struct lirc_rx51 *lirc_rx51, int usec)
  80. {
  81. int counter;
  82. BUG_ON(usec < 0);
  83. if (lirc_rx51->match == 0)
  84. counter = omap_dm_timer_read_counter(lirc_rx51->pulse_timer);
  85. else
  86. counter = lirc_rx51->match;
  87. counter += (u32)(lirc_rx51->fclk_khz * usec / (1000));
  88. omap_dm_timer_set_match(lirc_rx51->pulse_timer, 1, counter);
  89. omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer,
  90. OMAP_TIMER_INT_MATCH);
  91. if (tics_after(omap_dm_timer_read_counter(lirc_rx51->pulse_timer),
  92. counter)) {
  93. return 1;
  94. }
  95. return 0;
  96. }
  97. static irqreturn_t lirc_rx51_interrupt_handler(int irq, void *ptr)
  98. {
  99. unsigned int retval;
  100. struct lirc_rx51 *lirc_rx51 = ptr;
  101. retval = omap_dm_timer_read_status(lirc_rx51->pulse_timer);
  102. if (!retval)
  103. return IRQ_NONE;
  104. if (retval & ~OMAP_TIMER_INT_MATCH)
  105. dev_err_ratelimited(lirc_rx51->dev,
  106. ": Unexpected interrupt source: %x\n", retval);
  107. omap_dm_timer_write_status(lirc_rx51->pulse_timer,
  108. OMAP_TIMER_INT_MATCH |
  109. OMAP_TIMER_INT_OVERFLOW |
  110. OMAP_TIMER_INT_CAPTURE);
  111. if (lirc_rx51->wbuf_index < 0) {
  112. dev_err_ratelimited(lirc_rx51->dev,
  113. ": BUG wbuf_index has value of %i\n",
  114. lirc_rx51->wbuf_index);
  115. goto end;
  116. }
  117. /*
  118. * If we happen to hit an odd latency spike, loop through the
  119. * pulses until we catch up.
  120. */
  121. do {
  122. if (lirc_rx51->wbuf_index >= WBUF_LEN)
  123. goto end;
  124. if (lirc_rx51->wbuf[lirc_rx51->wbuf_index] == -1)
  125. goto end;
  126. if (lirc_rx51->wbuf_index % 2)
  127. lirc_rx51_off(lirc_rx51);
  128. else
  129. lirc_rx51_on(lirc_rx51);
  130. retval = pulse_timer_set_timeout(lirc_rx51,
  131. lirc_rx51->wbuf[lirc_rx51->wbuf_index]);
  132. lirc_rx51->wbuf_index++;
  133. } while (retval);
  134. return IRQ_HANDLED;
  135. end:
  136. /* Stop TX here */
  137. lirc_rx51_off(lirc_rx51);
  138. lirc_rx51->wbuf_index = -1;
  139. omap_dm_timer_stop(lirc_rx51->pwm_timer);
  140. omap_dm_timer_stop(lirc_rx51->pulse_timer);
  141. omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
  142. wake_up_interruptible(&lirc_rx51->wqueue);
  143. return IRQ_HANDLED;
  144. }
  145. static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51)
  146. {
  147. struct clk *clk_fclk;
  148. int retval, pwm_timer = lirc_rx51->pwm_timer_num;
  149. lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer);
  150. if (lirc_rx51->pwm_timer == NULL) {
  151. dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n",
  152. pwm_timer);
  153. return -EBUSY;
  154. }
  155. lirc_rx51->pulse_timer = omap_dm_timer_request();
  156. if (lirc_rx51->pulse_timer == NULL) {
  157. dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n");
  158. retval = -EBUSY;
  159. goto err1;
  160. }
  161. omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK);
  162. omap_dm_timer_set_source(lirc_rx51->pulse_timer,
  163. OMAP_TIMER_SRC_SYS_CLK);
  164. omap_dm_timer_enable(lirc_rx51->pwm_timer);
  165. omap_dm_timer_enable(lirc_rx51->pulse_timer);
  166. lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer);
  167. retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler,
  168. IRQF_DISABLED | IRQF_SHARED,
  169. "lirc_pulse_timer", lirc_rx51);
  170. if (retval) {
  171. dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n");
  172. goto err2;
  173. }
  174. clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer);
  175. lirc_rx51->fclk_khz = clk_fclk->rate / 1000;
  176. return 0;
  177. err2:
  178. omap_dm_timer_free(lirc_rx51->pulse_timer);
  179. err1:
  180. omap_dm_timer_free(lirc_rx51->pwm_timer);
  181. return retval;
  182. }
  183. static int lirc_rx51_free_port(struct lirc_rx51 *lirc_rx51)
  184. {
  185. omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
  186. free_irq(lirc_rx51->irq_num, lirc_rx51);
  187. lirc_rx51_off(lirc_rx51);
  188. omap_dm_timer_disable(lirc_rx51->pwm_timer);
  189. omap_dm_timer_disable(lirc_rx51->pulse_timer);
  190. omap_dm_timer_free(lirc_rx51->pwm_timer);
  191. omap_dm_timer_free(lirc_rx51->pulse_timer);
  192. lirc_rx51->wbuf_index = -1;
  193. return 0;
  194. }
  195. static ssize_t lirc_rx51_write(struct file *file, const char *buf,
  196. size_t n, loff_t *ppos)
  197. {
  198. int count, i;
  199. struct lirc_rx51 *lirc_rx51 = file->private_data;
  200. if (n % sizeof(int))
  201. return -EINVAL;
  202. count = n / sizeof(int);
  203. if ((count > WBUF_LEN) || (count % 2 == 0))
  204. return -EINVAL;
  205. /* Wait any pending transfers to finish */
  206. wait_event_interruptible(lirc_rx51->wqueue, lirc_rx51->wbuf_index < 0);
  207. if (copy_from_user(lirc_rx51->wbuf, buf, n))
  208. return -EFAULT;
  209. /* Sanity check the input pulses */
  210. for (i = 0; i < count; i++)
  211. if (lirc_rx51->wbuf[i] < 0)
  212. return -EINVAL;
  213. init_timing_params(lirc_rx51);
  214. if (count < WBUF_LEN)
  215. lirc_rx51->wbuf[count] = -1; /* Insert termination mark */
  216. /*
  217. * Adjust latency requirements so the device doesn't go in too
  218. * deep sleep states
  219. */
  220. lirc_rx51->pdata->set_max_mpu_wakeup_lat(lirc_rx51->dev, 50);
  221. lirc_rx51_on(lirc_rx51);
  222. lirc_rx51->wbuf_index = 1;
  223. pulse_timer_set_timeout(lirc_rx51, lirc_rx51->wbuf[0]);
  224. /*
  225. * Don't return back to the userspace until the transfer has
  226. * finished
  227. */
  228. wait_event_interruptible(lirc_rx51->wqueue, lirc_rx51->wbuf_index < 0);
  229. /* We can sleep again */
  230. lirc_rx51->pdata->set_max_mpu_wakeup_lat(lirc_rx51->dev, -1);
  231. return n;
  232. }
  233. static long lirc_rx51_ioctl(struct file *filep,
  234. unsigned int cmd, unsigned long arg)
  235. {
  236. int result;
  237. unsigned long value;
  238. unsigned int ivalue;
  239. struct lirc_rx51 *lirc_rx51 = filep->private_data;
  240. switch (cmd) {
  241. case LIRC_GET_SEND_MODE:
  242. result = put_user(LIRC_MODE_PULSE, (unsigned long *)arg);
  243. if (result)
  244. return result;
  245. break;
  246. case LIRC_SET_SEND_MODE:
  247. result = get_user(value, (unsigned long *)arg);
  248. if (result)
  249. return result;
  250. /* only LIRC_MODE_PULSE supported */
  251. if (value != LIRC_MODE_PULSE)
  252. return -ENOSYS;
  253. break;
  254. case LIRC_GET_REC_MODE:
  255. result = put_user(0, (unsigned long *) arg);
  256. if (result)
  257. return result;
  258. break;
  259. case LIRC_GET_LENGTH:
  260. return -ENOSYS;
  261. break;
  262. case LIRC_SET_SEND_DUTY_CYCLE:
  263. result = get_user(ivalue, (unsigned int *) arg);
  264. if (result)
  265. return result;
  266. if (ivalue <= 0 || ivalue > 100) {
  267. dev_err(lirc_rx51->dev, ": invalid duty cycle %d\n",
  268. ivalue);
  269. return -EINVAL;
  270. }
  271. lirc_rx51->duty_cycle = ivalue;
  272. break;
  273. case LIRC_SET_SEND_CARRIER:
  274. result = get_user(ivalue, (unsigned int *) arg);
  275. if (result)
  276. return result;
  277. if (ivalue > 500000 || ivalue < 20000) {
  278. dev_err(lirc_rx51->dev, ": invalid carrier freq %d\n",
  279. ivalue);
  280. return -EINVAL;
  281. }
  282. lirc_rx51->freq = ivalue;
  283. break;
  284. case LIRC_GET_FEATURES:
  285. result = put_user(LIRC_RX51_DRIVER_FEATURES,
  286. (unsigned long *) arg);
  287. if (result)
  288. return result;
  289. break;
  290. default:
  291. return -ENOIOCTLCMD;
  292. }
  293. return 0;
  294. }
  295. static int lirc_rx51_open(struct inode *inode, struct file *file)
  296. {
  297. struct lirc_rx51 *lirc_rx51 = lirc_get_pdata(file);
  298. BUG_ON(!lirc_rx51);
  299. file->private_data = lirc_rx51;
  300. if (test_and_set_bit(1, &lirc_rx51->device_is_open))
  301. return -EBUSY;
  302. return lirc_rx51_init_port(lirc_rx51);
  303. }
  304. static int lirc_rx51_release(struct inode *inode, struct file *file)
  305. {
  306. struct lirc_rx51 *lirc_rx51 = file->private_data;
  307. lirc_rx51_free_port(lirc_rx51);
  308. clear_bit(1, &lirc_rx51->device_is_open);
  309. return 0;
  310. }
  311. static struct lirc_rx51 lirc_rx51 = {
  312. .freq = 38000,
  313. .duty_cycle = 50,
  314. .wbuf_index = -1,
  315. };
  316. static const struct file_operations lirc_fops = {
  317. .owner = THIS_MODULE,
  318. .write = lirc_rx51_write,
  319. .unlocked_ioctl = lirc_rx51_ioctl,
  320. .read = lirc_dev_fop_read,
  321. .poll = lirc_dev_fop_poll,
  322. .open = lirc_rx51_open,
  323. .release = lirc_rx51_release,
  324. };
  325. static struct lirc_driver lirc_rx51_driver = {
  326. .name = DRIVER_NAME,
  327. .minor = -1,
  328. .code_length = 1,
  329. .data = &lirc_rx51,
  330. .fops = &lirc_fops,
  331. .owner = THIS_MODULE,
  332. };
  333. #ifdef CONFIG_PM
  334. static int lirc_rx51_suspend(struct platform_device *dev, pm_message_t state)
  335. {
  336. /*
  337. * In case the device is still open, do not suspend. Normally
  338. * this should not be a problem as lircd only keeps the device
  339. * open only for short periods of time. We also don't want to
  340. * get involved with race conditions that might happen if we
  341. * were in a middle of a transmit. Thus, we defer any suspend
  342. * actions until transmit has completed.
  343. */
  344. if (test_and_set_bit(1, &lirc_rx51.device_is_open))
  345. return -EAGAIN;
  346. clear_bit(1, &lirc_rx51.device_is_open);
  347. return 0;
  348. }
  349. static int lirc_rx51_resume(struct platform_device *dev)
  350. {
  351. return 0;
  352. }
  353. #else
  354. #define lirc_rx51_suspend NULL
  355. #define lirc_rx51_resume NULL
  356. #endif /* CONFIG_PM */
  357. static int lirc_rx51_probe(struct platform_device *dev)
  358. {
  359. lirc_rx51_driver.features = LIRC_RX51_DRIVER_FEATURES;
  360. lirc_rx51.pdata = dev->dev.platform_data;
  361. lirc_rx51.pwm_timer_num = lirc_rx51.pdata->pwm_timer;
  362. lirc_rx51.dev = &dev->dev;
  363. lirc_rx51_driver.dev = &dev->dev;
  364. lirc_rx51_driver.minor = lirc_register_driver(&lirc_rx51_driver);
  365. init_waitqueue_head(&lirc_rx51.wqueue);
  366. if (lirc_rx51_driver.minor < 0) {
  367. dev_err(lirc_rx51.dev, ": lirc_register_driver failed: %d\n",
  368. lirc_rx51_driver.minor);
  369. return lirc_rx51_driver.minor;
  370. }
  371. dev_info(lirc_rx51.dev, "registration ok, minor: %d, pwm: %d\n",
  372. lirc_rx51_driver.minor, lirc_rx51.pwm_timer_num);
  373. return 0;
  374. }
  375. static int __exit lirc_rx51_remove(struct platform_device *dev)
  376. {
  377. return lirc_unregister_driver(lirc_rx51_driver.minor);
  378. }
  379. struct platform_driver lirc_rx51_platform_driver = {
  380. .probe = lirc_rx51_probe,
  381. .remove = __exit_p(lirc_rx51_remove),
  382. .suspend = lirc_rx51_suspend,
  383. .resume = lirc_rx51_resume,
  384. .driver = {
  385. .name = DRIVER_NAME,
  386. .owner = THIS_MODULE,
  387. },
  388. };
  389. module_platform_driver(lirc_rx51_platform_driver);
  390. MODULE_DESCRIPTION("LIRC TX driver for Nokia RX51");
  391. MODULE_AUTHOR("Nokia Corporation");
  392. MODULE_LICENSE("GPL");