s5p_mfc_cmd_v6.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156
  1. /*
  2. * linux/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com/
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include "s5p_mfc_common.h"
  13. #include "s5p_mfc_cmd.h"
  14. #include "s5p_mfc_debug.h"
  15. #include "s5p_mfc_intr.h"
  16. #include "s5p_mfc_opr.h"
  17. int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd,
  18. struct s5p_mfc_cmd_args *args)
  19. {
  20. mfc_debug(2, "Issue the command: %d\n", cmd);
  21. /* Reset RISC2HOST command */
  22. mfc_write(dev, 0x0, S5P_FIMV_RISC2HOST_CMD_V6);
  23. /* Issue the command */
  24. mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD_V6);
  25. mfc_write(dev, 0x1, S5P_FIMV_HOST2RISC_INT_V6);
  26. return 0;
  27. }
  28. int s5p_mfc_sys_init_cmd_v6(struct s5p_mfc_dev *dev)
  29. {
  30. struct s5p_mfc_cmd_args h2r_args;
  31. struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
  32. s5p_mfc_hw_call(dev->mfc_ops, alloc_dev_context_buffer, dev);
  33. mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
  34. mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
  35. return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SYS_INIT_V6,
  36. &h2r_args);
  37. }
  38. int s5p_mfc_sleep_cmd_v6(struct s5p_mfc_dev *dev)
  39. {
  40. struct s5p_mfc_cmd_args h2r_args;
  41. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  42. return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SLEEP_V6,
  43. &h2r_args);
  44. }
  45. int s5p_mfc_wakeup_cmd_v6(struct s5p_mfc_dev *dev)
  46. {
  47. struct s5p_mfc_cmd_args h2r_args;
  48. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  49. return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_WAKEUP_V6,
  50. &h2r_args);
  51. }
  52. /* Open a new instance and get its number */
  53. int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
  54. {
  55. struct s5p_mfc_dev *dev = ctx->dev;
  56. struct s5p_mfc_cmd_args h2r_args;
  57. int codec_type;
  58. mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode);
  59. dev->curr_ctx = ctx->num;
  60. switch (ctx->codec_mode) {
  61. case S5P_MFC_CODEC_H264_DEC:
  62. codec_type = S5P_FIMV_CODEC_H264_DEC_V6;
  63. break;
  64. case S5P_MFC_CODEC_H264_MVC_DEC:
  65. codec_type = S5P_FIMV_CODEC_H264_MVC_DEC_V6;
  66. break;
  67. case S5P_MFC_CODEC_VC1_DEC:
  68. codec_type = S5P_FIMV_CODEC_VC1_DEC_V6;
  69. break;
  70. case S5P_MFC_CODEC_MPEG4_DEC:
  71. codec_type = S5P_FIMV_CODEC_MPEG4_DEC_V6;
  72. break;
  73. case S5P_MFC_CODEC_MPEG2_DEC:
  74. codec_type = S5P_FIMV_CODEC_MPEG2_DEC_V6;
  75. break;
  76. case S5P_MFC_CODEC_H263_DEC:
  77. codec_type = S5P_FIMV_CODEC_H263_DEC_V6;
  78. break;
  79. case S5P_MFC_CODEC_VC1RCV_DEC:
  80. codec_type = S5P_FIMV_CODEC_VC1RCV_DEC_V6;
  81. break;
  82. case S5P_MFC_CODEC_VP8_DEC:
  83. codec_type = S5P_FIMV_CODEC_VP8_DEC_V6;
  84. break;
  85. case S5P_MFC_CODEC_H264_ENC:
  86. codec_type = S5P_FIMV_CODEC_H264_ENC_V6;
  87. break;
  88. case S5P_MFC_CODEC_H264_MVC_ENC:
  89. codec_type = S5P_FIMV_CODEC_H264_MVC_ENC_V6;
  90. break;
  91. case S5P_MFC_CODEC_MPEG4_ENC:
  92. codec_type = S5P_FIMV_CODEC_MPEG4_ENC_V6;
  93. break;
  94. case S5P_MFC_CODEC_H263_ENC:
  95. codec_type = S5P_FIMV_CODEC_H263_ENC_V6;
  96. break;
  97. default:
  98. codec_type = S5P_FIMV_CODEC_NONE_V6;
  99. };
  100. mfc_write(dev, codec_type, S5P_FIMV_CODEC_TYPE_V6);
  101. mfc_write(dev, ctx->ctx.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
  102. mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
  103. mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */
  104. return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6,
  105. &h2r_args);
  106. }
  107. /* Close instance */
  108. int s5p_mfc_close_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
  109. {
  110. struct s5p_mfc_dev *dev = ctx->dev;
  111. struct s5p_mfc_cmd_args h2r_args;
  112. int ret = 0;
  113. dev->curr_ctx = ctx->num;
  114. if (ctx->state != MFCINST_FREE) {
  115. mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
  116. ret = s5p_mfc_cmd_host2risc_v6(dev,
  117. S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6,
  118. &h2r_args);
  119. } else {
  120. ret = -EINVAL;
  121. }
  122. return ret;
  123. }
  124. /* Initialize cmd function pointers for MFC v6 */
  125. static struct s5p_mfc_hw_cmds s5p_mfc_cmds_v6 = {
  126. .cmd_host2risc = s5p_mfc_cmd_host2risc_v6,
  127. .sys_init_cmd = s5p_mfc_sys_init_cmd_v6,
  128. .sleep_cmd = s5p_mfc_sleep_cmd_v6,
  129. .wakeup_cmd = s5p_mfc_wakeup_cmd_v6,
  130. .open_inst_cmd = s5p_mfc_open_inst_cmd_v6,
  131. .close_inst_cmd = s5p_mfc_close_inst_cmd_v6,
  132. };
  133. struct s5p_mfc_hw_cmds *s5p_mfc_init_hw_cmds_v6(void)
  134. {
  135. return &s5p_mfc_cmds_v6;
  136. }