coda.c 56 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/of.h>
  25. #include <linux/platform_data/imx-iram.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-ioctl.h>
  29. #include <media/v4l2-mem2mem.h>
  30. #include <media/videobuf2-core.h>
  31. #include <media/videobuf2-dma-contig.h>
  32. #include "coda.h"
  33. #define CODA_NAME "coda"
  34. #define CODA_MAX_INSTANCES 4
  35. #define CODA_FMO_BUF_SIZE 32
  36. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  37. #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  38. #define CODA_PARA_BUF_SIZE (10 * 1024)
  39. #define CODA_ISRAM_SIZE (2048 * 2)
  40. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  41. #define CODA_MAX_FRAMEBUFFERS 2
  42. #define MAX_W 720
  43. #define MAX_H 576
  44. #define CODA_MAX_FRAME_SIZE 0x90000
  45. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  46. #define CODA_DEFAULT_GAMMA 4096
  47. #define MIN_W 176
  48. #define MIN_H 144
  49. #define MAX_W 720
  50. #define MAX_H 576
  51. #define S_ALIGN 1 /* multiple of 2 */
  52. #define W_ALIGN 1 /* multiple of 2 */
  53. #define H_ALIGN 1 /* multiple of 2 */
  54. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  55. static int coda_debug;
  56. module_param(coda_debug, int, 0);
  57. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  58. enum {
  59. V4L2_M2M_SRC = 0,
  60. V4L2_M2M_DST = 1,
  61. };
  62. enum coda_fmt_type {
  63. CODA_FMT_ENC,
  64. CODA_FMT_RAW,
  65. };
  66. enum coda_inst_type {
  67. CODA_INST_ENCODER,
  68. CODA_INST_DECODER,
  69. };
  70. enum coda_product {
  71. CODA_DX6 = 0xf001,
  72. CODA_7541 = 0xf012,
  73. };
  74. struct coda_fmt {
  75. char *name;
  76. u32 fourcc;
  77. enum coda_fmt_type type;
  78. };
  79. struct coda_devtype {
  80. char *firmware;
  81. enum coda_product product;
  82. struct coda_fmt *formats;
  83. unsigned int num_formats;
  84. size_t workbuf_size;
  85. };
  86. /* Per-queue, driver-specific private data */
  87. struct coda_q_data {
  88. unsigned int width;
  89. unsigned int height;
  90. unsigned int sizeimage;
  91. struct coda_fmt *fmt;
  92. };
  93. struct coda_aux_buf {
  94. void *vaddr;
  95. dma_addr_t paddr;
  96. u32 size;
  97. };
  98. struct coda_dev {
  99. struct v4l2_device v4l2_dev;
  100. struct video_device vfd;
  101. struct platform_device *plat_dev;
  102. const struct coda_devtype *devtype;
  103. void __iomem *regs_base;
  104. struct clk *clk_per;
  105. struct clk *clk_ahb;
  106. struct coda_aux_buf codebuf;
  107. struct coda_aux_buf workbuf;
  108. long unsigned int iram_paddr;
  109. spinlock_t irqlock;
  110. struct mutex dev_mutex;
  111. struct v4l2_m2m_dev *m2m_dev;
  112. struct vb2_alloc_ctx *alloc_ctx;
  113. struct list_head instances;
  114. unsigned long instance_mask;
  115. struct delayed_work timeout;
  116. struct completion done;
  117. };
  118. struct coda_params {
  119. u8 rot_mode;
  120. u8 h264_intra_qp;
  121. u8 h264_inter_qp;
  122. u8 mpeg4_intra_qp;
  123. u8 mpeg4_inter_qp;
  124. u8 gop_size;
  125. int codec_mode;
  126. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  127. u32 framerate;
  128. u16 bitrate;
  129. u32 slice_max_bits;
  130. u32 slice_max_mb;
  131. };
  132. struct coda_ctx {
  133. struct coda_dev *dev;
  134. struct list_head list;
  135. int aborting;
  136. int rawstreamon;
  137. int compstreamon;
  138. u32 isequence;
  139. struct coda_q_data q_data[2];
  140. enum coda_inst_type inst_type;
  141. enum v4l2_colorspace colorspace;
  142. struct coda_params params;
  143. struct v4l2_m2m_ctx *m2m_ctx;
  144. struct v4l2_ctrl_handler ctrls;
  145. struct v4l2_fh fh;
  146. int gopcounter;
  147. char vpu_header[3][64];
  148. int vpu_header_size[3];
  149. struct coda_aux_buf parabuf;
  150. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  151. int num_internal_frames;
  152. int idx;
  153. };
  154. static const u8 coda_filler_nal[14] = { 0x00, 0x00, 0x00, 0x01, 0x0c, 0xff,
  155. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80 };
  156. static const u8 coda_filler_size[8] = { 0, 7, 14, 13, 12, 11, 10, 9 };
  157. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  158. {
  159. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  160. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  161. writel(data, dev->regs_base + reg);
  162. }
  163. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  164. {
  165. u32 data;
  166. data = readl(dev->regs_base + reg);
  167. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  168. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  169. return data;
  170. }
  171. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  172. {
  173. return coda_read(dev, CODA_REG_BIT_BUSY);
  174. }
  175. static inline int coda_is_initialized(struct coda_dev *dev)
  176. {
  177. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  178. }
  179. static int coda_wait_timeout(struct coda_dev *dev)
  180. {
  181. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  182. while (coda_isbusy(dev)) {
  183. if (time_after(jiffies, timeout))
  184. return -ETIMEDOUT;
  185. }
  186. return 0;
  187. }
  188. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  189. {
  190. struct coda_dev *dev = ctx->dev;
  191. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  192. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  193. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  194. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  195. }
  196. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  197. {
  198. struct coda_dev *dev = ctx->dev;
  199. coda_command_async(ctx, cmd);
  200. return coda_wait_timeout(dev);
  201. }
  202. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  203. enum v4l2_buf_type type)
  204. {
  205. switch (type) {
  206. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  207. return &(ctx->q_data[V4L2_M2M_SRC]);
  208. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  209. return &(ctx->q_data[V4L2_M2M_DST]);
  210. default:
  211. BUG();
  212. }
  213. return NULL;
  214. }
  215. /*
  216. * Add one array of supported formats for each version of Coda:
  217. * i.MX27 -> codadx6
  218. * i.MX51 -> coda7
  219. * i.MX6 -> coda960
  220. */
  221. static struct coda_fmt codadx6_formats[] = {
  222. {
  223. .name = "YUV 4:2:0 Planar",
  224. .fourcc = V4L2_PIX_FMT_YUV420,
  225. .type = CODA_FMT_RAW,
  226. },
  227. {
  228. .name = "H264 Encoded Stream",
  229. .fourcc = V4L2_PIX_FMT_H264,
  230. .type = CODA_FMT_ENC,
  231. },
  232. {
  233. .name = "MPEG4 Encoded Stream",
  234. .fourcc = V4L2_PIX_FMT_MPEG4,
  235. .type = CODA_FMT_ENC,
  236. },
  237. };
  238. static struct coda_fmt coda7_formats[] = {
  239. {
  240. .name = "YUV 4:2:0 Planar",
  241. .fourcc = V4L2_PIX_FMT_YUV420,
  242. .type = CODA_FMT_RAW,
  243. },
  244. {
  245. .name = "H264 Encoded Stream",
  246. .fourcc = V4L2_PIX_FMT_H264,
  247. .type = CODA_FMT_ENC,
  248. },
  249. {
  250. .name = "MPEG4 Encoded Stream",
  251. .fourcc = V4L2_PIX_FMT_MPEG4,
  252. .type = CODA_FMT_ENC,
  253. },
  254. };
  255. static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
  256. {
  257. struct coda_fmt *formats = dev->devtype->formats;
  258. int num_formats = dev->devtype->num_formats;
  259. unsigned int k;
  260. for (k = 0; k < num_formats; k++) {
  261. if (formats[k].fourcc == f->fmt.pix.pixelformat)
  262. break;
  263. }
  264. if (k == num_formats)
  265. return NULL;
  266. return &formats[k];
  267. }
  268. /*
  269. * V4L2 ioctl() operations.
  270. */
  271. static int vidioc_querycap(struct file *file, void *priv,
  272. struct v4l2_capability *cap)
  273. {
  274. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  275. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  276. strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
  277. /*
  278. * This is only a mem-to-mem video device. The capture and output
  279. * device capability flags are left only for backward compatibility
  280. * and are scheduled for removal.
  281. */
  282. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  283. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  284. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  285. return 0;
  286. }
  287. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  288. enum coda_fmt_type type)
  289. {
  290. struct coda_ctx *ctx = fh_to_ctx(priv);
  291. struct coda_dev *dev = ctx->dev;
  292. struct coda_fmt *formats = dev->devtype->formats;
  293. struct coda_fmt *fmt;
  294. int num_formats = dev->devtype->num_formats;
  295. int i, num = 0;
  296. for (i = 0; i < num_formats; i++) {
  297. if (formats[i].type == type) {
  298. if (num == f->index)
  299. break;
  300. ++num;
  301. }
  302. }
  303. if (i < num_formats) {
  304. fmt = &formats[i];
  305. strlcpy(f->description, fmt->name, sizeof(f->description));
  306. f->pixelformat = fmt->fourcc;
  307. return 0;
  308. }
  309. /* Format not found */
  310. return -EINVAL;
  311. }
  312. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  313. struct v4l2_fmtdesc *f)
  314. {
  315. return enum_fmt(priv, f, CODA_FMT_ENC);
  316. }
  317. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  318. struct v4l2_fmtdesc *f)
  319. {
  320. return enum_fmt(priv, f, CODA_FMT_RAW);
  321. }
  322. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  323. {
  324. struct vb2_queue *vq;
  325. struct coda_q_data *q_data;
  326. struct coda_ctx *ctx = fh_to_ctx(priv);
  327. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  328. if (!vq)
  329. return -EINVAL;
  330. q_data = get_q_data(ctx, f->type);
  331. f->fmt.pix.field = V4L2_FIELD_NONE;
  332. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  333. f->fmt.pix.width = q_data->width;
  334. f->fmt.pix.height = q_data->height;
  335. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  336. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  337. else /* encoded formats h.264/mpeg4 */
  338. f->fmt.pix.bytesperline = 0;
  339. f->fmt.pix.sizeimage = q_data->sizeimage;
  340. f->fmt.pix.colorspace = ctx->colorspace;
  341. return 0;
  342. }
  343. static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
  344. {
  345. enum v4l2_field field;
  346. field = f->fmt.pix.field;
  347. if (field == V4L2_FIELD_ANY)
  348. field = V4L2_FIELD_NONE;
  349. else if (V4L2_FIELD_NONE != field)
  350. return -EINVAL;
  351. /* V4L2 specification suggests the driver corrects the format struct
  352. * if any of the dimensions is unsupported */
  353. f->fmt.pix.field = field;
  354. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  355. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  356. W_ALIGN, &f->fmt.pix.height,
  357. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  358. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  359. f->fmt.pix.sizeimage = f->fmt.pix.width *
  360. f->fmt.pix.height * 3 / 2;
  361. } else { /*encoded formats h.264/mpeg4 */
  362. f->fmt.pix.bytesperline = 0;
  363. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  364. }
  365. return 0;
  366. }
  367. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  368. struct v4l2_format *f)
  369. {
  370. int ret;
  371. struct coda_fmt *fmt;
  372. struct coda_ctx *ctx = fh_to_ctx(priv);
  373. fmt = find_format(ctx->dev, f);
  374. /*
  375. * Since decoding support is not implemented yet do not allow
  376. * CODA_FMT_RAW formats in the capture interface.
  377. */
  378. if (!fmt || !(fmt->type == CODA_FMT_ENC))
  379. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  380. f->fmt.pix.colorspace = ctx->colorspace;
  381. ret = vidioc_try_fmt(ctx->dev, f);
  382. if (ret < 0)
  383. return ret;
  384. return 0;
  385. }
  386. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  387. struct v4l2_format *f)
  388. {
  389. struct coda_ctx *ctx = fh_to_ctx(priv);
  390. struct coda_fmt *fmt;
  391. int ret;
  392. fmt = find_format(ctx->dev, f);
  393. /*
  394. * Since decoding support is not implemented yet do not allow
  395. * CODA_FMT formats in the capture interface.
  396. */
  397. if (!fmt || !(fmt->type == CODA_FMT_RAW))
  398. f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
  399. if (!f->fmt.pix.colorspace)
  400. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  401. ret = vidioc_try_fmt(ctx->dev, f);
  402. if (ret < 0)
  403. return ret;
  404. return 0;
  405. }
  406. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  407. {
  408. struct coda_q_data *q_data;
  409. struct vb2_queue *vq;
  410. int ret;
  411. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  412. if (!vq)
  413. return -EINVAL;
  414. q_data = get_q_data(ctx, f->type);
  415. if (!q_data)
  416. return -EINVAL;
  417. if (vb2_is_busy(vq)) {
  418. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  419. return -EBUSY;
  420. }
  421. ret = vidioc_try_fmt(ctx->dev, f);
  422. if (ret)
  423. return ret;
  424. q_data->fmt = find_format(ctx->dev, f);
  425. q_data->width = f->fmt.pix.width;
  426. q_data->height = f->fmt.pix.height;
  427. q_data->sizeimage = f->fmt.pix.sizeimage;
  428. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  429. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  430. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  431. return 0;
  432. }
  433. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  434. struct v4l2_format *f)
  435. {
  436. int ret;
  437. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  438. if (ret)
  439. return ret;
  440. return vidioc_s_fmt(fh_to_ctx(priv), f);
  441. }
  442. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  443. struct v4l2_format *f)
  444. {
  445. struct coda_ctx *ctx = fh_to_ctx(priv);
  446. int ret;
  447. ret = vidioc_try_fmt_vid_out(file, priv, f);
  448. if (ret)
  449. return ret;
  450. ret = vidioc_s_fmt(ctx, f);
  451. if (ret)
  452. ctx->colorspace = f->fmt.pix.colorspace;
  453. return ret;
  454. }
  455. static int vidioc_reqbufs(struct file *file, void *priv,
  456. struct v4l2_requestbuffers *reqbufs)
  457. {
  458. struct coda_ctx *ctx = fh_to_ctx(priv);
  459. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  460. }
  461. static int vidioc_querybuf(struct file *file, void *priv,
  462. struct v4l2_buffer *buf)
  463. {
  464. struct coda_ctx *ctx = fh_to_ctx(priv);
  465. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  466. }
  467. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  468. {
  469. struct coda_ctx *ctx = fh_to_ctx(priv);
  470. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  471. }
  472. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  473. {
  474. struct coda_ctx *ctx = fh_to_ctx(priv);
  475. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  476. }
  477. static int vidioc_streamon(struct file *file, void *priv,
  478. enum v4l2_buf_type type)
  479. {
  480. struct coda_ctx *ctx = fh_to_ctx(priv);
  481. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  482. }
  483. static int vidioc_streamoff(struct file *file, void *priv,
  484. enum v4l2_buf_type type)
  485. {
  486. struct coda_ctx *ctx = fh_to_ctx(priv);
  487. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  488. }
  489. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  490. .vidioc_querycap = vidioc_querycap,
  491. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  492. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  493. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  494. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  495. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  496. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  497. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  498. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  499. .vidioc_reqbufs = vidioc_reqbufs,
  500. .vidioc_querybuf = vidioc_querybuf,
  501. .vidioc_qbuf = vidioc_qbuf,
  502. .vidioc_dqbuf = vidioc_dqbuf,
  503. .vidioc_streamon = vidioc_streamon,
  504. .vidioc_streamoff = vidioc_streamoff,
  505. };
  506. /*
  507. * Mem-to-mem operations.
  508. */
  509. static void coda_device_run(void *m2m_priv)
  510. {
  511. struct coda_ctx *ctx = m2m_priv;
  512. struct coda_q_data *q_data_src, *q_data_dst;
  513. struct vb2_buffer *src_buf, *dst_buf;
  514. struct coda_dev *dev = ctx->dev;
  515. int force_ipicture;
  516. int quant_param = 0;
  517. u32 picture_y, picture_cb, picture_cr;
  518. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  519. u32 dst_fourcc;
  520. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  521. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  522. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  523. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  524. dst_fourcc = q_data_dst->fmt->fourcc;
  525. src_buf->v4l2_buf.sequence = ctx->isequence;
  526. dst_buf->v4l2_buf.sequence = ctx->isequence;
  527. ctx->isequence++;
  528. /*
  529. * Workaround coda firmware BUG that only marks the first
  530. * frame as IDR. This is a problem for some decoders that can't
  531. * recover when a frame is lost.
  532. */
  533. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  534. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  535. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  536. } else {
  537. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  538. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  539. }
  540. /*
  541. * Copy headers at the beginning of the first frame for H.264 only.
  542. * In MPEG4 they are already copied by the coda.
  543. */
  544. if (src_buf->v4l2_buf.sequence == 0) {
  545. pic_stream_buffer_addr =
  546. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  547. ctx->vpu_header_size[0] +
  548. ctx->vpu_header_size[1] +
  549. ctx->vpu_header_size[2];
  550. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  551. ctx->vpu_header_size[0] -
  552. ctx->vpu_header_size[1] -
  553. ctx->vpu_header_size[2];
  554. memcpy(vb2_plane_vaddr(dst_buf, 0),
  555. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  556. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  557. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  558. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  559. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  560. ctx->vpu_header_size[2]);
  561. } else {
  562. pic_stream_buffer_addr =
  563. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  564. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  565. }
  566. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  567. force_ipicture = 1;
  568. switch (dst_fourcc) {
  569. case V4L2_PIX_FMT_H264:
  570. quant_param = ctx->params.h264_intra_qp;
  571. break;
  572. case V4L2_PIX_FMT_MPEG4:
  573. quant_param = ctx->params.mpeg4_intra_qp;
  574. break;
  575. default:
  576. v4l2_warn(&ctx->dev->v4l2_dev,
  577. "cannot set intra qp, fmt not supported\n");
  578. break;
  579. }
  580. } else {
  581. force_ipicture = 0;
  582. switch (dst_fourcc) {
  583. case V4L2_PIX_FMT_H264:
  584. quant_param = ctx->params.h264_inter_qp;
  585. break;
  586. case V4L2_PIX_FMT_MPEG4:
  587. quant_param = ctx->params.mpeg4_inter_qp;
  588. break;
  589. default:
  590. v4l2_warn(&ctx->dev->v4l2_dev,
  591. "cannot set inter qp, fmt not supported\n");
  592. break;
  593. }
  594. }
  595. /* submit */
  596. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  597. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  598. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  599. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  600. picture_cr = picture_cb + q_data_src->width / 2 *
  601. q_data_src->height / 2;
  602. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  603. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  604. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  605. coda_write(dev, force_ipicture << 1 & 0x2,
  606. CODA_CMD_ENC_PIC_OPTION);
  607. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  608. coda_write(dev, pic_stream_buffer_size / 1024,
  609. CODA_CMD_ENC_PIC_BB_SIZE);
  610. if (dev->devtype->product == CODA_7541) {
  611. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  612. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  613. CODA7_REG_BIT_AXI_SRAM_USE);
  614. }
  615. /* 1 second timeout in case CODA locks up */
  616. schedule_delayed_work(&dev->timeout, HZ);
  617. INIT_COMPLETION(dev->done);
  618. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  619. }
  620. static int coda_job_ready(void *m2m_priv)
  621. {
  622. struct coda_ctx *ctx = m2m_priv;
  623. /*
  624. * For both 'P' and 'key' frame cases 1 picture
  625. * and 1 frame are needed.
  626. */
  627. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
  628. !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  629. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  630. "not ready: not enough video buffers.\n");
  631. return 0;
  632. }
  633. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  634. "job ready\n");
  635. return 1;
  636. }
  637. static void coda_job_abort(void *priv)
  638. {
  639. struct coda_ctx *ctx = priv;
  640. struct coda_dev *dev = ctx->dev;
  641. ctx->aborting = 1;
  642. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  643. "Aborting task\n");
  644. v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
  645. }
  646. static void coda_lock(void *m2m_priv)
  647. {
  648. struct coda_ctx *ctx = m2m_priv;
  649. struct coda_dev *pcdev = ctx->dev;
  650. mutex_lock(&pcdev->dev_mutex);
  651. }
  652. static void coda_unlock(void *m2m_priv)
  653. {
  654. struct coda_ctx *ctx = m2m_priv;
  655. struct coda_dev *pcdev = ctx->dev;
  656. mutex_unlock(&pcdev->dev_mutex);
  657. }
  658. static struct v4l2_m2m_ops coda_m2m_ops = {
  659. .device_run = coda_device_run,
  660. .job_ready = coda_job_ready,
  661. .job_abort = coda_job_abort,
  662. .lock = coda_lock,
  663. .unlock = coda_unlock,
  664. };
  665. static void set_default_params(struct coda_ctx *ctx)
  666. {
  667. struct coda_dev *dev = ctx->dev;
  668. ctx->params.codec_mode = CODA_MODE_INVALID;
  669. ctx->colorspace = V4L2_COLORSPACE_REC709;
  670. ctx->params.framerate = 30;
  671. ctx->aborting = 0;
  672. /* Default formats for output and input queues */
  673. ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
  674. ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
  675. ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
  676. ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
  677. ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
  678. ctx->q_data[V4L2_M2M_DST].width = MAX_W;
  679. ctx->q_data[V4L2_M2M_DST].height = MAX_H;
  680. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  681. }
  682. /*
  683. * Queue operations
  684. */
  685. static int coda_queue_setup(struct vb2_queue *vq,
  686. const struct v4l2_format *fmt,
  687. unsigned int *nbuffers, unsigned int *nplanes,
  688. unsigned int sizes[], void *alloc_ctxs[])
  689. {
  690. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  691. struct coda_q_data *q_data;
  692. unsigned int size;
  693. q_data = get_q_data(ctx, vq->type);
  694. size = q_data->sizeimage;
  695. *nplanes = 1;
  696. sizes[0] = size;
  697. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  698. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  699. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  700. return 0;
  701. }
  702. static int coda_buf_prepare(struct vb2_buffer *vb)
  703. {
  704. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  705. struct coda_q_data *q_data;
  706. q_data = get_q_data(ctx, vb->vb2_queue->type);
  707. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  708. v4l2_warn(&ctx->dev->v4l2_dev,
  709. "%s data will not fit into plane (%lu < %lu)\n",
  710. __func__, vb2_plane_size(vb, 0),
  711. (long)q_data->sizeimage);
  712. return -EINVAL;
  713. }
  714. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  715. return 0;
  716. }
  717. static void coda_buf_queue(struct vb2_buffer *vb)
  718. {
  719. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  720. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  721. }
  722. static void coda_wait_prepare(struct vb2_queue *q)
  723. {
  724. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  725. coda_unlock(ctx);
  726. }
  727. static void coda_wait_finish(struct vb2_queue *q)
  728. {
  729. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  730. coda_lock(ctx);
  731. }
  732. static void coda_free_framebuffers(struct coda_ctx *ctx)
  733. {
  734. int i;
  735. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
  736. if (ctx->internal_frames[i].vaddr) {
  737. dma_free_coherent(&ctx->dev->plat_dev->dev,
  738. ctx->internal_frames[i].size,
  739. ctx->internal_frames[i].vaddr,
  740. ctx->internal_frames[i].paddr);
  741. ctx->internal_frames[i].vaddr = NULL;
  742. }
  743. }
  744. }
  745. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  746. {
  747. struct coda_dev *dev = ctx->dev;
  748. int height = q_data->height;
  749. int width = q_data->width;
  750. u32 *p;
  751. int i;
  752. /* Allocate frame buffers */
  753. ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
  754. for (i = 0; i < ctx->num_internal_frames; i++) {
  755. ctx->internal_frames[i].size = q_data->sizeimage;
  756. if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
  757. ctx->internal_frames[i].size += width / 2 * height / 2;
  758. ctx->internal_frames[i].vaddr = dma_alloc_coherent(
  759. &dev->plat_dev->dev, ctx->internal_frames[i].size,
  760. &ctx->internal_frames[i].paddr, GFP_KERNEL);
  761. if (!ctx->internal_frames[i].vaddr) {
  762. coda_free_framebuffers(ctx);
  763. return -ENOMEM;
  764. }
  765. }
  766. /* Register frame buffers in the parameter buffer */
  767. p = ctx->parabuf.vaddr;
  768. if (dev->devtype->product == CODA_DX6) {
  769. for (i = 0; i < ctx->num_internal_frames; i++) {
  770. p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
  771. p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
  772. p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
  773. }
  774. } else {
  775. for (i = 0; i < ctx->num_internal_frames; i += 2) {
  776. p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
  777. p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
  778. p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
  779. if (fourcc == V4L2_PIX_FMT_H264)
  780. p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
  781. if (i + 1 < ctx->num_internal_frames) {
  782. p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
  783. p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
  784. p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
  785. if (fourcc == V4L2_PIX_FMT_H264)
  786. p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
  787. }
  788. }
  789. }
  790. return 0;
  791. }
  792. static int coda_h264_padding(int size, char *p)
  793. {
  794. int nal_size;
  795. int diff;
  796. diff = size - (size & ~0x7);
  797. if (diff == 0)
  798. return 0;
  799. nal_size = coda_filler_size[diff];
  800. memcpy(p, coda_filler_nal, nal_size);
  801. /* Add rbsp stop bit and trailing at the end */
  802. *(p + nal_size - 1) = 0x80;
  803. return nal_size;
  804. }
  805. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  806. {
  807. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  808. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  809. u32 bitstream_buf, bitstream_size;
  810. struct coda_dev *dev = ctx->dev;
  811. struct coda_q_data *q_data_src, *q_data_dst;
  812. struct vb2_buffer *buf;
  813. u32 dst_fourcc;
  814. u32 value;
  815. int ret;
  816. if (count < 1)
  817. return -EINVAL;
  818. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  819. ctx->rawstreamon = 1;
  820. else
  821. ctx->compstreamon = 1;
  822. /* Don't start the coda unless both queues are on */
  823. if (!(ctx->rawstreamon & ctx->compstreamon))
  824. return 0;
  825. if (coda_isbusy(dev))
  826. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0)
  827. return -EBUSY;
  828. ctx->gopcounter = ctx->params.gop_size - 1;
  829. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  830. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  831. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  832. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  833. bitstream_size = q_data_dst->sizeimage;
  834. dst_fourcc = q_data_dst->fmt->fourcc;
  835. /* Find out whether coda must encode or decode */
  836. if (q_data_src->fmt->type == CODA_FMT_RAW &&
  837. q_data_dst->fmt->type == CODA_FMT_ENC) {
  838. ctx->inst_type = CODA_INST_ENCODER;
  839. } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
  840. q_data_dst->fmt->type == CODA_FMT_RAW) {
  841. ctx->inst_type = CODA_INST_DECODER;
  842. v4l2_err(v4l2_dev, "decoding not supported.\n");
  843. return -EINVAL;
  844. } else {
  845. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  846. return -EINVAL;
  847. }
  848. if (!coda_is_initialized(dev)) {
  849. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  850. return -EFAULT;
  851. }
  852. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  853. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
  854. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
  855. switch (dev->devtype->product) {
  856. case CODA_DX6:
  857. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  858. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  859. break;
  860. default:
  861. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  862. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  863. }
  864. if (dev->devtype->product == CODA_DX6) {
  865. /* Configure the coda */
  866. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  867. }
  868. /* Could set rotation here if needed */
  869. switch (dev->devtype->product) {
  870. case CODA_DX6:
  871. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  872. break;
  873. default:
  874. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  875. }
  876. value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  877. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  878. coda_write(dev, ctx->params.framerate,
  879. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  880. switch (dst_fourcc) {
  881. case V4L2_PIX_FMT_MPEG4:
  882. if (dev->devtype->product == CODA_DX6)
  883. ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
  884. else
  885. ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
  886. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  887. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  888. break;
  889. case V4L2_PIX_FMT_H264:
  890. if (dev->devtype->product == CODA_DX6)
  891. ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
  892. else
  893. ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
  894. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  895. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  896. break;
  897. default:
  898. v4l2_err(v4l2_dev,
  899. "dst format (0x%08x) invalid.\n", dst_fourcc);
  900. return -EINVAL;
  901. }
  902. switch (ctx->params.slice_mode) {
  903. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  904. value = 0;
  905. break;
  906. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  907. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  908. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  909. value |= 1 & CODA_SLICING_MODE_MASK;
  910. break;
  911. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  912. value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  913. value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  914. value |= 1 & CODA_SLICING_MODE_MASK;
  915. break;
  916. }
  917. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  918. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  919. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  920. if (ctx->params.bitrate) {
  921. /* Rate control enabled */
  922. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  923. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  924. } else {
  925. value = 0;
  926. }
  927. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  928. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  929. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  930. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  931. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  932. /* set default gamma */
  933. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  934. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  935. value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
  936. value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
  937. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  938. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  939. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  940. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  941. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  942. if (dev->devtype->product == CODA_DX6) {
  943. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  944. } else {
  945. coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  946. coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  947. }
  948. }
  949. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  950. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  951. return -ETIMEDOUT;
  952. }
  953. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
  954. return -EFAULT;
  955. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  956. if (ret < 0)
  957. return ret;
  958. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  959. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  960. if (dev->devtype->product != CODA_DX6) {
  961. coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  962. coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  963. coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  964. coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  965. coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  966. coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  967. }
  968. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  969. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  970. return -ETIMEDOUT;
  971. }
  972. /* Save stream headers */
  973. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  974. switch (dst_fourcc) {
  975. case V4L2_PIX_FMT_H264:
  976. /*
  977. * Get SPS in the first frame and copy it to an
  978. * intermediate buffer.
  979. */
  980. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  981. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  982. coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
  983. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  984. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  985. return -ETIMEDOUT;
  986. }
  987. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  988. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  989. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  990. ctx->vpu_header_size[0]);
  991. /*
  992. * Get PPS in the first frame and copy it to an
  993. * intermediate buffer.
  994. */
  995. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  996. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  997. coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
  998. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  999. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1000. return -ETIMEDOUT;
  1001. }
  1002. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1003. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1004. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1005. ctx->vpu_header_size[1]);
  1006. /*
  1007. * Length of H.264 headers is variable and thus it might not be
  1008. * aligned for the coda to append the encoded frame. In that is
  1009. * the case a filler NAL must be added to header 2.
  1010. */
  1011. ctx->vpu_header_size[2] = coda_h264_padding(
  1012. (ctx->vpu_header_size[0] +
  1013. ctx->vpu_header_size[1]),
  1014. ctx->vpu_header[2]);
  1015. break;
  1016. case V4L2_PIX_FMT_MPEG4:
  1017. /*
  1018. * Get VOS in the first frame and copy it to an
  1019. * intermediate buffer
  1020. */
  1021. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1022. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1023. coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
  1024. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1025. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1026. return -ETIMEDOUT;
  1027. }
  1028. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1029. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1030. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1031. ctx->vpu_header_size[0]);
  1032. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1033. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1034. coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
  1035. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1036. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1037. return -ETIMEDOUT;
  1038. }
  1039. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1040. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1041. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1042. ctx->vpu_header_size[1]);
  1043. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1044. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1045. coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
  1046. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1047. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1048. return -ETIMEDOUT;
  1049. }
  1050. ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1051. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1052. memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
  1053. ctx->vpu_header_size[2]);
  1054. break;
  1055. default:
  1056. /* No more formats need to save headers at the moment */
  1057. break;
  1058. }
  1059. return 0;
  1060. }
  1061. static int coda_stop_streaming(struct vb2_queue *q)
  1062. {
  1063. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1064. struct coda_dev *dev = ctx->dev;
  1065. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1066. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1067. "%s: output\n", __func__);
  1068. ctx->rawstreamon = 0;
  1069. } else {
  1070. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1071. "%s: capture\n", __func__);
  1072. ctx->compstreamon = 0;
  1073. }
  1074. /* Don't stop the coda unless both queues are off */
  1075. if (ctx->rawstreamon || ctx->compstreamon)
  1076. return 0;
  1077. if (coda_isbusy(dev)) {
  1078. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0) {
  1079. v4l2_warn(&dev->v4l2_dev,
  1080. "%s: timeout, sending SEQ_END anyway\n", __func__);
  1081. }
  1082. }
  1083. cancel_delayed_work(&dev->timeout);
  1084. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1085. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1086. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1087. v4l2_err(&dev->v4l2_dev,
  1088. "CODA_COMMAND_SEQ_END failed\n");
  1089. return -ETIMEDOUT;
  1090. }
  1091. coda_free_framebuffers(ctx);
  1092. return 0;
  1093. }
  1094. static struct vb2_ops coda_qops = {
  1095. .queue_setup = coda_queue_setup,
  1096. .buf_prepare = coda_buf_prepare,
  1097. .buf_queue = coda_buf_queue,
  1098. .wait_prepare = coda_wait_prepare,
  1099. .wait_finish = coda_wait_finish,
  1100. .start_streaming = coda_start_streaming,
  1101. .stop_streaming = coda_stop_streaming,
  1102. };
  1103. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1104. {
  1105. struct coda_ctx *ctx =
  1106. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1107. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1108. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1109. switch (ctrl->id) {
  1110. case V4L2_CID_HFLIP:
  1111. if (ctrl->val)
  1112. ctx->params.rot_mode |= CODA_MIR_HOR;
  1113. else
  1114. ctx->params.rot_mode &= ~CODA_MIR_HOR;
  1115. break;
  1116. case V4L2_CID_VFLIP:
  1117. if (ctrl->val)
  1118. ctx->params.rot_mode |= CODA_MIR_VER;
  1119. else
  1120. ctx->params.rot_mode &= ~CODA_MIR_VER;
  1121. break;
  1122. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1123. ctx->params.bitrate = ctrl->val / 1000;
  1124. break;
  1125. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1126. ctx->params.gop_size = ctrl->val;
  1127. break;
  1128. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1129. ctx->params.h264_intra_qp = ctrl->val;
  1130. break;
  1131. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1132. ctx->params.h264_inter_qp = ctrl->val;
  1133. break;
  1134. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1135. ctx->params.mpeg4_intra_qp = ctrl->val;
  1136. break;
  1137. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1138. ctx->params.mpeg4_inter_qp = ctrl->val;
  1139. break;
  1140. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1141. ctx->params.slice_mode = ctrl->val;
  1142. break;
  1143. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1144. ctx->params.slice_max_mb = ctrl->val;
  1145. break;
  1146. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
  1147. ctx->params.slice_max_bits = ctrl->val * 8;
  1148. break;
  1149. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1150. break;
  1151. default:
  1152. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1153. "Invalid control, id=%d, val=%d\n",
  1154. ctrl->id, ctrl->val);
  1155. return -EINVAL;
  1156. }
  1157. return 0;
  1158. }
  1159. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1160. .s_ctrl = coda_s_ctrl,
  1161. };
  1162. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1163. {
  1164. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1165. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1166. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1167. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1168. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1169. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1170. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1171. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1172. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1173. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1174. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1175. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1176. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1177. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1178. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1179. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1180. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1181. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1182. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1183. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
  1184. V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
  1185. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1186. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1187. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1188. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
  1189. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1190. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1191. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1192. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1193. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1194. if (ctx->ctrls.error) {
  1195. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1196. ctx->ctrls.error);
  1197. return -EINVAL;
  1198. }
  1199. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1200. }
  1201. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1202. struct vb2_queue *dst_vq)
  1203. {
  1204. struct coda_ctx *ctx = priv;
  1205. int ret;
  1206. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1207. src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1208. src_vq->drv_priv = ctx;
  1209. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1210. src_vq->ops = &coda_qops;
  1211. src_vq->mem_ops = &vb2_dma_contig_memops;
  1212. ret = vb2_queue_init(src_vq);
  1213. if (ret)
  1214. return ret;
  1215. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1216. dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1217. dst_vq->drv_priv = ctx;
  1218. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1219. dst_vq->ops = &coda_qops;
  1220. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1221. return vb2_queue_init(dst_vq);
  1222. }
  1223. static int coda_next_free_instance(struct coda_dev *dev)
  1224. {
  1225. return ffz(dev->instance_mask);
  1226. }
  1227. static int coda_open(struct file *file)
  1228. {
  1229. struct coda_dev *dev = video_drvdata(file);
  1230. struct coda_ctx *ctx = NULL;
  1231. int ret = 0;
  1232. int idx;
  1233. idx = coda_next_free_instance(dev);
  1234. if (idx >= CODA_MAX_INSTANCES)
  1235. return -EBUSY;
  1236. set_bit(idx, &dev->instance_mask);
  1237. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1238. if (!ctx)
  1239. return -ENOMEM;
  1240. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1241. file->private_data = &ctx->fh;
  1242. v4l2_fh_add(&ctx->fh);
  1243. ctx->dev = dev;
  1244. ctx->idx = idx;
  1245. set_default_params(ctx);
  1246. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1247. &coda_queue_init);
  1248. if (IS_ERR(ctx->m2m_ctx)) {
  1249. int ret = PTR_ERR(ctx->m2m_ctx);
  1250. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1251. __func__, ret);
  1252. goto err;
  1253. }
  1254. ret = coda_ctrls_setup(ctx);
  1255. if (ret) {
  1256. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1257. goto err;
  1258. }
  1259. ctx->fh.ctrl_handler = &ctx->ctrls;
  1260. ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
  1261. CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
  1262. if (!ctx->parabuf.vaddr) {
  1263. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1264. ret = -ENOMEM;
  1265. goto err;
  1266. }
  1267. coda_lock(ctx);
  1268. list_add(&ctx->list, &dev->instances);
  1269. coda_unlock(ctx);
  1270. clk_prepare_enable(dev->clk_per);
  1271. clk_prepare_enable(dev->clk_ahb);
  1272. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1273. ctx->idx, ctx);
  1274. return 0;
  1275. err:
  1276. v4l2_fh_del(&ctx->fh);
  1277. v4l2_fh_exit(&ctx->fh);
  1278. kfree(ctx);
  1279. return ret;
  1280. }
  1281. static int coda_release(struct file *file)
  1282. {
  1283. struct coda_dev *dev = video_drvdata(file);
  1284. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1285. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1286. ctx);
  1287. coda_lock(ctx);
  1288. list_del(&ctx->list);
  1289. coda_unlock(ctx);
  1290. dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
  1291. ctx->parabuf.vaddr, ctx->parabuf.paddr);
  1292. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1293. v4l2_ctrl_handler_free(&ctx->ctrls);
  1294. clk_disable_unprepare(dev->clk_per);
  1295. clk_disable_unprepare(dev->clk_ahb);
  1296. v4l2_fh_del(&ctx->fh);
  1297. v4l2_fh_exit(&ctx->fh);
  1298. clear_bit(ctx->idx, &dev->instance_mask);
  1299. kfree(ctx);
  1300. return 0;
  1301. }
  1302. static unsigned int coda_poll(struct file *file,
  1303. struct poll_table_struct *wait)
  1304. {
  1305. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1306. int ret;
  1307. coda_lock(ctx);
  1308. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1309. coda_unlock(ctx);
  1310. return ret;
  1311. }
  1312. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1313. {
  1314. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1315. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1316. }
  1317. static const struct v4l2_file_operations coda_fops = {
  1318. .owner = THIS_MODULE,
  1319. .open = coda_open,
  1320. .release = coda_release,
  1321. .poll = coda_poll,
  1322. .unlocked_ioctl = video_ioctl2,
  1323. .mmap = coda_mmap,
  1324. };
  1325. static irqreturn_t coda_irq_handler(int irq, void *data)
  1326. {
  1327. struct vb2_buffer *src_buf, *dst_buf;
  1328. struct coda_dev *dev = data;
  1329. u32 wr_ptr, start_ptr;
  1330. struct coda_ctx *ctx;
  1331. cancel_delayed_work(&dev->timeout);
  1332. /* read status register to attend the IRQ */
  1333. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1334. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1335. CODA_REG_BIT_INT_CLEAR);
  1336. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1337. if (ctx == NULL) {
  1338. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1339. return IRQ_HANDLED;
  1340. }
  1341. if (ctx->aborting) {
  1342. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1343. "task has been aborted\n");
  1344. return IRQ_HANDLED;
  1345. }
  1346. if (coda_isbusy(ctx->dev)) {
  1347. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1348. "coda is still busy!!!!\n");
  1349. return IRQ_NONE;
  1350. }
  1351. complete(&dev->done);
  1352. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1353. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1354. /* Get results from the coda */
  1355. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1356. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1357. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
  1358. /* Calculate bytesused field */
  1359. if (dst_buf->v4l2_buf.sequence == 0) {
  1360. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
  1361. ctx->vpu_header_size[0] +
  1362. ctx->vpu_header_size[1] +
  1363. ctx->vpu_header_size[2];
  1364. } else {
  1365. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
  1366. }
  1367. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1368. wr_ptr - start_ptr);
  1369. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1370. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1371. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1372. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1373. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1374. } else {
  1375. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1376. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1377. }
  1378. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1379. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1380. ctx->gopcounter--;
  1381. if (ctx->gopcounter < 0)
  1382. ctx->gopcounter = ctx->params.gop_size - 1;
  1383. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1384. "job finished: encoding frame (%d) (%s)\n",
  1385. dst_buf->v4l2_buf.sequence,
  1386. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1387. "KEYFRAME" : "PFRAME");
  1388. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1389. return IRQ_HANDLED;
  1390. }
  1391. static void coda_timeout(struct work_struct *work)
  1392. {
  1393. struct coda_ctx *ctx;
  1394. struct coda_dev *dev = container_of(to_delayed_work(work),
  1395. struct coda_dev, timeout);
  1396. if (completion_done(&dev->done))
  1397. return;
  1398. complete(&dev->done);
  1399. v4l2_err(&dev->v4l2_dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1400. mutex_lock(&dev->dev_mutex);
  1401. list_for_each_entry(ctx, &dev->instances, list) {
  1402. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1403. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1404. }
  1405. mutex_unlock(&dev->dev_mutex);
  1406. }
  1407. static u32 coda_supported_firmwares[] = {
  1408. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1409. CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
  1410. };
  1411. static bool coda_firmware_supported(u32 vernum)
  1412. {
  1413. int i;
  1414. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1415. if (vernum == coda_supported_firmwares[i])
  1416. return true;
  1417. return false;
  1418. }
  1419. static char *coda_product_name(int product)
  1420. {
  1421. static char buf[9];
  1422. switch (product) {
  1423. case CODA_DX6:
  1424. return "CodaDx6";
  1425. case CODA_7541:
  1426. return "CODA7541";
  1427. default:
  1428. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1429. return buf;
  1430. }
  1431. }
  1432. static int coda_hw_init(struct coda_dev *dev)
  1433. {
  1434. u16 product, major, minor, release;
  1435. u32 data;
  1436. u16 *p;
  1437. int i;
  1438. clk_prepare_enable(dev->clk_per);
  1439. clk_prepare_enable(dev->clk_ahb);
  1440. /*
  1441. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1442. * The 16-bit chars in the code buffer are in memory access
  1443. * order, re-sort them to CODA order for register download.
  1444. * Data in this SRAM survives a reboot.
  1445. */
  1446. p = (u16 *)dev->codebuf.vaddr;
  1447. if (dev->devtype->product == CODA_DX6) {
  1448. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1449. data = CODA_DOWN_ADDRESS_SET(i) |
  1450. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1451. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1452. }
  1453. } else {
  1454. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1455. data = CODA_DOWN_ADDRESS_SET(i) |
  1456. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1457. 3 - (i % 4)]);
  1458. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1459. }
  1460. }
  1461. /* Tell the BIT where to find everything it needs */
  1462. coda_write(dev, dev->workbuf.paddr,
  1463. CODA_REG_BIT_WORK_BUF_ADDR);
  1464. coda_write(dev, dev->codebuf.paddr,
  1465. CODA_REG_BIT_CODE_BUF_ADDR);
  1466. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1467. /* Set default values */
  1468. switch (dev->devtype->product) {
  1469. case CODA_DX6:
  1470. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1471. break;
  1472. default:
  1473. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1474. }
  1475. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1476. if (dev->devtype->product != CODA_DX6)
  1477. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1478. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1479. CODA_REG_BIT_INT_ENABLE);
  1480. /* Reset VPU and start processor */
  1481. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1482. data |= CODA_REG_RESET_ENABLE;
  1483. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1484. udelay(10);
  1485. data &= ~CODA_REG_RESET_ENABLE;
  1486. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1487. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1488. /* Load firmware */
  1489. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1490. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1491. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1492. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1493. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1494. if (coda_wait_timeout(dev)) {
  1495. clk_disable_unprepare(dev->clk_per);
  1496. clk_disable_unprepare(dev->clk_ahb);
  1497. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1498. return -EIO;
  1499. }
  1500. /* Check we are compatible with the loaded firmware */
  1501. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1502. product = CODA_FIRMWARE_PRODUCT(data);
  1503. major = CODA_FIRMWARE_MAJOR(data);
  1504. minor = CODA_FIRMWARE_MINOR(data);
  1505. release = CODA_FIRMWARE_RELEASE(data);
  1506. clk_disable_unprepare(dev->clk_per);
  1507. clk_disable_unprepare(dev->clk_ahb);
  1508. if (product != dev->devtype->product) {
  1509. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1510. " Version: %u.%u.%u\n",
  1511. coda_product_name(dev->devtype->product),
  1512. coda_product_name(product), major, minor, release);
  1513. return -EINVAL;
  1514. }
  1515. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1516. coda_product_name(product));
  1517. if (coda_firmware_supported(data)) {
  1518. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1519. major, minor, release);
  1520. } else {
  1521. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1522. "%u.%u.%u\n", major, minor, release);
  1523. }
  1524. return 0;
  1525. }
  1526. static void coda_fw_callback(const struct firmware *fw, void *context)
  1527. {
  1528. struct coda_dev *dev = context;
  1529. struct platform_device *pdev = dev->plat_dev;
  1530. int ret;
  1531. if (!fw) {
  1532. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1533. return;
  1534. }
  1535. /* allocate auxiliary per-device code buffer for the BIT processor */
  1536. dev->codebuf.size = fw->size;
  1537. dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
  1538. &dev->codebuf.paddr,
  1539. GFP_KERNEL);
  1540. if (!dev->codebuf.vaddr) {
  1541. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1542. return;
  1543. }
  1544. /* Copy the whole firmware image to the code buffer */
  1545. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1546. release_firmware(fw);
  1547. ret = coda_hw_init(dev);
  1548. if (ret) {
  1549. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1550. return;
  1551. }
  1552. dev->vfd.fops = &coda_fops,
  1553. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1554. dev->vfd.release = video_device_release_empty,
  1555. dev->vfd.lock = &dev->dev_mutex;
  1556. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1557. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1558. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1559. video_set_drvdata(&dev->vfd, dev);
  1560. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1561. if (IS_ERR(dev->alloc_ctx)) {
  1562. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1563. return;
  1564. }
  1565. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1566. if (IS_ERR(dev->m2m_dev)) {
  1567. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1568. goto rel_ctx;
  1569. }
  1570. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1571. if (ret) {
  1572. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1573. goto rel_m2m;
  1574. }
  1575. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1576. dev->vfd.num);
  1577. return;
  1578. rel_m2m:
  1579. v4l2_m2m_release(dev->m2m_dev);
  1580. rel_ctx:
  1581. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1582. }
  1583. static int coda_firmware_request(struct coda_dev *dev)
  1584. {
  1585. char *fw = dev->devtype->firmware;
  1586. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1587. coda_product_name(dev->devtype->product));
  1588. return request_firmware_nowait(THIS_MODULE, true,
  1589. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1590. }
  1591. enum coda_platform {
  1592. CODA_IMX27,
  1593. CODA_IMX53,
  1594. };
  1595. static const struct coda_devtype coda_devdata[] = {
  1596. [CODA_IMX27] = {
  1597. .firmware = "v4l-codadx6-imx27.bin",
  1598. .product = CODA_DX6,
  1599. .formats = codadx6_formats,
  1600. .num_formats = ARRAY_SIZE(codadx6_formats),
  1601. },
  1602. [CODA_IMX53] = {
  1603. .firmware = "v4l-coda7541-imx53.bin",
  1604. .product = CODA_7541,
  1605. .formats = coda7_formats,
  1606. .num_formats = ARRAY_SIZE(coda7_formats),
  1607. },
  1608. };
  1609. static struct platform_device_id coda_platform_ids[] = {
  1610. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  1611. { .name = "coda-imx53", .driver_data = CODA_IMX53 },
  1612. { /* sentinel */ }
  1613. };
  1614. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  1615. #ifdef CONFIG_OF
  1616. static const struct of_device_id coda_dt_ids[] = {
  1617. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  1618. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  1619. { /* sentinel */ }
  1620. };
  1621. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  1622. #endif
  1623. static int coda_probe(struct platform_device *pdev)
  1624. {
  1625. const struct of_device_id *of_id =
  1626. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  1627. const struct platform_device_id *pdev_id;
  1628. struct coda_dev *dev;
  1629. struct resource *res;
  1630. int ret, irq;
  1631. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  1632. if (!dev) {
  1633. dev_err(&pdev->dev, "Not enough memory for %s\n",
  1634. CODA_NAME);
  1635. return -ENOMEM;
  1636. }
  1637. spin_lock_init(&dev->irqlock);
  1638. INIT_LIST_HEAD(&dev->instances);
  1639. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  1640. init_completion(&dev->done);
  1641. complete(&dev->done);
  1642. dev->plat_dev = pdev;
  1643. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  1644. if (IS_ERR(dev->clk_per)) {
  1645. dev_err(&pdev->dev, "Could not get per clock\n");
  1646. return PTR_ERR(dev->clk_per);
  1647. }
  1648. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1649. if (IS_ERR(dev->clk_ahb)) {
  1650. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1651. return PTR_ERR(dev->clk_ahb);
  1652. }
  1653. /* Get memory for physical registers */
  1654. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1655. if (res == NULL) {
  1656. dev_err(&pdev->dev, "failed to get memory region resource\n");
  1657. return -ENOENT;
  1658. }
  1659. if (devm_request_mem_region(&pdev->dev, res->start,
  1660. resource_size(res), CODA_NAME) == NULL) {
  1661. dev_err(&pdev->dev, "failed to request memory region\n");
  1662. return -ENOENT;
  1663. }
  1664. dev->regs_base = devm_ioremap(&pdev->dev, res->start,
  1665. resource_size(res));
  1666. if (!dev->regs_base) {
  1667. dev_err(&pdev->dev, "failed to ioremap address region\n");
  1668. return -ENOENT;
  1669. }
  1670. /* IRQ */
  1671. irq = platform_get_irq(pdev, 0);
  1672. if (irq < 0) {
  1673. dev_err(&pdev->dev, "failed to get irq resource\n");
  1674. return -ENOENT;
  1675. }
  1676. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  1677. 0, CODA_NAME, dev) < 0) {
  1678. dev_err(&pdev->dev, "failed to request irq\n");
  1679. return -ENOENT;
  1680. }
  1681. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1682. if (ret)
  1683. return ret;
  1684. mutex_init(&dev->dev_mutex);
  1685. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  1686. if (of_id) {
  1687. dev->devtype = of_id->data;
  1688. } else if (pdev_id) {
  1689. dev->devtype = &coda_devdata[pdev_id->driver_data];
  1690. } else {
  1691. v4l2_device_unregister(&dev->v4l2_dev);
  1692. return -EINVAL;
  1693. }
  1694. /* allocate auxiliary per-device buffers for the BIT processor */
  1695. switch (dev->devtype->product) {
  1696. case CODA_DX6:
  1697. dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
  1698. break;
  1699. default:
  1700. dev->workbuf.size = CODA7_WORK_BUF_SIZE;
  1701. }
  1702. dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
  1703. &dev->workbuf.paddr,
  1704. GFP_KERNEL);
  1705. if (!dev->workbuf.vaddr) {
  1706. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  1707. v4l2_device_unregister(&dev->v4l2_dev);
  1708. return -ENOMEM;
  1709. }
  1710. if (dev->devtype->product == CODA_DX6) {
  1711. dev->iram_paddr = 0xffff4c00;
  1712. } else {
  1713. void __iomem *iram_vaddr;
  1714. iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
  1715. &dev->iram_paddr);
  1716. if (!iram_vaddr) {
  1717. dev_err(&pdev->dev, "unable to alloc iram\n");
  1718. return -ENOMEM;
  1719. }
  1720. }
  1721. platform_set_drvdata(pdev, dev);
  1722. return coda_firmware_request(dev);
  1723. }
  1724. static int coda_remove(struct platform_device *pdev)
  1725. {
  1726. struct coda_dev *dev = platform_get_drvdata(pdev);
  1727. video_unregister_device(&dev->vfd);
  1728. if (dev->m2m_dev)
  1729. v4l2_m2m_release(dev->m2m_dev);
  1730. if (dev->alloc_ctx)
  1731. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1732. v4l2_device_unregister(&dev->v4l2_dev);
  1733. if (dev->iram_paddr)
  1734. iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
  1735. if (dev->codebuf.vaddr)
  1736. dma_free_coherent(&pdev->dev, dev->codebuf.size,
  1737. &dev->codebuf.vaddr, dev->codebuf.paddr);
  1738. if (dev->workbuf.vaddr)
  1739. dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
  1740. dev->workbuf.paddr);
  1741. return 0;
  1742. }
  1743. static struct platform_driver coda_driver = {
  1744. .probe = coda_probe,
  1745. .remove = coda_remove,
  1746. .driver = {
  1747. .name = CODA_NAME,
  1748. .owner = THIS_MODULE,
  1749. .of_match_table = of_match_ptr(coda_dt_ids),
  1750. },
  1751. .id_table = coda_platform_ids,
  1752. };
  1753. module_platform_driver(coda_driver);
  1754. MODULE_LICENSE("GPL");
  1755. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  1756. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");