ddbridge-core.c 42 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729
  1. /*
  2. * ddbridge.c: Digital Devices PCIe bridge driver
  3. *
  4. * Copyright (C) 2010-2011 Digital Devices GmbH
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 only, as published by the Free Software Foundation.
  9. *
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20. * 02110-1301, USA
  21. * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include <linux/poll.h>
  29. #include <linux/io.h>
  30. #include <linux/pci.h>
  31. #include <linux/pci_ids.h>
  32. #include <linux/timer.h>
  33. #include <linux/i2c.h>
  34. #include <linux/swab.h>
  35. #include <linux/vmalloc.h>
  36. #include "ddbridge.h"
  37. #include "ddbridge-regs.h"
  38. #include "tda18271c2dd.h"
  39. #include "stv6110x.h"
  40. #include "stv090x.h"
  41. #include "lnbh24.h"
  42. #include "drxk.h"
  43. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  44. /* MSI had problems with lost interrupts, fixed but needs testing */
  45. #undef CONFIG_PCI_MSI
  46. /******************************************************************************/
  47. static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
  48. {
  49. struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
  50. .buf = val, .len = 1 } };
  51. return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
  52. }
  53. static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
  54. {
  55. struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
  56. .buf = &reg, .len = 1 },
  57. {.addr = adr, .flags = I2C_M_RD,
  58. .buf = val, .len = 1 } };
  59. return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
  60. }
  61. static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
  62. u16 reg, u8 *val)
  63. {
  64. u8 msg[2] = {reg>>8, reg&0xff};
  65. struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
  66. .buf = msg, .len = 2},
  67. {.addr = adr, .flags = I2C_M_RD,
  68. .buf = val, .len = 1} };
  69. return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
  70. }
  71. static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
  72. {
  73. struct ddb *dev = i2c->dev;
  74. int stat;
  75. u32 val;
  76. i2c->done = 0;
  77. ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
  78. stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
  79. if (stat <= 0) {
  80. printk(KERN_ERR "I2C timeout\n");
  81. { /* MSI debugging*/
  82. u32 istat = ddbreadl(INTERRUPT_STATUS);
  83. printk(KERN_ERR "IRS %08x\n", istat);
  84. ddbwritel(istat, INTERRUPT_ACK);
  85. }
  86. return -EIO;
  87. }
  88. val = ddbreadl(i2c->regs+I2C_COMMAND);
  89. if (val & 0x70000)
  90. return -EIO;
  91. return 0;
  92. }
  93. static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
  94. struct i2c_msg msg[], int num)
  95. {
  96. struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
  97. struct ddb *dev = i2c->dev;
  98. u8 addr = 0;
  99. if (num)
  100. addr = msg[0].addr;
  101. if (num == 2 && msg[1].flags & I2C_M_RD &&
  102. !(msg[0].flags & I2C_M_RD)) {
  103. memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
  104. msg[0].buf, msg[0].len);
  105. ddbwritel(msg[0].len|(msg[1].len << 16),
  106. i2c->regs+I2C_TASKLENGTH);
  107. if (!ddb_i2c_cmd(i2c, addr, 1)) {
  108. memcpy_fromio(msg[1].buf,
  109. dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
  110. msg[1].len);
  111. return num;
  112. }
  113. }
  114. if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
  115. ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
  116. ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
  117. if (!ddb_i2c_cmd(i2c, addr, 2))
  118. return num;
  119. }
  120. if (num == 1 && (msg[0].flags & I2C_M_RD)) {
  121. ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
  122. if (!ddb_i2c_cmd(i2c, addr, 3)) {
  123. ddbcpyfrom(msg[0].buf,
  124. I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
  125. return num;
  126. }
  127. }
  128. return -EIO;
  129. }
  130. static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
  131. {
  132. return I2C_FUNC_SMBUS_EMUL;
  133. }
  134. struct i2c_algorithm ddb_i2c_algo = {
  135. .master_xfer = ddb_i2c_master_xfer,
  136. .functionality = ddb_i2c_functionality,
  137. };
  138. static void ddb_i2c_release(struct ddb *dev)
  139. {
  140. int i;
  141. struct ddb_i2c *i2c;
  142. struct i2c_adapter *adap;
  143. for (i = 0; i < dev->info->port_num; i++) {
  144. i2c = &dev->i2c[i];
  145. adap = &i2c->adap;
  146. i2c_del_adapter(adap);
  147. }
  148. }
  149. static int ddb_i2c_init(struct ddb *dev)
  150. {
  151. int i, j, stat = 0;
  152. struct ddb_i2c *i2c;
  153. struct i2c_adapter *adap;
  154. for (i = 0; i < dev->info->port_num; i++) {
  155. i2c = &dev->i2c[i];
  156. i2c->dev = dev;
  157. i2c->nr = i;
  158. i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
  159. i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
  160. i2c->regs = 0x80 + i * 0x20;
  161. ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
  162. ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
  163. i2c->regs + I2C_TASKADDRESS);
  164. init_waitqueue_head(&i2c->wq);
  165. adap = &i2c->adap;
  166. i2c_set_adapdata(adap, i2c);
  167. #ifdef I2C_ADAP_CLASS_TV_DIGITAL
  168. adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
  169. #else
  170. #ifdef I2C_CLASS_TV_ANALOG
  171. adap->class = I2C_CLASS_TV_ANALOG;
  172. #endif
  173. #endif
  174. strcpy(adap->name, "ddbridge");
  175. adap->algo = &ddb_i2c_algo;
  176. adap->algo_data = (void *)i2c;
  177. adap->dev.parent = &dev->pdev->dev;
  178. stat = i2c_add_adapter(adap);
  179. if (stat)
  180. break;
  181. }
  182. if (stat)
  183. for (j = 0; j < i; j++) {
  184. i2c = &dev->i2c[j];
  185. adap = &i2c->adap;
  186. i2c_del_adapter(adap);
  187. }
  188. return stat;
  189. }
  190. /******************************************************************************/
  191. /******************************************************************************/
  192. /******************************************************************************/
  193. #if 0
  194. static void set_table(struct ddb *dev, u32 off,
  195. dma_addr_t *pbuf, u32 num)
  196. {
  197. u32 i, base;
  198. u64 mem;
  199. base = DMA_BASE_ADDRESS_TABLE + off;
  200. for (i = 0; i < num; i++) {
  201. mem = pbuf[i];
  202. ddbwritel(mem & 0xffffffff, base + i * 8);
  203. ddbwritel(mem >> 32, base + i * 8 + 4);
  204. }
  205. }
  206. #endif
  207. static void ddb_address_table(struct ddb *dev)
  208. {
  209. u32 i, j, base;
  210. u64 mem;
  211. dma_addr_t *pbuf;
  212. for (i = 0; i < dev->info->port_num * 2; i++) {
  213. base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
  214. pbuf = dev->input[i].pbuf;
  215. for (j = 0; j < dev->input[i].dma_buf_num; j++) {
  216. mem = pbuf[j];
  217. ddbwritel(mem & 0xffffffff, base + j * 8);
  218. ddbwritel(mem >> 32, base + j * 8 + 4);
  219. }
  220. }
  221. for (i = 0; i < dev->info->port_num; i++) {
  222. base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
  223. pbuf = dev->output[i].pbuf;
  224. for (j = 0; j < dev->output[i].dma_buf_num; j++) {
  225. mem = pbuf[j];
  226. ddbwritel(mem & 0xffffffff, base + j * 8);
  227. ddbwritel(mem >> 32, base + j * 8 + 4);
  228. }
  229. }
  230. }
  231. static void io_free(struct pci_dev *pdev, u8 **vbuf,
  232. dma_addr_t *pbuf, u32 size, int num)
  233. {
  234. int i;
  235. for (i = 0; i < num; i++) {
  236. if (vbuf[i]) {
  237. pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
  238. vbuf[i] = 0;
  239. }
  240. }
  241. }
  242. static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
  243. dma_addr_t *pbuf, u32 size, int num)
  244. {
  245. int i;
  246. for (i = 0; i < num; i++) {
  247. vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
  248. if (!vbuf[i])
  249. return -ENOMEM;
  250. }
  251. return 0;
  252. }
  253. static int ddb_buffers_alloc(struct ddb *dev)
  254. {
  255. int i;
  256. struct ddb_port *port;
  257. for (i = 0; i < dev->info->port_num; i++) {
  258. port = &dev->port[i];
  259. switch (port->class) {
  260. case DDB_PORT_TUNER:
  261. if (io_alloc(dev->pdev, port->input[0]->vbuf,
  262. port->input[0]->pbuf,
  263. port->input[0]->dma_buf_size,
  264. port->input[0]->dma_buf_num) < 0)
  265. return -1;
  266. if (io_alloc(dev->pdev, port->input[1]->vbuf,
  267. port->input[1]->pbuf,
  268. port->input[1]->dma_buf_size,
  269. port->input[1]->dma_buf_num) < 0)
  270. return -1;
  271. break;
  272. case DDB_PORT_CI:
  273. if (io_alloc(dev->pdev, port->input[0]->vbuf,
  274. port->input[0]->pbuf,
  275. port->input[0]->dma_buf_size,
  276. port->input[0]->dma_buf_num) < 0)
  277. return -1;
  278. if (io_alloc(dev->pdev, port->output->vbuf,
  279. port->output->pbuf,
  280. port->output->dma_buf_size,
  281. port->output->dma_buf_num) < 0)
  282. return -1;
  283. break;
  284. default:
  285. break;
  286. }
  287. }
  288. ddb_address_table(dev);
  289. return 0;
  290. }
  291. static void ddb_buffers_free(struct ddb *dev)
  292. {
  293. int i;
  294. struct ddb_port *port;
  295. for (i = 0; i < dev->info->port_num; i++) {
  296. port = &dev->port[i];
  297. io_free(dev->pdev, port->input[0]->vbuf,
  298. port->input[0]->pbuf,
  299. port->input[0]->dma_buf_size,
  300. port->input[0]->dma_buf_num);
  301. io_free(dev->pdev, port->input[1]->vbuf,
  302. port->input[1]->pbuf,
  303. port->input[1]->dma_buf_size,
  304. port->input[1]->dma_buf_num);
  305. io_free(dev->pdev, port->output->vbuf,
  306. port->output->pbuf,
  307. port->output->dma_buf_size,
  308. port->output->dma_buf_num);
  309. }
  310. }
  311. static void ddb_input_start(struct ddb_input *input)
  312. {
  313. struct ddb *dev = input->port->dev;
  314. spin_lock_irq(&input->lock);
  315. input->cbuf = 0;
  316. input->coff = 0;
  317. /* reset */
  318. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  319. ddbwritel(2, TS_INPUT_CONTROL(input->nr));
  320. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  321. ddbwritel((1 << 16) |
  322. (input->dma_buf_num << 11) |
  323. (input->dma_buf_size >> 7),
  324. DMA_BUFFER_SIZE(input->nr));
  325. ddbwritel(0, DMA_BUFFER_ACK(input->nr));
  326. ddbwritel(1, DMA_BASE_WRITE);
  327. ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
  328. ddbwritel(9, TS_INPUT_CONTROL(input->nr));
  329. input->running = 1;
  330. spin_unlock_irq(&input->lock);
  331. }
  332. static void ddb_input_stop(struct ddb_input *input)
  333. {
  334. struct ddb *dev = input->port->dev;
  335. spin_lock_irq(&input->lock);
  336. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  337. ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
  338. input->running = 0;
  339. spin_unlock_irq(&input->lock);
  340. }
  341. static void ddb_output_start(struct ddb_output *output)
  342. {
  343. struct ddb *dev = output->port->dev;
  344. spin_lock_irq(&output->lock);
  345. output->cbuf = 0;
  346. output->coff = 0;
  347. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  348. ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
  349. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  350. ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
  351. ddbwritel((1 << 16) |
  352. (output->dma_buf_num << 11) |
  353. (output->dma_buf_size >> 7),
  354. DMA_BUFFER_SIZE(output->nr + 8));
  355. ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
  356. ddbwritel(1, DMA_BASE_READ);
  357. ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
  358. /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
  359. ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
  360. output->running = 1;
  361. spin_unlock_irq(&output->lock);
  362. }
  363. static void ddb_output_stop(struct ddb_output *output)
  364. {
  365. struct ddb *dev = output->port->dev;
  366. spin_lock_irq(&output->lock);
  367. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  368. ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
  369. output->running = 0;
  370. spin_unlock_irq(&output->lock);
  371. }
  372. static u32 ddb_output_free(struct ddb_output *output)
  373. {
  374. u32 idx, off, stat = output->stat;
  375. s32 diff;
  376. idx = (stat >> 11) & 0x1f;
  377. off = (stat & 0x7ff) << 7;
  378. if (output->cbuf != idx) {
  379. if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
  380. (output->dma_buf_size - output->coff <= 188))
  381. return 0;
  382. return 188;
  383. }
  384. diff = off - output->coff;
  385. if (diff <= 0 || diff > 188)
  386. return 188;
  387. return 0;
  388. }
  389. static ssize_t ddb_output_write(struct ddb_output *output,
  390. const u8 *buf, size_t count)
  391. {
  392. struct ddb *dev = output->port->dev;
  393. u32 idx, off, stat = output->stat;
  394. u32 left = count, len;
  395. idx = (stat >> 11) & 0x1f;
  396. off = (stat & 0x7ff) << 7;
  397. while (left) {
  398. len = output->dma_buf_size - output->coff;
  399. if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
  400. (off == 0)) {
  401. if (len <= 188)
  402. break;
  403. len -= 188;
  404. }
  405. if (output->cbuf == idx) {
  406. if (off > output->coff) {
  407. #if 1
  408. len = off - output->coff;
  409. len -= (len % 188);
  410. if (len <= 188)
  411. #endif
  412. break;
  413. len -= 188;
  414. }
  415. }
  416. if (len > left)
  417. len = left;
  418. if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
  419. buf, len))
  420. return -EIO;
  421. left -= len;
  422. buf += len;
  423. output->coff += len;
  424. if (output->coff == output->dma_buf_size) {
  425. output->coff = 0;
  426. output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
  427. }
  428. ddbwritel((output->cbuf << 11) | (output->coff >> 7),
  429. DMA_BUFFER_ACK(output->nr + 8));
  430. }
  431. return count - left;
  432. }
  433. static u32 ddb_input_avail(struct ddb_input *input)
  434. {
  435. struct ddb *dev = input->port->dev;
  436. u32 idx, off, stat = input->stat;
  437. u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
  438. idx = (stat >> 11) & 0x1f;
  439. off = (stat & 0x7ff) << 7;
  440. if (ctrl & 4) {
  441. printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
  442. ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
  443. return 0;
  444. }
  445. if (input->cbuf != idx)
  446. return 188;
  447. return 0;
  448. }
  449. static ssize_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count)
  450. {
  451. struct ddb *dev = input->port->dev;
  452. u32 left = count;
  453. u32 idx, free, stat = input->stat;
  454. int ret;
  455. idx = (stat >> 11) & 0x1f;
  456. while (left) {
  457. if (input->cbuf == idx)
  458. return count - left;
  459. free = input->dma_buf_size - input->coff;
  460. if (free > left)
  461. free = left;
  462. ret = copy_to_user(buf, input->vbuf[input->cbuf] +
  463. input->coff, free);
  464. if (ret)
  465. return -EFAULT;
  466. input->coff += free;
  467. if (input->coff == input->dma_buf_size) {
  468. input->coff = 0;
  469. input->cbuf = (input->cbuf+1) % input->dma_buf_num;
  470. }
  471. left -= free;
  472. ddbwritel((input->cbuf << 11) | (input->coff >> 7),
  473. DMA_BUFFER_ACK(input->nr));
  474. }
  475. return count;
  476. }
  477. /******************************************************************************/
  478. /******************************************************************************/
  479. /******************************************************************************/
  480. #if 0
  481. static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
  482. {
  483. int i;
  484. for (i = 0; i < dev->info->port_num * 2; i++) {
  485. if (dev->input[i].fe == fe)
  486. return &dev->input[i];
  487. }
  488. return NULL;
  489. }
  490. #endif
  491. static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
  492. {
  493. struct ddb_input *input = fe->sec_priv;
  494. struct ddb_port *port = input->port;
  495. int status;
  496. if (enable) {
  497. mutex_lock(&port->i2c_gate_lock);
  498. status = input->gate_ctrl(fe, 1);
  499. } else {
  500. status = input->gate_ctrl(fe, 0);
  501. mutex_unlock(&port->i2c_gate_lock);
  502. }
  503. return status;
  504. }
  505. static int demod_attach_drxk(struct ddb_input *input)
  506. {
  507. struct i2c_adapter *i2c = &input->port->i2c->adap;
  508. struct dvb_frontend *fe;
  509. struct drxk_config config;
  510. memset(&config, 0, sizeof(config));
  511. config.microcode_name = "drxk_a3.mc";
  512. config.qam_demod_parameter_count = 4;
  513. config.adr = 0x29 + (input->nr & 1);
  514. fe = input->fe = dvb_attach(drxk_attach, &config, i2c);
  515. if (!input->fe) {
  516. printk(KERN_ERR "No DRXK found!\n");
  517. return -ENODEV;
  518. }
  519. fe->sec_priv = input;
  520. input->gate_ctrl = fe->ops.i2c_gate_ctrl;
  521. fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
  522. return 0;
  523. }
  524. static int tuner_attach_tda18271(struct ddb_input *input)
  525. {
  526. struct i2c_adapter *i2c = &input->port->i2c->adap;
  527. struct dvb_frontend *fe;
  528. if (input->fe->ops.i2c_gate_ctrl)
  529. input->fe->ops.i2c_gate_ctrl(input->fe, 1);
  530. fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
  531. if (!fe) {
  532. printk(KERN_ERR "No TDA18271 found!\n");
  533. return -ENODEV;
  534. }
  535. if (input->fe->ops.i2c_gate_ctrl)
  536. input->fe->ops.i2c_gate_ctrl(input->fe, 0);
  537. return 0;
  538. }
  539. /******************************************************************************/
  540. /******************************************************************************/
  541. /******************************************************************************/
  542. static struct stv090x_config stv0900 = {
  543. .device = STV0900,
  544. .demod_mode = STV090x_DUAL,
  545. .clk_mode = STV090x_CLK_EXT,
  546. .xtal = 27000000,
  547. .address = 0x69,
  548. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  549. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  550. .repeater_level = STV090x_RPTLEVEL_16,
  551. .adc1_range = STV090x_ADC_1Vpp,
  552. .adc2_range = STV090x_ADC_1Vpp,
  553. .diseqc_envelope_mode = true,
  554. };
  555. static struct stv090x_config stv0900_aa = {
  556. .device = STV0900,
  557. .demod_mode = STV090x_DUAL,
  558. .clk_mode = STV090x_CLK_EXT,
  559. .xtal = 27000000,
  560. .address = 0x68,
  561. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  562. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  563. .repeater_level = STV090x_RPTLEVEL_16,
  564. .adc1_range = STV090x_ADC_1Vpp,
  565. .adc2_range = STV090x_ADC_1Vpp,
  566. .diseqc_envelope_mode = true,
  567. };
  568. static struct stv6110x_config stv6110a = {
  569. .addr = 0x60,
  570. .refclk = 27000000,
  571. .clk_div = 1,
  572. };
  573. static struct stv6110x_config stv6110b = {
  574. .addr = 0x63,
  575. .refclk = 27000000,
  576. .clk_div = 1,
  577. };
  578. static int demod_attach_stv0900(struct ddb_input *input, int type)
  579. {
  580. struct i2c_adapter *i2c = &input->port->i2c->adap;
  581. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  582. input->fe = dvb_attach(stv090x_attach, feconf, i2c,
  583. (input->nr & 1) ? STV090x_DEMODULATOR_1
  584. : STV090x_DEMODULATOR_0);
  585. if (!input->fe) {
  586. printk(KERN_ERR "No STV0900 found!\n");
  587. return -ENODEV;
  588. }
  589. if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
  590. 0, (input->nr & 1) ?
  591. (0x09 - type) : (0x0b - type))) {
  592. printk(KERN_ERR "No LNBH24 found!\n");
  593. return -ENODEV;
  594. }
  595. return 0;
  596. }
  597. static int tuner_attach_stv6110(struct ddb_input *input, int type)
  598. {
  599. struct i2c_adapter *i2c = &input->port->i2c->adap;
  600. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  601. struct stv6110x_config *tunerconf = (input->nr & 1) ?
  602. &stv6110b : &stv6110a;
  603. struct stv6110x_devctl *ctl;
  604. ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
  605. if (!ctl) {
  606. printk(KERN_ERR "No STV6110X found!\n");
  607. return -ENODEV;
  608. }
  609. printk(KERN_INFO "attach tuner input %d adr %02x\n",
  610. input->nr, tunerconf->addr);
  611. feconf->tuner_init = ctl->tuner_init;
  612. feconf->tuner_sleep = ctl->tuner_sleep;
  613. feconf->tuner_set_mode = ctl->tuner_set_mode;
  614. feconf->tuner_set_frequency = ctl->tuner_set_frequency;
  615. feconf->tuner_get_frequency = ctl->tuner_get_frequency;
  616. feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
  617. feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
  618. feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
  619. feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
  620. feconf->tuner_set_refclk = ctl->tuner_set_refclk;
  621. feconf->tuner_get_status = ctl->tuner_get_status;
  622. return 0;
  623. }
  624. static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
  625. int (*start_feed)(struct dvb_demux_feed *),
  626. int (*stop_feed)(struct dvb_demux_feed *),
  627. void *priv)
  628. {
  629. dvbdemux->priv = priv;
  630. dvbdemux->filternum = 256;
  631. dvbdemux->feednum = 256;
  632. dvbdemux->start_feed = start_feed;
  633. dvbdemux->stop_feed = stop_feed;
  634. dvbdemux->write_to_decoder = NULL;
  635. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  636. DMX_SECTION_FILTERING |
  637. DMX_MEMORY_BASED_FILTERING);
  638. return dvb_dmx_init(dvbdemux);
  639. }
  640. static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
  641. struct dvb_demux *dvbdemux,
  642. struct dmx_frontend *hw_frontend,
  643. struct dmx_frontend *mem_frontend,
  644. struct dvb_adapter *dvb_adapter)
  645. {
  646. int ret;
  647. dmxdev->filternum = 256;
  648. dmxdev->demux = &dvbdemux->dmx;
  649. dmxdev->capabilities = 0;
  650. ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
  651. if (ret < 0)
  652. return ret;
  653. hw_frontend->source = DMX_FRONTEND_0;
  654. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
  655. mem_frontend->source = DMX_MEMORY_FE;
  656. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
  657. return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
  658. }
  659. static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
  660. {
  661. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  662. struct ddb_input *input = dvbdmx->priv;
  663. if (!input->users)
  664. ddb_input_start(input);
  665. return ++input->users;
  666. }
  667. static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
  668. {
  669. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  670. struct ddb_input *input = dvbdmx->priv;
  671. if (--input->users)
  672. return input->users;
  673. ddb_input_stop(input);
  674. return 0;
  675. }
  676. static void dvb_input_detach(struct ddb_input *input)
  677. {
  678. struct dvb_adapter *adap = &input->adap;
  679. struct dvb_demux *dvbdemux = &input->demux;
  680. switch (input->attached) {
  681. case 5:
  682. if (input->fe2)
  683. dvb_unregister_frontend(input->fe2);
  684. if (input->fe) {
  685. dvb_unregister_frontend(input->fe);
  686. dvb_frontend_detach(input->fe);
  687. input->fe = NULL;
  688. }
  689. case 4:
  690. dvb_net_release(&input->dvbnet);
  691. case 3:
  692. dvbdemux->dmx.close(&dvbdemux->dmx);
  693. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  694. &input->hw_frontend);
  695. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  696. &input->mem_frontend);
  697. dvb_dmxdev_release(&input->dmxdev);
  698. case 2:
  699. dvb_dmx_release(&input->demux);
  700. case 1:
  701. dvb_unregister_adapter(adap);
  702. }
  703. input->attached = 0;
  704. }
  705. static int dvb_input_attach(struct ddb_input *input)
  706. {
  707. int ret;
  708. struct ddb_port *port = input->port;
  709. struct dvb_adapter *adap = &input->adap;
  710. struct dvb_demux *dvbdemux = &input->demux;
  711. ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
  712. &input->port->dev->pdev->dev,
  713. adapter_nr);
  714. if (ret < 0) {
  715. printk(KERN_ERR "ddbridge: Could not register adapter."
  716. "Check if you enabled enough adapters in dvb-core!\n");
  717. return ret;
  718. }
  719. input->attached = 1;
  720. ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
  721. start_feed,
  722. stop_feed, input);
  723. if (ret < 0)
  724. return ret;
  725. input->attached = 2;
  726. ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
  727. &input->hw_frontend,
  728. &input->mem_frontend, adap);
  729. if (ret < 0)
  730. return ret;
  731. input->attached = 3;
  732. ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
  733. if (ret < 0)
  734. return ret;
  735. input->attached = 4;
  736. input->fe = 0;
  737. switch (port->type) {
  738. case DDB_TUNER_DVBS_ST:
  739. if (demod_attach_stv0900(input, 0) < 0)
  740. return -ENODEV;
  741. if (tuner_attach_stv6110(input, 0) < 0)
  742. return -ENODEV;
  743. if (input->fe) {
  744. if (dvb_register_frontend(adap, input->fe) < 0)
  745. return -ENODEV;
  746. }
  747. break;
  748. case DDB_TUNER_DVBS_ST_AA:
  749. if (demod_attach_stv0900(input, 1) < 0)
  750. return -ENODEV;
  751. if (tuner_attach_stv6110(input, 1) < 0)
  752. return -ENODEV;
  753. if (input->fe) {
  754. if (dvb_register_frontend(adap, input->fe) < 0)
  755. return -ENODEV;
  756. }
  757. break;
  758. case DDB_TUNER_DVBCT_TR:
  759. if (demod_attach_drxk(input) < 0)
  760. return -ENODEV;
  761. if (tuner_attach_tda18271(input) < 0)
  762. return -ENODEV;
  763. if (input->fe) {
  764. if (dvb_register_frontend(adap, input->fe) < 0)
  765. return -ENODEV;
  766. }
  767. if (input->fe2) {
  768. if (dvb_register_frontend(adap, input->fe2) < 0)
  769. return -ENODEV;
  770. input->fe2->tuner_priv = input->fe->tuner_priv;
  771. memcpy(&input->fe2->ops.tuner_ops,
  772. &input->fe->ops.tuner_ops,
  773. sizeof(struct dvb_tuner_ops));
  774. }
  775. break;
  776. }
  777. input->attached = 5;
  778. return 0;
  779. }
  780. /****************************************************************************/
  781. /****************************************************************************/
  782. static ssize_t ts_write(struct file *file, const char *buf,
  783. size_t count, loff_t *ppos)
  784. {
  785. struct dvb_device *dvbdev = file->private_data;
  786. struct ddb_output *output = dvbdev->priv;
  787. size_t left = count;
  788. int stat;
  789. while (left) {
  790. if (ddb_output_free(output) < 188) {
  791. if (file->f_flags & O_NONBLOCK)
  792. break;
  793. if (wait_event_interruptible(
  794. output->wq, ddb_output_free(output) >= 188) < 0)
  795. break;
  796. }
  797. stat = ddb_output_write(output, buf, left);
  798. if (stat < 0)
  799. break;
  800. buf += stat;
  801. left -= stat;
  802. }
  803. return (left == count) ? -EAGAIN : (count - left);
  804. }
  805. static ssize_t ts_read(struct file *file, char *buf,
  806. size_t count, loff_t *ppos)
  807. {
  808. struct dvb_device *dvbdev = file->private_data;
  809. struct ddb_output *output = dvbdev->priv;
  810. struct ddb_input *input = output->port->input[0];
  811. int left, read;
  812. count -= count % 188;
  813. left = count;
  814. while (left) {
  815. if (ddb_input_avail(input) < 188) {
  816. if (file->f_flags & O_NONBLOCK)
  817. break;
  818. if (wait_event_interruptible(
  819. input->wq, ddb_input_avail(input) >= 188) < 0)
  820. break;
  821. }
  822. read = ddb_input_read(input, buf, left);
  823. if (read < 0)
  824. return read;
  825. left -= read;
  826. buf += read;
  827. }
  828. return (left == count) ? -EAGAIN : (count - left);
  829. }
  830. static unsigned int ts_poll(struct file *file, poll_table *wait)
  831. {
  832. /*
  833. struct dvb_device *dvbdev = file->private_data;
  834. struct ddb_output *output = dvbdev->priv;
  835. struct ddb_input *input = output->port->input[0];
  836. */
  837. unsigned int mask = 0;
  838. #if 0
  839. if (data_avail_to_read)
  840. mask |= POLLIN | POLLRDNORM;
  841. if (data_avail_to_write)
  842. mask |= POLLOUT | POLLWRNORM;
  843. poll_wait(file, &read_queue, wait);
  844. poll_wait(file, &write_queue, wait);
  845. #endif
  846. return mask;
  847. }
  848. static const struct file_operations ci_fops = {
  849. .owner = THIS_MODULE,
  850. .read = ts_read,
  851. .write = ts_write,
  852. .open = dvb_generic_open,
  853. .release = dvb_generic_release,
  854. .poll = ts_poll,
  855. .mmap = 0,
  856. };
  857. static struct dvb_device dvbdev_ci = {
  858. .priv = 0,
  859. .readers = -1,
  860. .writers = -1,
  861. .users = -1,
  862. .fops = &ci_fops,
  863. };
  864. /****************************************************************************/
  865. /****************************************************************************/
  866. /****************************************************************************/
  867. static void input_tasklet(unsigned long data)
  868. {
  869. struct ddb_input *input = (struct ddb_input *) data;
  870. struct ddb *dev = input->port->dev;
  871. spin_lock(&input->lock);
  872. if (!input->running) {
  873. spin_unlock(&input->lock);
  874. return;
  875. }
  876. input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
  877. if (input->port->class == DDB_PORT_TUNER) {
  878. if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
  879. printk(KERN_ERR "Overflow input %d\n", input->nr);
  880. while (input->cbuf != ((input->stat >> 11) & 0x1f)
  881. || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
  882. dvb_dmx_swfilter_packets(&input->demux,
  883. input->vbuf[input->cbuf],
  884. input->dma_buf_size / 188);
  885. input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
  886. ddbwritel((input->cbuf << 11),
  887. DMA_BUFFER_ACK(input->nr));
  888. input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
  889. }
  890. }
  891. if (input->port->class == DDB_PORT_CI)
  892. wake_up(&input->wq);
  893. spin_unlock(&input->lock);
  894. }
  895. static void output_tasklet(unsigned long data)
  896. {
  897. struct ddb_output *output = (struct ddb_output *) data;
  898. struct ddb *dev = output->port->dev;
  899. spin_lock(&output->lock);
  900. if (!output->running) {
  901. spin_unlock(&output->lock);
  902. return;
  903. }
  904. output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
  905. wake_up(&output->wq);
  906. spin_unlock(&output->lock);
  907. }
  908. struct cxd2099_cfg cxd_cfg = {
  909. .bitrate = 62000,
  910. .adr = 0x40,
  911. .polarity = 1,
  912. .clock_mode = 1,
  913. };
  914. static int ddb_ci_attach(struct ddb_port *port)
  915. {
  916. int ret;
  917. ret = dvb_register_adapter(&port->output->adap,
  918. "DDBridge",
  919. THIS_MODULE,
  920. &port->dev->pdev->dev,
  921. adapter_nr);
  922. if (ret < 0)
  923. return ret;
  924. port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
  925. if (!port->en) {
  926. dvb_unregister_adapter(&port->output->adap);
  927. return -ENODEV;
  928. }
  929. ddb_input_start(port->input[0]);
  930. ddb_output_start(port->output);
  931. dvb_ca_en50221_init(&port->output->adap,
  932. port->en, 0, 1);
  933. ret = dvb_register_device(&port->output->adap, &port->output->dev,
  934. &dvbdev_ci, (void *) port->output,
  935. DVB_DEVICE_SEC);
  936. return ret;
  937. }
  938. static int ddb_port_attach(struct ddb_port *port)
  939. {
  940. int ret = 0;
  941. switch (port->class) {
  942. case DDB_PORT_TUNER:
  943. ret = dvb_input_attach(port->input[0]);
  944. if (ret < 0)
  945. break;
  946. ret = dvb_input_attach(port->input[1]);
  947. break;
  948. case DDB_PORT_CI:
  949. ret = ddb_ci_attach(port);
  950. break;
  951. default:
  952. break;
  953. }
  954. if (ret < 0)
  955. printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
  956. return ret;
  957. }
  958. static int ddb_ports_attach(struct ddb *dev)
  959. {
  960. int i, ret = 0;
  961. struct ddb_port *port;
  962. for (i = 0; i < dev->info->port_num; i++) {
  963. port = &dev->port[i];
  964. ret = ddb_port_attach(port);
  965. if (ret < 0)
  966. break;
  967. }
  968. return ret;
  969. }
  970. static void ddb_ports_detach(struct ddb *dev)
  971. {
  972. int i;
  973. struct ddb_port *port;
  974. for (i = 0; i < dev->info->port_num; i++) {
  975. port = &dev->port[i];
  976. switch (port->class) {
  977. case DDB_PORT_TUNER:
  978. dvb_input_detach(port->input[0]);
  979. dvb_input_detach(port->input[1]);
  980. break;
  981. case DDB_PORT_CI:
  982. if (port->output->dev)
  983. dvb_unregister_device(port->output->dev);
  984. if (port->en) {
  985. ddb_input_stop(port->input[0]);
  986. ddb_output_stop(port->output);
  987. dvb_ca_en50221_release(port->en);
  988. kfree(port->en);
  989. port->en = 0;
  990. dvb_unregister_adapter(&port->output->adap);
  991. }
  992. break;
  993. }
  994. }
  995. }
  996. /****************************************************************************/
  997. /****************************************************************************/
  998. static int port_has_ci(struct ddb_port *port)
  999. {
  1000. u8 val;
  1001. return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
  1002. }
  1003. static int port_has_stv0900(struct ddb_port *port)
  1004. {
  1005. u8 val;
  1006. if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
  1007. return 0;
  1008. return 1;
  1009. }
  1010. static int port_has_stv0900_aa(struct ddb_port *port)
  1011. {
  1012. u8 val;
  1013. if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
  1014. return 0;
  1015. return 1;
  1016. }
  1017. static int port_has_drxks(struct ddb_port *port)
  1018. {
  1019. u8 val;
  1020. if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
  1021. return 0;
  1022. if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
  1023. return 0;
  1024. return 1;
  1025. }
  1026. static void ddb_port_probe(struct ddb_port *port)
  1027. {
  1028. struct ddb *dev = port->dev;
  1029. char *modname = "NO MODULE";
  1030. port->class = DDB_PORT_NONE;
  1031. if (port_has_ci(port)) {
  1032. modname = "CI";
  1033. port->class = DDB_PORT_CI;
  1034. ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1035. } else if (port_has_stv0900(port)) {
  1036. modname = "DUAL DVB-S2";
  1037. port->class = DDB_PORT_TUNER;
  1038. port->type = DDB_TUNER_DVBS_ST;
  1039. ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1040. } else if (port_has_stv0900_aa(port)) {
  1041. modname = "DUAL DVB-S2";
  1042. port->class = DDB_PORT_TUNER;
  1043. port->type = DDB_TUNER_DVBS_ST_AA;
  1044. ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1045. } else if (port_has_drxks(port)) {
  1046. modname = "DUAL DVB-C/T";
  1047. port->class = DDB_PORT_TUNER;
  1048. port->type = DDB_TUNER_DVBCT_TR;
  1049. ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1050. }
  1051. printk(KERN_INFO "Port %d (TAB %d): %s\n",
  1052. port->nr, port->nr+1, modname);
  1053. }
  1054. static void ddb_input_init(struct ddb_port *port, int nr)
  1055. {
  1056. struct ddb *dev = port->dev;
  1057. struct ddb_input *input = &dev->input[nr];
  1058. input->nr = nr;
  1059. input->port = port;
  1060. input->dma_buf_num = INPUT_DMA_BUFS;
  1061. input->dma_buf_size = INPUT_DMA_SIZE;
  1062. ddbwritel(0, TS_INPUT_CONTROL(nr));
  1063. ddbwritel(2, TS_INPUT_CONTROL(nr));
  1064. ddbwritel(0, TS_INPUT_CONTROL(nr));
  1065. ddbwritel(0, DMA_BUFFER_ACK(nr));
  1066. tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
  1067. spin_lock_init(&input->lock);
  1068. init_waitqueue_head(&input->wq);
  1069. }
  1070. static void ddb_output_init(struct ddb_port *port, int nr)
  1071. {
  1072. struct ddb *dev = port->dev;
  1073. struct ddb_output *output = &dev->output[nr];
  1074. output->nr = nr;
  1075. output->port = port;
  1076. output->dma_buf_num = OUTPUT_DMA_BUFS;
  1077. output->dma_buf_size = OUTPUT_DMA_SIZE;
  1078. ddbwritel(0, TS_OUTPUT_CONTROL(nr));
  1079. ddbwritel(2, TS_OUTPUT_CONTROL(nr));
  1080. ddbwritel(0, TS_OUTPUT_CONTROL(nr));
  1081. tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
  1082. init_waitqueue_head(&output->wq);
  1083. }
  1084. static void ddb_ports_init(struct ddb *dev)
  1085. {
  1086. int i;
  1087. struct ddb_port *port;
  1088. for (i = 0; i < dev->info->port_num; i++) {
  1089. port = &dev->port[i];
  1090. port->dev = dev;
  1091. port->nr = i;
  1092. port->i2c = &dev->i2c[i];
  1093. port->input[0] = &dev->input[2 * i];
  1094. port->input[1] = &dev->input[2 * i + 1];
  1095. port->output = &dev->output[i];
  1096. mutex_init(&port->i2c_gate_lock);
  1097. ddb_port_probe(port);
  1098. ddb_input_init(port, 2 * i);
  1099. ddb_input_init(port, 2 * i + 1);
  1100. ddb_output_init(port, i);
  1101. }
  1102. }
  1103. static void ddb_ports_release(struct ddb *dev)
  1104. {
  1105. int i;
  1106. struct ddb_port *port;
  1107. for (i = 0; i < dev->info->port_num; i++) {
  1108. port = &dev->port[i];
  1109. port->dev = dev;
  1110. tasklet_kill(&port->input[0]->tasklet);
  1111. tasklet_kill(&port->input[1]->tasklet);
  1112. tasklet_kill(&port->output->tasklet);
  1113. }
  1114. }
  1115. /****************************************************************************/
  1116. /****************************************************************************/
  1117. /****************************************************************************/
  1118. static void irq_handle_i2c(struct ddb *dev, int n)
  1119. {
  1120. struct ddb_i2c *i2c = &dev->i2c[n];
  1121. i2c->done = 1;
  1122. wake_up(&i2c->wq);
  1123. }
  1124. static irqreturn_t irq_handler(int irq, void *dev_id)
  1125. {
  1126. struct ddb *dev = (struct ddb *) dev_id;
  1127. u32 s = ddbreadl(INTERRUPT_STATUS);
  1128. if (!s)
  1129. return IRQ_NONE;
  1130. do {
  1131. ddbwritel(s, INTERRUPT_ACK);
  1132. if (s & 0x00000001)
  1133. irq_handle_i2c(dev, 0);
  1134. if (s & 0x00000002)
  1135. irq_handle_i2c(dev, 1);
  1136. if (s & 0x00000004)
  1137. irq_handle_i2c(dev, 2);
  1138. if (s & 0x00000008)
  1139. irq_handle_i2c(dev, 3);
  1140. if (s & 0x00000100)
  1141. tasklet_schedule(&dev->input[0].tasklet);
  1142. if (s & 0x00000200)
  1143. tasklet_schedule(&dev->input[1].tasklet);
  1144. if (s & 0x00000400)
  1145. tasklet_schedule(&dev->input[2].tasklet);
  1146. if (s & 0x00000800)
  1147. tasklet_schedule(&dev->input[3].tasklet);
  1148. if (s & 0x00001000)
  1149. tasklet_schedule(&dev->input[4].tasklet);
  1150. if (s & 0x00002000)
  1151. tasklet_schedule(&dev->input[5].tasklet);
  1152. if (s & 0x00004000)
  1153. tasklet_schedule(&dev->input[6].tasklet);
  1154. if (s & 0x00008000)
  1155. tasklet_schedule(&dev->input[7].tasklet);
  1156. if (s & 0x00010000)
  1157. tasklet_schedule(&dev->output[0].tasklet);
  1158. if (s & 0x00020000)
  1159. tasklet_schedule(&dev->output[1].tasklet);
  1160. if (s & 0x00040000)
  1161. tasklet_schedule(&dev->output[2].tasklet);
  1162. if (s & 0x00080000)
  1163. tasklet_schedule(&dev->output[3].tasklet);
  1164. /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
  1165. } while ((s = ddbreadl(INTERRUPT_STATUS)));
  1166. return IRQ_HANDLED;
  1167. }
  1168. /******************************************************************************/
  1169. /******************************************************************************/
  1170. /******************************************************************************/
  1171. static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
  1172. {
  1173. u32 data, shift;
  1174. if (wlen > 4)
  1175. ddbwritel(1, SPI_CONTROL);
  1176. while (wlen > 4) {
  1177. /* FIXME: check for big-endian */
  1178. data = swab32(*(u32 *)wbuf);
  1179. wbuf += 4;
  1180. wlen -= 4;
  1181. ddbwritel(data, SPI_DATA);
  1182. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1183. ;
  1184. }
  1185. if (rlen)
  1186. ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
  1187. else
  1188. ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
  1189. data = 0;
  1190. shift = ((4 - wlen) * 8);
  1191. while (wlen) {
  1192. data <<= 8;
  1193. data |= *wbuf;
  1194. wlen--;
  1195. wbuf++;
  1196. }
  1197. if (shift)
  1198. data <<= shift;
  1199. ddbwritel(data, SPI_DATA);
  1200. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1201. ;
  1202. if (!rlen) {
  1203. ddbwritel(0, SPI_CONTROL);
  1204. return 0;
  1205. }
  1206. if (rlen > 4)
  1207. ddbwritel(1, SPI_CONTROL);
  1208. while (rlen > 4) {
  1209. ddbwritel(0xffffffff, SPI_DATA);
  1210. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1211. ;
  1212. data = ddbreadl(SPI_DATA);
  1213. *(u32 *) rbuf = swab32(data);
  1214. rbuf += 4;
  1215. rlen -= 4;
  1216. }
  1217. ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
  1218. ddbwritel(0xffffffff, SPI_DATA);
  1219. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1220. ;
  1221. data = ddbreadl(SPI_DATA);
  1222. ddbwritel(0, SPI_CONTROL);
  1223. if (rlen < 4)
  1224. data <<= ((4 - rlen) * 8);
  1225. while (rlen > 0) {
  1226. *rbuf = ((data >> 24) & 0xff);
  1227. data <<= 8;
  1228. rbuf++;
  1229. rlen--;
  1230. }
  1231. return 0;
  1232. }
  1233. #define DDB_MAGIC 'd'
  1234. struct ddb_flashio {
  1235. __u8 *write_buf;
  1236. __u32 write_len;
  1237. __u8 *read_buf;
  1238. __u32 read_len;
  1239. };
  1240. #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
  1241. #define DDB_NAME "ddbridge"
  1242. static u32 ddb_num;
  1243. static struct ddb *ddbs[32];
  1244. static struct class *ddb_class;
  1245. static int ddb_major;
  1246. static int ddb_open(struct inode *inode, struct file *file)
  1247. {
  1248. struct ddb *dev = ddbs[iminor(inode)];
  1249. file->private_data = dev;
  1250. return 0;
  1251. }
  1252. static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1253. {
  1254. struct ddb *dev = file->private_data;
  1255. void *parg = (void *)arg;
  1256. int res;
  1257. switch (cmd) {
  1258. case IOCTL_DDB_FLASHIO:
  1259. {
  1260. struct ddb_flashio fio;
  1261. u8 *rbuf, *wbuf;
  1262. if (copy_from_user(&fio, parg, sizeof(fio)))
  1263. return -EFAULT;
  1264. if (fio.write_len > 1028 || fio.read_len > 1028)
  1265. return -EINVAL;
  1266. if (fio.write_len + fio.read_len > 1028)
  1267. return -EINVAL;
  1268. wbuf = &dev->iobuf[0];
  1269. rbuf = wbuf + fio.write_len;
  1270. if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
  1271. return -EFAULT;
  1272. res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
  1273. if (res)
  1274. return res;
  1275. if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
  1276. return -EFAULT;
  1277. break;
  1278. }
  1279. default:
  1280. return -ENOTTY;
  1281. }
  1282. return 0;
  1283. }
  1284. static const struct file_operations ddb_fops = {
  1285. .unlocked_ioctl = ddb_ioctl,
  1286. .open = ddb_open,
  1287. };
  1288. static char *ddb_devnode(struct device *device, umode_t *mode)
  1289. {
  1290. struct ddb *dev = dev_get_drvdata(device);
  1291. return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
  1292. }
  1293. static int ddb_class_create(void)
  1294. {
  1295. ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
  1296. if (ddb_major < 0)
  1297. return ddb_major;
  1298. ddb_class = class_create(THIS_MODULE, DDB_NAME);
  1299. if (IS_ERR(ddb_class)) {
  1300. unregister_chrdev(ddb_major, DDB_NAME);
  1301. return PTR_ERR(ddb_class);
  1302. }
  1303. ddb_class->devnode = ddb_devnode;
  1304. return 0;
  1305. }
  1306. static void ddb_class_destroy(void)
  1307. {
  1308. class_destroy(ddb_class);
  1309. unregister_chrdev(ddb_major, DDB_NAME);
  1310. }
  1311. static int ddb_device_create(struct ddb *dev)
  1312. {
  1313. dev->nr = ddb_num++;
  1314. dev->ddb_dev = device_create(ddb_class, NULL,
  1315. MKDEV(ddb_major, dev->nr),
  1316. dev, "ddbridge%d", dev->nr);
  1317. ddbs[dev->nr] = dev;
  1318. if (IS_ERR(dev->ddb_dev))
  1319. return -1;
  1320. return 0;
  1321. }
  1322. static void ddb_device_destroy(struct ddb *dev)
  1323. {
  1324. ddb_num--;
  1325. if (IS_ERR(dev->ddb_dev))
  1326. return;
  1327. device_destroy(ddb_class, MKDEV(ddb_major, 0));
  1328. }
  1329. /****************************************************************************/
  1330. /****************************************************************************/
  1331. /****************************************************************************/
  1332. static void ddb_unmap(struct ddb *dev)
  1333. {
  1334. if (dev->regs)
  1335. iounmap(dev->regs);
  1336. vfree(dev);
  1337. }
  1338. static void ddb_remove(struct pci_dev *pdev)
  1339. {
  1340. struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev);
  1341. ddb_ports_detach(dev);
  1342. ddb_i2c_release(dev);
  1343. ddbwritel(0, INTERRUPT_ENABLE);
  1344. free_irq(dev->pdev->irq, dev);
  1345. #ifdef CONFIG_PCI_MSI
  1346. if (dev->msi)
  1347. pci_disable_msi(dev->pdev);
  1348. #endif
  1349. ddb_ports_release(dev);
  1350. ddb_buffers_free(dev);
  1351. ddb_device_destroy(dev);
  1352. ddb_unmap(dev);
  1353. pci_set_drvdata(pdev, 0);
  1354. pci_disable_device(pdev);
  1355. }
  1356. static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1357. {
  1358. struct ddb *dev;
  1359. int stat = 0;
  1360. int irq_flag = IRQF_SHARED;
  1361. if (pci_enable_device(pdev) < 0)
  1362. return -ENODEV;
  1363. dev = vmalloc(sizeof(struct ddb));
  1364. if (dev == NULL)
  1365. return -ENOMEM;
  1366. memset(dev, 0, sizeof(struct ddb));
  1367. dev->pdev = pdev;
  1368. pci_set_drvdata(pdev, dev);
  1369. dev->info = (struct ddb_info *) id->driver_data;
  1370. printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
  1371. dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
  1372. pci_resource_len(dev->pdev, 0));
  1373. if (!dev->regs) {
  1374. stat = -ENOMEM;
  1375. goto fail;
  1376. }
  1377. printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
  1378. #ifdef CONFIG_PCI_MSI
  1379. if (pci_msi_enabled())
  1380. stat = pci_enable_msi(dev->pdev);
  1381. if (stat) {
  1382. printk(KERN_INFO ": MSI not available.\n");
  1383. } else {
  1384. irq_flag = 0;
  1385. dev->msi = 1;
  1386. }
  1387. #endif
  1388. stat = request_irq(dev->pdev->irq, irq_handler,
  1389. irq_flag, "DDBridge", (void *) dev);
  1390. if (stat < 0)
  1391. goto fail1;
  1392. ddbwritel(0, DMA_BASE_WRITE);
  1393. ddbwritel(0, DMA_BASE_READ);
  1394. ddbwritel(0xffffffff, INTERRUPT_ACK);
  1395. ddbwritel(0xfff0f, INTERRUPT_ENABLE);
  1396. ddbwritel(0, MSI1_ENABLE);
  1397. if (ddb_i2c_init(dev) < 0)
  1398. goto fail1;
  1399. ddb_ports_init(dev);
  1400. if (ddb_buffers_alloc(dev) < 0) {
  1401. printk(KERN_INFO ": Could not allocate buffer memory\n");
  1402. goto fail2;
  1403. }
  1404. if (ddb_ports_attach(dev) < 0)
  1405. goto fail3;
  1406. ddb_device_create(dev);
  1407. return 0;
  1408. fail3:
  1409. ddb_ports_detach(dev);
  1410. printk(KERN_ERR "fail3\n");
  1411. ddb_ports_release(dev);
  1412. fail2:
  1413. printk(KERN_ERR "fail2\n");
  1414. ddb_buffers_free(dev);
  1415. fail1:
  1416. printk(KERN_ERR "fail1\n");
  1417. if (dev->msi)
  1418. pci_disable_msi(dev->pdev);
  1419. free_irq(dev->pdev->irq, dev);
  1420. fail:
  1421. printk(KERN_ERR "fail\n");
  1422. ddb_unmap(dev);
  1423. pci_set_drvdata(pdev, 0);
  1424. pci_disable_device(pdev);
  1425. return -1;
  1426. }
  1427. /******************************************************************************/
  1428. /******************************************************************************/
  1429. /******************************************************************************/
  1430. static struct ddb_info ddb_none = {
  1431. .type = DDB_NONE,
  1432. .name = "Digital Devices PCIe bridge",
  1433. };
  1434. static struct ddb_info ddb_octopus = {
  1435. .type = DDB_OCTOPUS,
  1436. .name = "Digital Devices Octopus DVB adapter",
  1437. .port_num = 4,
  1438. };
  1439. static struct ddb_info ddb_octopus_le = {
  1440. .type = DDB_OCTOPUS,
  1441. .name = "Digital Devices Octopus LE DVB adapter",
  1442. .port_num = 2,
  1443. };
  1444. static struct ddb_info ddb_v6 = {
  1445. .type = DDB_OCTOPUS,
  1446. .name = "Digital Devices Cine S2 V6 DVB adapter",
  1447. .port_num = 3,
  1448. };
  1449. #define DDVID 0xdd01 /* Digital Devices Vendor ID */
  1450. #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
  1451. .vendor = _vend, .device = _dev, \
  1452. .subvendor = _subvend, .subdevice = _subdev, \
  1453. .driver_data = (unsigned long)&_driverdata }
  1454. static const struct pci_device_id ddb_id_tbl[] = {
  1455. DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
  1456. DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
  1457. DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
  1458. DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus),
  1459. DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
  1460. /* in case sub-ids got deleted in flash */
  1461. DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
  1462. {0}
  1463. };
  1464. MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
  1465. static struct pci_driver ddb_pci_driver = {
  1466. .name = "DDBridge",
  1467. .id_table = ddb_id_tbl,
  1468. .probe = ddb_probe,
  1469. .remove = ddb_remove,
  1470. };
  1471. static __init int module_init_ddbridge(void)
  1472. {
  1473. int ret;
  1474. printk(KERN_INFO "Digital Devices PCIE bridge driver, "
  1475. "Copyright (C) 2010-11 Digital Devices GmbH\n");
  1476. ret = ddb_class_create();
  1477. if (ret < 0)
  1478. return ret;
  1479. ret = pci_register_driver(&ddb_pci_driver);
  1480. if (ret < 0)
  1481. ddb_class_destroy();
  1482. return ret;
  1483. }
  1484. static __exit void module_exit_ddbridge(void)
  1485. {
  1486. pci_unregister_driver(&ddb_pci_driver);
  1487. ddb_class_destroy();
  1488. }
  1489. module_init(module_init_ddbridge);
  1490. module_exit(module_exit_ddbridge);
  1491. MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
  1492. MODULE_AUTHOR("Ralph Metzler");
  1493. MODULE_LICENSE("GPL");
  1494. MODULE_VERSION("0.5");