tvp7002.c 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139
  1. /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
  2. * Digitizer with Horizontal PLL registers
  3. *
  4. * Copyright (C) 2009 Texas Instruments Inc
  5. * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
  6. *
  7. * This code is partially based upon the TVP5150 driver
  8. * written by Mauro Carvalho Chehab (mchehab@infradead.org),
  9. * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  10. * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  11. * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #include <linux/delay.h>
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/videodev2.h>
  31. #include <linux/module.h>
  32. #include <linux/v4l2-dv-timings.h>
  33. #include <media/tvp7002.h>
  34. #include <media/v4l2-device.h>
  35. #include <media/v4l2-chip-ident.h>
  36. #include <media/v4l2-common.h>
  37. #include <media/v4l2-ctrls.h>
  38. #include "tvp7002_reg.h"
  39. MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  40. MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  41. MODULE_LICENSE("GPL");
  42. /* Module Name */
  43. #define TVP7002_MODULE_NAME "tvp7002"
  44. /* I2C retry attempts */
  45. #define I2C_RETRY_COUNT (5)
  46. /* End of registers */
  47. #define TVP7002_EOR 0x5c
  48. /* Read write definition for registers */
  49. #define TVP7002_READ 0
  50. #define TVP7002_WRITE 1
  51. #define TVP7002_RESERVED 2
  52. /* Interlaced vs progressive mask and shift */
  53. #define TVP7002_IP_SHIFT 5
  54. #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT)
  55. /* Shift for CPL and LPF registers */
  56. #define TVP7002_CL_SHIFT 8
  57. #define TVP7002_CL_MASK 0x0f
  58. /* Debug functions */
  59. static bool debug;
  60. module_param(debug, bool, 0644);
  61. MODULE_PARM_DESC(debug, "Debug level (0-2)");
  62. /* Structure for register values */
  63. struct i2c_reg_value {
  64. u8 reg;
  65. u8 value;
  66. u8 type;
  67. };
  68. /*
  69. * Register default values (according to tvp7002 datasheet)
  70. * In the case of read-only registers, the value (0xff) is
  71. * never written. R/W functionality is controlled by the
  72. * writable bit in the register struct definition.
  73. */
  74. static const struct i2c_reg_value tvp7002_init_default[] = {
  75. { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  76. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  77. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  78. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  79. { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  80. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  81. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  82. { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  83. { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  84. { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  85. { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  86. { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  87. { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  88. { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  89. { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  90. { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
  91. { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
  92. { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
  93. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  94. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  95. { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
  96. { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
  97. { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
  98. { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
  99. { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
  100. { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
  101. { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
  102. { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
  103. { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
  104. { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
  105. { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
  106. { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
  107. { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
  108. { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
  109. { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
  110. { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  111. { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  112. { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  113. { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
  114. { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
  115. { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
  116. { 0x29, 0x08, TVP7002_RESERVED },
  117. { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
  118. /* PWR_CTL is controlled only by the probe and reset functions */
  119. { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
  120. { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
  121. { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
  122. { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
  123. { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
  124. { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
  125. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  126. { 0x32, 0x18, TVP7002_RESERVED },
  127. { 0x33, 0x60, TVP7002_RESERVED },
  128. { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
  129. { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
  130. { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
  131. { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
  132. { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
  133. { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
  134. { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
  135. { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
  136. { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
  137. { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
  138. { 0x3e, 0x60, TVP7002_RESERVED },
  139. { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
  140. { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
  141. { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  142. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  143. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  144. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  145. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  146. { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
  147. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  148. { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  149. { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  150. { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
  151. { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
  152. { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
  153. { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
  154. { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
  155. { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
  156. { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
  157. { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
  158. { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
  159. { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
  160. { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
  161. { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
  162. { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
  163. { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
  164. { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
  165. { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
  166. { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
  167. { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
  168. /* This signals end of register values */
  169. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  170. };
  171. /* Register parameters for 480P */
  172. static const struct i2c_reg_value tvp7002_parms_480P[] = {
  173. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
  174. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
  175. { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
  176. { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
  177. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  178. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
  179. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  180. { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
  181. { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
  182. { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
  183. { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
  184. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  185. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  186. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  187. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  188. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  189. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  190. };
  191. /* Register parameters for 576P */
  192. static const struct i2c_reg_value tvp7002_parms_576P[] = {
  193. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
  194. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  195. { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
  196. { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
  197. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  198. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
  199. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  200. { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  201. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  202. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  203. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  204. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  205. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  206. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  207. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  208. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  209. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  210. };
  211. /* Register parameters for 1080I60 */
  212. static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
  213. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  214. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  215. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  216. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  217. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  218. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  219. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  220. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  221. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  222. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  223. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  224. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  225. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  226. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  227. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  228. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  229. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  230. };
  231. /* Register parameters for 1080P60 */
  232. static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
  233. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  234. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  235. { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
  236. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  237. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  238. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  239. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  240. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  241. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  242. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  243. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  244. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  245. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  246. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  247. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  248. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  249. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  250. };
  251. /* Register parameters for 1080I50 */
  252. static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
  253. { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
  254. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  255. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  256. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  257. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  258. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  259. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  260. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  261. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  262. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  263. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  264. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  265. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  266. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  267. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  268. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  269. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  270. };
  271. /* Register parameters for 720P60 */
  272. static const struct i2c_reg_value tvp7002_parms_720P60[] = {
  273. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  274. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  275. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  276. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  277. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  278. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  279. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  280. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  281. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  282. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  283. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  284. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  285. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  286. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  287. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  288. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  289. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  290. };
  291. /* Register parameters for 720P50 */
  292. static const struct i2c_reg_value tvp7002_parms_720P50[] = {
  293. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
  294. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
  295. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  296. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  297. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  298. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  299. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  300. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  301. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  302. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  303. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  304. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  305. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  306. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  307. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  308. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  309. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  310. };
  311. /* Preset definition for handling device operation */
  312. struct tvp7002_preset_definition {
  313. u32 preset;
  314. struct v4l2_dv_timings timings;
  315. const struct i2c_reg_value *p_settings;
  316. enum v4l2_colorspace color_space;
  317. enum v4l2_field scanmode;
  318. u16 progressive;
  319. u16 lines_per_frame;
  320. u16 cpl_min;
  321. u16 cpl_max;
  322. };
  323. /* Struct list for digital video presets */
  324. static const struct tvp7002_preset_definition tvp7002_presets[] = {
  325. {
  326. V4L2_DV_720P60,
  327. V4L2_DV_BT_CEA_1280X720P60,
  328. tvp7002_parms_720P60,
  329. V4L2_COLORSPACE_REC709,
  330. V4L2_FIELD_NONE,
  331. 1,
  332. 0x2EE,
  333. 135,
  334. 153
  335. },
  336. {
  337. V4L2_DV_1080I60,
  338. V4L2_DV_BT_CEA_1920X1080I60,
  339. tvp7002_parms_1080I60,
  340. V4L2_COLORSPACE_REC709,
  341. V4L2_FIELD_INTERLACED,
  342. 0,
  343. 0x465,
  344. 181,
  345. 205
  346. },
  347. {
  348. V4L2_DV_1080I50,
  349. V4L2_DV_BT_CEA_1920X1080I50,
  350. tvp7002_parms_1080I50,
  351. V4L2_COLORSPACE_REC709,
  352. V4L2_FIELD_INTERLACED,
  353. 0,
  354. 0x465,
  355. 217,
  356. 245
  357. },
  358. {
  359. V4L2_DV_720P50,
  360. V4L2_DV_BT_CEA_1280X720P50,
  361. tvp7002_parms_720P50,
  362. V4L2_COLORSPACE_REC709,
  363. V4L2_FIELD_NONE,
  364. 1,
  365. 0x2EE,
  366. 163,
  367. 183
  368. },
  369. {
  370. V4L2_DV_1080P60,
  371. V4L2_DV_BT_CEA_1920X1080P60,
  372. tvp7002_parms_1080P60,
  373. V4L2_COLORSPACE_REC709,
  374. V4L2_FIELD_NONE,
  375. 1,
  376. 0x465,
  377. 90,
  378. 102
  379. },
  380. {
  381. V4L2_DV_480P59_94,
  382. V4L2_DV_BT_CEA_720X480P59_94,
  383. tvp7002_parms_480P,
  384. V4L2_COLORSPACE_SMPTE170M,
  385. V4L2_FIELD_NONE,
  386. 1,
  387. 0x20D,
  388. 0xffff,
  389. 0xffff
  390. },
  391. {
  392. V4L2_DV_576P50,
  393. V4L2_DV_BT_CEA_720X576P50,
  394. tvp7002_parms_576P,
  395. V4L2_COLORSPACE_SMPTE170M,
  396. V4L2_FIELD_NONE,
  397. 1,
  398. 0x271,
  399. 0xffff,
  400. 0xffff
  401. }
  402. };
  403. #define NUM_PRESETS ARRAY_SIZE(tvp7002_presets)
  404. /* Device definition */
  405. struct tvp7002 {
  406. struct v4l2_subdev sd;
  407. struct v4l2_ctrl_handler hdl;
  408. const struct tvp7002_config *pdata;
  409. int ver;
  410. int streaming;
  411. const struct tvp7002_preset_definition *current_preset;
  412. };
  413. /*
  414. * to_tvp7002 - Obtain device handler TVP7002
  415. * @sd: ptr to v4l2_subdev struct
  416. *
  417. * Returns device handler tvp7002.
  418. */
  419. static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
  420. {
  421. return container_of(sd, struct tvp7002, sd);
  422. }
  423. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  424. {
  425. return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
  426. }
  427. /*
  428. * tvp7002_read - Read a value from a register in an TVP7002
  429. * @sd: ptr to v4l2_subdev struct
  430. * @addr: TVP7002 register address
  431. * @dst: pointer to 8-bit destination
  432. *
  433. * Returns value read if successful, or non-zero (-1) otherwise.
  434. */
  435. static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
  436. {
  437. struct i2c_client *c = v4l2_get_subdevdata(sd);
  438. int retry;
  439. int error;
  440. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  441. error = i2c_smbus_read_byte_data(c, addr);
  442. if (error >= 0) {
  443. *dst = (u8)error;
  444. return 0;
  445. }
  446. msleep_interruptible(10);
  447. }
  448. v4l2_err(sd, "TVP7002 read error %d\n", error);
  449. return error;
  450. }
  451. /*
  452. * tvp7002_read_err() - Read a register value with error code
  453. * @sd: pointer to standard V4L2 sub-device structure
  454. * @reg: destination register
  455. * @val: value to be read
  456. * @err: pointer to error value
  457. *
  458. * Read a value in a register and save error value in pointer.
  459. * Also update the register table if successful
  460. */
  461. static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
  462. u8 *dst, int *err)
  463. {
  464. if (!*err)
  465. *err = tvp7002_read(sd, reg, dst);
  466. }
  467. /*
  468. * tvp7002_write() - Write a value to a register in TVP7002
  469. * @sd: ptr to v4l2_subdev struct
  470. * @addr: TVP7002 register address
  471. * @value: value to be written to the register
  472. *
  473. * Write a value to a register in an TVP7002 decoder device.
  474. * Returns zero if successful, or non-zero otherwise.
  475. */
  476. static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
  477. {
  478. struct i2c_client *c;
  479. int retry;
  480. int error;
  481. c = v4l2_get_subdevdata(sd);
  482. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  483. error = i2c_smbus_write_byte_data(c, addr, value);
  484. if (error >= 0)
  485. return 0;
  486. v4l2_warn(sd, "Write: retry ... %d\n", retry);
  487. msleep_interruptible(10);
  488. }
  489. v4l2_err(sd, "TVP7002 write error %d\n", error);
  490. return error;
  491. }
  492. /*
  493. * tvp7002_write_err() - Write a register value with error code
  494. * @sd: pointer to standard V4L2 sub-device structure
  495. * @reg: destination register
  496. * @val: value to be written
  497. * @err: pointer to error value
  498. *
  499. * Write a value in a register and save error value in pointer.
  500. * Also update the register table if successful
  501. */
  502. static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
  503. u8 val, int *err)
  504. {
  505. if (!*err)
  506. *err = tvp7002_write(sd, reg, val);
  507. }
  508. /*
  509. * tvp7002_g_chip_ident() - Get chip identification number
  510. * @sd: ptr to v4l2_subdev struct
  511. * @chip: ptr to v4l2_dbg_chip_ident struct
  512. *
  513. * Obtains the chip's identification number.
  514. * Returns zero or -EINVAL if read operation fails.
  515. */
  516. static int tvp7002_g_chip_ident(struct v4l2_subdev *sd,
  517. struct v4l2_dbg_chip_ident *chip)
  518. {
  519. u8 rev;
  520. int error;
  521. struct i2c_client *client = v4l2_get_subdevdata(sd);
  522. error = tvp7002_read(sd, TVP7002_CHIP_REV, &rev);
  523. if (error < 0)
  524. return error;
  525. return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP7002, rev);
  526. }
  527. /*
  528. * tvp7002_write_inittab() - Write initialization values
  529. * @sd: ptr to v4l2_subdev struct
  530. * @regs: ptr to i2c_reg_value struct
  531. *
  532. * Write initialization values.
  533. * Returns zero or -EINVAL if read operation fails.
  534. */
  535. static int tvp7002_write_inittab(struct v4l2_subdev *sd,
  536. const struct i2c_reg_value *regs)
  537. {
  538. int error = 0;
  539. /* Initialize the first (defined) registers */
  540. while (TVP7002_EOR != regs->reg) {
  541. if (TVP7002_WRITE == regs->type)
  542. tvp7002_write_err(sd, regs->reg, regs->value, &error);
  543. regs++;
  544. }
  545. return error;
  546. }
  547. /*
  548. * tvp7002_s_dv_preset() - Set digital video preset
  549. * @sd: ptr to v4l2_subdev struct
  550. * @dv_preset: ptr to v4l2_dv_preset struct
  551. *
  552. * Set the digital video preset for a TVP7002 decoder device.
  553. * Returns zero when successful or -EINVAL if register access fails.
  554. */
  555. static int tvp7002_s_dv_preset(struct v4l2_subdev *sd,
  556. struct v4l2_dv_preset *dv_preset)
  557. {
  558. struct tvp7002 *device = to_tvp7002(sd);
  559. u32 preset;
  560. int i;
  561. for (i = 0; i < NUM_PRESETS; i++) {
  562. preset = tvp7002_presets[i].preset;
  563. if (preset == dv_preset->preset) {
  564. device->current_preset = &tvp7002_presets[i];
  565. return tvp7002_write_inittab(sd, tvp7002_presets[i].p_settings);
  566. }
  567. }
  568. return -EINVAL;
  569. }
  570. static int tvp7002_s_dv_timings(struct v4l2_subdev *sd,
  571. struct v4l2_dv_timings *dv_timings)
  572. {
  573. struct tvp7002 *device = to_tvp7002(sd);
  574. const struct v4l2_bt_timings *bt = &dv_timings->bt;
  575. int i;
  576. if (dv_timings->type != V4L2_DV_BT_656_1120)
  577. return -EINVAL;
  578. for (i = 0; i < NUM_PRESETS; i++) {
  579. const struct v4l2_bt_timings *t = &tvp7002_presets[i].timings.bt;
  580. if (!memcmp(bt, t, &bt->standards - &bt->width)) {
  581. device->current_preset = &tvp7002_presets[i];
  582. return tvp7002_write_inittab(sd, tvp7002_presets[i].p_settings);
  583. }
  584. }
  585. return -EINVAL;
  586. }
  587. static int tvp7002_g_dv_timings(struct v4l2_subdev *sd,
  588. struct v4l2_dv_timings *dv_timings)
  589. {
  590. struct tvp7002 *device = to_tvp7002(sd);
  591. *dv_timings = device->current_preset->timings;
  592. return 0;
  593. }
  594. /*
  595. * tvp7002_s_ctrl() - Set a control
  596. * @ctrl: ptr to v4l2_ctrl struct
  597. *
  598. * Set a control in TVP7002 decoder device.
  599. * Returns zero when successful or -EINVAL if register access fails.
  600. */
  601. static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
  602. {
  603. struct v4l2_subdev *sd = to_sd(ctrl);
  604. int error = 0;
  605. switch (ctrl->id) {
  606. case V4L2_CID_GAIN:
  607. tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
  608. tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
  609. tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
  610. return error;
  611. }
  612. return -EINVAL;
  613. }
  614. /*
  615. * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
  616. * @sd: pointer to standard V4L2 sub-device structure
  617. * @f: pointer to mediabus format structure
  618. *
  619. * Negotiate the image capture size and mediabus format.
  620. * There is only one possible format, so this single function works for
  621. * get, set and try.
  622. */
  623. static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
  624. {
  625. struct tvp7002 *device = to_tvp7002(sd);
  626. struct v4l2_dv_enum_preset e_preset;
  627. int error;
  628. /* Calculate height and width based on current standard */
  629. error = v4l_fill_dv_preset_info(device->current_preset->preset, &e_preset);
  630. if (error)
  631. return error;
  632. f->width = e_preset.width;
  633. f->height = e_preset.height;
  634. f->code = V4L2_MBUS_FMT_YUYV10_1X20;
  635. f->field = device->current_preset->scanmode;
  636. f->colorspace = device->current_preset->color_space;
  637. v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d",
  638. f->width, f->height);
  639. return 0;
  640. }
  641. /*
  642. * tvp7002_query_dv_preset() - query DV preset
  643. * @sd: pointer to standard V4L2 sub-device structure
  644. * @qpreset: standard V4L2 v4l2_dv_preset structure
  645. *
  646. * Returns the current DV preset by TVP7002. If no active input is
  647. * detected, returns -EINVAL
  648. */
  649. static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
  650. {
  651. const struct tvp7002_preset_definition *presets = tvp7002_presets;
  652. u8 progressive;
  653. u32 lpfr;
  654. u32 cpln;
  655. int error = 0;
  656. u8 lpf_lsb;
  657. u8 lpf_msb;
  658. u8 cpl_lsb;
  659. u8 cpl_msb;
  660. /* Return invalid index if no active input is detected */
  661. *index = NUM_PRESETS;
  662. /* Read standards from device registers */
  663. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
  664. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
  665. if (error < 0)
  666. return error;
  667. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
  668. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
  669. if (error < 0)
  670. return error;
  671. /* Get lines per frame, clocks per line and interlaced/progresive */
  672. lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
  673. cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
  674. progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
  675. /* Do checking of video modes */
  676. for (*index = 0; *index < NUM_PRESETS; (*index)++, presets++)
  677. if (lpfr == presets->lines_per_frame &&
  678. progressive == presets->progressive) {
  679. if (presets->cpl_min == 0xffff)
  680. break;
  681. if (cpln >= presets->cpl_min && cpln <= presets->cpl_max)
  682. break;
  683. }
  684. if (*index == NUM_PRESETS) {
  685. v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
  686. lpfr, cpln);
  687. return -ENOLINK;
  688. }
  689. /* Update lines per frame and clocks per line info */
  690. v4l2_dbg(1, debug, sd, "detected preset: %d\n", *index);
  691. return 0;
  692. }
  693. static int tvp7002_query_dv_preset(struct v4l2_subdev *sd,
  694. struct v4l2_dv_preset *qpreset)
  695. {
  696. int index;
  697. int err = tvp7002_query_dv(sd, &index);
  698. if (err || index == NUM_PRESETS) {
  699. qpreset->preset = V4L2_DV_INVALID;
  700. if (err == -ENOLINK)
  701. err = 0;
  702. return err;
  703. }
  704. qpreset->preset = tvp7002_presets[index].preset;
  705. return 0;
  706. }
  707. static int tvp7002_query_dv_timings(struct v4l2_subdev *sd,
  708. struct v4l2_dv_timings *timings)
  709. {
  710. int index;
  711. int err = tvp7002_query_dv(sd, &index);
  712. if (err)
  713. return err;
  714. *timings = tvp7002_presets[index].timings;
  715. return 0;
  716. }
  717. #ifdef CONFIG_VIDEO_ADV_DEBUG
  718. /*
  719. * tvp7002_g_register() - Get the value of a register
  720. * @sd: ptr to v4l2_subdev struct
  721. * @reg: ptr to v4l2_dbg_register struct
  722. *
  723. * Get the value of a TVP7002 decoder device register.
  724. * Returns zero when successful, -EINVAL if register read fails or
  725. * access to I2C client fails, -EPERM if the call is not allowed
  726. * by disabled CAP_SYS_ADMIN.
  727. */
  728. static int tvp7002_g_register(struct v4l2_subdev *sd,
  729. struct v4l2_dbg_register *reg)
  730. {
  731. struct i2c_client *client = v4l2_get_subdevdata(sd);
  732. u8 val;
  733. int ret;
  734. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  735. return -EINVAL;
  736. if (!capable(CAP_SYS_ADMIN))
  737. return -EPERM;
  738. ret = tvp7002_read(sd, reg->reg & 0xff, &val);
  739. reg->val = val;
  740. return ret;
  741. }
  742. /*
  743. * tvp7002_s_register() - set a control
  744. * @sd: ptr to v4l2_subdev struct
  745. * @reg: ptr to v4l2_dbg_register struct
  746. *
  747. * Get the value of a TVP7002 decoder device register.
  748. * Returns zero when successful, -EINVAL if register read fails or
  749. * -EPERM if call not allowed.
  750. */
  751. static int tvp7002_s_register(struct v4l2_subdev *sd,
  752. struct v4l2_dbg_register *reg)
  753. {
  754. struct i2c_client *client = v4l2_get_subdevdata(sd);
  755. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  756. return -EINVAL;
  757. if (!capable(CAP_SYS_ADMIN))
  758. return -EPERM;
  759. return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
  760. }
  761. #endif
  762. /*
  763. * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats
  764. * @sd: pointer to standard V4L2 sub-device structure
  765. * @index: format index
  766. * @code: pointer to mediabus format
  767. *
  768. * Enumerate supported mediabus formats.
  769. */
  770. static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
  771. enum v4l2_mbus_pixelcode *code)
  772. {
  773. /* Check requested format index is within range */
  774. if (index)
  775. return -EINVAL;
  776. *code = V4L2_MBUS_FMT_YUYV10_1X20;
  777. return 0;
  778. }
  779. /*
  780. * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
  781. * @sd: pointer to standard V4L2 sub-device structure
  782. * @enable: streaming enable or disable
  783. *
  784. * Sets streaming to enable or disable, if possible.
  785. */
  786. static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
  787. {
  788. struct tvp7002 *device = to_tvp7002(sd);
  789. int error = 0;
  790. if (device->streaming == enable)
  791. return 0;
  792. if (enable) {
  793. /* Set output state on (low impedance means stream on) */
  794. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00);
  795. device->streaming = enable;
  796. } else {
  797. /* Set output state off (high impedance means stream off) */
  798. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03);
  799. if (error)
  800. v4l2_dbg(1, debug, sd, "Unable to stop streaming\n");
  801. device->streaming = enable;
  802. }
  803. return error;
  804. }
  805. /*
  806. * tvp7002_log_status() - Print information about register settings
  807. * @sd: ptr to v4l2_subdev struct
  808. *
  809. * Log register values of a TVP7002 decoder device.
  810. * Returns zero or -EINVAL if read operation fails.
  811. */
  812. static int tvp7002_log_status(struct v4l2_subdev *sd)
  813. {
  814. const struct tvp7002_preset_definition *presets = tvp7002_presets;
  815. struct tvp7002 *device = to_tvp7002(sd);
  816. struct v4l2_dv_enum_preset e_preset;
  817. struct v4l2_dv_preset detected;
  818. int i;
  819. detected.preset = V4L2_DV_INVALID;
  820. /* Find my current standard*/
  821. tvp7002_query_dv_preset(sd, &detected);
  822. /* Print standard related code values */
  823. for (i = 0; i < NUM_PRESETS; i++, presets++)
  824. if (presets->preset == detected.preset)
  825. break;
  826. if (v4l_fill_dv_preset_info(device->current_preset->preset, &e_preset))
  827. return -EINVAL;
  828. v4l2_info(sd, "Selected DV Preset: %s\n", e_preset.name);
  829. v4l2_info(sd, " Pixels per line: %u\n", e_preset.width);
  830. v4l2_info(sd, " Lines per frame: %u\n\n", e_preset.height);
  831. if (i == NUM_PRESETS) {
  832. v4l2_info(sd, "Detected DV Preset: None\n");
  833. } else {
  834. if (v4l_fill_dv_preset_info(presets->preset, &e_preset))
  835. return -EINVAL;
  836. v4l2_info(sd, "Detected DV Preset: %s\n", e_preset.name);
  837. v4l2_info(sd, " Pixels per line: %u\n", e_preset.width);
  838. v4l2_info(sd, " Lines per frame: %u\n\n", e_preset.height);
  839. }
  840. v4l2_info(sd, "Streaming enabled: %s\n",
  841. device->streaming ? "yes" : "no");
  842. /* Print the current value of the gain control */
  843. v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
  844. return 0;
  845. }
  846. /*
  847. * tvp7002_enum_dv_presets() - Enum supported digital video formats
  848. * @sd: pointer to standard V4L2 sub-device structure
  849. * @preset: pointer to format struct
  850. *
  851. * Enumerate supported digital video formats.
  852. */
  853. static int tvp7002_enum_dv_presets(struct v4l2_subdev *sd,
  854. struct v4l2_dv_enum_preset *preset)
  855. {
  856. /* Check requested format index is within range */
  857. if (preset->index >= NUM_PRESETS)
  858. return -EINVAL;
  859. return v4l_fill_dv_preset_info(tvp7002_presets[preset->index].preset, preset);
  860. }
  861. static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
  862. struct v4l2_enum_dv_timings *timings)
  863. {
  864. /* Check requested format index is within range */
  865. if (timings->index >= NUM_PRESETS)
  866. return -EINVAL;
  867. timings->timings = tvp7002_presets[timings->index].timings;
  868. return 0;
  869. }
  870. static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
  871. .s_ctrl = tvp7002_s_ctrl,
  872. };
  873. /* V4L2 core operation handlers */
  874. static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
  875. .g_chip_ident = tvp7002_g_chip_ident,
  876. .log_status = tvp7002_log_status,
  877. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  878. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  879. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  880. .g_ctrl = v4l2_subdev_g_ctrl,
  881. .s_ctrl = v4l2_subdev_s_ctrl,
  882. .queryctrl = v4l2_subdev_queryctrl,
  883. .querymenu = v4l2_subdev_querymenu,
  884. #ifdef CONFIG_VIDEO_ADV_DEBUG
  885. .g_register = tvp7002_g_register,
  886. .s_register = tvp7002_s_register,
  887. #endif
  888. };
  889. /* Specific video subsystem operation handlers */
  890. static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
  891. .enum_dv_presets = tvp7002_enum_dv_presets,
  892. .s_dv_preset = tvp7002_s_dv_preset,
  893. .query_dv_preset = tvp7002_query_dv_preset,
  894. .g_dv_timings = tvp7002_g_dv_timings,
  895. .s_dv_timings = tvp7002_s_dv_timings,
  896. .enum_dv_timings = tvp7002_enum_dv_timings,
  897. .query_dv_timings = tvp7002_query_dv_timings,
  898. .s_stream = tvp7002_s_stream,
  899. .g_mbus_fmt = tvp7002_mbus_fmt,
  900. .try_mbus_fmt = tvp7002_mbus_fmt,
  901. .s_mbus_fmt = tvp7002_mbus_fmt,
  902. .enum_mbus_fmt = tvp7002_enum_mbus_fmt,
  903. };
  904. /* V4L2 top level operation handlers */
  905. static const struct v4l2_subdev_ops tvp7002_ops = {
  906. .core = &tvp7002_core_ops,
  907. .video = &tvp7002_video_ops,
  908. };
  909. /*
  910. * tvp7002_probe - Probe a TVP7002 device
  911. * @c: ptr to i2c_client struct
  912. * @id: ptr to i2c_device_id struct
  913. *
  914. * Initialize the TVP7002 device
  915. * Returns zero when successful, -EINVAL if register read fails or
  916. * -EIO if i2c access is not available.
  917. */
  918. static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id)
  919. {
  920. struct v4l2_subdev *sd;
  921. struct tvp7002 *device;
  922. struct v4l2_dv_preset preset;
  923. int polarity_a;
  924. int polarity_b;
  925. u8 revision;
  926. int error;
  927. /* Check if the adapter supports the needed features */
  928. if (!i2c_check_functionality(c->adapter,
  929. I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
  930. return -EIO;
  931. if (!c->dev.platform_data) {
  932. v4l_err(c, "No platform data!!\n");
  933. return -ENODEV;
  934. }
  935. device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
  936. if (!device)
  937. return -ENOMEM;
  938. sd = &device->sd;
  939. device->pdata = c->dev.platform_data;
  940. device->current_preset = tvp7002_presets;
  941. /* Tell v4l2 the device is ready */
  942. v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
  943. v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
  944. c->addr, c->adapter->name);
  945. error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
  946. if (error < 0)
  947. return error;
  948. /* Get revision number */
  949. v4l2_info(sd, "Rev. %02x detected.\n", revision);
  950. if (revision != 0x02)
  951. v4l2_info(sd, "Unknown revision detected.\n");
  952. /* Initializes TVP7002 to its default values */
  953. error = tvp7002_write_inittab(sd, tvp7002_init_default);
  954. if (error < 0)
  955. return error;
  956. /* Set polarity information after registers have been set */
  957. polarity_a = 0x20 | device->pdata->hs_polarity << 5
  958. | device->pdata->vs_polarity << 2;
  959. error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
  960. if (error < 0)
  961. return error;
  962. polarity_b = 0x01 | device->pdata->fid_polarity << 2
  963. | device->pdata->sog_polarity << 1
  964. | device->pdata->clk_polarity;
  965. error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
  966. if (error < 0)
  967. return error;
  968. /* Set registers according to default video mode */
  969. preset.preset = device->current_preset->preset;
  970. error = tvp7002_s_dv_preset(sd, &preset);
  971. v4l2_ctrl_handler_init(&device->hdl, 1);
  972. v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
  973. V4L2_CID_GAIN, 0, 255, 1, 0);
  974. sd->ctrl_handler = &device->hdl;
  975. if (device->hdl.error) {
  976. int err = device->hdl.error;
  977. v4l2_ctrl_handler_free(&device->hdl);
  978. return err;
  979. }
  980. v4l2_ctrl_handler_setup(&device->hdl);
  981. return 0;
  982. }
  983. /*
  984. * tvp7002_remove - Remove TVP7002 device support
  985. * @c: ptr to i2c_client struct
  986. *
  987. * Reset the TVP7002 device
  988. * Returns zero.
  989. */
  990. static int tvp7002_remove(struct i2c_client *c)
  991. {
  992. struct v4l2_subdev *sd = i2c_get_clientdata(c);
  993. struct tvp7002 *device = to_tvp7002(sd);
  994. v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
  995. "on address 0x%x\n", c->addr);
  996. v4l2_device_unregister_subdev(sd);
  997. v4l2_ctrl_handler_free(&device->hdl);
  998. return 0;
  999. }
  1000. /* I2C Device ID table */
  1001. static const struct i2c_device_id tvp7002_id[] = {
  1002. { "tvp7002", 0 },
  1003. { }
  1004. };
  1005. MODULE_DEVICE_TABLE(i2c, tvp7002_id);
  1006. /* I2C driver data */
  1007. static struct i2c_driver tvp7002_driver = {
  1008. .driver = {
  1009. .owner = THIS_MODULE,
  1010. .name = TVP7002_MODULE_NAME,
  1011. },
  1012. .probe = tvp7002_probe,
  1013. .remove = tvp7002_remove,
  1014. .id_table = tvp7002_id,
  1015. };
  1016. module_i2c_driver(tvp7002_driver);