mt9v032.c 24 KB

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  1. /*
  2. * Driver for MT9V032 CMOS Image Sensor from Micron
  3. *
  4. * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  5. *
  6. * Based on the MT9M001 driver,
  7. *
  8. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/i2c.h>
  16. #include <linux/log2.h>
  17. #include <linux/mutex.h>
  18. #include <linux/slab.h>
  19. #include <linux/videodev2.h>
  20. #include <linux/v4l2-mediabus.h>
  21. #include <linux/module.h>
  22. #include <media/mt9v032.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-subdev.h>
  26. #define MT9V032_PIXEL_ARRAY_HEIGHT 492
  27. #define MT9V032_PIXEL_ARRAY_WIDTH 782
  28. #define MT9V032_SYSCLK_FREQ_DEF 26600000
  29. #define MT9V032_CHIP_VERSION 0x00
  30. #define MT9V032_CHIP_ID_REV1 0x1311
  31. #define MT9V032_CHIP_ID_REV3 0x1313
  32. #define MT9V032_COLUMN_START 0x01
  33. #define MT9V032_COLUMN_START_MIN 1
  34. #define MT9V032_COLUMN_START_DEF 1
  35. #define MT9V032_COLUMN_START_MAX 752
  36. #define MT9V032_ROW_START 0x02
  37. #define MT9V032_ROW_START_MIN 4
  38. #define MT9V032_ROW_START_DEF 5
  39. #define MT9V032_ROW_START_MAX 482
  40. #define MT9V032_WINDOW_HEIGHT 0x03
  41. #define MT9V032_WINDOW_HEIGHT_MIN 1
  42. #define MT9V032_WINDOW_HEIGHT_DEF 480
  43. #define MT9V032_WINDOW_HEIGHT_MAX 480
  44. #define MT9V032_WINDOW_WIDTH 0x04
  45. #define MT9V032_WINDOW_WIDTH_MIN 1
  46. #define MT9V032_WINDOW_WIDTH_DEF 752
  47. #define MT9V032_WINDOW_WIDTH_MAX 752
  48. #define MT9V032_HORIZONTAL_BLANKING 0x05
  49. #define MT9V032_HORIZONTAL_BLANKING_MIN 43
  50. #define MT9V032_HORIZONTAL_BLANKING_DEF 94
  51. #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
  52. #define MT9V032_VERTICAL_BLANKING 0x06
  53. #define MT9V032_VERTICAL_BLANKING_MIN 4
  54. #define MT9V032_VERTICAL_BLANKING_DEF 45
  55. #define MT9V032_VERTICAL_BLANKING_MAX 3000
  56. #define MT9V032_CHIP_CONTROL 0x07
  57. #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
  58. #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
  59. #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
  60. #define MT9V032_SHUTTER_WIDTH1 0x08
  61. #define MT9V032_SHUTTER_WIDTH2 0x09
  62. #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
  63. #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
  64. #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
  65. #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
  66. #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
  67. #define MT9V032_RESET 0x0c
  68. #define MT9V032_READ_MODE 0x0d
  69. #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
  70. #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
  71. #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
  72. #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
  73. #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
  74. #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
  75. #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
  76. #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
  77. #define MT9V032_PIXEL_OPERATION_MODE 0x0f
  78. #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
  79. #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
  80. #define MT9V032_ANALOG_GAIN 0x35
  81. #define MT9V032_ANALOG_GAIN_MIN 16
  82. #define MT9V032_ANALOG_GAIN_DEF 16
  83. #define MT9V032_ANALOG_GAIN_MAX 64
  84. #define MT9V032_MAX_ANALOG_GAIN 0x36
  85. #define MT9V032_MAX_ANALOG_GAIN_MAX 127
  86. #define MT9V032_FRAME_DARK_AVERAGE 0x42
  87. #define MT9V032_DARK_AVG_THRESH 0x46
  88. #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
  89. #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
  90. #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
  91. #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
  92. #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
  93. #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
  94. #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
  95. #define MT9V032_PIXEL_CLOCK 0x74
  96. #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
  97. #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
  98. #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
  99. #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
  100. #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
  101. #define MT9V032_TEST_PATTERN 0x7f
  102. #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
  103. #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
  104. #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
  105. #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
  106. #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
  107. #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
  108. #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
  109. #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
  110. #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
  111. #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
  112. #define MT9V032_AEC_AGC_ENABLE 0xaf
  113. #define MT9V032_AEC_ENABLE (1 << 0)
  114. #define MT9V032_AGC_ENABLE (1 << 1)
  115. #define MT9V032_THERMAL_INFO 0xc1
  116. struct mt9v032 {
  117. struct v4l2_subdev subdev;
  118. struct media_pad pad;
  119. struct v4l2_mbus_framefmt format;
  120. struct v4l2_rect crop;
  121. struct v4l2_ctrl_handler ctrls;
  122. struct {
  123. struct v4l2_ctrl *link_freq;
  124. struct v4l2_ctrl *pixel_rate;
  125. };
  126. struct mutex power_lock;
  127. int power_count;
  128. struct mt9v032_platform_data *pdata;
  129. u32 sysclk;
  130. u16 chip_control;
  131. u16 aec_agc;
  132. u16 hblank;
  133. struct {
  134. struct v4l2_ctrl *test_pattern;
  135. struct v4l2_ctrl *test_pattern_color;
  136. };
  137. };
  138. static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
  139. {
  140. return container_of(sd, struct mt9v032, subdev);
  141. }
  142. static int mt9v032_read(struct i2c_client *client, const u8 reg)
  143. {
  144. s32 data = i2c_smbus_read_word_swapped(client, reg);
  145. dev_dbg(&client->dev, "%s: read 0x%04x from 0x%02x\n", __func__,
  146. data, reg);
  147. return data;
  148. }
  149. static int mt9v032_write(struct i2c_client *client, const u8 reg,
  150. const u16 data)
  151. {
  152. dev_dbg(&client->dev, "%s: writing 0x%04x to 0x%02x\n", __func__,
  153. data, reg);
  154. return i2c_smbus_write_word_swapped(client, reg, data);
  155. }
  156. static int mt9v032_set_chip_control(struct mt9v032 *mt9v032, u16 clear, u16 set)
  157. {
  158. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  159. u16 value = (mt9v032->chip_control & ~clear) | set;
  160. int ret;
  161. ret = mt9v032_write(client, MT9V032_CHIP_CONTROL, value);
  162. if (ret < 0)
  163. return ret;
  164. mt9v032->chip_control = value;
  165. return 0;
  166. }
  167. static int
  168. mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
  169. {
  170. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  171. u16 value = mt9v032->aec_agc;
  172. int ret;
  173. if (enable)
  174. value |= which;
  175. else
  176. value &= ~which;
  177. ret = mt9v032_write(client, MT9V032_AEC_AGC_ENABLE, value);
  178. if (ret < 0)
  179. return ret;
  180. mt9v032->aec_agc = value;
  181. return 0;
  182. }
  183. static int
  184. mt9v032_update_hblank(struct mt9v032 *mt9v032)
  185. {
  186. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  187. struct v4l2_rect *crop = &mt9v032->crop;
  188. return mt9v032_write(client, MT9V032_HORIZONTAL_BLANKING,
  189. max_t(s32, mt9v032->hblank, 660 - crop->width));
  190. }
  191. #define EXT_CLK 25000000
  192. static int mt9v032_power_on(struct mt9v032 *mt9v032)
  193. {
  194. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  195. int ret;
  196. if (mt9v032->pdata->set_clock) {
  197. mt9v032->pdata->set_clock(&mt9v032->subdev, mt9v032->sysclk);
  198. udelay(1);
  199. }
  200. /* Reset the chip and stop data read out */
  201. ret = mt9v032_write(client, MT9V032_RESET, 1);
  202. if (ret < 0)
  203. return ret;
  204. ret = mt9v032_write(client, MT9V032_RESET, 0);
  205. if (ret < 0)
  206. return ret;
  207. return mt9v032_write(client, MT9V032_CHIP_CONTROL, 0);
  208. }
  209. static void mt9v032_power_off(struct mt9v032 *mt9v032)
  210. {
  211. if (mt9v032->pdata->set_clock)
  212. mt9v032->pdata->set_clock(&mt9v032->subdev, 0);
  213. }
  214. static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
  215. {
  216. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  217. int ret;
  218. if (!on) {
  219. mt9v032_power_off(mt9v032);
  220. return 0;
  221. }
  222. ret = mt9v032_power_on(mt9v032);
  223. if (ret < 0)
  224. return ret;
  225. /* Configure the pixel clock polarity */
  226. if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
  227. ret = mt9v032_write(client, MT9V032_PIXEL_CLOCK,
  228. MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
  229. if (ret < 0)
  230. return ret;
  231. }
  232. /* Disable the noise correction algorithm and restore the controls. */
  233. ret = mt9v032_write(client, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
  234. if (ret < 0)
  235. return ret;
  236. return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
  237. }
  238. /* -----------------------------------------------------------------------------
  239. * V4L2 subdev video operations
  240. */
  241. static struct v4l2_mbus_framefmt *
  242. __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh,
  243. unsigned int pad, enum v4l2_subdev_format_whence which)
  244. {
  245. switch (which) {
  246. case V4L2_SUBDEV_FORMAT_TRY:
  247. return v4l2_subdev_get_try_format(fh, pad);
  248. case V4L2_SUBDEV_FORMAT_ACTIVE:
  249. return &mt9v032->format;
  250. default:
  251. return NULL;
  252. }
  253. }
  254. static struct v4l2_rect *
  255. __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh,
  256. unsigned int pad, enum v4l2_subdev_format_whence which)
  257. {
  258. switch (which) {
  259. case V4L2_SUBDEV_FORMAT_TRY:
  260. return v4l2_subdev_get_try_crop(fh, pad);
  261. case V4L2_SUBDEV_FORMAT_ACTIVE:
  262. return &mt9v032->crop;
  263. default:
  264. return NULL;
  265. }
  266. }
  267. static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
  268. {
  269. const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE
  270. | MT9V032_CHIP_CONTROL_DOUT_ENABLE
  271. | MT9V032_CHIP_CONTROL_SEQUENTIAL;
  272. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  273. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  274. struct v4l2_mbus_framefmt *format = &mt9v032->format;
  275. struct v4l2_rect *crop = &mt9v032->crop;
  276. unsigned int hratio;
  277. unsigned int vratio;
  278. int ret;
  279. if (!enable)
  280. return mt9v032_set_chip_control(mt9v032, mode, 0);
  281. /* Configure the window size and row/column bin */
  282. hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
  283. vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
  284. ret = mt9v032_write(client, MT9V032_READ_MODE,
  285. (hratio - 1) << MT9V032_READ_MODE_ROW_BIN_SHIFT |
  286. (vratio - 1) << MT9V032_READ_MODE_COLUMN_BIN_SHIFT);
  287. if (ret < 0)
  288. return ret;
  289. ret = mt9v032_write(client, MT9V032_COLUMN_START, crop->left);
  290. if (ret < 0)
  291. return ret;
  292. ret = mt9v032_write(client, MT9V032_ROW_START, crop->top);
  293. if (ret < 0)
  294. return ret;
  295. ret = mt9v032_write(client, MT9V032_WINDOW_WIDTH, crop->width);
  296. if (ret < 0)
  297. return ret;
  298. ret = mt9v032_write(client, MT9V032_WINDOW_HEIGHT, crop->height);
  299. if (ret < 0)
  300. return ret;
  301. ret = mt9v032_update_hblank(mt9v032);
  302. if (ret < 0)
  303. return ret;
  304. /* Switch to master "normal" mode */
  305. return mt9v032_set_chip_control(mt9v032, 0, mode);
  306. }
  307. static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
  308. struct v4l2_subdev_fh *fh,
  309. struct v4l2_subdev_mbus_code_enum *code)
  310. {
  311. if (code->index > 0)
  312. return -EINVAL;
  313. code->code = V4L2_MBUS_FMT_SGRBG10_1X10;
  314. return 0;
  315. }
  316. static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
  317. struct v4l2_subdev_fh *fh,
  318. struct v4l2_subdev_frame_size_enum *fse)
  319. {
  320. if (fse->index >= 8 || fse->code != V4L2_MBUS_FMT_SGRBG10_1X10)
  321. return -EINVAL;
  322. fse->min_width = MT9V032_WINDOW_WIDTH_DEF / fse->index;
  323. fse->max_width = fse->min_width;
  324. fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / fse->index;
  325. fse->max_height = fse->min_height;
  326. return 0;
  327. }
  328. static int mt9v032_get_format(struct v4l2_subdev *subdev,
  329. struct v4l2_subdev_fh *fh,
  330. struct v4l2_subdev_format *format)
  331. {
  332. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  333. format->format = *__mt9v032_get_pad_format(mt9v032, fh, format->pad,
  334. format->which);
  335. return 0;
  336. }
  337. static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032,
  338. unsigned int hratio)
  339. {
  340. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  341. int ret;
  342. ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
  343. mt9v032->sysclk / hratio);
  344. if (ret < 0)
  345. dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
  346. }
  347. static int mt9v032_set_format(struct v4l2_subdev *subdev,
  348. struct v4l2_subdev_fh *fh,
  349. struct v4l2_subdev_format *format)
  350. {
  351. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  352. struct v4l2_mbus_framefmt *__format;
  353. struct v4l2_rect *__crop;
  354. unsigned int width;
  355. unsigned int height;
  356. unsigned int hratio;
  357. unsigned int vratio;
  358. __crop = __mt9v032_get_pad_crop(mt9v032, fh, format->pad,
  359. format->which);
  360. /* Clamp the width and height to avoid dividing by zero. */
  361. width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
  362. max(__crop->width / 8, MT9V032_WINDOW_WIDTH_MIN),
  363. __crop->width);
  364. height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
  365. max(__crop->height / 8, MT9V032_WINDOW_HEIGHT_MIN),
  366. __crop->height);
  367. hratio = DIV_ROUND_CLOSEST(__crop->width, width);
  368. vratio = DIV_ROUND_CLOSEST(__crop->height, height);
  369. __format = __mt9v032_get_pad_format(mt9v032, fh, format->pad,
  370. format->which);
  371. __format->width = __crop->width / hratio;
  372. __format->height = __crop->height / vratio;
  373. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  374. mt9v032_configure_pixel_rate(mt9v032, hratio);
  375. format->format = *__format;
  376. return 0;
  377. }
  378. static int mt9v032_get_crop(struct v4l2_subdev *subdev,
  379. struct v4l2_subdev_fh *fh,
  380. struct v4l2_subdev_crop *crop)
  381. {
  382. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  383. crop->rect = *__mt9v032_get_pad_crop(mt9v032, fh, crop->pad,
  384. crop->which);
  385. return 0;
  386. }
  387. static int mt9v032_set_crop(struct v4l2_subdev *subdev,
  388. struct v4l2_subdev_fh *fh,
  389. struct v4l2_subdev_crop *crop)
  390. {
  391. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  392. struct v4l2_mbus_framefmt *__format;
  393. struct v4l2_rect *__crop;
  394. struct v4l2_rect rect;
  395. /* Clamp the crop rectangle boundaries and align them to a non multiple
  396. * of 2 pixels to ensure a GRBG Bayer pattern.
  397. */
  398. rect.left = clamp(ALIGN(crop->rect.left + 1, 2) - 1,
  399. MT9V032_COLUMN_START_MIN,
  400. MT9V032_COLUMN_START_MAX);
  401. rect.top = clamp(ALIGN(crop->rect.top + 1, 2) - 1,
  402. MT9V032_ROW_START_MIN,
  403. MT9V032_ROW_START_MAX);
  404. rect.width = clamp(ALIGN(crop->rect.width, 2),
  405. MT9V032_WINDOW_WIDTH_MIN,
  406. MT9V032_WINDOW_WIDTH_MAX);
  407. rect.height = clamp(ALIGN(crop->rect.height, 2),
  408. MT9V032_WINDOW_HEIGHT_MIN,
  409. MT9V032_WINDOW_HEIGHT_MAX);
  410. rect.width = min(rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
  411. rect.height = min(rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
  412. __crop = __mt9v032_get_pad_crop(mt9v032, fh, crop->pad, crop->which);
  413. if (rect.width != __crop->width || rect.height != __crop->height) {
  414. /* Reset the output image size if the crop rectangle size has
  415. * been modified.
  416. */
  417. __format = __mt9v032_get_pad_format(mt9v032, fh, crop->pad,
  418. crop->which);
  419. __format->width = rect.width;
  420. __format->height = rect.height;
  421. if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  422. mt9v032_configure_pixel_rate(mt9v032, 1);
  423. }
  424. *__crop = rect;
  425. crop->rect = rect;
  426. return 0;
  427. }
  428. /* -----------------------------------------------------------------------------
  429. * V4L2 subdev control operations
  430. */
  431. #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
  432. static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
  433. {
  434. struct mt9v032 *mt9v032 =
  435. container_of(ctrl->handler, struct mt9v032, ctrls);
  436. struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
  437. u32 freq;
  438. u16 data;
  439. switch (ctrl->id) {
  440. case V4L2_CID_AUTOGAIN:
  441. return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
  442. ctrl->val);
  443. case V4L2_CID_GAIN:
  444. return mt9v032_write(client, MT9V032_ANALOG_GAIN, ctrl->val);
  445. case V4L2_CID_EXPOSURE_AUTO:
  446. return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
  447. !ctrl->val);
  448. case V4L2_CID_EXPOSURE:
  449. return mt9v032_write(client, MT9V032_TOTAL_SHUTTER_WIDTH,
  450. ctrl->val);
  451. case V4L2_CID_HBLANK:
  452. mt9v032->hblank = ctrl->val;
  453. return mt9v032_update_hblank(mt9v032);
  454. case V4L2_CID_VBLANK:
  455. return mt9v032_write(client, MT9V032_VERTICAL_BLANKING,
  456. ctrl->val);
  457. case V4L2_CID_PIXEL_RATE:
  458. case V4L2_CID_LINK_FREQ:
  459. if (mt9v032->link_freq == NULL)
  460. break;
  461. freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
  462. mt9v032->pixel_rate->val64 = freq;
  463. mt9v032->sysclk = freq;
  464. break;
  465. case V4L2_CID_TEST_PATTERN:
  466. switch (mt9v032->test_pattern->val) {
  467. case 0:
  468. data = 0;
  469. break;
  470. case 1:
  471. data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
  472. | MT9V032_TEST_PATTERN_ENABLE;
  473. break;
  474. case 2:
  475. data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
  476. | MT9V032_TEST_PATTERN_ENABLE;
  477. break;
  478. case 3:
  479. data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
  480. | MT9V032_TEST_PATTERN_ENABLE;
  481. break;
  482. default:
  483. data = (mt9v032->test_pattern_color->val <<
  484. MT9V032_TEST_PATTERN_DATA_SHIFT)
  485. | MT9V032_TEST_PATTERN_USE_DATA
  486. | MT9V032_TEST_PATTERN_ENABLE
  487. | MT9V032_TEST_PATTERN_FLIP;
  488. break;
  489. }
  490. return mt9v032_write(client, MT9V032_TEST_PATTERN, data);
  491. }
  492. return 0;
  493. }
  494. static struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
  495. .s_ctrl = mt9v032_s_ctrl,
  496. };
  497. static const char * const mt9v032_test_pattern_menu[] = {
  498. "Disabled",
  499. "Gray Vertical Shade",
  500. "Gray Horizontal Shade",
  501. "Gray Diagonal Shade",
  502. "Plain",
  503. };
  504. static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
  505. .ops = &mt9v032_ctrl_ops,
  506. .id = V4L2_CID_TEST_PATTERN_COLOR,
  507. .type = V4L2_CTRL_TYPE_INTEGER,
  508. .name = "Test Pattern Color",
  509. .min = 0,
  510. .max = 1023,
  511. .step = 1,
  512. .def = 0,
  513. .flags = 0,
  514. };
  515. /* -----------------------------------------------------------------------------
  516. * V4L2 subdev core operations
  517. */
  518. static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
  519. {
  520. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  521. int ret = 0;
  522. mutex_lock(&mt9v032->power_lock);
  523. /* If the power count is modified from 0 to != 0 or from != 0 to 0,
  524. * update the power state.
  525. */
  526. if (mt9v032->power_count == !on) {
  527. ret = __mt9v032_set_power(mt9v032, !!on);
  528. if (ret < 0)
  529. goto done;
  530. }
  531. /* Update the power count. */
  532. mt9v032->power_count += on ? 1 : -1;
  533. WARN_ON(mt9v032->power_count < 0);
  534. done:
  535. mutex_unlock(&mt9v032->power_lock);
  536. return ret;
  537. }
  538. /* -----------------------------------------------------------------------------
  539. * V4L2 subdev internal operations
  540. */
  541. static int mt9v032_registered(struct v4l2_subdev *subdev)
  542. {
  543. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  544. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  545. s32 data;
  546. int ret;
  547. dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
  548. client->addr);
  549. ret = mt9v032_power_on(mt9v032);
  550. if (ret < 0) {
  551. dev_err(&client->dev, "MT9V032 power up failed\n");
  552. return ret;
  553. }
  554. /* Read and check the sensor version */
  555. data = mt9v032_read(client, MT9V032_CHIP_VERSION);
  556. if (data != MT9V032_CHIP_ID_REV1 && data != MT9V032_CHIP_ID_REV3) {
  557. dev_err(&client->dev, "MT9V032 not detected, wrong version "
  558. "0x%04x\n", data);
  559. return -ENODEV;
  560. }
  561. mt9v032_power_off(mt9v032);
  562. dev_info(&client->dev, "MT9V032 detected at address 0x%02x\n",
  563. client->addr);
  564. mt9v032_configure_pixel_rate(mt9v032, 1);
  565. return ret;
  566. }
  567. static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  568. {
  569. struct v4l2_mbus_framefmt *format;
  570. struct v4l2_rect *crop;
  571. crop = v4l2_subdev_get_try_crop(fh, 0);
  572. crop->left = MT9V032_COLUMN_START_DEF;
  573. crop->top = MT9V032_ROW_START_DEF;
  574. crop->width = MT9V032_WINDOW_WIDTH_DEF;
  575. crop->height = MT9V032_WINDOW_HEIGHT_DEF;
  576. format = v4l2_subdev_get_try_format(fh, 0);
  577. format->code = V4L2_MBUS_FMT_SGRBG10_1X10;
  578. format->width = MT9V032_WINDOW_WIDTH_DEF;
  579. format->height = MT9V032_WINDOW_HEIGHT_DEF;
  580. format->field = V4L2_FIELD_NONE;
  581. format->colorspace = V4L2_COLORSPACE_SRGB;
  582. return mt9v032_set_power(subdev, 1);
  583. }
  584. static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  585. {
  586. return mt9v032_set_power(subdev, 0);
  587. }
  588. static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
  589. .s_power = mt9v032_set_power,
  590. };
  591. static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
  592. .s_stream = mt9v032_s_stream,
  593. };
  594. static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
  595. .enum_mbus_code = mt9v032_enum_mbus_code,
  596. .enum_frame_size = mt9v032_enum_frame_size,
  597. .get_fmt = mt9v032_get_format,
  598. .set_fmt = mt9v032_set_format,
  599. .get_crop = mt9v032_get_crop,
  600. .set_crop = mt9v032_set_crop,
  601. };
  602. static struct v4l2_subdev_ops mt9v032_subdev_ops = {
  603. .core = &mt9v032_subdev_core_ops,
  604. .video = &mt9v032_subdev_video_ops,
  605. .pad = &mt9v032_subdev_pad_ops,
  606. };
  607. static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
  608. .registered = mt9v032_registered,
  609. .open = mt9v032_open,
  610. .close = mt9v032_close,
  611. };
  612. /* -----------------------------------------------------------------------------
  613. * Driver initialization and probing
  614. */
  615. static int mt9v032_probe(struct i2c_client *client,
  616. const struct i2c_device_id *did)
  617. {
  618. struct mt9v032_platform_data *pdata = client->dev.platform_data;
  619. struct mt9v032 *mt9v032;
  620. unsigned int i;
  621. int ret;
  622. if (!i2c_check_functionality(client->adapter,
  623. I2C_FUNC_SMBUS_WORD_DATA)) {
  624. dev_warn(&client->adapter->dev,
  625. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
  626. return -EIO;
  627. }
  628. mt9v032 = kzalloc(sizeof(*mt9v032), GFP_KERNEL);
  629. if (!mt9v032)
  630. return -ENOMEM;
  631. mutex_init(&mt9v032->power_lock);
  632. mt9v032->pdata = pdata;
  633. v4l2_ctrl_handler_init(&mt9v032->ctrls, 10);
  634. v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  635. V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
  636. v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  637. V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
  638. MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
  639. v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  640. V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
  641. V4L2_EXPOSURE_AUTO);
  642. v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  643. V4L2_CID_EXPOSURE, MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
  644. MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1,
  645. MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
  646. v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  647. V4L2_CID_HBLANK, MT9V032_HORIZONTAL_BLANKING_MIN,
  648. MT9V032_HORIZONTAL_BLANKING_MAX, 1,
  649. MT9V032_HORIZONTAL_BLANKING_DEF);
  650. v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  651. V4L2_CID_VBLANK, MT9V032_VERTICAL_BLANKING_MIN,
  652. MT9V032_VERTICAL_BLANKING_MAX, 1,
  653. MT9V032_VERTICAL_BLANKING_DEF);
  654. mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
  655. &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
  656. ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
  657. mt9v032_test_pattern_menu);
  658. mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
  659. &mt9v032_test_pattern_color, NULL);
  660. v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
  661. mt9v032->pixel_rate =
  662. v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
  663. V4L2_CID_PIXEL_RATE, 0, 0, 1, 0);
  664. if (pdata && pdata->link_freqs) {
  665. unsigned int def = 0;
  666. for (i = 0; pdata->link_freqs[i]; ++i) {
  667. if (pdata->link_freqs[i] == pdata->link_def_freq)
  668. def = i;
  669. }
  670. mt9v032->link_freq =
  671. v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
  672. &mt9v032_ctrl_ops,
  673. V4L2_CID_LINK_FREQ, i - 1, def,
  674. pdata->link_freqs);
  675. v4l2_ctrl_cluster(2, &mt9v032->link_freq);
  676. }
  677. mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
  678. if (mt9v032->ctrls.error)
  679. printk(KERN_INFO "%s: control initialization error %d\n",
  680. __func__, mt9v032->ctrls.error);
  681. mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
  682. mt9v032->crop.top = MT9V032_ROW_START_DEF;
  683. mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
  684. mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
  685. mt9v032->format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
  686. mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
  687. mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
  688. mt9v032->format.field = V4L2_FIELD_NONE;
  689. mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
  690. mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
  691. mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
  692. mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
  693. v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
  694. mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
  695. mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  696. mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
  697. ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0);
  698. if (ret < 0)
  699. kfree(mt9v032);
  700. return ret;
  701. }
  702. static int mt9v032_remove(struct i2c_client *client)
  703. {
  704. struct v4l2_subdev *subdev = i2c_get_clientdata(client);
  705. struct mt9v032 *mt9v032 = to_mt9v032(subdev);
  706. v4l2_device_unregister_subdev(subdev);
  707. media_entity_cleanup(&subdev->entity);
  708. kfree(mt9v032);
  709. return 0;
  710. }
  711. static const struct i2c_device_id mt9v032_id[] = {
  712. { "mt9v032", 0 },
  713. { }
  714. };
  715. MODULE_DEVICE_TABLE(i2c, mt9v032_id);
  716. static struct i2c_driver mt9v032_driver = {
  717. .driver = {
  718. .name = "mt9v032",
  719. },
  720. .probe = mt9v032_probe,
  721. .remove = mt9v032_remove,
  722. .id_table = mt9v032_id,
  723. };
  724. module_i2c_driver(mt9v032_driver);
  725. MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
  726. MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
  727. MODULE_LICENSE("GPL");