adv7343.c 13 KB

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  1. /*
  2. * adv7343 - ADV7343 Video Encoder Driver
  3. *
  4. * The encoder hardware does not support SECAM.
  5. *
  6. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/ctype.h>
  20. #include <linux/slab.h>
  21. #include <linux/i2c.h>
  22. #include <linux/device.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <linux/videodev2.h>
  26. #include <linux/uaccess.h>
  27. #include <media/adv7343.h>
  28. #include <media/v4l2-device.h>
  29. #include <media/v4l2-chip-ident.h>
  30. #include <media/v4l2-ctrls.h>
  31. #include "adv7343_regs.h"
  32. MODULE_DESCRIPTION("ADV7343 video encoder driver");
  33. MODULE_LICENSE("GPL");
  34. static int debug;
  35. module_param(debug, int, 0644);
  36. MODULE_PARM_DESC(debug, "Debug level 0-1");
  37. struct adv7343_state {
  38. struct v4l2_subdev sd;
  39. struct v4l2_ctrl_handler hdl;
  40. const struct adv7343_platform_data *pdata;
  41. u8 reg00;
  42. u8 reg01;
  43. u8 reg02;
  44. u8 reg35;
  45. u8 reg80;
  46. u8 reg82;
  47. u32 output;
  48. v4l2_std_id std;
  49. };
  50. static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
  51. {
  52. return container_of(sd, struct adv7343_state, sd);
  53. }
  54. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  55. {
  56. return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
  57. }
  58. static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  59. {
  60. struct i2c_client *client = v4l2_get_subdevdata(sd);
  61. return i2c_smbus_write_byte_data(client, reg, value);
  62. }
  63. static const u8 adv7343_init_reg_val[] = {
  64. ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
  65. ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
  66. ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
  67. ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
  68. ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
  69. ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
  70. ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
  71. ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
  72. ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
  73. ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
  74. ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
  75. ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
  76. ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
  77. ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
  78. ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
  79. ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
  80. ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
  81. ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
  82. ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
  83. ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
  84. };
  85. /*
  86. * 2^32
  87. * FSC(reg) = FSC (HZ) * --------
  88. * 27000000
  89. */
  90. static const struct adv7343_std_info stdinfo[] = {
  91. {
  92. /* FSC(Hz) = 3,579,545.45 Hz */
  93. SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
  94. }, {
  95. /* FSC(Hz) = 3,575,611.00 Hz */
  96. SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
  97. }, {
  98. /* FSC(Hz) = 3,582,056.00 */
  99. SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
  100. }, {
  101. /* FSC(Hz) = 4,433,618.75 Hz */
  102. SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
  103. }, {
  104. /* FSC(Hz) = 4,433,618.75 Hz */
  105. SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
  106. }, {
  107. /* FSC(Hz) = 4,433,618.75 Hz */
  108. SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
  109. }, {
  110. /* FSC(Hz) = 4,433,618.75 Hz */
  111. SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
  112. },
  113. };
  114. static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
  115. {
  116. struct adv7343_state *state = to_state(sd);
  117. struct adv7343_std_info *std_info;
  118. int num_std;
  119. char *fsc_ptr;
  120. u8 reg, val;
  121. int err = 0;
  122. int i = 0;
  123. std_info = (struct adv7343_std_info *)stdinfo;
  124. num_std = ARRAY_SIZE(stdinfo);
  125. for (i = 0; i < num_std; i++) {
  126. if (std_info[i].stdid & std)
  127. break;
  128. }
  129. if (i == num_std) {
  130. v4l2_dbg(1, debug, sd,
  131. "Invalid std or std is not supported: %llx\n",
  132. (unsigned long long)std);
  133. return -EINVAL;
  134. }
  135. /* Set the standard */
  136. val = state->reg80 & (~(SD_STD_MASK));
  137. val |= std_info[i].standard_val3;
  138. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  139. if (err < 0)
  140. goto setstd_exit;
  141. state->reg80 = val;
  142. /* Configure the input mode register */
  143. val = state->reg01 & (~((u8) INPUT_MODE_MASK));
  144. val |= SD_INPUT_MODE;
  145. err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
  146. if (err < 0)
  147. goto setstd_exit;
  148. state->reg01 = val;
  149. /* Program the sub carrier frequency registers */
  150. fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
  151. reg = ADV7343_FSC_REG0;
  152. for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
  153. err = adv7343_write(sd, reg, *fsc_ptr);
  154. if (err < 0)
  155. goto setstd_exit;
  156. }
  157. val = state->reg80;
  158. /* Filter settings */
  159. if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
  160. val &= 0x03;
  161. else if (std & ~V4L2_STD_SECAM)
  162. val |= 0x04;
  163. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  164. if (err < 0)
  165. goto setstd_exit;
  166. state->reg80 = val;
  167. setstd_exit:
  168. if (err != 0)
  169. v4l2_err(sd, "Error setting std, write failed\n");
  170. return err;
  171. }
  172. static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
  173. {
  174. struct adv7343_state *state = to_state(sd);
  175. unsigned char val;
  176. int err = 0;
  177. if (output_type > ADV7343_SVIDEO_ID) {
  178. v4l2_dbg(1, debug, sd,
  179. "Invalid output type or output type not supported:%d\n",
  180. output_type);
  181. return -EINVAL;
  182. }
  183. /* Enable Appropriate DAC */
  184. val = state->reg00 & 0x03;
  185. /* configure default configuration */
  186. if (!state->pdata)
  187. if (output_type == ADV7343_COMPOSITE_ID)
  188. val |= ADV7343_COMPOSITE_POWER_VALUE;
  189. else if (output_type == ADV7343_COMPONENT_ID)
  190. val |= ADV7343_COMPONENT_POWER_VALUE;
  191. else
  192. val |= ADV7343_SVIDEO_POWER_VALUE;
  193. else
  194. val = state->pdata->mode_config.sleep_mode << 0 |
  195. state->pdata->mode_config.pll_control << 1 |
  196. state->pdata->mode_config.dac_3 << 2 |
  197. state->pdata->mode_config.dac_2 << 3 |
  198. state->pdata->mode_config.dac_1 << 4 |
  199. state->pdata->mode_config.dac_6 << 5 |
  200. state->pdata->mode_config.dac_5 << 6 |
  201. state->pdata->mode_config.dac_4 << 7;
  202. err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
  203. if (err < 0)
  204. goto setoutput_exit;
  205. state->reg00 = val;
  206. /* Enable YUV output */
  207. val = state->reg02 | YUV_OUTPUT_SELECT;
  208. err = adv7343_write(sd, ADV7343_MODE_REG0, val);
  209. if (err < 0)
  210. goto setoutput_exit;
  211. state->reg02 = val;
  212. /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
  213. val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
  214. if (state->pdata && state->pdata->sd_config.sd_dac_out1)
  215. val = val | (state->pdata->sd_config.sd_dac_out1 << 1);
  216. else if (state->pdata && !state->pdata->sd_config.sd_dac_out1)
  217. val = val & ~(state->pdata->sd_config.sd_dac_out1 << 1);
  218. if (state->pdata && state->pdata->sd_config.sd_dac_out2)
  219. val = val | (state->pdata->sd_config.sd_dac_out2 << 2);
  220. else if (state->pdata && !state->pdata->sd_config.sd_dac_out2)
  221. val = val & ~(state->pdata->sd_config.sd_dac_out2 << 2);
  222. err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
  223. if (err < 0)
  224. goto setoutput_exit;
  225. state->reg82 = val;
  226. /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
  227. * zero */
  228. val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
  229. err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
  230. if (err < 0)
  231. goto setoutput_exit;
  232. state->reg35 = val;
  233. setoutput_exit:
  234. if (err != 0)
  235. v4l2_err(sd, "Error setting output, write failed\n");
  236. return err;
  237. }
  238. static int adv7343_log_status(struct v4l2_subdev *sd)
  239. {
  240. struct adv7343_state *state = to_state(sd);
  241. v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
  242. v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
  243. ((state->output == 1) ? "Component" : "S-Video"));
  244. return 0;
  245. }
  246. static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
  247. {
  248. struct v4l2_subdev *sd = to_sd(ctrl);
  249. switch (ctrl->id) {
  250. case V4L2_CID_BRIGHTNESS:
  251. return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
  252. ctrl->val);
  253. case V4L2_CID_HUE:
  254. return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
  255. case V4L2_CID_GAIN:
  256. return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
  257. }
  258. return -EINVAL;
  259. }
  260. static int adv7343_g_chip_ident(struct v4l2_subdev *sd,
  261. struct v4l2_dbg_chip_ident *chip)
  262. {
  263. struct i2c_client *client = v4l2_get_subdevdata(sd);
  264. return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7343, 0);
  265. }
  266. static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
  267. .s_ctrl = adv7343_s_ctrl,
  268. };
  269. static const struct v4l2_subdev_core_ops adv7343_core_ops = {
  270. .log_status = adv7343_log_status,
  271. .g_chip_ident = adv7343_g_chip_ident,
  272. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  273. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  274. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  275. .g_ctrl = v4l2_subdev_g_ctrl,
  276. .s_ctrl = v4l2_subdev_s_ctrl,
  277. .queryctrl = v4l2_subdev_queryctrl,
  278. .querymenu = v4l2_subdev_querymenu,
  279. };
  280. static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
  281. {
  282. struct adv7343_state *state = to_state(sd);
  283. int err = 0;
  284. if (state->std == std)
  285. return 0;
  286. err = adv7343_setstd(sd, std);
  287. if (!err)
  288. state->std = std;
  289. return err;
  290. }
  291. static int adv7343_s_routing(struct v4l2_subdev *sd,
  292. u32 input, u32 output, u32 config)
  293. {
  294. struct adv7343_state *state = to_state(sd);
  295. int err = 0;
  296. if (state->output == output)
  297. return 0;
  298. err = adv7343_setoutput(sd, output);
  299. if (!err)
  300. state->output = output;
  301. return err;
  302. }
  303. static const struct v4l2_subdev_video_ops adv7343_video_ops = {
  304. .s_std_output = adv7343_s_std_output,
  305. .s_routing = adv7343_s_routing,
  306. };
  307. static const struct v4l2_subdev_ops adv7343_ops = {
  308. .core = &adv7343_core_ops,
  309. .video = &adv7343_video_ops,
  310. };
  311. static int adv7343_initialize(struct v4l2_subdev *sd)
  312. {
  313. struct adv7343_state *state = to_state(sd);
  314. int err = 0;
  315. int i;
  316. for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
  317. err = adv7343_write(sd, adv7343_init_reg_val[i],
  318. adv7343_init_reg_val[i+1]);
  319. if (err) {
  320. v4l2_err(sd, "Error initializing\n");
  321. return err;
  322. }
  323. }
  324. /* Configure for default video standard */
  325. err = adv7343_setoutput(sd, state->output);
  326. if (err < 0) {
  327. v4l2_err(sd, "Error setting output during init\n");
  328. return -EINVAL;
  329. }
  330. err = adv7343_setstd(sd, state->std);
  331. if (err < 0) {
  332. v4l2_err(sd, "Error setting std during init\n");
  333. return -EINVAL;
  334. }
  335. return err;
  336. }
  337. static int adv7343_probe(struct i2c_client *client,
  338. const struct i2c_device_id *id)
  339. {
  340. struct adv7343_state *state;
  341. int err;
  342. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  343. return -ENODEV;
  344. v4l_info(client, "chip found @ 0x%x (%s)\n",
  345. client->addr << 1, client->adapter->name);
  346. state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
  347. GFP_KERNEL);
  348. if (state == NULL)
  349. return -ENOMEM;
  350. /* Copy board specific information here */
  351. state->pdata = client->dev.platform_data;
  352. state->reg00 = 0x80;
  353. state->reg01 = 0x00;
  354. state->reg02 = 0x20;
  355. state->reg35 = 0x00;
  356. state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
  357. state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
  358. state->output = ADV7343_COMPOSITE_ID;
  359. state->std = V4L2_STD_NTSC;
  360. v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
  361. v4l2_ctrl_handler_init(&state->hdl, 2);
  362. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  363. V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
  364. ADV7343_BRIGHTNESS_MAX, 1,
  365. ADV7343_BRIGHTNESS_DEF);
  366. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  367. V4L2_CID_HUE, ADV7343_HUE_MIN,
  368. ADV7343_HUE_MAX, 1,
  369. ADV7343_HUE_DEF);
  370. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  371. V4L2_CID_GAIN, ADV7343_GAIN_MIN,
  372. ADV7343_GAIN_MAX, 1,
  373. ADV7343_GAIN_DEF);
  374. state->sd.ctrl_handler = &state->hdl;
  375. if (state->hdl.error) {
  376. int err = state->hdl.error;
  377. v4l2_ctrl_handler_free(&state->hdl);
  378. return err;
  379. }
  380. v4l2_ctrl_handler_setup(&state->hdl);
  381. err = adv7343_initialize(&state->sd);
  382. if (err)
  383. v4l2_ctrl_handler_free(&state->hdl);
  384. return err;
  385. }
  386. static int adv7343_remove(struct i2c_client *client)
  387. {
  388. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  389. struct adv7343_state *state = to_state(sd);
  390. v4l2_device_unregister_subdev(sd);
  391. v4l2_ctrl_handler_free(&state->hdl);
  392. return 0;
  393. }
  394. static const struct i2c_device_id adv7343_id[] = {
  395. {"adv7343", 0},
  396. {},
  397. };
  398. MODULE_DEVICE_TABLE(i2c, adv7343_id);
  399. static struct i2c_driver adv7343_driver = {
  400. .driver = {
  401. .owner = THIS_MODULE,
  402. .name = "adv7343",
  403. },
  404. .probe = adv7343_probe,
  405. .remove = adv7343_remove,
  406. .id_table = adv7343_id,
  407. };
  408. module_i2c_driver(adv7343_driver);