tda18271c2dd.c 29 KB

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  1. /*
  2. * tda18271c2dd: Driver for the TDA18271C2 tuner
  3. *
  4. * Copyright (C) 2010 Digital Devices GmbH
  5. *
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 only, as published by the Free Software Foundation.
  10. *
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  21. * 02110-1301, USA
  22. * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/init.h>
  28. #include <linux/delay.h>
  29. #include <linux/firmware.h>
  30. #include <linux/i2c.h>
  31. #include <asm/div64.h>
  32. #include "dvb_frontend.h"
  33. #include "tda18271c2dd.h"
  34. struct SStandardParam {
  35. s32 m_IFFrequency;
  36. u32 m_BandWidth;
  37. u8 m_EP3_4_0;
  38. u8 m_EB22;
  39. };
  40. struct SMap {
  41. u32 m_Frequency;
  42. u8 m_Param;
  43. };
  44. struct SMapI {
  45. u32 m_Frequency;
  46. s32 m_Param;
  47. };
  48. struct SMap2 {
  49. u32 m_Frequency;
  50. u8 m_Param1;
  51. u8 m_Param2;
  52. };
  53. struct SRFBandMap {
  54. u32 m_RF_max;
  55. u32 m_RF1_Default;
  56. u32 m_RF2_Default;
  57. u32 m_RF3_Default;
  58. };
  59. enum ERegister {
  60. ID = 0,
  61. TM,
  62. PL,
  63. EP1, EP2, EP3, EP4, EP5,
  64. CPD, CD1, CD2, CD3,
  65. MPD, MD1, MD2, MD3,
  66. EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10,
  67. EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20,
  68. EB21, EB22, EB23,
  69. NUM_REGS
  70. };
  71. struct tda_state {
  72. struct i2c_adapter *i2c;
  73. u8 adr;
  74. u32 m_Frequency;
  75. u32 IF;
  76. u8 m_IFLevelAnalog;
  77. u8 m_IFLevelDigital;
  78. u8 m_IFLevelDVBC;
  79. u8 m_IFLevelDVBT;
  80. u8 m_EP4;
  81. u8 m_EP3_Standby;
  82. bool m_bMaster;
  83. s32 m_SettlingTime;
  84. u8 m_Regs[NUM_REGS];
  85. /* Tracking filter settings for band 0..6 */
  86. u32 m_RF1[7];
  87. s32 m_RF_A1[7];
  88. s32 m_RF_B1[7];
  89. u32 m_RF2[7];
  90. s32 m_RF_A2[7];
  91. s32 m_RF_B2[7];
  92. u32 m_RF3[7];
  93. u8 m_TMValue_RFCal; /* Calibration temperatur */
  94. bool m_bFMInput; /* true to use Pin 8 for FM Radio */
  95. };
  96. static int PowerScan(struct tda_state *state,
  97. u8 RFBand, u32 RF_in,
  98. u32 *pRF_Out, bool *pbcal);
  99. static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
  100. {
  101. struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
  102. .buf = data, .len = len} };
  103. return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
  104. }
  105. static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
  106. {
  107. struct i2c_msg msg = {.addr = adr, .flags = 0,
  108. .buf = data, .len = len};
  109. if (i2c_transfer(adap, &msg, 1) != 1) {
  110. printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr);
  111. return -1;
  112. }
  113. return 0;
  114. }
  115. static int WriteRegs(struct tda_state *state,
  116. u8 SubAddr, u8 *Regs, u16 nRegs)
  117. {
  118. u8 data[nRegs+1];
  119. data[0] = SubAddr;
  120. memcpy(data + 1, Regs, nRegs);
  121. return i2c_write(state->i2c, state->adr, data, nRegs+1);
  122. }
  123. static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg)
  124. {
  125. u8 msg[2] = {SubAddr, Reg};
  126. return i2c_write(state->i2c, state->adr, msg, 2);
  127. }
  128. static int Read(struct tda_state *state, u8 * Regs)
  129. {
  130. return i2c_readn(state->i2c, state->adr, Regs, 16);
  131. }
  132. static int ReadExtented(struct tda_state *state, u8 * Regs)
  133. {
  134. return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
  135. }
  136. static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo)
  137. {
  138. return WriteRegs(state, RegFrom,
  139. &state->m_Regs[RegFrom], RegTo-RegFrom+1);
  140. }
  141. static int UpdateReg(struct tda_state *state, u8 Reg)
  142. {
  143. return WriteReg(state, Reg, state->m_Regs[Reg]);
  144. }
  145. #include "tda18271c2dd_maps.h"
  146. static void reset(struct tda_state *state)
  147. {
  148. u32 ulIFLevelAnalog = 0;
  149. u32 ulIFLevelDigital = 2;
  150. u32 ulIFLevelDVBC = 7;
  151. u32 ulIFLevelDVBT = 6;
  152. u32 ulXTOut = 0;
  153. u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */
  154. u32 ulSlave = 0;
  155. u32 ulFMInput = 0;
  156. u32 ulSettlingTime = 100;
  157. state->m_Frequency = 0;
  158. state->m_SettlingTime = 100;
  159. state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;
  160. state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;
  161. state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;
  162. state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
  163. state->m_EP4 = 0x20;
  164. if (ulXTOut != 0)
  165. state->m_EP4 |= 0x40;
  166. state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
  167. state->m_bMaster = (ulSlave == 0);
  168. state->m_SettlingTime = ulSettlingTime;
  169. state->m_bFMInput = (ulFMInput == 2);
  170. }
  171. static bool SearchMap1(struct SMap Map[],
  172. u32 Frequency, u8 *pParam)
  173. {
  174. int i = 0;
  175. while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency))
  176. i += 1;
  177. if (Map[i].m_Frequency == 0)
  178. return false;
  179. *pParam = Map[i].m_Param;
  180. return true;
  181. }
  182. static bool SearchMap2(struct SMapI Map[],
  183. u32 Frequency, s32 *pParam)
  184. {
  185. int i = 0;
  186. while ((Map[i].m_Frequency != 0) &&
  187. (Frequency > Map[i].m_Frequency))
  188. i += 1;
  189. if (Map[i].m_Frequency == 0)
  190. return false;
  191. *pParam = Map[i].m_Param;
  192. return true;
  193. }
  194. static bool SearchMap3(struct SMap2 Map[], u32 Frequency,
  195. u8 *pParam1, u8 *pParam2)
  196. {
  197. int i = 0;
  198. while ((Map[i].m_Frequency != 0) &&
  199. (Frequency > Map[i].m_Frequency))
  200. i += 1;
  201. if (Map[i].m_Frequency == 0)
  202. return false;
  203. *pParam1 = Map[i].m_Param1;
  204. *pParam2 = Map[i].m_Param2;
  205. return true;
  206. }
  207. static bool SearchMap4(struct SRFBandMap Map[],
  208. u32 Frequency, u8 *pRFBand)
  209. {
  210. int i = 0;
  211. while (i < 7 && (Frequency > Map[i].m_RF_max))
  212. i += 1;
  213. if (i == 7)
  214. return false;
  215. *pRFBand = i;
  216. return true;
  217. }
  218. static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
  219. {
  220. int status = 0;
  221. do {
  222. u8 Regs[16];
  223. state->m_Regs[TM] |= 0x10;
  224. status = UpdateReg(state, TM);
  225. if (status < 0)
  226. break;
  227. status = Read(state, Regs);
  228. if (status < 0)
  229. break;
  230. if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) ||
  231. ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) {
  232. state->m_Regs[TM] ^= 0x20;
  233. status = UpdateReg(state, TM);
  234. if (status < 0)
  235. break;
  236. msleep(10);
  237. status = Read(state, Regs);
  238. if (status < 0)
  239. break;
  240. }
  241. *pTM_Value = (Regs[TM] & 0x20)
  242. ? m_Thermometer_Map_2[Regs[TM] & 0x0F]
  243. : m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
  244. state->m_Regs[TM] &= ~0x10; /* Thermometer off */
  245. status = UpdateReg(state, TM);
  246. if (status < 0)
  247. break;
  248. state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */
  249. status = UpdateReg(state, EP4);
  250. if (status < 0)
  251. break;
  252. } while (0);
  253. return status;
  254. }
  255. static int StandBy(struct tda_state *state)
  256. {
  257. int status = 0;
  258. do {
  259. state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */
  260. status = UpdateReg(state, EB12);
  261. if (status < 0)
  262. break;
  263. state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */
  264. status = UpdateReg(state, EB18);
  265. if (status < 0)
  266. break;
  267. state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */
  268. state->m_Regs[EP3] = state->m_EP3_Standby;
  269. status = UpdateReg(state, EP3);
  270. if (status < 0)
  271. break;
  272. state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */
  273. status = UpdateRegs(state, EB21, EB23);
  274. if (status < 0)
  275. break;
  276. } while (0);
  277. return status;
  278. }
  279. static int CalcMainPLL(struct tda_state *state, u32 freq)
  280. {
  281. u8 PostDiv;
  282. u8 Div;
  283. u64 OscFreq;
  284. u32 MainDiv;
  285. if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div))
  286. return -EINVAL;
  287. OscFreq = (u64) freq * (u64) Div;
  288. OscFreq *= (u64) 16384;
  289. do_div(OscFreq, (u64)16000000);
  290. MainDiv = OscFreq;
  291. state->m_Regs[MPD] = PostDiv & 0x77;
  292. state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
  293. state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
  294. state->m_Regs[MD3] = (MainDiv & 0xFF);
  295. return UpdateRegs(state, MPD, MD3);
  296. }
  297. static int CalcCalPLL(struct tda_state *state, u32 freq)
  298. {
  299. u8 PostDiv;
  300. u8 Div;
  301. u64 OscFreq;
  302. u32 CalDiv;
  303. if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div))
  304. return -EINVAL;
  305. OscFreq = (u64)freq * (u64)Div;
  306. /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */
  307. OscFreq *= (u64)16384;
  308. do_div(OscFreq, (u64)16000000);
  309. CalDiv = OscFreq;
  310. state->m_Regs[CPD] = PostDiv;
  311. state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
  312. state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
  313. state->m_Regs[CD3] = (CalDiv & 0xFF);
  314. return UpdateRegs(state, CPD, CD3);
  315. }
  316. static int CalibrateRF(struct tda_state *state,
  317. u8 RFBand, u32 freq, s32 *pCprog)
  318. {
  319. int status = 0;
  320. u8 Regs[NUM_REGS];
  321. do {
  322. u8 BP_Filter = 0;
  323. u8 GainTaper = 0;
  324. u8 RFC_K = 0;
  325. u8 RFC_M = 0;
  326. state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */
  327. status = UpdateReg(state, EP4);
  328. if (status < 0)
  329. break;
  330. state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */
  331. status = UpdateReg(state, EB18);
  332. if (status < 0)
  333. break;
  334. /* Switching off LT (as datasheet says) causes calibration on C1 to fail */
  335. /* (Readout of Cprog is allways 255) */
  336. if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */
  337. state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */
  338. if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) &&
  339. SearchMap1(m_GainTaper_Map, freq, &GainTaper) &&
  340. SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M)))
  341. return -EINVAL;
  342. state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
  343. state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
  344. state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
  345. status = UpdateRegs(state, EP1, EP3);
  346. if (status < 0)
  347. break;
  348. status = UpdateReg(state, EB13);
  349. if (status < 0)
  350. break;
  351. state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */
  352. status = UpdateReg(state, EB4);
  353. if (status < 0)
  354. break;
  355. state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */
  356. status = UpdateReg(state, EB7);
  357. if (status < 0)
  358. break;
  359. state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */
  360. status = UpdateReg(state, EB14);
  361. if (status < 0)
  362. break;
  363. state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */
  364. status = UpdateReg(state, EB20);
  365. if (status < 0)
  366. break;
  367. state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */
  368. status = UpdateRegs(state, EP4, EP5);
  369. if (status < 0)
  370. break;
  371. status = CalcCalPLL(state, freq);
  372. if (status < 0)
  373. break;
  374. status = CalcMainPLL(state, freq + 1000000);
  375. if (status < 0)
  376. break;
  377. msleep(5);
  378. status = UpdateReg(state, EP2);
  379. if (status < 0)
  380. break;
  381. status = UpdateReg(state, EP1);
  382. if (status < 0)
  383. break;
  384. status = UpdateReg(state, EP2);
  385. if (status < 0)
  386. break;
  387. status = UpdateReg(state, EP1);
  388. if (status < 0)
  389. break;
  390. state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */
  391. status = UpdateReg(state, EB4);
  392. if (status < 0)
  393. break;
  394. state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */
  395. status = UpdateReg(state, EB7);
  396. if (status < 0)
  397. break;
  398. msleep(10);
  399. state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */
  400. status = UpdateReg(state, EB20);
  401. if (status < 0)
  402. break;
  403. msleep(60);
  404. state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */
  405. state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */
  406. state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */
  407. status = UpdateReg(state, EB18);
  408. if (status < 0)
  409. break;
  410. status = UpdateRegs(state, EP3, EP4);
  411. if (status < 0)
  412. break;
  413. status = UpdateReg(state, EP1);
  414. if (status < 0)
  415. break;
  416. status = ReadExtented(state, Regs);
  417. if (status < 0)
  418. break;
  419. *pCprog = Regs[EB14];
  420. } while (0);
  421. return status;
  422. }
  423. static int RFTrackingFiltersInit(struct tda_state *state,
  424. u8 RFBand)
  425. {
  426. int status = 0;
  427. u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
  428. u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default;
  429. u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default;
  430. bool bcal = false;
  431. s32 Cprog_cal1 = 0;
  432. s32 Cprog_table1 = 0;
  433. s32 Cprog_cal2 = 0;
  434. s32 Cprog_table2 = 0;
  435. s32 Cprog_cal3 = 0;
  436. s32 Cprog_table3 = 0;
  437. state->m_RF_A1[RFBand] = 0;
  438. state->m_RF_B1[RFBand] = 0;
  439. state->m_RF_A2[RFBand] = 0;
  440. state->m_RF_B2[RFBand] = 0;
  441. do {
  442. status = PowerScan(state, RFBand, RF1, &RF1, &bcal);
  443. if (status < 0)
  444. break;
  445. if (bcal) {
  446. status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1);
  447. if (status < 0)
  448. break;
  449. }
  450. SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1);
  451. if (!bcal)
  452. Cprog_cal1 = Cprog_table1;
  453. state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
  454. /* state->m_RF_A1[RF_Band] = ???? */
  455. if (RF2 == 0)
  456. break;
  457. status = PowerScan(state, RFBand, RF2, &RF2, &bcal);
  458. if (status < 0)
  459. break;
  460. if (bcal) {
  461. status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2);
  462. if (status < 0)
  463. break;
  464. }
  465. SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2);
  466. if (!bcal)
  467. Cprog_cal2 = Cprog_table2;
  468. state->m_RF_A1[RFBand] =
  469. (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
  470. ((s32)(RF2) - (s32)(RF1));
  471. if (RF3 == 0)
  472. break;
  473. status = PowerScan(state, RFBand, RF3, &RF3, &bcal);
  474. if (status < 0)
  475. break;
  476. if (bcal) {
  477. status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3);
  478. if (status < 0)
  479. break;
  480. }
  481. SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3);
  482. if (!bcal)
  483. Cprog_cal3 = Cprog_table3;
  484. state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2));
  485. state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
  486. } while (0);
  487. state->m_RF1[RFBand] = RF1;
  488. state->m_RF2[RFBand] = RF2;
  489. state->m_RF3[RFBand] = RF3;
  490. #if 0
  491. printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__,
  492. RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2,
  493. state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3);
  494. #endif
  495. return status;
  496. }
  497. static int PowerScan(struct tda_state *state,
  498. u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal)
  499. {
  500. int status = 0;
  501. do {
  502. u8 Gain_Taper = 0;
  503. s32 RFC_Cprog = 0;
  504. u8 CID_Target = 0;
  505. u8 CountLimit = 0;
  506. u32 freq_MainPLL;
  507. u8 Regs[NUM_REGS];
  508. u8 CID_Gain;
  509. s32 Count = 0;
  510. int sign = 1;
  511. bool wait = false;
  512. if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) &&
  513. SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) &&
  514. SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) {
  515. printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__);
  516. return -EINVAL;
  517. }
  518. state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
  519. state->m_Regs[EB14] = (RFC_Cprog);
  520. status = UpdateReg(state, EP2);
  521. if (status < 0)
  522. break;
  523. status = UpdateReg(state, EB14);
  524. if (status < 0)
  525. break;
  526. freq_MainPLL = RF_in + 1000000;
  527. status = CalcMainPLL(state, freq_MainPLL);
  528. if (status < 0)
  529. break;
  530. msleep(5);
  531. state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */
  532. status = UpdateReg(state, EP4);
  533. if (status < 0)
  534. break;
  535. status = UpdateReg(state, EP2); /* Launch power measurement */
  536. if (status < 0)
  537. break;
  538. status = ReadExtented(state, Regs);
  539. if (status < 0)
  540. break;
  541. CID_Gain = Regs[EB10] & 0x3F;
  542. state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */
  543. *pRF_Out = RF_in;
  544. while (CID_Gain < CID_Target) {
  545. freq_MainPLL = RF_in + sign * Count + 1000000;
  546. status = CalcMainPLL(state, freq_MainPLL);
  547. if (status < 0)
  548. break;
  549. msleep(wait ? 5 : 1);
  550. wait = false;
  551. status = UpdateReg(state, EP2); /* Launch power measurement */
  552. if (status < 0)
  553. break;
  554. status = ReadExtented(state, Regs);
  555. if (status < 0)
  556. break;
  557. CID_Gain = Regs[EB10] & 0x3F;
  558. Count += 200000;
  559. if (Count < CountLimit * 100000)
  560. continue;
  561. if (sign < 0)
  562. break;
  563. sign = -sign;
  564. Count = 200000;
  565. wait = true;
  566. }
  567. status = status;
  568. if (status < 0)
  569. break;
  570. if (CID_Gain >= CID_Target) {
  571. *pbcal = true;
  572. *pRF_Out = freq_MainPLL - 1000000;
  573. } else
  574. *pbcal = false;
  575. } while (0);
  576. return status;
  577. }
  578. static int PowerScanInit(struct tda_state *state)
  579. {
  580. int status = 0;
  581. do {
  582. state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
  583. state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */
  584. status = UpdateRegs(state, EP3, EP4);
  585. if (status < 0)
  586. break;
  587. state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */
  588. status = UpdateReg(state, EB18);
  589. if (status < 0)
  590. break;
  591. state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */
  592. state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
  593. status = UpdateRegs(state, EB21, EB23);
  594. if (status < 0)
  595. break;
  596. } while (0);
  597. return status;
  598. }
  599. static int CalcRFFilterCurve(struct tda_state *state)
  600. {
  601. int status = 0;
  602. do {
  603. msleep(200); /* Temperature stabilisation */
  604. status = PowerScanInit(state);
  605. if (status < 0)
  606. break;
  607. status = RFTrackingFiltersInit(state, 0);
  608. if (status < 0)
  609. break;
  610. status = RFTrackingFiltersInit(state, 1);
  611. if (status < 0)
  612. break;
  613. status = RFTrackingFiltersInit(state, 2);
  614. if (status < 0)
  615. break;
  616. status = RFTrackingFiltersInit(state, 3);
  617. if (status < 0)
  618. break;
  619. status = RFTrackingFiltersInit(state, 4);
  620. if (status < 0)
  621. break;
  622. status = RFTrackingFiltersInit(state, 5);
  623. if (status < 0)
  624. break;
  625. status = RFTrackingFiltersInit(state, 6);
  626. if (status < 0)
  627. break;
  628. status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */
  629. if (status < 0)
  630. break;
  631. } while (0);
  632. return status;
  633. }
  634. static int FixedContentsI2CUpdate(struct tda_state *state)
  635. {
  636. static u8 InitRegs[] = {
  637. 0x08, 0x80, 0xC6,
  638. 0xDF, 0x16, 0x60, 0x80,
  639. 0x80, 0x00, 0x00, 0x00,
  640. 0x00, 0x00, 0x00, 0x00,
  641. 0xFC, 0x01, 0x84, 0x41,
  642. 0x01, 0x84, 0x40, 0x07,
  643. 0x00, 0x00, 0x96, 0x3F,
  644. 0xC1, 0x00, 0x8F, 0x00,
  645. 0x00, 0x8C, 0x00, 0x20,
  646. 0xB3, 0x48, 0xB0,
  647. };
  648. int status = 0;
  649. memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1);
  650. do {
  651. status = UpdateRegs(state, TM, EB23);
  652. if (status < 0)
  653. break;
  654. /* AGC1 gain setup */
  655. state->m_Regs[EB17] = 0x00;
  656. status = UpdateReg(state, EB17);
  657. if (status < 0)
  658. break;
  659. state->m_Regs[EB17] = 0x03;
  660. status = UpdateReg(state, EB17);
  661. if (status < 0)
  662. break;
  663. state->m_Regs[EB17] = 0x43;
  664. status = UpdateReg(state, EB17);
  665. if (status < 0)
  666. break;
  667. state->m_Regs[EB17] = 0x4C;
  668. status = UpdateReg(state, EB17);
  669. if (status < 0)
  670. break;
  671. /* IRC Cal Low band */
  672. state->m_Regs[EP3] = 0x1F;
  673. state->m_Regs[EP4] = 0x66;
  674. state->m_Regs[EP5] = 0x81;
  675. state->m_Regs[CPD] = 0xCC;
  676. state->m_Regs[CD1] = 0x6C;
  677. state->m_Regs[CD2] = 0x00;
  678. state->m_Regs[CD3] = 0x00;
  679. state->m_Regs[MPD] = 0xC5;
  680. state->m_Regs[MD1] = 0x77;
  681. state->m_Regs[MD2] = 0x08;
  682. state->m_Regs[MD3] = 0x00;
  683. status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */
  684. if (status < 0)
  685. break;
  686. #if 0
  687. state->m_Regs[EB4] = 0x61; /* missing in sw */
  688. status = UpdateReg(state, EB4);
  689. if (status < 0)
  690. break;
  691. msleep(1);
  692. state->m_Regs[EB4] = 0x41;
  693. status = UpdateReg(state, EB4);
  694. if (status < 0)
  695. break;
  696. #endif
  697. msleep(5);
  698. status = UpdateReg(state, EP1);
  699. if (status < 0)
  700. break;
  701. msleep(5);
  702. state->m_Regs[EP5] = 0x85;
  703. state->m_Regs[CPD] = 0xCB;
  704. state->m_Regs[CD1] = 0x66;
  705. state->m_Regs[CD2] = 0x70;
  706. status = UpdateRegs(state, EP3, CD3);
  707. if (status < 0)
  708. break;
  709. msleep(5);
  710. status = UpdateReg(state, EP2);
  711. if (status < 0)
  712. break;
  713. msleep(30);
  714. /* IRC Cal mid band */
  715. state->m_Regs[EP5] = 0x82;
  716. state->m_Regs[CPD] = 0xA8;
  717. state->m_Regs[CD2] = 0x00;
  718. state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */
  719. state->m_Regs[MD1] = 0x73;
  720. state->m_Regs[MD2] = 0x1A;
  721. status = UpdateRegs(state, EP3, MD3);
  722. if (status < 0)
  723. break;
  724. msleep(5);
  725. status = UpdateReg(state, EP1);
  726. if (status < 0)
  727. break;
  728. msleep(5);
  729. state->m_Regs[EP5] = 0x86;
  730. state->m_Regs[CPD] = 0xA8;
  731. state->m_Regs[CD1] = 0x66;
  732. state->m_Regs[CD2] = 0xA0;
  733. status = UpdateRegs(state, EP3, CD3);
  734. if (status < 0)
  735. break;
  736. msleep(5);
  737. status = UpdateReg(state, EP2);
  738. if (status < 0)
  739. break;
  740. msleep(30);
  741. /* IRC Cal high band */
  742. state->m_Regs[EP5] = 0x83;
  743. state->m_Regs[CPD] = 0x98;
  744. state->m_Regs[CD1] = 0x65;
  745. state->m_Regs[CD2] = 0x00;
  746. state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */
  747. state->m_Regs[MD1] = 0x71;
  748. state->m_Regs[MD2] = 0xCD;
  749. status = UpdateRegs(state, EP3, MD3);
  750. if (status < 0)
  751. break;
  752. msleep(5);
  753. status = UpdateReg(state, EP1);
  754. if (status < 0)
  755. break;
  756. msleep(5);
  757. state->m_Regs[EP5] = 0x87;
  758. state->m_Regs[CD1] = 0x65;
  759. state->m_Regs[CD2] = 0x50;
  760. status = UpdateRegs(state, EP3, CD3);
  761. if (status < 0)
  762. break;
  763. msleep(5);
  764. status = UpdateReg(state, EP2);
  765. if (status < 0)
  766. break;
  767. msleep(30);
  768. /* Back to normal */
  769. state->m_Regs[EP4] = 0x64;
  770. status = UpdateReg(state, EP4);
  771. if (status < 0)
  772. break;
  773. status = UpdateReg(state, EP1);
  774. if (status < 0)
  775. break;
  776. } while (0);
  777. return status;
  778. }
  779. static int InitCal(struct tda_state *state)
  780. {
  781. int status = 0;
  782. do {
  783. status = FixedContentsI2CUpdate(state);
  784. if (status < 0)
  785. break;
  786. status = CalcRFFilterCurve(state);
  787. if (status < 0)
  788. break;
  789. status = StandBy(state);
  790. if (status < 0)
  791. break;
  792. /* m_bInitDone = true; */
  793. } while (0);
  794. return status;
  795. };
  796. static int RFTrackingFiltersCorrection(struct tda_state *state,
  797. u32 Frequency)
  798. {
  799. int status = 0;
  800. s32 Cprog_table;
  801. u8 RFBand;
  802. u8 dCoverdT;
  803. if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) ||
  804. !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) ||
  805. !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT))
  806. return -EINVAL;
  807. do {
  808. u8 TMValue_Current;
  809. u32 RF1 = state->m_RF1[RFBand];
  810. u32 RF2 = state->m_RF1[RFBand];
  811. u32 RF3 = state->m_RF1[RFBand];
  812. s32 RF_A1 = state->m_RF_A1[RFBand];
  813. s32 RF_B1 = state->m_RF_B1[RFBand];
  814. s32 RF_A2 = state->m_RF_A2[RFBand];
  815. s32 RF_B2 = state->m_RF_B2[RFBand];
  816. s32 Capprox = 0;
  817. int TComp;
  818. state->m_Regs[EP3] &= ~0xE0; /* Power up */
  819. status = UpdateReg(state, EP3);
  820. if (status < 0)
  821. break;
  822. status = ThermometerRead(state, &TMValue_Current);
  823. if (status < 0)
  824. break;
  825. if (RF3 == 0 || Frequency < RF2)
  826. Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
  827. else
  828. Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
  829. TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
  830. Capprox += TComp;
  831. if (Capprox < 0)
  832. Capprox = 0;
  833. else if (Capprox > 255)
  834. Capprox = 255;
  835. /* TODO Temperature compensation. There is defenitely a scale factor */
  836. /* missing in the datasheet, so leave it out for now. */
  837. state->m_Regs[EB14] = Capprox;
  838. status = UpdateReg(state, EB14);
  839. if (status < 0)
  840. break;
  841. } while (0);
  842. return status;
  843. }
  844. static int ChannelConfiguration(struct tda_state *state,
  845. u32 Frequency, int Standard)
  846. {
  847. s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency;
  848. int status = 0;
  849. u8 BP_Filter = 0;
  850. u8 RF_Band = 0;
  851. u8 GainTaper = 0;
  852. u8 IR_Meas = 0;
  853. state->IF = IntermediateFrequency;
  854. /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */
  855. /* get values from tables */
  856. if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) &&
  857. SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) &&
  858. SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) &&
  859. SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) {
  860. printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__);
  861. return -EINVAL;
  862. }
  863. do {
  864. state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
  865. state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */
  866. /* m_EP4 default for XToutOn, CAL_Mode (0) */
  867. state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog);
  868. /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */
  869. if (Standard <= HF_AnalogMax)
  870. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
  871. else if (Standard <= HF_ATSC)
  872. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
  873. else if (Standard <= HF_DVBC)
  874. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
  875. else
  876. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
  877. if ((Standard == HF_FM_Radio) && state->m_bFMInput)
  878. state->m_Regs[EP4] |= 80;
  879. state->m_Regs[MPD] &= ~0x80;
  880. if (Standard > HF_AnalogMax)
  881. state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */
  882. state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
  883. /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */
  884. if (Standard == HF_FM_Radio)
  885. state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
  886. else
  887. state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */
  888. status = UpdateRegs(state, EB22, EB23);
  889. if (status < 0)
  890. break;
  891. state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */
  892. state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
  893. state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
  894. state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
  895. (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */
  896. /* AGC1_always_master = 0 */
  897. /* AGC_firstn = 0 */
  898. status = UpdateReg(state, EB1);
  899. if (status < 0)
  900. break;
  901. if (state->m_bMaster) {
  902. status = CalcMainPLL(state, Frequency + IntermediateFrequency);
  903. if (status < 0)
  904. break;
  905. status = UpdateRegs(state, TM, EP5);
  906. if (status < 0)
  907. break;
  908. state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */
  909. status = UpdateReg(state, EB4);
  910. if (status < 0)
  911. break;
  912. msleep(1);
  913. state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */
  914. status = UpdateReg(state, EB4);
  915. if (status < 0)
  916. break;
  917. } else {
  918. u8 PostDiv = 0;
  919. u8 Div;
  920. status = CalcCalPLL(state, Frequency + IntermediateFrequency);
  921. if (status < 0)
  922. break;
  923. SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div);
  924. state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
  925. status = UpdateReg(state, MPD);
  926. if (status < 0)
  927. break;
  928. status = UpdateRegs(state, TM, EP5);
  929. if (status < 0)
  930. break;
  931. state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */
  932. status = UpdateReg(state, EB7);
  933. if (status < 0)
  934. break;
  935. msleep(1);
  936. state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */
  937. status = UpdateReg(state, EB7);
  938. if (status < 0)
  939. break;
  940. }
  941. msleep(20);
  942. if (Standard != HF_FM_Radio)
  943. state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */
  944. status = UpdateReg(state, EP3);
  945. if (status < 0)
  946. break;
  947. } while (0);
  948. return status;
  949. }
  950. static int sleep(struct dvb_frontend *fe)
  951. {
  952. struct tda_state *state = fe->tuner_priv;
  953. StandBy(state);
  954. return 0;
  955. }
  956. static int init(struct dvb_frontend *fe)
  957. {
  958. return 0;
  959. }
  960. static int release(struct dvb_frontend *fe)
  961. {
  962. kfree(fe->tuner_priv);
  963. fe->tuner_priv = NULL;
  964. return 0;
  965. }
  966. static int set_params(struct dvb_frontend *fe)
  967. {
  968. struct tda_state *state = fe->tuner_priv;
  969. int status = 0;
  970. int Standard;
  971. u32 bw = fe->dtv_property_cache.bandwidth_hz;
  972. u32 delsys = fe->dtv_property_cache.delivery_system;
  973. state->m_Frequency = fe->dtv_property_cache.frequency;
  974. switch (delsys) {
  975. case SYS_DVBT:
  976. case SYS_DVBT2:
  977. switch (bw) {
  978. case 6000000:
  979. Standard = HF_DVBT_6MHZ;
  980. break;
  981. case 7000000:
  982. Standard = HF_DVBT_7MHZ;
  983. break;
  984. case 8000000:
  985. Standard = HF_DVBT_8MHZ;
  986. break;
  987. default:
  988. return -EINVAL;
  989. }
  990. case SYS_DVBC_ANNEX_A:
  991. case SYS_DVBC_ANNEX_C:
  992. if (bw <= 6000000)
  993. Standard = HF_DVBC_6MHZ;
  994. else if (bw <= 7000000)
  995. Standard = HF_DVBC_7MHZ;
  996. else
  997. Standard = HF_DVBC_8MHZ;
  998. break;
  999. default:
  1000. return -EINVAL;
  1001. }
  1002. do {
  1003. status = RFTrackingFiltersCorrection(state, state->m_Frequency);
  1004. if (status < 0)
  1005. break;
  1006. status = ChannelConfiguration(state, state->m_Frequency,
  1007. Standard);
  1008. if (status < 0)
  1009. break;
  1010. msleep(state->m_SettlingTime); /* Allow AGC's to settle down */
  1011. } while (0);
  1012. return status;
  1013. }
  1014. #if 0
  1015. static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc)
  1016. {
  1017. if (IFAgc < 500) {
  1018. /* Scale this from 0 to 50000 */
  1019. *pSignalStrength = IFAgc * 100;
  1020. } else {
  1021. /* Scale range 500-1500 to 50000-80000 */
  1022. *pSignalStrength = 50000 + (IFAgc - 500) * 30;
  1023. }
  1024. return 0;
  1025. }
  1026. #endif
  1027. static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  1028. {
  1029. struct tda_state *state = fe->tuner_priv;
  1030. *frequency = state->IF;
  1031. return 0;
  1032. }
  1033. static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  1034. {
  1035. /* struct tda_state *state = fe->tuner_priv; */
  1036. /* *bandwidth = priv->bandwidth; */
  1037. return 0;
  1038. }
  1039. static struct dvb_tuner_ops tuner_ops = {
  1040. .info = {
  1041. .name = "NXP TDA18271C2D",
  1042. .frequency_min = 47125000,
  1043. .frequency_max = 865000000,
  1044. .frequency_step = 62500
  1045. },
  1046. .init = init,
  1047. .sleep = sleep,
  1048. .set_params = set_params,
  1049. .release = release,
  1050. .get_if_frequency = get_if_frequency,
  1051. .get_bandwidth = get_bandwidth,
  1052. };
  1053. struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
  1054. struct i2c_adapter *i2c, u8 adr)
  1055. {
  1056. struct tda_state *state;
  1057. state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
  1058. if (!state)
  1059. return NULL;
  1060. fe->tuner_priv = state;
  1061. state->adr = adr;
  1062. state->i2c = i2c;
  1063. memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
  1064. reset(state);
  1065. InitCal(state);
  1066. return fe;
  1067. }
  1068. EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
  1069. MODULE_DESCRIPTION("TDA18271C2 driver");
  1070. MODULE_AUTHOR("DD");
  1071. MODULE_LICENSE("GPL");