lpc32xx_ts.c 10 KB

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  1. /*
  2. * LPC32xx built-in touchscreen driver
  3. *
  4. * Copyright (C) 2010 NXP Semiconductors
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/platform_device.h>
  17. #include <linux/init.h>
  18. #include <linux/input.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/module.h>
  21. #include <linux/clk.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/of.h>
  25. /*
  26. * Touchscreen controller register offsets
  27. */
  28. #define LPC32XX_TSC_STAT 0x00
  29. #define LPC32XX_TSC_SEL 0x04
  30. #define LPC32XX_TSC_CON 0x08
  31. #define LPC32XX_TSC_FIFO 0x0C
  32. #define LPC32XX_TSC_DTR 0x10
  33. #define LPC32XX_TSC_RTR 0x14
  34. #define LPC32XX_TSC_UTR 0x18
  35. #define LPC32XX_TSC_TTR 0x1C
  36. #define LPC32XX_TSC_DXP 0x20
  37. #define LPC32XX_TSC_MIN_X 0x24
  38. #define LPC32XX_TSC_MAX_X 0x28
  39. #define LPC32XX_TSC_MIN_Y 0x2C
  40. #define LPC32XX_TSC_MAX_Y 0x30
  41. #define LPC32XX_TSC_AUX_UTR 0x34
  42. #define LPC32XX_TSC_AUX_MIN 0x38
  43. #define LPC32XX_TSC_AUX_MAX 0x3C
  44. #define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
  45. #define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
  46. #define LPC32XX_TSC_SEL_DEFVAL 0x0284
  47. #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11)
  48. #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
  49. #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
  50. #define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
  51. #define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
  52. #define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
  53. #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16)
  54. #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF)
  55. #define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
  56. #define LPC32XX_TSC_MIN_XY_VAL 0x0
  57. #define LPC32XX_TSC_MAX_XY_VAL 0x3FF
  58. #define MOD_NAME "ts-lpc32xx"
  59. #define tsc_readl(dev, reg) \
  60. __raw_readl((dev)->tsc_base + (reg))
  61. #define tsc_writel(dev, reg, val) \
  62. __raw_writel((val), (dev)->tsc_base + (reg))
  63. struct lpc32xx_tsc {
  64. struct input_dev *dev;
  65. void __iomem *tsc_base;
  66. int irq;
  67. struct clk *clk;
  68. };
  69. static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc)
  70. {
  71. while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) &
  72. LPC32XX_TSC_STAT_FIFO_EMPTY))
  73. tsc_readl(tsc, LPC32XX_TSC_FIFO);
  74. }
  75. static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
  76. {
  77. u32 tmp, rv[4], xs[4], ys[4];
  78. int idx;
  79. struct lpc32xx_tsc *tsc = dev_id;
  80. struct input_dev *input = tsc->dev;
  81. tmp = tsc_readl(tsc, LPC32XX_TSC_STAT);
  82. if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
  83. /* FIFO overflow - throw away samples */
  84. lpc32xx_fifo_clear(tsc);
  85. return IRQ_HANDLED;
  86. }
  87. /*
  88. * Gather and normalize 4 samples. Pen-up events may have less
  89. * than 4 samples, but its ok to pop 4 and let the last sample
  90. * pen status check drop the samples.
  91. */
  92. idx = 0;
  93. while (idx < 4 &&
  94. !(tsc_readl(tsc, LPC32XX_TSC_STAT) &
  95. LPC32XX_TSC_STAT_FIFO_EMPTY)) {
  96. tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO);
  97. xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
  98. LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
  99. ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
  100. LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
  101. rv[idx] = tmp;
  102. idx++;
  103. }
  104. /* Data is only valid if pen is still down in last sample */
  105. if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) {
  106. /* Use average of 2nd and 3rd sample for position */
  107. input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2);
  108. input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2);
  109. input_report_key(input, BTN_TOUCH, 1);
  110. } else {
  111. input_report_key(input, BTN_TOUCH, 0);
  112. }
  113. input_sync(input);
  114. return IRQ_HANDLED;
  115. }
  116. static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc)
  117. {
  118. /* Disable auto mode */
  119. tsc_writel(tsc, LPC32XX_TSC_CON,
  120. tsc_readl(tsc, LPC32XX_TSC_CON) &
  121. ~LPC32XX_TSC_ADCCON_AUTO_EN);
  122. clk_disable(tsc->clk);
  123. }
  124. static void lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc)
  125. {
  126. u32 tmp;
  127. clk_enable(tsc->clk);
  128. tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP;
  129. /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */
  130. tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
  131. LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
  132. LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10);
  133. tsc_writel(tsc, LPC32XX_TSC_CON, tmp);
  134. /* These values are all preset */
  135. tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL);
  136. tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL);
  137. tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL);
  138. tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL);
  139. tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL);
  140. /* Aux support is not used */
  141. tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0);
  142. tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0);
  143. tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0);
  144. /*
  145. * Set sample rate to about 240Hz per X/Y pair. A single measurement
  146. * consists of 4 pairs which gives about a 60Hz sample rate based on
  147. * a stable 32768Hz clock source. Values are in clocks.
  148. * Rate is (32768 / (RTR + XCONV + RTR + YCONV + DXP + TTR + UTR) / 4
  149. */
  150. tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2);
  151. tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2);
  152. tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10);
  153. tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4);
  154. tsc_writel(tsc, LPC32XX_TSC_UTR, 88);
  155. lpc32xx_fifo_clear(tsc);
  156. /* Enable automatic ts event capture */
  157. tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN);
  158. }
  159. static int lpc32xx_ts_open(struct input_dev *dev)
  160. {
  161. struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
  162. lpc32xx_setup_tsc(tsc);
  163. return 0;
  164. }
  165. static void lpc32xx_ts_close(struct input_dev *dev)
  166. {
  167. struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
  168. lpc32xx_stop_tsc(tsc);
  169. }
  170. static int lpc32xx_ts_probe(struct platform_device *pdev)
  171. {
  172. struct lpc32xx_tsc *tsc;
  173. struct input_dev *input;
  174. struct resource *res;
  175. resource_size_t size;
  176. int irq;
  177. int error;
  178. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  179. if (!res) {
  180. dev_err(&pdev->dev, "Can't get memory resource\n");
  181. return -ENOENT;
  182. }
  183. irq = platform_get_irq(pdev, 0);
  184. if (irq < 0) {
  185. dev_err(&pdev->dev, "Can't get interrupt resource\n");
  186. return irq;
  187. }
  188. tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
  189. input = input_allocate_device();
  190. if (!tsc || !input) {
  191. dev_err(&pdev->dev, "failed allocating memory\n");
  192. error = -ENOMEM;
  193. goto err_free_mem;
  194. }
  195. tsc->dev = input;
  196. tsc->irq = irq;
  197. size = resource_size(res);
  198. if (!request_mem_region(res->start, size, pdev->name)) {
  199. dev_err(&pdev->dev, "TSC registers are not free\n");
  200. error = -EBUSY;
  201. goto err_free_mem;
  202. }
  203. tsc->tsc_base = ioremap(res->start, size);
  204. if (!tsc->tsc_base) {
  205. dev_err(&pdev->dev, "Can't map memory\n");
  206. error = -ENOMEM;
  207. goto err_release_mem;
  208. }
  209. tsc->clk = clk_get(&pdev->dev, NULL);
  210. if (IS_ERR(tsc->clk)) {
  211. dev_err(&pdev->dev, "failed getting clock\n");
  212. error = PTR_ERR(tsc->clk);
  213. goto err_unmap;
  214. }
  215. input->name = MOD_NAME;
  216. input->phys = "lpc32xx/input0";
  217. input->id.bustype = BUS_HOST;
  218. input->id.vendor = 0x0001;
  219. input->id.product = 0x0002;
  220. input->id.version = 0x0100;
  221. input->dev.parent = &pdev->dev;
  222. input->open = lpc32xx_ts_open;
  223. input->close = lpc32xx_ts_close;
  224. input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
  225. input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
  226. input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL,
  227. LPC32XX_TSC_MAX_XY_VAL, 0, 0);
  228. input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL,
  229. LPC32XX_TSC_MAX_XY_VAL, 0, 0);
  230. input_set_drvdata(input, tsc);
  231. error = request_irq(tsc->irq, lpc32xx_ts_interrupt,
  232. 0, pdev->name, tsc);
  233. if (error) {
  234. dev_err(&pdev->dev, "failed requesting interrupt\n");
  235. goto err_put_clock;
  236. }
  237. error = input_register_device(input);
  238. if (error) {
  239. dev_err(&pdev->dev, "failed registering input device\n");
  240. goto err_free_irq;
  241. }
  242. platform_set_drvdata(pdev, tsc);
  243. device_init_wakeup(&pdev->dev, 1);
  244. return 0;
  245. err_free_irq:
  246. free_irq(tsc->irq, tsc);
  247. err_put_clock:
  248. clk_put(tsc->clk);
  249. err_unmap:
  250. iounmap(tsc->tsc_base);
  251. err_release_mem:
  252. release_mem_region(res->start, size);
  253. err_free_mem:
  254. input_free_device(input);
  255. kfree(tsc);
  256. return error;
  257. }
  258. static int lpc32xx_ts_remove(struct platform_device *pdev)
  259. {
  260. struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev);
  261. struct resource *res;
  262. device_init_wakeup(&pdev->dev, 0);
  263. free_irq(tsc->irq, tsc);
  264. input_unregister_device(tsc->dev);
  265. clk_put(tsc->clk);
  266. iounmap(tsc->tsc_base);
  267. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  268. release_mem_region(res->start, resource_size(res));
  269. kfree(tsc);
  270. return 0;
  271. }
  272. #ifdef CONFIG_PM
  273. static int lpc32xx_ts_suspend(struct device *dev)
  274. {
  275. struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
  276. struct input_dev *input = tsc->dev;
  277. /*
  278. * Suspend and resume can be called when the device hasn't been
  279. * enabled. If there are no users that have the device open, then
  280. * avoid calling the TSC stop and start functions as the TSC
  281. * isn't yet clocked.
  282. */
  283. mutex_lock(&input->mutex);
  284. if (input->users) {
  285. if (device_may_wakeup(dev))
  286. enable_irq_wake(tsc->irq);
  287. else
  288. lpc32xx_stop_tsc(tsc);
  289. }
  290. mutex_unlock(&input->mutex);
  291. return 0;
  292. }
  293. static int lpc32xx_ts_resume(struct device *dev)
  294. {
  295. struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
  296. struct input_dev *input = tsc->dev;
  297. mutex_lock(&input->mutex);
  298. if (input->users) {
  299. if (device_may_wakeup(dev))
  300. disable_irq_wake(tsc->irq);
  301. else
  302. lpc32xx_setup_tsc(tsc);
  303. }
  304. mutex_unlock(&input->mutex);
  305. return 0;
  306. }
  307. static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
  308. .suspend = lpc32xx_ts_suspend,
  309. .resume = lpc32xx_ts_resume,
  310. };
  311. #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
  312. #else
  313. #define LPC32XX_TS_PM_OPS NULL
  314. #endif
  315. #ifdef CONFIG_OF
  316. static struct of_device_id lpc32xx_tsc_of_match[] = {
  317. { .compatible = "nxp,lpc3220-tsc", },
  318. { },
  319. };
  320. MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match);
  321. #endif
  322. static struct platform_driver lpc32xx_ts_driver = {
  323. .probe = lpc32xx_ts_probe,
  324. .remove = lpc32xx_ts_remove,
  325. .driver = {
  326. .name = MOD_NAME,
  327. .owner = THIS_MODULE,
  328. .pm = LPC32XX_TS_PM_OPS,
  329. .of_match_table = of_match_ptr(lpc32xx_tsc_of_match),
  330. },
  331. };
  332. module_platform_driver(lpc32xx_ts_driver);
  333. MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
  334. MODULE_DESCRIPTION("LPC32XX TSC Driver");
  335. MODULE_LICENSE("GPL");
  336. MODULE_ALIAS("platform:lpc32xx_ts");