cq.c 22 KB

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  1. /*
  2. * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include <linux/slab.h>
  36. #include "mlx4_ib.h"
  37. #include "user.h"
  38. static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
  39. {
  40. struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  41. ibcq->comp_handler(ibcq, ibcq->cq_context);
  42. }
  43. static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
  44. {
  45. struct ib_event event;
  46. struct ib_cq *ibcq;
  47. if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
  48. pr_warn("Unexpected event type %d "
  49. "on CQ %06x\n", type, cq->cqn);
  50. return;
  51. }
  52. ibcq = &to_mibcq(cq)->ibcq;
  53. if (ibcq->event_handler) {
  54. event.device = ibcq->device;
  55. event.event = IB_EVENT_CQ_ERR;
  56. event.element.cq = ibcq;
  57. ibcq->event_handler(&event, ibcq->cq_context);
  58. }
  59. }
  60. static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
  61. {
  62. return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
  63. }
  64. static void *get_cqe(struct mlx4_ib_cq *cq, int n)
  65. {
  66. return get_cqe_from_buf(&cq->buf, n);
  67. }
  68. static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
  69. {
  70. struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  71. struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
  72. return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
  73. !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
  74. }
  75. static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
  76. {
  77. return get_sw_cqe(cq, cq->mcq.cons_index);
  78. }
  79. int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
  80. {
  81. struct mlx4_ib_cq *mcq = to_mcq(cq);
  82. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  83. return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
  84. }
  85. static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
  86. {
  87. int err;
  88. err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
  89. PAGE_SIZE * 2, &buf->buf);
  90. if (err)
  91. goto out;
  92. buf->entry_size = dev->dev->caps.cqe_size;
  93. err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
  94. &buf->mtt);
  95. if (err)
  96. goto err_buf;
  97. err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
  98. if (err)
  99. goto err_mtt;
  100. return 0;
  101. err_mtt:
  102. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  103. err_buf:
  104. mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
  105. out:
  106. return err;
  107. }
  108. static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
  109. {
  110. mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
  111. }
  112. static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
  113. struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
  114. u64 buf_addr, int cqe)
  115. {
  116. int err;
  117. int cqe_size = dev->dev->caps.cqe_size;
  118. *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
  119. IB_ACCESS_LOCAL_WRITE, 1);
  120. if (IS_ERR(*umem))
  121. return PTR_ERR(*umem);
  122. err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
  123. ilog2((*umem)->page_size), &buf->mtt);
  124. if (err)
  125. goto err_buf;
  126. err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
  127. if (err)
  128. goto err_mtt;
  129. return 0;
  130. err_mtt:
  131. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  132. err_buf:
  133. ib_umem_release(*umem);
  134. return err;
  135. }
  136. struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
  137. struct ib_ucontext *context,
  138. struct ib_udata *udata)
  139. {
  140. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  141. struct mlx4_ib_cq *cq;
  142. struct mlx4_uar *uar;
  143. int err;
  144. if (entries < 1 || entries > dev->dev->caps.max_cqes)
  145. return ERR_PTR(-EINVAL);
  146. cq = kmalloc(sizeof *cq, GFP_KERNEL);
  147. if (!cq)
  148. return ERR_PTR(-ENOMEM);
  149. entries = roundup_pow_of_two(entries + 1);
  150. cq->ibcq.cqe = entries - 1;
  151. mutex_init(&cq->resize_mutex);
  152. spin_lock_init(&cq->lock);
  153. cq->resize_buf = NULL;
  154. cq->resize_umem = NULL;
  155. if (context) {
  156. struct mlx4_ib_create_cq ucmd;
  157. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
  158. err = -EFAULT;
  159. goto err_cq;
  160. }
  161. err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
  162. ucmd.buf_addr, entries);
  163. if (err)
  164. goto err_cq;
  165. err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
  166. &cq->db);
  167. if (err)
  168. goto err_mtt;
  169. uar = &to_mucontext(context)->uar;
  170. } else {
  171. err = mlx4_db_alloc(dev->dev, &cq->db, 1);
  172. if (err)
  173. goto err_cq;
  174. cq->mcq.set_ci_db = cq->db.db;
  175. cq->mcq.arm_db = cq->db.db + 1;
  176. *cq->mcq.set_ci_db = 0;
  177. *cq->mcq.arm_db = 0;
  178. err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
  179. if (err)
  180. goto err_db;
  181. uar = &dev->priv_uar;
  182. }
  183. if (dev->eq_table)
  184. vector = dev->eq_table[vector % ibdev->num_comp_vectors];
  185. err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
  186. cq->db.dma, &cq->mcq, vector, 0);
  187. if (err)
  188. goto err_dbmap;
  189. cq->mcq.comp = mlx4_ib_cq_comp;
  190. cq->mcq.event = mlx4_ib_cq_event;
  191. if (context)
  192. if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
  193. err = -EFAULT;
  194. goto err_dbmap;
  195. }
  196. return &cq->ibcq;
  197. err_dbmap:
  198. if (context)
  199. mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
  200. err_mtt:
  201. mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
  202. if (context)
  203. ib_umem_release(cq->umem);
  204. else
  205. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  206. err_db:
  207. if (!context)
  208. mlx4_db_free(dev->dev, &cq->db);
  209. err_cq:
  210. kfree(cq);
  211. return ERR_PTR(err);
  212. }
  213. static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  214. int entries)
  215. {
  216. int err;
  217. if (cq->resize_buf)
  218. return -EBUSY;
  219. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  220. if (!cq->resize_buf)
  221. return -ENOMEM;
  222. err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
  223. if (err) {
  224. kfree(cq->resize_buf);
  225. cq->resize_buf = NULL;
  226. return err;
  227. }
  228. cq->resize_buf->cqe = entries - 1;
  229. return 0;
  230. }
  231. static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  232. int entries, struct ib_udata *udata)
  233. {
  234. struct mlx4_ib_resize_cq ucmd;
  235. int err;
  236. if (cq->resize_umem)
  237. return -EBUSY;
  238. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
  239. return -EFAULT;
  240. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  241. if (!cq->resize_buf)
  242. return -ENOMEM;
  243. err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
  244. &cq->resize_umem, ucmd.buf_addr, entries);
  245. if (err) {
  246. kfree(cq->resize_buf);
  247. cq->resize_buf = NULL;
  248. return err;
  249. }
  250. cq->resize_buf->cqe = entries - 1;
  251. return 0;
  252. }
  253. static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
  254. {
  255. u32 i;
  256. i = cq->mcq.cons_index;
  257. while (get_sw_cqe(cq, i & cq->ibcq.cqe))
  258. ++i;
  259. return i - cq->mcq.cons_index;
  260. }
  261. static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
  262. {
  263. struct mlx4_cqe *cqe, *new_cqe;
  264. int i;
  265. int cqe_size = cq->buf.entry_size;
  266. int cqe_inc = cqe_size == 64 ? 1 : 0;
  267. i = cq->mcq.cons_index;
  268. cqe = get_cqe(cq, i & cq->ibcq.cqe);
  269. cqe += cqe_inc;
  270. while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
  271. new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
  272. (i + 1) & cq->resize_buf->cqe);
  273. memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
  274. new_cqe += cqe_inc;
  275. new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
  276. (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
  277. cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
  278. cqe += cqe_inc;
  279. }
  280. ++cq->mcq.cons_index;
  281. }
  282. int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
  283. {
  284. struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
  285. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  286. struct mlx4_mtt mtt;
  287. int outst_cqe;
  288. int err;
  289. mutex_lock(&cq->resize_mutex);
  290. if (entries < 1 || entries > dev->dev->caps.max_cqes) {
  291. err = -EINVAL;
  292. goto out;
  293. }
  294. entries = roundup_pow_of_two(entries + 1);
  295. if (entries == ibcq->cqe + 1) {
  296. err = 0;
  297. goto out;
  298. }
  299. if (ibcq->uobject) {
  300. err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
  301. if (err)
  302. goto out;
  303. } else {
  304. /* Can't be smaller than the number of outstanding CQEs */
  305. outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
  306. if (entries < outst_cqe + 1) {
  307. err = 0;
  308. goto out;
  309. }
  310. err = mlx4_alloc_resize_buf(dev, cq, entries);
  311. if (err)
  312. goto out;
  313. }
  314. mtt = cq->buf.mtt;
  315. err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
  316. if (err)
  317. goto err_buf;
  318. mlx4_mtt_cleanup(dev->dev, &mtt);
  319. if (ibcq->uobject) {
  320. cq->buf = cq->resize_buf->buf;
  321. cq->ibcq.cqe = cq->resize_buf->cqe;
  322. ib_umem_release(cq->umem);
  323. cq->umem = cq->resize_umem;
  324. kfree(cq->resize_buf);
  325. cq->resize_buf = NULL;
  326. cq->resize_umem = NULL;
  327. } else {
  328. struct mlx4_ib_cq_buf tmp_buf;
  329. int tmp_cqe = 0;
  330. spin_lock_irq(&cq->lock);
  331. if (cq->resize_buf) {
  332. mlx4_ib_cq_resize_copy_cqes(cq);
  333. tmp_buf = cq->buf;
  334. tmp_cqe = cq->ibcq.cqe;
  335. cq->buf = cq->resize_buf->buf;
  336. cq->ibcq.cqe = cq->resize_buf->cqe;
  337. kfree(cq->resize_buf);
  338. cq->resize_buf = NULL;
  339. }
  340. spin_unlock_irq(&cq->lock);
  341. if (tmp_cqe)
  342. mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
  343. }
  344. goto out;
  345. err_buf:
  346. mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
  347. if (!ibcq->uobject)
  348. mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
  349. cq->resize_buf->cqe);
  350. kfree(cq->resize_buf);
  351. cq->resize_buf = NULL;
  352. if (cq->resize_umem) {
  353. ib_umem_release(cq->resize_umem);
  354. cq->resize_umem = NULL;
  355. }
  356. out:
  357. mutex_unlock(&cq->resize_mutex);
  358. return err;
  359. }
  360. int mlx4_ib_destroy_cq(struct ib_cq *cq)
  361. {
  362. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  363. struct mlx4_ib_cq *mcq = to_mcq(cq);
  364. mlx4_cq_free(dev->dev, &mcq->mcq);
  365. mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
  366. if (cq->uobject) {
  367. mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
  368. ib_umem_release(mcq->umem);
  369. } else {
  370. mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
  371. mlx4_db_free(dev->dev, &mcq->db);
  372. }
  373. kfree(mcq);
  374. return 0;
  375. }
  376. static void dump_cqe(void *cqe)
  377. {
  378. __be32 *buf = cqe;
  379. pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
  380. be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
  381. be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
  382. be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
  383. }
  384. static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
  385. struct ib_wc *wc)
  386. {
  387. if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
  388. pr_debug("local QP operation err "
  389. "(QPN %06x, WQE index %x, vendor syndrome %02x, "
  390. "opcode = %02x)\n",
  391. be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
  392. cqe->vendor_err_syndrome,
  393. cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  394. dump_cqe(cqe);
  395. }
  396. switch (cqe->syndrome) {
  397. case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
  398. wc->status = IB_WC_LOC_LEN_ERR;
  399. break;
  400. case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
  401. wc->status = IB_WC_LOC_QP_OP_ERR;
  402. break;
  403. case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
  404. wc->status = IB_WC_LOC_PROT_ERR;
  405. break;
  406. case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
  407. wc->status = IB_WC_WR_FLUSH_ERR;
  408. break;
  409. case MLX4_CQE_SYNDROME_MW_BIND_ERR:
  410. wc->status = IB_WC_MW_BIND_ERR;
  411. break;
  412. case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
  413. wc->status = IB_WC_BAD_RESP_ERR;
  414. break;
  415. case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
  416. wc->status = IB_WC_LOC_ACCESS_ERR;
  417. break;
  418. case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
  419. wc->status = IB_WC_REM_INV_REQ_ERR;
  420. break;
  421. case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
  422. wc->status = IB_WC_REM_ACCESS_ERR;
  423. break;
  424. case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
  425. wc->status = IB_WC_REM_OP_ERR;
  426. break;
  427. case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
  428. wc->status = IB_WC_RETRY_EXC_ERR;
  429. break;
  430. case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
  431. wc->status = IB_WC_RNR_RETRY_EXC_ERR;
  432. break;
  433. case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
  434. wc->status = IB_WC_REM_ABORT_ERR;
  435. break;
  436. default:
  437. wc->status = IB_WC_GENERAL_ERR;
  438. break;
  439. }
  440. wc->vendor_err = cqe->vendor_err_syndrome;
  441. }
  442. static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
  443. {
  444. return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
  445. MLX4_CQE_STATUS_IPV4F |
  446. MLX4_CQE_STATUS_IPV4OPT |
  447. MLX4_CQE_STATUS_IPV6 |
  448. MLX4_CQE_STATUS_IPOK)) ==
  449. cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
  450. MLX4_CQE_STATUS_IPOK)) &&
  451. (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
  452. MLX4_CQE_STATUS_TCP)) &&
  453. checksum == cpu_to_be16(0xffff);
  454. }
  455. static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
  456. unsigned tail, struct mlx4_cqe *cqe)
  457. {
  458. struct mlx4_ib_proxy_sqp_hdr *hdr;
  459. ib_dma_sync_single_for_cpu(qp->ibqp.device,
  460. qp->sqp_proxy_rcv[tail].map,
  461. sizeof (struct mlx4_ib_proxy_sqp_hdr),
  462. DMA_FROM_DEVICE);
  463. hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
  464. wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index);
  465. wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32);
  466. wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
  467. wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
  468. wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
  469. wc->dlid_path_bits = 0;
  470. return 0;
  471. }
  472. static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
  473. struct mlx4_ib_qp **cur_qp,
  474. struct ib_wc *wc)
  475. {
  476. struct mlx4_cqe *cqe;
  477. struct mlx4_qp *mqp;
  478. struct mlx4_ib_wq *wq;
  479. struct mlx4_ib_srq *srq;
  480. int is_send;
  481. int is_error;
  482. u32 g_mlpath_rqpn;
  483. u16 wqe_ctr;
  484. unsigned tail = 0;
  485. repoll:
  486. cqe = next_cqe_sw(cq);
  487. if (!cqe)
  488. return -EAGAIN;
  489. if (cq->buf.entry_size == 64)
  490. cqe++;
  491. ++cq->mcq.cons_index;
  492. /*
  493. * Make sure we read CQ entry contents after we've checked the
  494. * ownership bit.
  495. */
  496. rmb();
  497. is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
  498. is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  499. MLX4_CQE_OPCODE_ERROR;
  500. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
  501. is_send)) {
  502. pr_warn("Completion for NOP opcode detected!\n");
  503. return -EINVAL;
  504. }
  505. /* Resize CQ in progress */
  506. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
  507. if (cq->resize_buf) {
  508. struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
  509. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  510. cq->buf = cq->resize_buf->buf;
  511. cq->ibcq.cqe = cq->resize_buf->cqe;
  512. kfree(cq->resize_buf);
  513. cq->resize_buf = NULL;
  514. }
  515. goto repoll;
  516. }
  517. if (!*cur_qp ||
  518. (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
  519. /*
  520. * We do not have to take the QP table lock here,
  521. * because CQs will be locked while QPs are removed
  522. * from the table.
  523. */
  524. mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
  525. be32_to_cpu(cqe->vlan_my_qpn));
  526. if (unlikely(!mqp)) {
  527. pr_warn("CQ %06x with entry for unknown QPN %06x\n",
  528. cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
  529. return -EINVAL;
  530. }
  531. *cur_qp = to_mibqp(mqp);
  532. }
  533. wc->qp = &(*cur_qp)->ibqp;
  534. if (is_send) {
  535. wq = &(*cur_qp)->sq;
  536. if (!(*cur_qp)->sq_signal_bits) {
  537. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  538. wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
  539. }
  540. wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
  541. ++wq->tail;
  542. } else if ((*cur_qp)->ibqp.srq) {
  543. srq = to_msrq((*cur_qp)->ibqp.srq);
  544. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  545. wc->wr_id = srq->wrid[wqe_ctr];
  546. mlx4_ib_free_srq_wqe(srq, wqe_ctr);
  547. } else {
  548. wq = &(*cur_qp)->rq;
  549. tail = wq->tail & (wq->wqe_cnt - 1);
  550. wc->wr_id = wq->wrid[tail];
  551. ++wq->tail;
  552. }
  553. if (unlikely(is_error)) {
  554. mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
  555. return 0;
  556. }
  557. wc->status = IB_WC_SUCCESS;
  558. if (is_send) {
  559. wc->wc_flags = 0;
  560. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  561. case MLX4_OPCODE_RDMA_WRITE_IMM:
  562. wc->wc_flags |= IB_WC_WITH_IMM;
  563. case MLX4_OPCODE_RDMA_WRITE:
  564. wc->opcode = IB_WC_RDMA_WRITE;
  565. break;
  566. case MLX4_OPCODE_SEND_IMM:
  567. wc->wc_flags |= IB_WC_WITH_IMM;
  568. case MLX4_OPCODE_SEND:
  569. case MLX4_OPCODE_SEND_INVAL:
  570. wc->opcode = IB_WC_SEND;
  571. break;
  572. case MLX4_OPCODE_RDMA_READ:
  573. wc->opcode = IB_WC_RDMA_READ;
  574. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  575. break;
  576. case MLX4_OPCODE_ATOMIC_CS:
  577. wc->opcode = IB_WC_COMP_SWAP;
  578. wc->byte_len = 8;
  579. break;
  580. case MLX4_OPCODE_ATOMIC_FA:
  581. wc->opcode = IB_WC_FETCH_ADD;
  582. wc->byte_len = 8;
  583. break;
  584. case MLX4_OPCODE_MASKED_ATOMIC_CS:
  585. wc->opcode = IB_WC_MASKED_COMP_SWAP;
  586. wc->byte_len = 8;
  587. break;
  588. case MLX4_OPCODE_MASKED_ATOMIC_FA:
  589. wc->opcode = IB_WC_MASKED_FETCH_ADD;
  590. wc->byte_len = 8;
  591. break;
  592. case MLX4_OPCODE_BIND_MW:
  593. wc->opcode = IB_WC_BIND_MW;
  594. break;
  595. case MLX4_OPCODE_LSO:
  596. wc->opcode = IB_WC_LSO;
  597. break;
  598. case MLX4_OPCODE_FMR:
  599. wc->opcode = IB_WC_FAST_REG_MR;
  600. break;
  601. case MLX4_OPCODE_LOCAL_INVAL:
  602. wc->opcode = IB_WC_LOCAL_INV;
  603. break;
  604. }
  605. } else {
  606. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  607. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  608. case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
  609. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  610. wc->wc_flags = IB_WC_WITH_IMM;
  611. wc->ex.imm_data = cqe->immed_rss_invalid;
  612. break;
  613. case MLX4_RECV_OPCODE_SEND_INVAL:
  614. wc->opcode = IB_WC_RECV;
  615. wc->wc_flags = IB_WC_WITH_INVALIDATE;
  616. wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
  617. break;
  618. case MLX4_RECV_OPCODE_SEND:
  619. wc->opcode = IB_WC_RECV;
  620. wc->wc_flags = 0;
  621. break;
  622. case MLX4_RECV_OPCODE_SEND_IMM:
  623. wc->opcode = IB_WC_RECV;
  624. wc->wc_flags = IB_WC_WITH_IMM;
  625. wc->ex.imm_data = cqe->immed_rss_invalid;
  626. break;
  627. }
  628. if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
  629. if ((*cur_qp)->mlx4_ib_qp_type &
  630. (MLX4_IB_QPT_PROXY_SMI_OWNER |
  631. MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
  632. return use_tunnel_data(*cur_qp, cq, wc, tail, cqe);
  633. }
  634. wc->slid = be16_to_cpu(cqe->rlid);
  635. g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
  636. wc->src_qp = g_mlpath_rqpn & 0xffffff;
  637. wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
  638. wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
  639. wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
  640. wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
  641. cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
  642. if (rdma_port_get_link_layer(wc->qp->device,
  643. (*cur_qp)->port) == IB_LINK_LAYER_ETHERNET)
  644. wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
  645. else
  646. wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
  647. }
  648. return 0;
  649. }
  650. int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  651. {
  652. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  653. struct mlx4_ib_qp *cur_qp = NULL;
  654. unsigned long flags;
  655. int npolled;
  656. int err = 0;
  657. spin_lock_irqsave(&cq->lock, flags);
  658. for (npolled = 0; npolled < num_entries; ++npolled) {
  659. err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
  660. if (err)
  661. break;
  662. }
  663. mlx4_cq_set_ci(&cq->mcq);
  664. spin_unlock_irqrestore(&cq->lock, flags);
  665. if (err == 0 || err == -EAGAIN)
  666. return npolled;
  667. else
  668. return err;
  669. }
  670. int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
  671. {
  672. mlx4_cq_arm(&to_mcq(ibcq)->mcq,
  673. (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
  674. MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
  675. to_mdev(ibcq->device)->uar_map,
  676. MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
  677. return 0;
  678. }
  679. void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  680. {
  681. u32 prod_index;
  682. int nfreed = 0;
  683. struct mlx4_cqe *cqe, *dest;
  684. u8 owner_bit;
  685. int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
  686. /*
  687. * First we need to find the current producer index, so we
  688. * know where to start cleaning from. It doesn't matter if HW
  689. * adds new entries after this loop -- the QP we're worried
  690. * about is already in RESET, so the new entries won't come
  691. * from our QP and therefore don't need to be checked.
  692. */
  693. for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
  694. if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
  695. break;
  696. /*
  697. * Now sweep backwards through the CQ, removing CQ entries
  698. * that match our QP by copying older entries on top of them.
  699. */
  700. while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
  701. cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
  702. cqe += cqe_inc;
  703. if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
  704. if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
  705. mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
  706. ++nfreed;
  707. } else if (nfreed) {
  708. dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
  709. dest += cqe_inc;
  710. owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
  711. memcpy(dest, cqe, sizeof *cqe);
  712. dest->owner_sr_opcode = owner_bit |
  713. (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  714. }
  715. }
  716. if (nfreed) {
  717. cq->mcq.cons_index += nfreed;
  718. /*
  719. * Make sure update of buffer contents is done before
  720. * updating consumer index.
  721. */
  722. wmb();
  723. mlx4_cq_set_ci(&cq->mcq);
  724. }
  725. }
  726. void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  727. {
  728. spin_lock_irq(&cq->lock);
  729. __mlx4_ib_cq_clean(cq, qpn, srq);
  730. spin_unlock_irq(&cq->lock);
  731. }